KR100639752B1 - 3차원구조 메모리 - Google Patents

3차원구조 메모리 Download PDF

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Publication number
KR100639752B1
KR100639752B1 KR1019997009061A KR19997009061A KR100639752B1 KR 100639752 B1 KR100639752 B1 KR 100639752B1 KR 1019997009061 A KR1019997009061 A KR 1019997009061A KR 19997009061 A KR19997009061 A KR 19997009061A KR 100639752 B1 KR100639752 B1 KR 100639752B1
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South Korea
Prior art keywords
memory
substrate
circuit
integrated circuit
stacked integrated
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KR1019997009061A
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English (en)
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KR20010005983A (ko
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글렌 제이. 리디
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글렌 제이. 리디
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First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=25268870&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=KR100639752(B1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by 글렌 제이. 리디 filed Critical 글렌 제이. 리디
Priority to KR1020057018170A priority Critical patent/KR100785821B1/ko
Publication of KR20010005983A publication Critical patent/KR20010005983A/ko
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
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    • G11C29/846—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability by choosing redundant lines at an output stage
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Abstract

3차원구조(3DS) 메모리(100)는 다른 층상에서 메모리 회로(103)와 제어 로직 회로(101)간의 물리적 분리를 허용함으로써 각 층이 독립적으로 최적화될 수 있다. 하나의 제어 로직 회로(101)가 감소된 비용으로 수개의 메모리 회로(103)들을 만족시킨다. 3차원구조 메모리(100)의 제작은 메모리 회로(103)를 두께 50 마이크론 이하로 씨닝하고, 아직 웨이퍼 기판 형태인 회로 스택에 접착시키는 것을 포함한다. 고밀도 미립자로 된 층간 수직 버스 배선(105)이 사용된다. 3차원구조 메모리(100)의 제작방법은 몇가지 성능 및 물리적 크기의 효율화를 달성하였으며, 이미 정립된 반도체 공정기술로 실시되어진다.

Description

3차원구조 메모리{Three dimensional structure memory}
본 발명은 적층된 집적회로 메모리에 관한 것이다.
전자회로의 성능 향상과 비용 감소를 위한 제조방법들은, 거의 예외없이 회로의 집적도를 증가시키고, 트랜지스터 또는 캐패시터 등과 같은 회로소자들의 동일 갯수에 대한 그들의 물리적 크기를 감소시키는 방법들이다. 이러한 방법들은 1996년 현재 1000달러 이하의 가격으로 초당 1억번 이상의 동작을 수행할 수 있는 마이크로프로세서와 50달러 이하의 가격으로 50 나노세컨드(ns) 이하에서 데이터를 억세스하는 64 메가비트 디램(DRAM)을 생산해냈다. 이러한 회로들의 물리적 크기는 2 cm2 이하이다. 이러한 제조방법들은 주요 산업국가에서의 경제적 생활 수준을 상당한 정도로 지지해주고 있으며, 확실히 계속적으로 전세계에 걸쳐 인간의 일상생활에 중대한 영향을 미칠 것이다.
회로 제조방법은 공정 집적화 및 어셈블리 집적화라는 두가지 주요한 형태를 취한다. 역사적으로 이러한 두개의 제조 분야들 사이의 경계가 명확해져 왔지만, 최근 멀티칩 모듈(Multi-Chip Module;MCM)과 플립칩 다이 어태치(flip-chip die attach)의 사용의 증가와 함께 이러한 명확한 구분은 곧 사라지게 될 것이다. (여기서 집적회로(Integrated Circuit;IC)라는 용어는, 예를 들어 패키지 형태의 집적 회로와 대비하여 반도체 웨이퍼와 같은 회로기판으로부터 절단된 단독의 다이 형태의 집적회로에 대해 주로 사용한다.) 초기 다이 형태일 때는 집적회로의 대부분은 현재 개별적으로 패키징되고 있으나, MCM의 사용이 증가하고 있다. MCM에서 다이는 와이어본딩, DCA(Direct Chip Attach) 또는 FCA(Flip-Chip Attach)와 같은 통상적인 집적회로 다이 입/출력(I/O) 상호연결 접착방법에 의해 플래나(planar)방식으로 회로기판에 정상적으로 접착된다.
디램(DRAM), 에스램(SRAM), 플레시 이피롬(flash EPROM), 이이피롬(EEPROM), 강유전체(Ferroelectric), 지엠알(Giant MagnetoResistance;GMR)등과 같은 집적회로 메모리는, 메모리 어레이 회로와 동일 다이상에 집적된 제어기 회로와 함께 단일칩으로 구성되어 공통의 구조적 특성을 갖는다. 이러한 표준화 또는 통상화된 구성 또는 회로 레이아웃 구조는 대규모 메모리 회로에 있어서 제어기 회로와 메모리 어레이 회로의 설계상 서로간에 타협을 필요로 한다. 메모리셀 회로의 제작면적의 축소는 더욱더 밀집된 메모리 집적회로를 초래하게 되었으나, 이러한 메모리의 고 밀집도는 집적회로의 면적증가를 대신하여 한층 복잡해진 제어기 회로를 초래하게 되었다. 집적회로의 면적증가는 적어도 집적회로당 제조비용의 상승(웨이퍼당 집적회로수의 감소), 집적회로 수율의 저하(웨이퍼당 가동 집적회로수의 감소)를 의미하며, 최악의 경우, 경쟁력이 없는 비용 또는 신뢰성없는 동작으로 인해 제작될 수 없는 집적회로 디자인을 의미하게 된다.
메모리 밀도가 증가하고 개별적인 메모리셀 크기가 감소함에 따라 보다 많은 제어기 회로가 요구되어진다. DRAM과 같은 일부의 경우에는 집적회로(IC) 면적에 대한 백분율로서 메모리 IC의 제어기 회로가 40 %에 근접하거나 이를 초과한다. 제어기 회로의 일부는 독출동작 동안에 메모리 어레이 회로내에서 메모리셀의 상태, 전위 또는 전하를 감지하는 센스 앰프이다. 상기 센스 앰프회로는 제어기 회로에 있어서 중요한 부분이며, 센스 앰프가 점유하는 면적이 너무 크게 되지 않으면서도 보다 작아진 메모리셀을 감지하기 위하여 센스 앰프의 감도를 향상시키는 것은 IC 메모리 디자이너에게 있어서는 지속적인 연구과제가 된다.
만약 이러한 제어 회로와 메모리 회로 사이에 디자인상의 제한이나 타협이 존재하지 않았다면, 메모리 셀당 다중의 저장상태를 감지하는 것, 보다 감도가 커진 센스 앰프를 통한 보다 빨라진 메모리 억세스, 캐싱, 리프레시, 어드레스 변경 등과 같은 수많은 부가적인 기능들이 수행되도록 만들어졌을 것이다. 그러나 이러한 타협은 현재 모든 제작자들에 의해 채택되고 있기 때문에, 메모리 집적회로에 있어서 물리적 및 경제적 현실로 되고 있다.
DRAM의 용량은 한 세대로부터 다음 세대로 4 배씩, 즉 1 메가비트, 4 메가비트, 16 메가비트, 64 메가비트 DRAM으로 증가한다. 이와 같이 세대당 메모리 용량이 4 배씩 증가하면서 DRAM 회로면적은 점점 커지게 되었다. 새로운 DRAM 세대가 시작될 때에는 회로의 수율이 너무 낮기 때문에 대량 생산에 따르는 비용 효과가 없다. 새로운 DRAM 세대의 시작품이 선보인 이후 그 회로가 대량 생산되기 까지는 통상 수년이 걸린다.
적층식 또는 3차원(3D)식으로 다이를 조립하는 방법은 본명세서에 인용함으로써 통합되는 본 발명자의 미합중국 특허 제5,354,695호에 개시되어 있다. 더구 나, 메모리에 대하여도 3차원식의 다이 조립이 시도되었다. 달라스 텍사스의 텍사스 인스트루먼트사, 코스타 메사 캘리포니아의 어빈 센서사, 스코트 밸리 캘리포니아의 큐빅 메모리사가 모두 적층형 또는 3차원 DRAM 제품을 생산하려고 시도하였다. 세 경우 모두 다이 형태의 종래의 DRAM 회로를 적층하고, 적층된 각 DRAM 사이의 상호연결부는 적층된 외측 표면을 따라 형성하였다. 이러한 제품은 지난 수년 동안에 유용하였으며, 상업적으로 적용하기에는 너무 비싼 것으로 판명되었으나, 그들의 물리적 크기 또는 족적이 작기 때문에 우주선 및 군사적인 용도로서 일부 사용되었다.
본 명세서에서는 DRAM형 회로가 언급되며, 예로서 자주 사용되지만, 본 발명은 DRAM형 회로에 한정되는 것이 아니라는 것은 명백하다. 의심할 것도 없이 EEPROM(Electrically Erasable Programmable Read Only Memories), 플레시 EPROM, 강유전체, GMR(Giant Magneto Resistance) 또는 이러한 메모리셀들의 상호적 또는 내부적 조합물 등과 같은 메모리셀 형태들에 대하여도 3차원구조 메모리소자를 형성하기 위한 본 발명의 3차원 구조(3DS) 방법을 사용할 수 있다.
본 발명은 여러가지 가운데 다음의 목적들을 갖는다:
1. 종래의 모노리딕 회로 집적방법만으로 만들어진 회로보다 메가바이트 메모리당 몇 배의 저렴한 제작비용
2. 종래의 메모리 회로보다 몇 배의 향상된 성능
3. 종래의 메모리 회로보다 상당히 높아진 집적회로당 메모리 밀도
4. 회로면적의 크기, 비용에 대한 보다 커진 디자이너의 제어성
5. 내부의 제어기에 의한 메모리셀의 동적 및 정적 자기 테스트
6. 동적 에러 회복 및 재구성
7. 메모리 셀당 다중 레벨 저장
8. 가상 어드레스 변경, 어드레스 윈도윙, 간접 어드레싱 또는 내용 어드레싱 등과 같은 여러가지 어드레스 기능들, 아날로그회로 기능들 및 여러가지 그래픽 가속 및 마이크로프로세서 기능들
< 발명의 요약 >
본 발명의 3차원구조(3DS) 메모리 기술은 적층형 또는 3차원 회로 어셈블리 기술이다. 특징은 다음과 같다:
1. 메모리 회로와 제어 로직회로를 다른 층으로의 물리적 분리
2. 수개의 메모리회로에 대하여 하나의 제어 로직회로의 사용
3. 두께가 약 50 ㎛ 이하가 되도록 메모리 회로를 씨닝하고, 평탄하게 처리된 접착면을 가지고 유연한 기판을 형성하며, 여전히 웨이퍼 기판 형태로 회로 스택에 상기 회로를 접착하는 것
4. 수직적 버스 연결을 위한 고밀도 미립자 내부층의 사용.
상기 3차원구조 메모리 제조방법은 여러 가지의 성능 및 물리적 크기를 효율적으로 할 수 있으며, 이미 확립된 반도체 공정기술로 실시되어진다. DRAM 회로를 예로 들면, 0.25㎛ 공정기술로 만들어진 64 메가비트 DRAM은 다이의 크기가 84 mm2이며, 다이 크기에 대한 메모리면적의 비율이 40 %이며, 8 메가바이트의 저장을 위 한 억세스 타임이 50 ns이지만, 동일한 0.25㎛ 공정기술로 제작된 3차원구조 DRAM 집적회로는 다이의 크기가 18.6 mm2이며, 17개의 DRAM 어레이 회로층을 사용하며, 다이 크기에 대한 메모리 면적의 비율이 94.4 %이며, 64 메가바이트의 저장을 위한 예상되는 억세스 타임이 10 ns 이하이다. 상기 3차원구조 DRAM 집적회로의 제작방법은 전형적인 DRAM 집적회로 제작방법에 비하여 메가바이트당 비용면에서 몇 배의 감소를 나타낸다. 환언하면, 3차원구조 메모리 제작방법은, 하부구조의 레벨에서, 사용된 제조 공정기술과는 관계없이 근본적인 비용절감을 보여준다.
본 발명은 첨부된 도면과 결부하여 이하의 설명으로부터 보다 명확히 이해되어질 것이다.
도 1a는 방법 A와 방법 B에 의해 제작된 3차원구조 메모리 집적회로의 사시도로서, 종래의 전형적인 집적회로 다이와 동일한 I/O 접착패드의 물리적 외양을 보여주고 있다.
도 1b는 몇개의 씨닝된 회로층들 사이의 금속접착 상호연결부를 보여주는 3차원구조 메모리 집적회로의 단면도이다.
도 1c는 종래의 대형 집적회로 또는 다른 3차원구조 집적회로상에 면접되게 접착 및 상호연결된 3차원구조 DRAM 집적회로 스택의 사시도이다.
도 2a는 한 세트의 버스선의 데이터선, 즉 1 포트에 대한 3차원구조 DRAM 어레이회로 블록의 물리적 레이아웃을 보여주는 도면이다.
도 2b는 두 세트의 데이터선 버스선, 즉 2 포트에 대한 3차원구조 DRAM 어레 이회로 블록의 물리적 레이아웃을 보여주는 도면이다.
도 2c는 예시적인 메모리 제어기 회로의 일부의 물리적 레이아웃을 보여주는 도면이다.
도 3은 3차원 DRAM 어레이 블록에 대한 64개 분할을 보여주는 3차원 DRAM 어레이 회로의 물리적 레이아웃을 나타내는 도면이다.
도 4는 씨닝된 기판속으로 투입된 일반적인 3차원구조의 수직적 상호연결부를 보여주는 단면도이다.
도 5는 하향 선택되는 게이트선 독출 또는 기입의 선택을 위한 3차원구조 메모리 멀티플렉서의 레이아웃을 보여주는 도면이다.
도 1a 및 도 1b를 참조하면, 3차원구조(Three Dimensional Structure;3DS) 메모리장치(100)는 모든 회로층들 사이에서 미립자의 수직적 상호연결부를 갖는 집적회로층들의 스택이다. 상기 미립자의 층간 수직적 상호연결부란 용어는 중간에 개입된 소자요소가 있든가 또는 없든간에 회로층을 통과하며, 도 2a 및 도 2b에서 가장 잘 보여지는 바와 같이, 정상적으로 100 ㎛ 이하의 피치, 보다 전형적으로는 10 ㎛ 이하의 피치, 그러나 2 ㎛ 이하의 피치로 제한되지 않는 피치를 갖는 전기적 도전체를 의미하는 것으로 사용된다. 상기 미립자의 층간 수직적 상호연결부는 또한 여러 가지 회로층들을 함께 접착하는 기능을 수행한다. 도 1b에서 보여지는 바와 같이, 비록 상기 접착 및 상호연결층(105a)(105b) 등은 바람직하게는 금속이지만, 이하에서 충분히 설명되는 바와 같이 다른 재질도 또한 사용될 수 있다.
상기 접착 및 상호연결층(105a)(105b) 등에서 패턴(107a)(107b) 등은 집적회로층들 사이에서 수직적 상호연결 콘택을 정의하고 있으며, 이러한 콘택들을 서로로부터 그리고 잔존하는 접착물질로부터 전기적으로 분리하게 해주며, 이러한 패턴은 상기 접착층들에서 보이드 또는 유전체로 충전되는 공간의 형태를 취한다.
상기 3차원구조 메모리 스택은 전형적으로 제어기 회로(101)와, 전형적으로는 9 내지 32 개 사이이나, 층수에는 특별한 제한은 없는 일정한 수의 메모리 어레이 회로층(103)으로 구성되어 있다. 상기 제어기 회로는 정상적인 회로 두께(전형적으로 0.5 mm 또는 그 이상)를 갖지만, 각 메모리 어레이 회로층은 50 ㎛ 이하, 전형적으로는 10 ㎛ 이하의 두께로 낮은 스트레스를 갖는 씨닝된 유연한 회로이다. 종래의 I/O 접착패드들은 종래의 전형적인 패키징 방법을 사용하기 위해 최종 메모리 어레이 회로층상에 형성된다. 삽입형 상호연결(본 발명자에 의한 미합중국 특허 제5,323,035호 및 제5,453,404호에 개시됨), DCA(Direct Chip Attach) 또는 FCA(Flip-Chip Attach)와 같은 다른 금속 패턴들이 사용될 수도 있다.
나아가, 상기 미립자 층간 수직적 상호연결부는 3차원구조 메모리 다이와 종래의 다이(여기서 종래의 다이는 도 1c에서 보여지는 제어기 회로가 될 수 있다) 또는 3차원구조 메모리 다이와 다른 3차원 메모리 다이 사이에서 접착하는 직접적으로 단독의 다이를 위해 사용되어질 수 있다. 함께 접착되어지는 각 다이스의 면적(크기)은 다양할 수 있으며, 동일할 필요는 없다고 추정할 수 있다. 보다 구체적으로 도 1c를 참조하면, 3차원구조 DRAM 집적회로 스택(100)이 종래의 대형 집적회로 또는 다른 3차원구조 집적회로(107)상에 면접하여 접착 및 상호연결된다. 선택 적으로 상기 3차원구조 스택(100)은 상기 대형 다이의 일부로서 DRAM 제어기 회로를 갖는 DRAM 어레이 회로들만으로 구성될 수 있다. 만약 상기 DRAM 제어기 회로들이 상기 대형 다이의 일부이면, 그 때는 상기 3차원구조 DRAM 어레이 회로를 상기 DRAM 제어기에 연결하기 위해 미립자 수직 버스 상호연결부가 요구되어지며(상기 3차원구조 DRAM 집적회로 스택(100)의 면(109)에서), 그렇지 않으면 보다 큰 종래의 입자 상호연결이 상기 평탄화된 접착층속으로 접착(패턴)되어질 것이다.
도 3에서 보여지는 것처럼, 각 메모리 어레이 회로층은 메모리 어레이 블록(301)(정상적으로 면적이 5 mm2 이하)들로 구성된 메로리 어레이 회로(300)를 포함하며, 각 블록은 메모리 셀들(많은 점에서 DRAM 또는 EEPROM 회로의 셀 어레이와 동일한 방식), 버싱 전극들(busing electrodes) 및 디자이너의 선택에 따라 상기 메모리 어레이의 특정 로우 또는 컬럼을 선택하기 위한 인에이블 게이트(enabling gate)들로 구성된다. 상기 제어기 회로는 종래의 DRAM에서와 같은 전형적인 모노리딕 디자인의 메모리 회로의 주변영역에서 정상적으로 찾아볼 수 있는 센스 앰프, 어드레스, 제어 및 구동 로직으로 구성되어 있다.
미립자 버싱은 수직적으로 상기 제어기를 각 메모리 어레이층에 독립적으로 연결시켜서, 상기 제어기가 다른 어떤 층의 상태에 영향을 끼치지 않고서도 어떤 하나의 층에 구동력 또는 인에이블 신호들을 제공할 수 있도록 해준다. 이것은 상기 제어기로 하여금 상기 각 메모리 회로층들을 독립적으로 테스트, 독출 또는 기입하게 해준다.
도 2a 및 도 2b는 도 3의 블록(301)과 같은 메모리 어레이 블록의 가능한 레 이아웃의 예를 보여준다. 비록 블록의 단지 일부분만 보여지지만, 도시된 실시예에서, 상기 블록은 좌우대칭을 나타내어 전체 블록의 레이아웃이 도시된 부분으로부터 확인되어질 수 있게 해준다. 참조번호 뒤에 사용된 약자 "T", "L" 및 "TL" 은 각기 도면에는 보여지지 않는 대응하는 요소들을 암시하는 "Top", "Left" 및 "Top-Left"를 가리킨다.
도 2a를 참조하면, 블록의 중심부(200)는 메모리셀의 "바다"로 구성되어 있다. 논리적으로, 메모리셀의 집합체는 각기 일정한 수의 메모리셀, 즉 8 x 8의 어레이인 64개 메모리셀들을 포함하는 "마크로셀"(201)로 분할될 수 있다. 중심부의 주변부에는 도 4를 참조하여 이하에서 더욱 상세히 설명된, 층간 접착 및 버스 콘택 금속배선(400)을 포함하는 미립자 수직 상호연결부가 형성되어 있다. 상기 미립자 수직 상호연결부는 I/O 전력 및 접지 버스선(203TL), 메모리 회로층 선택선(205T), 메모리 마크로셀 컬럼 선택선(207T), 데이터선(209L) 및 게이트선 멀티플렉서("먹스") 선택선(209TL)을 포함한다. 도시된 실시예에서 게이트선 멀티플렉서(211T)는 8개의 광메모리 마크로셀 컬럼내에서 4개의 컬럼중의 하나를 선택하기 위해 사용되는 4:1 멀티플렉서이다. 대응하는 하단측 4:1 멀티플렉서는 8개 게이트선 광메모리 마크로셀 컬럼으로부터 단일 게이트선을 선택하기 위한 등가 8:1 멀티플렉서를 형성하기 위해 상단측 멀티플렉서(211T)와 연결된다.
4:1 게이트선 버스 멀티플렉서(500)의 한 실행태양이 도 5에 나타난다. 게이트선 인에이블(209TL')(예를 들어, 금속-1 층에 형성됨)은 각기 트랜지스터 501a 내지 501d를 제어한다. 각 게이트선 503a 내지 503d이 상기 트랜지스터들에 연결되 어 있다. 또한 대응하는 4:1 멀티플렉서(도시안됨)에 연결된 게이트선 505a 내지 505d가 부분적으로 보여진다. 게이트선 인에이블중의 하나가 활성화되면, 대응하는 게이트선은 멀티플렉서(예를 들어, 금속-2 층에 형성됨)의 출력선(507)에 연결된다. 상기 출력선은 선(509)(예를 들어, 금속-3 층에 형성되며 수직 버스 상호연결부의 금속 콘택(400)에 대응하는) 내지 텅스텐 플러그(511 및 513)를 통하여 하나 또는 그 이상의 수직 버스 콘택에 연결되어 있다. 상기 텅스텐 플러그(513)는 선(509)을 수직 상호연결부(도시안됨)에 연결시킨다.
다시 도 2a를 참조하면, 메모리 회로층의 경우에 상기 층은 I/O 인에이블(게이트)(213)이 제공되어지도록 제어기층 인에이블 신호(205T)로부터의 출력선 인에이블(게이트)을 포함할 수 있다.
메모리층 레벨에서, 각 메모리 블록(301)은 전기적으로 모든 다른 메모리 블록(301)으로부터 분리되어 있다. 따라서, 각 메모리 블록에 대한 수율은 독립적이다.
부가적인 독출/기입 포트들이 부가적인 게이트선 수직 상호연결을 할 수 있도록 부가되어질 수 있으며, 부가적인 수직 상호연결이 수직 상호연결의 수율을 향상시키기 위하여 중복방식으로 사용될 수 있다. 상기 3차원구조 메모리 회로는 하나 또는 그 이상의 데이터 독출 및 기입 버스 포트 상호연결부를 갖도록 설계될 수 있다. 도 2b를 참조하면, 메모리 블록(301')이 포트 P0(209L)와 다른 포트 P1(209L')을 갖는 것으로 나타난다. 수직 상호연결부의 수에 관한 유일한 제한은 이 러한 수직 상호연결부로 인하여 회로의 비용에 부과되는 총경비이다. 상기 미립자 수직 상호연결 방법은 단지 몇 퍼센트의 다이 면적의 증가로서 블록당 수천배의 상호연결을 허용한다.
예로서, 두개의 독출/기입 포트를 구비하는 4 메가비트의 DRAM 메모리 블록을 위한, 도 2b에서 보여지며 0.35 ㎛ 또는 0.15 ㎛ 디자인룰이 적용된 상기 수직 상호연결부의 총비용은 거의 5000개의 상호연결부로 구성되며, 상기 메모리 어레이 블록의 전체 면적의 6 %이하가 된다. 따라서, 3차원구조 DRAM 회로에서 각 메모리 어레이 회로층을 위한 상기 수직 상호연결부의 총비용은 6 %이하가 된다. 이것은 모노리딕 DRAM 회로 디자인에서 비메모리 셀영역의 백분율이 40 %를 초과하는 현재 진행되는 것보다 훨씬 적은 것이다. 완성된 3차원구조 DRAM 회로에서, 비메모리 셀영역의 백분율은 전형적으로 적층된 구조에 있는 모든 회로의 전체 면적의 10 %이하가 된다.
통상적으로 모노리딕 메모리 회로의 메모리셀들에 인접하여 발견되는 상기 3차원구조 메모리장치는 제어기능들을 분리하고, 그들을 제어기 회로에 대하여 격리시킨다. 이러한 제어기능들은 종래의 메모리 집적회로에서와 같이 각 메모리 어레이층상에서 발생한다기 보다는 상기 제어기 회로에서만 발생한다. 이것은 수개의 메모리 어레이층이 동일한 제어기 로직을 공유함으로써 경제적으로 유리하며, 따라서 종래의 메모리 디자인과 대비하여 2 배 이상 메모리셀당 총비용을 절감시킬 수 있다.
격리된 제어기 회로에 의한 제어기능의 분리는 그러한 기능을 위해 요구되는 보다 큰 면적(즉, 상기 메모리 어레이 블록의 한개 또는 여러 개의 면적과 동일한 면적) 만큼을 허용한다. 또한, 기능에 따른 이러한 물리적 분리는 제어 로직 및 메모리 어레이를 위해 사용된 매우 다른 두개의 제조기술상의 제조공정 분리를 허용해주며, 다시 종래의 메모리를 위해 사용된 보다 복잡하게 조합된 로직/메모리 제조기술에 대비하여 부가적인 제조비용의 절감을 실현시켜준다. 또한 상기 메모리 어레이는 제어 로직 기능들에 대한 공정요건을 고려함이 없이 공정기술로 제작될 수 있다. 이것은 현재의 메모리 회로의 경우 보다도 저비용으로 고성능의 제어기 기능을 디자인할 수 있게 해준다. 나아가, 상기 메모리 어레이 회로는 보다 적어진 공정 단계들로 제작될 수 있으며, 통상적으로 30 내지 40 %에 이르는 메모리 회로 제작비용을 절감할 수 있다(예를 들면, DRAM 어레이의 경우, 상기 공정기술은 CMOS에 비하여 NMOS 또는 PMOS 트랜지스터로 제한될 수 있다).
그러므로, 비록 열확산 금속 접착을 이용하여 메모리 제어기 기판과 메모리 어레이 기판간의 충분히 평탄한 면을 접착시키는 것이 바람직하지만, 본 발명의 보다 넓은 개념하에서는, 이방적으로 도전성을 띠는 에폭시 접착제와 같은 종래의 여러 가지 표면 접착방법중의 임의의 방법에 의해, 격리되어진 메모리 제어기와 메모리 어레이 기판 사이에 상호연결을 형성하여 랜덤 억세스 데이터 저장을 제공하도록 한다.
도 2c를 참조하면, 예시적인 메모리 제어기 회로의 일부 레이아웃이 보여진다. 상기 층간 접착 및 버스 콘택 금속배선은 도 2a와 관련하여 전술한 것과 동일한 패턴을 갖는다. 그러나, 메모리셀의 바다 대신에 예를 들어, 샌스 앰프 및 데이 터선 버퍼(215)를 포함하는 메모리 제어기 회로군이 제공된다. 다이 면적의 유용성이 향상됨에 따라 다중레벨 로직이 상기 센스 앰프 및 데이터선 버퍼(215)와 접착되어 제공될 수 있다. 또한, 어드레스 디코드, 게이트선 및 DRAM층 선택 로직(217), 리프레시 및 자기테스트 로직(219), ECC 로직(221), 윈도윙 로직(223) 등이 보여진다. 상기 자기테스트 로직, ECC 로직 및 윈도윙 로직은 통상적으로 DRAM 메모리 제어기 회로내에서 발견되는 기능들에 부가하여 제공된다. 다이의 크기 또는 사용된 제어기 회로층의 수에 의존하여, 예를 들어, 가상 메모리 관리, 간접 어드레싱 또는 내용 어드레싱과 같은 어드레스 기능, 데이터 압축, 데이터 압축해제, 오디오 인코딩, 오디오 디코딩, 비디오 인코딩, 비디오 디코딩, 음성인식, 필적인식, 전력 관리, 데이터베이스 처리, 그래픽 가속기능, 마이크로프로세서 기능(마이크로프로세서 기판의 부가를 포함) 등을 포함하는 수많은 다른 기능들 중 어느 것이 제공될 수도 있다.
3차원구조 메모리 회로 다이의 크기는 하나의 모노리딕층상에 메모리셀 및 제어기능 로직의 필요한 수를 포함한다는 본 제한조건에 의존하지 않는다. 이것은 회로 디자이너로 하여금 3차원구조 회로 다이의 크기를 축소하게 할 수 있고, 회로의 수율을 위해 보다 적정화된 다이 크기를 선택하게 할 수도 있다. 3차원구조 메모리 회로 다이의 크기는 기본적으로 최종적인 3차원구조 메모리 회로를 제조하기 위해 사용된 메모리 어레이 블록의 크기 및 수와, 메모리 어레이층의 수의 함수이다. (19층을 갖는 0.25 ㎛ 공정에 의한 DRAM 메모리 회로의 수율은 이하에서 설명하는 바와 같이 90 % 이상이 되는 것으로 나타난다.) 이러한 3차원구조 회로 다이 의 크기를 선택할 수 있다는 장점은 초기 제품으로 하여금 종래의 모노리딕 회로 디자인에 대하여 통상적으로 가능한 것보다 더 진보된 공정기술을 사용할 수 있게 해주는 것이다. 물론, 이것은 종래의 메모리 회로에 비하여 부가적인 비용의 감소 및 보다 향상된 성능을 내포하는 것이다.
[ 3차원구조 메모리소자 제조방법 ]
3차원구조 메모리 회로에 대한 두개의 기본적인 제조방법이 있다. 그러나, 이 두개의 3차원구조 메모리 제조방법은, 자체가 선택적으로 회로 구성층으로 될 수 있는 견고한 지지대 또는 공통의 기판상에 수많은 회로기판들을 열확산 금속접착(이하에서 열압축 접착이라고도 함)한다는 공통의 목적을 가지고 있다.
상기 지지대 또는 공통의 기판은 표준 반도체 웨이퍼, 쿼츠 웨이퍼 또는 3차원구조 회로의 공정단계, 회로의 동작 및 사용되는 처리장치에 적합한 조성물질을 갖는 기판이 될 수 있다. 상기 지지기판의 크기 및 형상은 가용한 제조장치 및 방법을 가장 적정화할 수 있는 선택적인 사항이다. 회로기판들은 상기 지지기판에 접착되고, 이어서 여러 가지 방법들을 통하여 씨닝된다. 회로기판들은 표준 단결정 반도체기판상에 형성되거나 또는 실리콘이나 쿼츠와 같은 적절한 기판상에 형성된 폴리실리콘 회로와 같은 것일 수 있다.
폴리실리콘 트랜지스터 회로는 폴리실리콘 회로들이 형성된 기판을 떼어내거나 재사용할 수 있도록 해주는 분리층을 접착할 수 있다는 중요한 비용절감의 요인을 갖는다. 폴리실리콘 트랜지스터 또는 TFT(Thin Film Transistor)장치는 광범위하게 사용되며, 유일하게 실리콘으로만 만들어질 필요는 없다.
3차원구조 메모리 회로의 다양한 회로층은 두개의 금속 표면, 전형적으로는 알루미늄간의 열확산을 이용하여 함께 접착된다. 접착되는 회로의 표면은, 적어도 접착되어질 (기판상에 형성된) 회로의 표면 영역위로 1 mm이하, 바람직하게는 1,000Å 이하의 표면 평탄도를 갖도록 화학적 기계적 폴리싱(CMP)방법에 의해 평탄화되며, 공정수행이 되지 않은 반도체 웨이퍼 또는 공정수행된 반도체 웨이퍼의 표면의 경우와 같이 매끄럽고 충분히 평탄하다. 상기 접착되어질 회로의 표면상에 있는 금속 접착물질은 서로 거울상이 되고, 도 2a, 도 2b, 도 2c 및 도 5에서 지시된 것처럼 다양한 수직 상호연결 콘택을 정의할 수 있도록 패턴되어진다. 두 회로기판의 접착단계는 동시에 상기 두 회로층 또는 기판간의 수직적 상호연결부를 형성하는 것이다.
회로층의 열확산 접합은 바람직하게는 약간의 H2O 및 O2를 포함하는 N2 분위기 및 제어된 압력을 갖는 챔버내에서 수행된다. 상기 접합장치는 접합되어질 기판들의 패턴들을 정렬하고, 일련의 계획된 압력과 접착물질로서 사용되는 금속의 형태에 따라 요구되는 시간주기 동안 하나 또는 그 이상의 온도하에서 이들을 함께 압착시킨다. 상기 접착물질의 두께는 통상적으로는 500Å 내지 15,000Å의 범위, 바람직하게는 1,500Å이 된다. 기판의 초기 접착은 접착패턴의 디자인에 따라서 1 torr 내지 740 torr 사이의 음압과 같이 표준압보다 낮은 압력하에서 수행되는 것이 바람직하다. 이것은 접착면 사이에 내부 음압을 남길 수 있으며, 외부의 대기압이 회복되면서 접착의 형성을 지원하며, 접착의 신뢰성을 증진시켜준다.
바람직한 접착물질은 순수한 알루미늄 또는 알루미늄 합금이지만, 알루미늄 에 한정되지 않고, 예를 들어 허용되는 온도 및 형성주기에서 허용가능한 표면접착 확산능력을 제공하는 Sn, Ti, In, Pb, Zn, Ni, Cu, Pt, Au 및 이들 금속의 합금을 포함할 수 있다. 상기 접착물질은 금속에 한정되지 않고, 고전도성 폴리실리콘과 같은 접착물질의 조합일 수 있으며, 그 일부는 실리콘다이옥사이드와 같은 비도전성일 수 있으며, 전술한 접착물질 선택에 대한 예시적인 형태는 회로층이 어떻게 접착되는가에 대하여는 제한을 받지 않는다.
금속 접착물질이 만족스러운 접착을 방해하거나 접착에 의해 형성된 수직 상호연결부에서 저항을 증가시킬지도 모르는 표면의 자연산화막을 형성하는 경우에는 상기 산화막은 제거되어야 한다. 상기 접착장치는 접착물질의 접착표면이 표면 자연산화막없이 이루어지도록 산화막 감소 기능을 제공한다. 표면산화막의 감소를 위한 가스분위기를 형성하는 방법들은 주지되어 있으며, 스퍼터링 식각, 플라즈마 식각 또는 이온밀 식각과 같은 자연산화막을 제거하는 다른 방법들도 있다. 알루미늄이 접착물질로 사용되는 경우, 접착표면에 형성되는 약 40Å 정도의 자연 알루미늄산화막은 접착 전에 제거하는 것이 바람직하다.
3차원구조 메모리회로의 씨닝된 유연한 기판 회로층들은 메모리 어레이 회로들이지만, 상기 씨닝된 기판 회로층들은 메모리 회로에 한정되는 것은 아니다. 다른 형태의 회로층으로서, 제어기 회로, EEPROM과 같은 비휘발성 메모리, 마이크로프로세서 로직 및 그래픽 또는 데이터베이스 처리를 지원하는 것과 같은 특정 로직기능이 적용된 것을 포함하는 부가적인 로직 회로 등이 될 수 있다. 이러한 회로층의 형태에 대한 선택은 회로설계의 기능적 요구가 뒤따르지만 3차원구조 메모리 제 조공정에 의해 제한되지는 않는다.
상기 씨닝된 유연한 기판 회로층들은 종래의 메모리 회로 제작시 일반적으로 사용되던 실리콘옥사이드 및 실리콘나이트라이드와 같은 높은 스트레스를 갖는 유전체와는 반대로 저스트레스의 실리콘다이옥사이드 및 실리콘나이트라이드 유전체와 같은 저스트레스(5 x 108 dynes/cm2 이하)의 유전체로 제작하는 것이 바람직하다. 이러한 저스트레스 유전체에 관하여는 인용에 의해 본 명세서에 통합되는 본 발명자의 미합중국 특허 제5,354,695호에서 논의되었다. 종래의 스트레스 레벨을 갖는 유전체가 3차원구조 DRAM 회로의 어셈블리에 사용될 수도 있지만, 만약 수개층 이상으로 적층된 어셈블리의 경우 어셈블리내의 각 층은 층의 증착막의 전체 스트레스가 5 x 108 dynes/cm2 이하가 되도록 스트레스의 균형이 이루어져야 한다. 본질적으로 낮은 스트레스의 증착막을 사용하는 것이, 개별적으로 증착된 막들의 스트레스가 동일하지 않지만 전체적으로 평가하여 낮은 스트레스를 갖도록 증착하는 방법보다는 바람직하다.
[ 방법 A, 3차원구조 메모리장치 제작 시퀀스 ]
이 제작 시퀀스는 수개의 회로층이 공통 또는 지지 기판에 접착되어지며 연속적으로 제자리에서 씨닝되는 것으로 가정한다. 제작된 3차원구조 메모리회로의 예가 도 1a에 나타난다.
1. 공통기판을 제2 회로기판의 상단측에 정렬하고 접착한다.
2A. 제2 회로기판의 이면 또는 노출면을 50 ㎛ 이하의 두께로 연마하고, 이 어서 표면을 폴리싱 또는 매끄럽게 한다. 여기서 씨닝된 기판은 유연한 기판이 된다.
선택적으로, 장치의 제작에 앞서 반도체기판 아래로 1 마이크론 이하에서 수 마이크론에 이르는 에치스톱(Etch stop)을 제2 기판내에 접착시킬 수도 있다. 이러한 에치스톱은 GeB(여기서 인용에 의해 통합되는 본 발명자의 미합중국 특허 제5,354,695호 및 제5,323,035호에서 설명됨)와 같은 에피택셜 형성막, 또는 상기 제2 기판의 상단측상의 상기 장치층의 바로 아래에 매몰 옥사이드 또는 나이트라이드 장벽 에치 스톱층을 형성하기 위한 산소 또는 질소의 저밀도 이온주입층이 될 수 있다. 상기 기판의 이면의 중요부분에 대한 초벌 연마를 한 후, 상기 제2 기판의 이면의 잔존하는 부분을 화학조에서 선택적으로 식각하며, 상기 에피택셜층 또는 이온주입층의 표면상에서 멈춘다. 필요하면 후속적으로 폴리싱 및 반응성 이온 식각(RIE) 단계가 제2 기판의 씨닝을 완료하기 위해 사용될 수도 있다.
다르게는, 장치 제작에 앞서 상기 제2 기판의 상단측 표면속으로 H2 등이 주입된 분리층이, 제2 기판의 이면의 대부분을 깨뜨려 재사용할 수 있도록 열공정 단계와 함께 사용될 수도 있다.
2B. 상기 제2 기판은, 택일적으로 특정한 화학적 방출제를 사용하여 활성화될 수 있는, 알루미늄, 티타늄, AlAs, KBr 등과 같은 분리층 위로 폴리실리콘 트랜지스터 또는 TFT가 형성된 회로가 될 수도 있다. 이어서, 제2 기판의 이면은 방출층을 활성화(용해)시켜 제거되며, 필요하면 상호연결 처리단계가 후속된다.
3. 제2 기판의 접착 표면측과 함께 도 4에서 보여지는 것과 같은 수직 상호 연결부를 형성하기 위해 제2 기판의 씨닝된 이면을 처리한다. 이면 처리는 전형적으로 유전체 및 금속 증착, 리소그라피 및 반응성 이온식각 등의 종래의 반도체 공정 단계들을 포함하며, 그 순서는 상당한 정도로 다양하게 할 수 있다. 이면 처리가 완료되면 부가적인 회로기판의 후속되는 접착을 촉진하기 위한 상단측 접착물질 패턴, 종래의 I/O 집적회로 접착패드(와이어 본딩) 패턴과 같은 최종 패턴, 3차원구조 메모리 회로를 다른 다이(다른 3차원구조 회로 또는 종래의 다이)에 열확산 접착하기 위한 패턴, 또는 삽입형 상호연결을 위한 패턴, 종래의 DCA(Direct Chip Attach) 또는 FCA(Flip-Chip Attach)를 위한 패턴과 유사한 금속 패턴층으로 된다.
보다 구체적으로 도 4를 참조하면, 액티브 회로장치를 제작하는 동안에 산화막 마스크(401)가 열적으로 성장 또는 증착된다. 이어서,수직 버스콘택(403)이, 예를 들어 폴리실리콘 게이트 형성단계와 일치하는 고농도 폴리실리콘으로부터 형성된다. 택일적으로, 콘택(403)은 금속으로 형성될 수도 있다. 이어서,종래의 DRAM 상호연결 구조(410)가 종래의 공정을 사용하여 형성된다. 상기 DRAM 상호연결부는 내부패드(405)를 포함할 수 있다. 웨이퍼의 DRAM 형성부(420)는 다양한 유전체 및 금속층을 포함한다. 비어(409)가 형성된 후 최종 패시베이션층(407)이 증착된다. 이어서 종래의 CMP 공정이 평탄면(411)을 얻기위해 사용되어진다. 이어서 콘택(413)과 도시되지 않은 접착표면이 최상의 금속층(예를 들어, 금속-3)에서 패턴되어진다.
약 1 내지 8 mm의 실리콘(또는 다른 반도체)기판(415)에 상기 제2 기판을 접착시키고 제2 기판의 이면을 씨닝한 후, 이어서 투입로(417)가 콘택(403)과 정합되 도록 형성된다. 다른 웨이퍼의 접착을 허용할 수 있도록 상기 콘택(403)과 거울상을 형성하는 콘택(421)이 형성될 수도 있다.
4. 만약 다른 회로층이 상기 3차원구조 회로 스택에 접착된다면, 단계 1 내지 3이 반복된다.
5A. 이어서 완료된 3차원구조 메모리 기판의 회로는 종래와 같이 절단되어 도 1a에서 보여지는 형태의 회로가 되는 다이(단독적으로 됨)가 되고, 종래의 집적회로의 경우와 같이 패키징된다.
5B. 이어서 완료된 3차원구조 메모리 기판의 회로들은 종래와 같이 절단되고, 이어서 전술한 단계 1의 회로기판의 접착시 사용된 것과 유사한 방식으로 제2 다이(종래의 집적회로) 또는 MCM 기판에 개별적으로 정렬 및 열확산 접합된다. (상기 종래의 다이 또는 MCM 기판은 상기 3차원구조 메모리 기판보다 큰 면적을 가질 수 있으며, 그래픽 제어기, 비디오 제어기 또는 마이크로프로세서를 포함함으로서 상기 3차원구조가 다른 회로의 일부로서 끼워질 수 있다.) 이러한 최종 접착단계는 전형적으로 상기 3차원구조 메모리 회로와 상기 다이 또는 MCM 기판과의 사이에 미립자 상호연결부를 결부시키지만, 또한 종래의 상호연결 패턴을 사용할 수도 있다. 더구나, 3차원구조 메모리 회로는 다이 형태의 종래의 집적회로 또는 MCM 기판에 면접하여 접착될 수 있으며, 종래의 I/O 상호연결을 형성하기 위해 와이어본딩이 사용될 수 있다.
[ 방법 B, 3차원구조 메모리장치 제작 시퀀스 ]
본 제작 시퀀스는 회로기판이 우선 전송기판에 접착되고, 씨닝되고 이어서 회로 스택의 한 층으로서 공통기판에 접착되는 것으로 가정한다. 이어서 상기 전송기판이 해체된다. 이 방법은 방법 A에 비하여, 최종 회로 스택에 접착되기에 앞서 기판을 씨닝할 수 있으며, 씨닝과 기판 회로층의 수직 상호연결 공정을 동시에 수행할 수 있다는 장점이 있다.
1. 해체층 또는 분리층을 사용하여 전송기판에 제2 회로기판을 접착시킨다. 상기 전송기판은 높은 공차를 갖는 평행면(TTV 또는 1㎛ 이하의 총두께 편차)을 가지며, 분리공정을 지원하기 위해 작은 홀들의 어레이로 관통될 수 있다. 상기 분리층은 접착물질의 전면증착층일 수 있다. 표면의 정확한 정렬은 요구되지 않는다.
2. 방법 A의 단계 2A 또는 2B를 수행한다.
3. 도 4에서 보여지는 바와 같이 제2 기판의 접착된 상단측 표면과 상호연결부를 형성하기 위해 제2 기판의 이면을 처리한다. 상기 이면 처리는 전형적으로 유전체 및 금속 증착, 리소그라피 및 RIE와 같은 종래의 반도체 공정 단계들을 포함하며, 그 순서는 상당히 다양하게 할 수 있다. 이면 처리가 완료되면, 부가적인 회로층의 후속 접착을 촉진하기 위해 공통 기판의 접착물질 패턴과 유사하게 패턴된 금속층으로 된다.
4. 제2 회로를 공통 또는 지지 기판(3차원구조 스택)에 접착시키고, 이것과 제2 회로 사이의 분리층을 활성화시켜 상기 전송기판을 해체한다.
5. 후속되는 기판 접착을 위한 상호연결부를 형성하기 위해 제2 기판의 노출된 상단측, 또는 종래의 I/O 집적회로 접착패드(와이어 본딩) 패턴과 같은 최종 패턴, 3차원구조 메모리 회로를 다른 다이(다른 3차원구조 회로 또는 종래의 다이)에 열확산 접착하기 위한 패턴, 또는 삽입형 상호연결, 종래의 DCA(Direct Chip Attach) 또는 FCA(Flip-Chip Attach)를 위한 패턴을 처리한다. 만약 다른 회로층을 상기 3차원구조 회로 스택에 접착시키려면 단계 1 내지 4를 반복한다.
6. 방법 A의 단계 5A 또는 5B를 수행한다.
[ 3차원구조 메모리장치 수율 증진방법들 ]
3차원구조 회로는 수직적으로 조립된 MCM(Multi-Chip Module)으로 생각할 수 있으며, MCM에서와 같이 최종 수율은 완성된 3차원구조 회로에서 각 구성회로(층)의 수율의 곱이 된다. 3차원구조 회로는 단일 메모리 집적회로를 접착하여 상승효과를 내는 수배의 수율 증진방법을 사용한다. 3차원구조 메모리 회로에서 사용된 수율 증진방법은 작아진 메모리 어레이 블록의 크기, 물리적으로 유일한 또는 독립된 수직 버스 상호연결부를 통한 메모리 어레이 블록의 전기적 분리, 내부 메모리 어레이 블록 게이트선의 여유분, 메모리 어레이층의 여유분(블록간 게이트선 여유분), 제어기 여유분 및 ECC(Error Correcting Codes)를 포함한다. 여유분이란 용어는 여분 요소에 의한 대체를 의미한다.
메모리 어레이 블록의 선택된 크기는 3차원구조 메모리 회로을 위한 수율 계산식에서 제1 요소이다. 각 메모리 어레이 블록은 제어기 회로에 의해 개별적으로(유일하게) 억세스되고 동력을 공급받으며, 동일한 메모리 어레이층 뿐만아니라 다른 메모리 어레이층의 것을 포함하는 모든 다른 메모리 어레이 블록과 각기 물리적으로 독립적이다. 메모리 어레이 블록의 크기는 전형적으로 5 mm2 이하이며, 바람직 하게는 3 mm2 이하지만, 특정 크기로 제한되지 않는다. 거의 모든 집적회로 제조공정에 대하여, 메모리 어레이 블록의 크기, NMOS 또는 PMOS 트랜지스터의 제조공정의 단순성, 다른 메모리 어레이 블록들로부터의 물리적 독립성은 줄잡아 99.5 % 이상의 정상수율을 제공한다. 이러한 수율은, 오픈 또는 쇼트된 상호연결부 또는 불량 메모리셀들과 같은 메모리 어레이 블록에서의 모든 점결함이 내부의 블록 또는 여분 게이트선의 내부 블록 세트로부터 대체되어 수리될 수 있다는 것을 가정한다. 완성된 메모리 어레이 블록을 사용할 수 없게 하는 메모리 어레이 블록내의 주요 결함은 여유분의 메모리 어레이층으로부터 상기 블록을 완전히 대체하도록 하게하거나 또는 3차원 회로의 불량을 초래한다.
3차원구조 DRAM 회로의 예에서, 메모리 어레이 블록의 스택의 수율은 수율계산식 Ys = (( 1- (1-Py)2)n)b으로부터 계산되며, 여기서 n은 DRAM 어레이층의 수이고, b는 DRAM 어레이당 블록의 수이며, Py는 면적이 3 mm2 이하의 DRAM 어레이 블록의 유효 수율(확률)을 나타낸다. DRAM 어레이 블록 라인들과 하나의 여유분 DRAM 어레이층에서 게이트선에 대하여 4 %의 DRAM 어레이 블록 여유분을 가정하며, 나아가 층당 블록수는 64이고, 스택당 메모리 어레이층의 수는 17이며, Py에 대한 유효값은 0.995으로 가정하면, 완성된 메모리 어레이(모든 메모리 어레이 블록 스택을 포함함)에 대한 스택 수율 Ys는 97,47 %가 된다.
이어서, 상기 메모리 어레이 스택 수율 Ys는 제어기의 수율 Yc로 곱하여진 다. 50 mm2 이하의 다이 크기를 가정하고, 0.5 ㎛ BiCMOS 또는 혼합신호 처리로부터 제작된 제어기에 대한 적절한 수율 Yc가 65 % 내지 85 % 사이라고 가정하면, 전체 3차원구조 메모리 회로 수율은 63.4 % 내지 82.8 %가 된다. 만약 여유분의 제어기 회로층이 상기 3차원구조 메모리 스택에 부가되면, 수율은 85.7 % 내지 95.2 %가 될 것이다.
메모리 어레이 블록의 유효 수율은 ECC 로직을 선택적으로 사용하면 더욱 증가될 것이다. ECC 로직은 일부 그룹의 데이터 비트의 크기에 대한 데이터 비트 에러를 정정해준다. ECC 로직의 동작을 위해 필요한 신드롬 비트들이 수직적으로 연관된 블록 스택에서 어떤 메모리 어레이층의 여유분 게이트선상에 저장될 것이다. 더구나, 필요하다면, ECC 신드롬 비트의 저장을 수용하기 위하여 부가적인 메모리 어레이층이 상기 회로에 부가될 수 있다.
[ 유리한 3차원구조 메모리소자 제어기 능력들 ]
종래의 메모리 회로와 비교하여 상기 3차원구조 제어기 회로는, 제어기 회로를 위해 유용한 부가적인 면적과 여러가지 혼합 신호처리 제작기술의 유용성에 기인한 여러 가지 유리한 능력들을 갖는다. 이러한 능력들의 일부가 동적인 게이트선 어드레스 배정을 갖는 메모리셀의 자기테스트, 가상 어드레스전환, 프로그램가능한 어드레스 윈도윙 또는 매핑, ECC, 데이터 압축 및 다중레벨 저장등이다.
동적 게이트선 어드레스 배정은 독출/기입 동작을 위한 층 및 게이트선을 가동하기 위하여 프로그래밍가능한 게이트의 사용을 의미한다. 이것은 저장된 메모리의 논리적 순서와 독립적이거나 또는 다른 메모리 저장의 물리적 순서를 허용한다.
각 세대의 메모리 장치를 테스트하는 것은 테스트 비용을 상당히 증가시켰다. 3차원구조 메모리 제어기는 다양한 메모리 어레이 블록들의 내부 테스트(자기 테스트)를 수행하기 위해 충분한 제어 로직을 접착시킴으로써 테스트 비용을 감소시킨다. 종래의 ATE방식의 회로 테스트는 단지 제어기 회로 기능의 확인을 위해서만 요구되어진다. 내부 테스트의 사상은 나아가 각 층상에서 각 메모리 어레이 블록의 여러 게이트선에 대응하여 유일한 어드레스들을 프로그램가능하게(동적으로) 배정하는 것으로 확장되었다. 3차원구조 제어기 회로의 자기테스트 능력은 3차원구조 메모리 회로가 제품에서 사용된 후 불량으로 된 게이트선의 어드레스를 재구성(대체)함으로써 회로의 신뢰성을 향상시키기 위한 수단 및 진단 기구로서 3차원구조 메모리 회로의 수명 동안에는 언제나 사용될 수 있다.
ECC는 제어기 회로에 포함된다면 프로그래밍 신호에 의해 가동되거나 또는 가동되지 않는, 또는 전용 기능을 수행하는 회로 능력이다.
데이터 압축 로직은 3차원구조 메모리 어레이에 저장될 수 있는 전체 데이터량을 증가시킬 수 있도록 해준다. 이런 목적을 위해 유용한 여러 가지 데이터 압축방법이 주지되어 있다.
레이져 센스 앰프는 보다 향상된 동적 성능과 메모리셀로부터 고속의 독출동작을 하게 해준다. 레이져 센스 앰프는 각 메모리셀에서 1비트 이상(다중 레벨 저장)의 정보를 저장하는 능력을 제공할 것으로 기대된다. 이러한 능력은 이미 플래시 EPROM과 같은 비휘발성 메모리 회로내에서 증명되어졌다. 다중레벨 저장은 또한 4기가비트 DRAM 세대의 회로에서 사용하기 위해 제안되었다.
본 발명은 그 정신 또는 본질적 특징으로부터 벗어남이 없이 다른 특정한 형태들로 실시될 수 있다는 것은 당업자라면 인식할 수 있을 것이다. 따라서 여기에 개시된 실시예들은 모든 점에서 예시적인 것이며, 제한적인 것으로 생각해서는 안된다. 본 발명의 범위는 전술한 설명보다도 첨부한 클레임들에 의해 표현되며, 그의 균등물 및 그 범위내에 속하는 모든 변화는 그 범위내에 포함된다.
본 명세서에서는 예로서 DRAM형 회로가 자주 사용되었지만, 본 발명은 DRAM형 회로에 한정되는 것이 아니라는 것은 명백하다. 의심할 것도 없이 EEPROM(Electrically Erasable Programmable Read Only Memories), 플레시 EPROM, 강유전체, GMR(Giant Magneto Resistance) 또는 이러한 메모리셀들의 상호적 또는 내부적 조합물 등과 같은 메모리셀 형태들에 대하여도 3차원구조 메모리소자를 형성하기 위해 본 발명의 3차원 구조(3DS) 방법을 사용할 수 있다.

Claims (93)

  1. 제1 기판상에 메모리 회로를 제작하는 단계;
    제2 기판상에 메모리 제어기 회로를 제작하는 단계; 및
    상기 메모리 회로와 메모리 제어기 회로 사이의 상호연결부들을 형성하기 위해 각자 단독으로는 랜덤 억세스 데이터 저장을 하기에는 충분하지 않는 상기 제1 기판 및 제2 기판을 접착하는 단계를 구비하며, 상기 접착하는 단계는 상기 제2 기판에 대한 제1 기판의 열확산 접착이며, 상기 기판중의 하나의 이면이 씨닝되고, 이어서 상기 기판을 관통하는 상호연결부들을 형성하며 상기 기판의 이면상에서 콘택을 형성할 수 있도록 공정처리되는 것을 특징으로 하는 랜덤 억세스 메모리 형성방법.
  2. 제 1항에 있어서, 상기 접착 단계는 적층된 집적회로 구조체를 형성하기 위하여 상기 제2 기판에 상기 제1 기판을 열확산 접착하는 것을 특징으로 하는 랜덤 억세스 메모리 형성방법.
  3. 제 2항에 있어서, 상기 상호연결부들의 적어도 일부는 100 마이크론 이하의 피치를 갖는 미립자의 수직적 상호연결부임을 특징으로 하는 랜덤 억세스 메모리 형성방법.
  4. 제 3항에 있어서, 상기 적층된 집적회로 구조체와 추가의 기판을 추가로 접착하는 단계를 구비하는 것을 특징으로 하는 랜덤 억세스 메모리 형성방법.
  5. 제 4항에 있어서, 상기 추가의 기판을 추가로 접착하는 단계는 상기 적층된 집적회로 구조와 상기 추가의 기판을 서로 열확산 접착하는 것임을 특징으로 하는 랜덤 억세스 메모리 형성방법.
  6. 제 5항에 있어서, 상기 열확산 접착은 100 마이크론 이하의 콘택 피치를 갖는 미립자 콘택 패턴들을 사용하는 것을 특징으로 하는 랜덤 억세스 메모리 형성방법.
  7. 제 6항에 있어서, 상기 미립자 콘택 패턴들은 상기 미립자의 수직적 상호연결부들의 연장부를 형성하는 것을 특징으로 하는 랜덤 억세스 메모리 형성방법.
  8. 제 1항에 있어서, 상기 적층된 집적회로 구조체와 추가의 기판을 추가로 접착하는 단계를 구비하는 것을 특징으로 하는 랜덤 억세스 메모리 형성방법.
  9. 제 8항에 있어서, 상기 추가의 기판을 추가로 접착하는 단계는 단독의 적층된 집적회로 구조체와 상기 추가의 기판을 와이어 접착하는 것임을 특징으로 하는 랜덤 억세스 메모리 형성방법.
  10. 제 1항에 있어서, 상기 상호연결부들의 적어도 일부는 평탄공정에 의해 형성되는 것을 특징으로 하는 랜덤 억세스 메모리 형성방법.
  11. 제 8항에 있어서, 상기 추가의 기판을 추가로 접착하는 단계는, 단독의 적층된 집적회로 구조체와 상기 더욱 적층된 집적회로 또는 종래의 집적회로와의 미립자의 수직적 상호연결 콘택 패턴의 열확산 금속접착인 것을 특징으로 하는 랜덤 억세스 메모리 형성방법.
  12. 제 8항에 있어서, 상기 추가의 기판을 추가로 접착하는 단계는, 단독의 적층된 집적회로 구조체와 상기 더욱 적층된 집적회로 또는 종래의 집적회로와의 상호연결 콘택 패턴의 열확산 금속접착인 것을 특징으로 하는 랜덤 억세스 메모리 형성방법.
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  14. 제 1항에 있어서, 상기 접착은 적층된 집적회로 구조체를 형성하기 위한 상기 제2 기판에 대한 제1 기판의 열확산 접착이며, 상기 방법은,
    적어도 하나의 부가적인 기판상에 적어도 하나의 부가적인 메모리 회로를 제작하는 단계; 및
    상기 적층된 집적회로 기판에 적어도 하나의 부가적인 기판을 접착하여 상기 적어도 하나의 부가적인 메모리 회로와 상기 메모리 제어기 회로 사이를 상호연결하며, 상기 상호연결부들의 적어도 일부가 메모리 회로가 형성된 기판을 관통하도록 하는 접착 단계를 더 구비하는 것을 특징으로 하는 랜덤 억세스 메모리 형성방법.
  15. 제 14항에 있어서, 상기 상호연결부들의 형성을 촉진하기 위해, 메모리 회로들이 형성된 기판을 씨닝된 기판이 되도록 씨닝하는 단계를 더 구비하는 것을 특징으로 하는 랜덤 억세스 메모리 형성방법.
  16. 제 15항에 있어서, 상기 상호연결부들의 적어도 일부는 100 마이크론 이하의 피치를 갖는 미립자의 수직적 상호연결부인 것을 특징으로 하는 랜덤 억세스 메모리 형성방법.
  17. 제 15항에 있어서, 상기 씨닝된 기판은 두께가 50 ㎛ 이하가 되도록 씨닝되는 것을 특징으로 하는 랜덤 억세스 메모리 형성방법.
  18. 제 15항에 있어서, 상기 씨닝된 기판의 반도체 부분은 1 내지 8 마이크론 범위의 두께로 씨닝되는 것을 특징으로 하는 랜덤 억세스 메모리 형성방법.
  19. 제 15항에 있어서, 상기 씨닝단계는 상기 기판들을 그라인딩하는 것을 포함하는 것을 특징으로 하는 랜덤 억세스 메모리 형성방법.
  20. 제 19항에 있어서, 상기 기판들은 접착되어진 후 그라인딩되는 것을 특징으로 하는 랜덤 억세스 메모리 형성방법.
  21. 제 19항에 있어서, 상기 기판들은 접착되어지기 전에 그라인딩되는 것을 특징으로 하는 랜덤 억세스 메모리 형성방법.
  22. 제 14항에 있어서, 적어도 하나의 상기 메모리 회로가 재사용가능한 기판상에 형성되며, 상기 메모리 회로가 형성된 층을 상기 재사용가능한 기판으로부터 분리하는 단계를 더 구비하는 것을 특징으로 하는 랜덤 억세스 메모리 형성방법.
  23. 제 22항에 있어서, 적어도 하나의 상기 메모리 회로가 폴리실리콘 트랜지스터로 형성된 것임을 특징으로 하는 랜덤 억세스 메모리 형성방법.
  24. 제 14항에 있어서, 상기 접착 단계는 열확산 접착을 포함하는 것을 특징으로 하는 랜덤 억세스 메모리 형성방법.
  25. 제 24항에 있어서, 짝을 이루는 콘택 패턴들이 함께 접착되어지는 각 표면상 에 형성되는 것을 특징으로 하는 랜덤 억세스 메모리 형성방법.
  26. 제 25항에 있어서, 짝을 이루는 콘택 패턴들은 주로 금속으로 형성되는 것을 특징으로 하는 랜덤 억세스 메모리 형성방법.
  27. 제 26항에 있어서, 상기 금속은 Al, Sn, Ti, In, Pb, Zn, Ni, Cu, Pt 및 Au, 및 이들의 합금으로 이루어진 그룹으로부터 선택된 금속을 포함하는 것을 특징으로 하는 랜덤 억세스 메모리 형성방법.
  28. 제 14항에 있어서, 상기 메모리 회로 및 메모리 제어기 회로는 반도체 회로이며, 상기 메모리 제어기 회로는 제1 반도체 공정기술을 사용하여 제작되며, 상기 메모리 회로는 다른 구별되는 제2 반도체 공정기술을 사용하여 제작되는 것을 특징으로 하는 랜덤 억세스 메모리 형성방법.
  29. 제 28항에 있어서, 상기 제1 반도체 공정기술은 제1 형태 및 제2 상보 형태의 액티브 반도체소자를 채용하는 것을 특징으로 하는 랜덤 억세스 메모리 형성방법.
  30. 제 28항에 있어서, 상기 제2 반도체 공정기술에 따라 형성된 반도체소자는 모두 단일 형태의 모스(MOS) 반도체소자를 포함하는 것을 특징으로 하는 랜덤 억세 스 메모리 형성방법.
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  38. 메모리 회로 및 메모리 제어기 회로 중의 하나가 그 위에 형성된 강체인 제1 기판; 및
    상기 제1 기판에 접착되어 있으며, 상기 메모리 회로 및 메모리 제어기 회로 중의 나머지 것이 그 위에 형성된 적어도 하나의 유연한 기판;을 구비하는 것을 특징으로 하는 적층된 집적회로 메모리.
  39. 제 38항에 있어서, 상기 제1 기판은 그 위에 상기 메모리 회로가 형성되어 있으며 적층된 메모리 회로 기판들의 일부이며, 상기 제2 기판은 그 위에 메모리 제어기 회로가 형성된 것임을 특징으로 하는 적층된 집적회로 메모리.
  40. 제 39항에 있어서, 상기 제1 및 제2 기판들은 단독의 다이를 이루며, 상기 제2 기판이 상기 제1 기판보다 큰 면적을 갖는 것을 특징으로 하는 적층된 집적회로 메모리.
  41. 제 40항에 있어서, 상기 제2 기판은 그 위에 상기 메모리 제어기 회로와 분리된 부가 회로가 형성된 것을 특징으로 하는 적층된 집적회로 메모리.
  42. 제 41항에 있어서, 상기 부가 회로는 그래픽 디스플레이 서브시스템의 일부인 것을 특징으로 하는 적층된 집적회로 메모리.
  43. 제 41항에 있어서, 상기 부가 회로는 마이크로 프로세서를 포함하는 것을 특징으로 하는 적층된 집적회로 메모리.
  44. 제 38항에 있어서, 상기 유연한 기판은 메모리 I/O 패드를 포함하는 것을 특징으로 하는 적층된 집적회로 메모리.
  45. 제 44항에 있어서, 상기 메모리 회로는 상기 제1 기판과 접착되는 상기 유연 한 기판의 상부 표면 근처에 형성되며, 상기 메모리 I/O 패드는 상기 유연한 기판의 반대쪽 저부 표면 근처에 형성된 것을 특징으로 하는 적층된 집적회로 메모리.
  46. 제 38항에 있어서, 상기 메모리 회로 및 메모리 제어기 회로는 수직적 상호연결부에 의해 연결되는 것을 특징으로 하는 적층된 집적회로 메모리.
  47. 제 46항에 있어서, 상기 수직적 상호연결부는 100 마이크론 이하의 피치에서 형성된 미립자의 수직적 상호연결부를 포함하는 것을 특징으로 하는 적층된 집적회로 메모리.
  48. 제 47항에 있어서, 상기 미립자의 수직적 상호연결부들의 적어도 일부는 2차원으로 어레이된 것을 특징으로 하는 적층된 집적회로 메모리.
  49. 제 47항에 있어서, 상기 메모리 회로는 2차원 어레이의 메모리 블록을 포함하며, 상기 각 메모리 블록은 상기 메모리 제어기에 상기 메모리 블록을 연결하는 제1 포트를 형성하는 미립자의 수직적 상호연결부의 어레이 근처에 형성되는 것을 특징으로 하는 적층된 집적회로 메모리.
  50. 제 49항에 있어서, 상기 메모리 블록의 적어도 일부는 상기 메모리 제어기에 상기 메모리 블록을 연결하는 제2 포트를 형성하는 미립자의 수직적 상호연결부의 어레이 근처에 형성되는 것을 특징으로 하는 적층된 집적회로 메모리.
  51. 제 38항에 있어서, 상기 메모리 회로의 적어도 하나는 여분의 메모리 위치를 제공하는 것을 특징으로 하는 적층된 집적회로 메모리.
  52. 제 51항에 있어서, 여분의 메모리 회로가 형성된 유연한 부가 기판을 더 포함하는 것을 특징으로 하는 적층된 집적회로 메모리.
  53. 제 52항에 있어서, 상기 메모리 제어기 회로는 ECC 로직을 포함하며, 상기 여분 메모리 회로내에서 ECC 신드롬을 저장하도록 프로그래밍된 것을 특징으로 하는 적층된 집적회로 메모리.
  54. 제 51항에 있어서, 상기 메모리 제어기 회로는 상기 메모리 회로를 테스트하기 위한 로직을 포함하는 것을 특징으로 하는 적층된 집적회로 메모리.
  55. 제 54항에 있어서, 상기 메모리 제어기 회로는 메모리 회로에서 결함적인 메모리 위치에 대하여 여분의 메모리 위치를 대체하도록 프로그래밍된 것을 특징으로 하는 적층된 집적회로 메모리.
  56. 제 38항에 있어서, 상기 메모리 제어기 회로는, 가상 메모리 관리, 간접 어 드레싱, 내용 어드레싱, 데이터 압축, 데이터 압축해제, 그래픽 가속, 오디오 인코딩, 오디오 디코딩, 비디오 인코딩, 비디오 디코딩, 음성인식, 필적인식, 전력관리 및 데이터베이스 처리 기능들 중의 적어도 하나를 수행하기 위한 로직을 포함하는것을 특징으로 하는 적층된 집적회로 메모리.
  57. 제 38항에 있어서, 상기 유연한 기판에 접착되며, 그 위에 여분의 메모리 제어기가 형성된 제2 기판을 더 포함하는 것을 특징으로 하는 적층된 집적회로 메모리.
  58. 제 38항에 있어서, 상기 유연한 기판에 접착되며, 그 위에 마이크로 프로세서가 형성된 제2 기판을 더 포함하는 것을 특징으로 하는 적층된 집적회로 메모리.
  59. 제 38항에 있어서, 상기 메모리 제어기회로는 상기 메모리 회로의 데이터선에 연결된 센스 증폭기를 포함하는 것을 특징으로 하는 적층된 집적회로 메모리.
  60. 제 59항에 있어서, 상기 센스 증폭기는 둘 이상의 신호레벨들을 식별하며, 각 센스 증폭기는 다중레벨 출력신호를 산출하는 것을 특징으로 하는 적층된 집적회로 메모리.
  61. 제 59항에 있어서, 상기 센스 증폭기는 10 ns 이하의 절환속도를 나타낼 수 있는 크기인 것을 특징으로 하는 적층된 집적회로 메모리.
  62. 집적회로들 사이에서 상호연결부를 형성하기 위해 각기 그 위에 집적회로가 형성된 다중 기판들을 함께 접착하는 방법에 있어서,
    제1 및 제2 각 기판상의 서로 짝을 이루는 표면을 처리하여 상기 짝을 이루는 각 표면의 기본적 평탄도를 얻도록 하는 단계;
    상기 짝을 이루는 표면상에 짝을 이루는 미립자의 상호연결 패턴을 형성하는 단계;
    상기 짝을 이루는 표면의 미립자, 플래나 열확산 접착을 수행하는 단계; 및
    상기 상호연결부의 형성을 촉진시키기 위해 상기 집적회로가 형성된 상기 기판의 적어도 하나를 씨닝된 기판이 되도록 씨닝하고, 상기 씨닝된 기판의 이면처리를 수행하는 단계;를 구비하는 것을 특징으로 하는 접착방법.
  63. 제 62항에 있어서, 상기 제2 기판에 대한 제1 기판의 열확산 접착은 적층된 집적회로 구조체를 형성하는 것을 특징으로 하는 접착방법.
  64. 제 63항에 있어서, 상기 상호연결부의 적어도 일부는 100 마이크론 이하의 피치를 갖는 미립자의 수직적 상호연결부인 것임을 특징으로 하는 접착방법.
  65. 제 64항에 있어서, 상기 적층된 집적회로 구조체와 추가의 기판을 추가로 접 착하는 단계를 포함하는 것을 특징으로 하는 접착방법.
  66. 제 65항에 있어서, 상기 적층된 집적회로 구조체와 상기 추가의 기판을 서로 접착하는 것은 열확산 접착인 것임을 특징으로 하는 접착방법.
  67. 제 66항에 있어서, 상기 열확산 접착은 100 마이크론 이하의 콘택 피치를 갖는 미립자의 콘택 패턴을 사용하는 것을 특징으로 하는 접착방법.
  68. 제 67항에 있어서, 상기 미립자 콘택 패턴은 상기 미립자 수직 상호연결부의 연장부를 형성하는 것을 특징으로 하는 접착방법.
  69. 제 62항에 있어서, 상기 적층된 집적회로 구조체와 추가의 기판을 접착하는 단계를 더 구비하는 것을 특징으로 하는 접착방법.
  70. 제 69항에 있어서, 상기 접착단계는 단독의 적층된 집적회로 구조체와 상기 추가의 기판을 와이어 접착하는 것임을 특징으로 하는 접착방법.
  71. 제 62항에 있어서, 상기 상호연결부의 적어도 일부는 평탄공정에 의해 형성되는 것임을 특징으로 하는 접착방법.
  72. 제 69항에 있어서, 상기 추가의 접착단계는 단독의 적층된 집적회로 구조체와 상기 추가로 적층된 집적회로 또는 통상의 집적회로의 미립자 수직 상호연결 콘택 패턴의 열확산 금속접착인 것임을 특징으로 하는 접착방법.
  73. 제 69항에 있어서, 상기 추가의 접착단계는 단독의 적층된 집적회로 구조체와 상기 추가의 적층된 집적회로 또는 종래의 집적회로의 상호연결 콘택 패턴의 열확산 금속접착인 것임을 특징으로 하는 접착방법.
  74. 삭제
  75. 제 62항에 있어서, 상기 상호연결부들의 형성을 촉진시키기 위해 상기 집적회로가 형성된 상기 기판을 씨닝된 기판이 되도록 씨닝하는 단계를 더 구비하는 것을 특징으로 하는 접착방법.
  76. 제 75항에 있어서, 상기 상호연결부들의 적어도 일부는 100 마이크론 이하의 피치를 갖는 미립자 수직 상호연결부인 것임을 특징으로 하는 접착방법.
  77. 제 75항에 있어서, 상기 씨닝된 기판은 두께가 50 ㎛ 이하로 씨닝되는 것을 특징으로 하는 접착방법.
  78. 제 75항에 있어서, 상기 씨닝된 기판의 반도체부분은 약 1 내지 8 마이크론 범위의 두께로 씨닝되는 것을 특징으로 하는 접착방법.
  79. 제 75항에 있어서, 상기 씨닝단계는 상기 기판들을 그라인딩하는 단계를 포함하는 것을 특징으로 하는 접착방법.
  80. 제 79항에 있어서, 상기 기판들은 접착된 후 그라인딩되는 것을 특징으로 하는 접착방법.
  81. 제 79항에 있어서, 상기 기판들은 접착하기 전에 그라인딩되는 것을 특징으로 하는 접착방법.
  82. 제 72항에 있어서, 상기 적어도 하나의 집적회로는 재사용가능한 기판상에 형성되며, 상기 집적회로가 형성된 층을 상기 재사용가능한 기판으로부터 분리하는 단계를 더 구비하는 것을 특징으로 하는 접착방법.
  83. 제 82항에 있어서, 상기 적어도 하나의 집적회로는 폴리실리콘 트랜지스터로 형성된 것임을 특징으로 하는 접착방법.
  84. 삭제
  85. 제 72항에 있어서, 짝을 이루는 콘택 패턴들이 함께 접착되는 각 표면상에 형성된 것을 특징으로 하는 접착방법.
  86. 제 85항에 있어서, 상기 짝을 이루는 콘택 패턴들은 주로 금속으로 형성된 것을 특징으로 하는 접착방법.
  87. 제 86항에 있어서, 상기 금속은 Al, Sn, Ti, In, Pb, Zn, Ni, Cu, Pt, Au 및 이들의 합금으로 이루어진 그룹으로부터 선택된 금속을 포함하는 것을 특징으로 하는 접착방법.
  88. 제 1항에 있어서, 상기 메모리 제어기 회로 내에 센스 증폭기를 결합시키는 단계 및 상기 센스 증폭기를 상기 메모리회로의 데이터선에 연결하는 단계를 더 포함하는 것을 특징으로 하는 방법.
  89. 제 88항에 있어서, 둘 이상의 신호 레벨들을 식별하기 위해 상기 센스 증폭기를 사용하는 단계 및 상기 각 센스 증폭기로부터 다중 레벨의 출력신호를 산출하는 단계를 더 포함하는 것을 특징으로 하는 방법.
  90. 제 1항에 있어서, 상기 메모리 제어기회로는 반도체 공정기술을 사용하여 제작되며, 상기 메모리 회로는 서로 다른 공정기술을 사용하여 형성되는 것을 특징으로 하는 방법.
  91. 제 90항에 있어서, 상기 다른 공정기술은 디램(DRAM), 에스램(SRAM), 플레시 이피롬(FLASH EPROM), 이이피롬(EEEPROM), 강유전체(Ferroelectric) 및 지엠알 (Giant Magnet Resistance;GMR)로 이루어진 그룹으로부터 선택된 것임을 특징으로 하는 방법.
  92. 제 1항에 있어서, 상기 열확산 접착에 의해 접착된 표면들은 상호연결된 금속배선과 상호연결되지 않은 금속배선을 포함하여,
    그에 따라 상기 열확산 접착은 상기 상호연결된 금속배선을 통하여 전기적 상호연결이 이루어지며, 동시에 상기 상호연결되지 않은 금속배선을 통하여 기계적 접착이 이루어지는 것을 특징으로 하는 방법.
  93. 제 62항에 있어서, 상기 열확산 접착에 의해 접착된 표면들은 상호연결된 금속배선과 상호연결되지 않은 금속배선을 포함하여,
    그에 따라 상기 열확산 접착은 상기 상호연결된 금속배선을 통하여 전기적 상호연결이 이루어지며, 동시에 상기 상호연결되지 않은 금속배선을 통하여 기계적 접착이 이루어지는 것을 특징으로 하는 방법.
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US5915167A (en) 1999-06-22
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