IT1274925B - Architettura di memoria per dischi a stato solido - Google Patents

Architettura di memoria per dischi a stato solido

Info

Publication number
IT1274925B
IT1274925B ITRM940602A ITRM940602A IT1274925B IT 1274925 B IT1274925 B IT 1274925B IT RM940602 A ITRM940602 A IT RM940602A IT RM940602 A ITRM940602 A IT RM940602A IT 1274925 B IT1274925 B IT 1274925B
Authority
IT
Italy
Prior art keywords
block
data
memory
addresses
transcoding
Prior art date
Application number
ITRM940602A
Other languages
English (en)
Inventor
Zenzo Maurizio Di
Rodolfo Grimani
Original Assignee
Texas Instruments Italia Spa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Italia Spa filed Critical Texas Instruments Italia Spa
Priority to ITRM940602A priority Critical patent/IT1274925B/it
Publication of ITRM940602A0 publication Critical patent/ITRM940602A0/it
Priority to EP95830379A priority patent/EP0704801B1/en
Priority to DE1995629135 priority patent/DE69529135T2/de
Priority to JP7243403A priority patent/JPH08203294A/ja
Priority to US08/531,984 priority patent/US5745673A/en
Publication of ITRM940602A1 publication Critical patent/ITRM940602A1/it
Application granted granted Critical
Publication of IT1274925B publication Critical patent/IT1274925B/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/76—Masking faults in memories by using spares or by reconfiguring using address translation or modifications
    • G11C29/765—Masking faults in memories by using spares or by reconfiguring using address translation or modifications in solid state disks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
    • G11B20/1833—Error detection or correction; Testing, e.g. of drop-outs by adding special lists or symbols to the coded information

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Dram (AREA)

Abstract

Memoria per disco a stato solido (SSD), comprendente i seguenti blocchi funzionali: un blocco di memoria (DATA ARRAY) in cui sono scritti i bytes di dati di verifica; un blocco di memoria di transcodifica (SCRAMBLE RAM) contenente la tabella che permette la riallocazione degli indirizzi della matrice dati, contenente righe ridondanti; un blocco (SCRAM DEC) per la decodifica degli indirizzi della tabella di decodificazione; un blocco logico (FUSE LOGIC) che permette l'operazione di individuazione delle righe non utilizzabili e la loro sostituzione con le dette righe ridondanti; un blocco di codice di correzione di errore (ECC) che implementa l'algoritmo di correzione degli errori; un blocco di buffer di ingresso (LOGICAL ROW ADDRESS BUFFER) che immagazzina l'indirizzo di riga proveniente dal bus esterno: un blocco di memoria non volatile (FAIL MAP), programmata durante il collaudo e disponibile ad un eventuale processore per la gestione del contenuto della memoria di transcodifica (SCRAMBLE RAM); un blocco contatore di parole (WORD COUNTER) che, pilotato dal segnale di cadenzamento (clock) esterno, conta il numero di parole che sono state indirizzate e genera gli indirizzi delle parole; due blocchi di buffer di ingresso e di uscita (DATA IN/OUT) per i dati in scrittura ed in lettura; un blocco di multiplexer (MUX) che pilota il flusso dei dati o alla memoria dei dati (DATI ARRAY) o alla memoria di transcodifica (SCRAMBLE RAM).
ITRM940602A 1994-09-21 1994-09-21 Architettura di memoria per dischi a stato solido IT1274925B (it)

Priority Applications (5)

Application Number Priority Date Filing Date Title
ITRM940602A IT1274925B (it) 1994-09-21 1994-09-21 Architettura di memoria per dischi a stato solido
EP95830379A EP0704801B1 (en) 1994-09-21 1995-09-15 Memory architecture for solid state disc
DE1995629135 DE69529135T2 (de) 1994-09-21 1995-09-15 Speicherarchitektur für Halbleiterfestplatten
JP7243403A JPH08203294A (ja) 1994-09-21 1995-09-21 メモリ
US08/531,984 US5745673A (en) 1994-09-21 1995-09-21 Memory architecture for solid state discs

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
ITRM940602A IT1274925B (it) 1994-09-21 1994-09-21 Architettura di memoria per dischi a stato solido
US08/531,984 US5745673A (en) 1994-09-21 1995-09-21 Memory architecture for solid state discs

Publications (3)

Publication Number Publication Date
ITRM940602A0 ITRM940602A0 (it) 1994-09-21
ITRM940602A1 ITRM940602A1 (it) 1996-03-21
IT1274925B true IT1274925B (it) 1997-07-29

Family

ID=26332068

Family Applications (1)

Application Number Title Priority Date Filing Date
ITRM940602A IT1274925B (it) 1994-09-21 1994-09-21 Architettura di memoria per dischi a stato solido

Country Status (4)

Country Link
US (1) US5745673A (it)
EP (1) EP0704801B1 (it)
JP (1) JPH08203294A (it)
IT (1) IT1274925B (it)

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US5354695A (en) * 1992-04-08 1994-10-11 Leedy Glenn J Membrane dielectric isolation IC fabrication
US6714625B1 (en) * 1992-04-08 2004-03-30 Elm Technology Corporation Lithography device for semiconductor circuit pattern generation
US6009536A (en) * 1996-09-20 1999-12-28 Micron Electronics, Inc. Method for using fuse identification codes for masking bad bits on memory modules
US6551857B2 (en) 1997-04-04 2003-04-22 Elm Technology Corporation Three dimensional structure integrated circuits
US5915167A (en) * 1997-04-04 1999-06-22 Elm Technology Corporation Three dimensional structure memory
US6314527B1 (en) 1998-03-05 2001-11-06 Micron Technology, Inc. Recovery of useful areas of partially defective synchronous memory components
US6332183B1 (en) 1998-03-05 2001-12-18 Micron Technology, Inc. Method for recovery of useful areas of partially defective synchronous memory components
US6381707B1 (en) 1998-04-28 2002-04-30 Micron Technology, Inc. System for decoding addresses for a defective memory array
US6381708B1 (en) 1998-04-28 2002-04-30 Micron Technology, Inc. Method for decoding addresses for a defective memory array
US6496876B1 (en) 1998-12-21 2002-12-17 Micron Technology, Inc. System and method for storing a tag to identify a functional storage location in a memory device
US6578157B1 (en) 2000-03-06 2003-06-10 Micron Technology, Inc. Method and apparatus for recovery of useful areas of partially defective direct rambus rimm components
US7269765B1 (en) 2000-04-13 2007-09-11 Micron Technology, Inc. Method and apparatus for storing failing part locations in a module
DE10109558C1 (de) * 2001-02-28 2003-01-30 Siemens Ag Empfängerseitige Zusatzschaltung für den Boundary Scan bei der Datenübertragung mit differentiellen Signalen
US7036068B2 (en) 2001-07-25 2006-04-25 Hewlett-Packard Development Company, L.P. Error correction coding and decoding in a solid-state storage device
US20030023922A1 (en) * 2001-07-25 2003-01-30 Davis James A. Fault tolerant magnetoresistive solid-state storage device
US6981196B2 (en) 2001-07-25 2005-12-27 Hewlett-Packard Development Company, L.P. Data storage method for use in a magnetoresistive solid-state storage device
US6973604B2 (en) 2002-03-08 2005-12-06 Hewlett-Packard Development Company, L.P. Allocation of sparing resources in a magnetoresistive solid-state storage device
AU2003255254A1 (en) * 2002-08-08 2004-02-25 Glenn J. Leedy Vertical system integration
US7761773B2 (en) * 2005-06-30 2010-07-20 Sigmatel, Inc. Semiconductor device including a unique identifier and error correction code
WO2008070798A1 (en) 2006-12-06 2008-06-12 Fusion Multisystems, Inc. (Dba Fusion-Io) Apparatus, system, and method for managing commands of solid-state storage using bank interleave
CN101067972B (zh) * 2007-04-23 2012-04-25 北京兆易创新科技有限公司 一种存储器检错纠错编码电路及利用其读写数据的方法
US7836226B2 (en) 2007-12-06 2010-11-16 Fusion-Io, Inc. Apparatus, system, and method for coordinating storage requests in a multi-processor/multi-thread environment
US8423837B2 (en) * 2009-02-13 2013-04-16 Texas Instruments Incorporated High reliability and low power redundancy for memory
EP2366148B1 (en) 2009-04-21 2013-06-12 International Business Machines Corporation Apparatus and method for controlling a solid state disk ( ssd ) device
TWI464581B (zh) * 2011-02-21 2014-12-11 Etron Technology Inc 非揮發性記憶體模組、非揮發性記憶體處理系統、與相關非揮發性記憶體管理方法
JP6018508B2 (ja) * 2013-01-09 2016-11-02 エスアイアイ・セミコンダクタ株式会社 不揮発性半導体記憶装置及びそのテスト方法
US9934151B2 (en) 2016-06-28 2018-04-03 Dell Products, Lp System and method for dynamic optimization for burst and sustained performance in solid state drives
CN107454072B (zh) * 2017-07-28 2020-04-17 中国人民解放军信息工程大学 一种多路数据内容的对比方法及装置
US11074189B2 (en) 2019-06-20 2021-07-27 International Business Machines Corporation FlatFlash system for byte granularity accessibility of memory in a unified memory-storage hierarchy

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DE3032630C2 (de) * 1980-08-29 1983-12-22 Siemens AG, 1000 Berlin und 8000 München Halbleiterspeicher aus Speicherbausteinen mit redundanten Speicherbereichen und Verfahren zu dessen Betrieb
JPS6134793A (ja) * 1984-07-27 1986-02-19 Hitachi Ltd ダイナミツクメモリ装置における診断及びエラ−訂正装置
JP2530610B2 (ja) * 1986-02-27 1996-09-04 富士通株式会社 半導体記憶装置
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EP0505652B1 (en) * 1991-03-29 1996-03-13 International Business Machines Corporation Memory system with adaptable redundancy
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Also Published As

Publication number Publication date
EP0704801A3 (en) 1999-03-10
ITRM940602A0 (it) 1994-09-21
JPH08203294A (ja) 1996-08-09
EP0704801A2 (en) 1996-04-03
ITRM940602A1 (it) 1996-03-21
EP0704801B1 (en) 2002-12-11
US5745673A (en) 1998-04-28

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