ATE477537T1 - Prädiktive generierung von fehlerkorrekturkodes für hochgeschwindigkeits-byte-schreiben in einem halbleiterspeicher - Google Patents

Prädiktive generierung von fehlerkorrekturkodes für hochgeschwindigkeits-byte-schreiben in einem halbleiterspeicher

Info

Publication number
ATE477537T1
ATE477537T1 AT05823321T AT05823321T ATE477537T1 AT E477537 T1 ATE477537 T1 AT E477537T1 AT 05823321 T AT05823321 T AT 05823321T AT 05823321 T AT05823321 T AT 05823321T AT E477537 T1 ATE477537 T1 AT E477537T1
Authority
AT
Austria
Prior art keywords
data word
write
check bits
read
merged
Prior art date
Application number
AT05823321T
Other languages
English (en)
Inventor
Wingyu Leung
Kit Tam
Original Assignee
Mosys Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mosys Inc filed Critical Mosys Inc
Application granted granted Critical
Publication of ATE477537T1 publication Critical patent/ATE477537T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • G06F11/1056—Updating check bits on partial write, i.e. read/modify/write
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4078—Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Detection And Correction Of Errors (AREA)
  • Dram (AREA)
AT05823321T 2004-11-23 2005-11-03 Prädiktive generierung von fehlerkorrekturkodes für hochgeschwindigkeits-byte-schreiben in einem halbleiterspeicher ATE477537T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/997,604 US7392456B2 (en) 2004-11-23 2004-11-23 Predictive error correction code generation facilitating high-speed byte-write in a semiconductor memory
PCT/US2005/040086 WO2006057793A2 (en) 2004-11-23 2005-11-03 Predictive error correction code generation facilitating high-speed byte-write in a semiconductor memory

Publications (1)

Publication Number Publication Date
ATE477537T1 true ATE477537T1 (de) 2010-08-15

Family

ID=36462279

Family Applications (2)

Application Number Title Priority Date Filing Date
AT05823321T ATE477537T1 (de) 2004-11-23 2005-11-03 Prädiktive generierung von fehlerkorrekturkodes für hochgeschwindigkeits-byte-schreiben in einem halbleiterspeicher
AT05823326T ATE511139T1 (de) 2004-11-23 2005-11-03 Teilwortschreibung unterstützender transparenter fehlerkorrekturspeicher

Family Applications After (1)

Application Number Title Priority Date Filing Date
AT05823326T ATE511139T1 (de) 2004-11-23 2005-11-03 Teilwortschreibung unterstützender transparenter fehlerkorrekturspeicher

Country Status (5)

Country Link
US (2) US7392456B2 (de)
EP (1) EP1815338B1 (de)
AT (2) ATE477537T1 (de)
DE (1) DE602005022916D1 (de)
WO (1) WO2006057793A2 (de)

Families Citing this family (48)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006309147A (ja) * 2005-03-30 2006-11-09 Kyocera Mita Corp トナーカートリッジ及びそのシャッタ構造
US7274618B2 (en) * 2005-06-24 2007-09-25 Monolithic System Technology, Inc. Word line driver for DRAM embedded in a logic process
US7499307B2 (en) * 2005-06-24 2009-03-03 Mosys, Inc. Scalable embedded DRAM array
EP1748374A1 (de) * 2005-07-08 2007-01-31 STMicroelectronics SA Verfahren und Vorrichtung zum Schutz eines Speichers gegen Angriffe mittels Fehlerinjektion
JP4339914B2 (ja) * 2006-01-31 2009-10-07 富士通株式会社 エラー訂正コード生成方法及びメモリ管理装置
JP2007242162A (ja) * 2006-03-09 2007-09-20 Toshiba Corp 半導体記憶装置
US8069377B2 (en) * 2006-06-26 2011-11-29 Micron Technology, Inc. Integrated circuit having memory array including ECC and column redundancy and method of operating the same
US7844888B2 (en) * 2006-09-29 2010-11-30 Qimonda Ag Electronic device, method for operating an electronic device, memory circuit and method of operating a memory circuit
US8042022B2 (en) 2007-03-08 2011-10-18 Micron Technology, Inc. Method, system, and apparatus for distributed decoding during prolonged refresh
KR101326898B1 (ko) * 2007-04-26 2013-11-20 에이저 시스템즈 엘엘시 메모리 디바이스, 집적 회로 및 메모리 디바이스에서 사용하기 위한 방법
US7930615B2 (en) 2007-05-31 2011-04-19 Agere Systems Inc. Memory device with error correction capability and preemptive partial word write operation
EP2169555A4 (de) * 2007-06-20 2011-01-05 Fujitsu Ltd Cache-steuerung, cache-steuerverfahren und cache-steuerprogramm
US20090070655A1 (en) * 2007-09-11 2009-03-12 Silicon Motion, Inc. Method for Generating an ECC Code for a Memory Device
JP4820795B2 (ja) * 2007-10-04 2011-11-24 パナソニック株式会社 半導体記憶装置
US8484411B1 (en) * 2007-12-31 2013-07-09 Synopsys Inc. System and method for improving access efficiency to a dynamic random access memory
US7814300B2 (en) 2008-04-30 2010-10-12 Freescale Semiconductor, Inc. Configurable pipeline to process an operation at alternate pipeline stages depending on ECC/parity protection mode of memory access
US20090327535A1 (en) * 2008-06-30 2009-12-31 Liu Tz-Yi Adjustable read latency for memory device in page-mode access
US8161355B2 (en) 2009-02-11 2012-04-17 Mosys, Inc. Automatic refresh for improving data retention and endurance characteristics of an embedded non-volatile memory in a standard CMOS logic process
JP2013033560A (ja) 2009-12-03 2013-02-14 Panasonic Corp 半導体記憶装置
KR20110087036A (ko) * 2010-01-25 2011-08-02 삼성전자주식회사 덮어쓰기 가능한 불휘발성 메모리 장치 및 그것의 데이터 쓰기 방법
US8438344B2 (en) * 2010-03-12 2013-05-07 Texas Instruments Incorporated Low overhead and timing improved architecture for performing error checking and correction for memories and buses in system-on-chips, and other circuits, systems and processes
US8621324B2 (en) 2010-12-10 2013-12-31 Qualcomm Incorporated Embedded DRAM having low power self-correction capability
US8612834B2 (en) * 2011-03-08 2013-12-17 Intel Corporation Apparatus, system, and method for decoding linear block codes in a memory controller
KR101788737B1 (ko) * 2011-05-12 2017-10-24 에스케이하이닉스 주식회사 반도체 시스템
US9003260B2 (en) * 2011-06-29 2015-04-07 Texas Instruments Incorporated Partial-writes to ECC (error check code) enabled memories
US8707133B2 (en) 2011-12-05 2014-04-22 Lsi Corporation Method and apparatus to reduce a quantity of error detection/correction bits in memory coupled to a data-protected processor port
US8869008B2 (en) 2013-01-17 2014-10-21 Apple Inc. Adaptation of analog memory cell read thresholds using partial ECC syndromes
WO2014205590A1 (en) * 2013-06-24 2014-12-31 Micron Technology, Inc. Circuits, apparatuses, and methods for correcting data errors
GB2516831B (en) 2013-07-31 2020-10-21 Advanced Risc Mach Ltd Error code management in systems permitting partial writes
CN105431905B (zh) 2013-09-24 2019-05-07 拉姆伯斯公司 具有内部读取-修改-写入操作的存储部件
US9495242B2 (en) 2014-07-30 2016-11-15 International Business Machines Corporation Adaptive error correction in a memory system
US9583219B2 (en) 2014-09-27 2017-02-28 Qualcomm Incorporated Method and apparatus for in-system repair of memory in burst refresh
US10298271B2 (en) 2015-02-03 2019-05-21 Infineon Technologies Ag Method and apparatus for providing a joint error correction code for a combined data frame comprising first data of a first data channel and second data of a second data channel and sensor system
US10289508B2 (en) 2015-02-03 2019-05-14 Infineon Technologies Ag Sensor system and method for identifying faults related to a substrate
US9412461B1 (en) * 2015-03-10 2016-08-09 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device
US10346170B2 (en) * 2015-05-05 2019-07-09 Intel Corporation Performing partial register write operations in a processor
US20160378151A1 (en) * 2015-06-26 2016-12-29 Intel Corporation Rack scale architecture (rsa) and shared memory controller (smc) techniques of fast zeroing
US10522237B2 (en) 2015-08-07 2019-12-31 Mentor Graphics Corporation Low power VLSI designs using circuit failure in sequential cells as low voltage check for limit of operation
US10025652B2 (en) 2015-10-27 2018-07-17 Western Digital Technologies, Inc. Error location pointers for non volatile memory
US9904595B1 (en) * 2016-08-23 2018-02-27 Texas Instruments Incorporated Error correction hardware with fault detection
US10372531B2 (en) * 2017-01-05 2019-08-06 Texas Instruments Incorporated Error-correcting code memory
KR20190031787A (ko) 2017-09-18 2019-03-27 삼성전자주식회사 병렬 리드-모디파이-라이트 동작을 수행하는 메모리 장치
US10691532B2 (en) 2018-06-29 2020-06-23 Alibaba Group Holding Limited Storage drive error-correcting code-assisted scrubbing for dynamic random-access memory retention time handling
US11042181B2 (en) * 2018-11-01 2021-06-22 Siemens Industry Software Inc. Local clock injection and independent capture for circuit test of multiple cores in clock mesh architecture
WO2021075076A1 (ja) * 2019-10-15 2021-04-22 株式会社ソニー・インタラクティブエンタテインメント 情報処理装置、及び情報処理方法
US11398289B2 (en) * 2020-01-27 2022-07-26 Stmicroelectronics International N.V. Memory calibration device, system and method
US11094372B1 (en) * 2020-05-07 2021-08-17 Powerchip Semiconductor Manufacturing Corporation Partial writing method of dram memoryl device to reduce power consumption associated with large voltage swing of internal input/output lines
US11847348B2 (en) * 2021-08-24 2023-12-19 Apple Inc. Multi-activation techniques for partial write operations

Family Cites Families (85)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3814921A (en) * 1972-11-15 1974-06-04 Honeywell Inf Systems Apparatus and method for a memory partial-write of error correcting encoded data
US3969706A (en) 1974-10-08 1976-07-13 Mostek Corporation Dynamic random access memory misfet integrated circuit
US4045783A (en) 1976-04-12 1977-08-30 Standard Microsystems Corporation Mos one transistor cell ram having divided and balanced bit lines, coupled by regenerative flip-flop sense amplifiers, and balanced access circuitry
JPS5555499A (en) 1978-10-16 1980-04-23 Nec Corp Memory control unit
JPS5647988A (en) 1979-09-20 1981-04-30 Nec Corp Semiconductor memory device
US4317201A (en) 1980-04-01 1982-02-23 Honeywell, Inc. Error detecting and correcting RAM assembly
US4380812A (en) 1980-04-25 1983-04-19 Data General Corporation Refresh and error detection and correction technique for a data processing system
US4345328A (en) 1980-06-30 1982-08-17 Sperry Corporation ECC Check bit generation using through checking parity bits
US5177743A (en) 1982-02-15 1993-01-05 Hitachi, Ltd. Semiconductor memory
US4561095A (en) 1982-07-19 1985-12-24 Fairchild Camera & Instrument Corporation High-speed error correcting random access memory system
JPS60219700A (ja) 1984-04-13 1985-11-02 Sharp Corp 誤り訂正機能内蔵半導体集積回路
JPS6134793A (ja) 1984-07-27 1986-02-19 Hitachi Ltd ダイナミツクメモリ装置における診断及びエラ−訂正装置
US4726021A (en) 1985-04-17 1988-02-16 Hitachi, Ltd. Semiconductor memory having error correcting means
US4933904A (en) 1985-11-29 1990-06-12 General Electric Company Dense EPROM having serially coupled floating gate transistors
US4794597A (en) 1986-03-28 1988-12-27 Mitsubishi Denki Kabushiki Kaisha Memory device equipped with a RAS circuit
US4768197A (en) * 1986-09-15 1988-08-30 Amdahl Corporation Cache error code update
JPH07118193B2 (ja) 1986-09-18 1995-12-18 富士通株式会社 半導体記憶装置
US4740968A (en) 1986-10-27 1988-04-26 International Business Machines Corporation ECC circuit failure detector/quick word verifier
US4939694A (en) 1986-11-03 1990-07-03 Hewlett-Packard Company Defect tolerant self-testing self-repairing memory system
US4782487A (en) 1987-05-15 1988-11-01 Digital Equipment Corporation Memory test method and apparatus
US4817095A (en) * 1987-05-15 1989-03-28 Digital Equipment Corporation Byte write error code method and apparatus
US4884271A (en) * 1987-12-28 1989-11-28 International Business Machines Corporation Error checking and correcting for read-modified-write operations
JPH01183000A (ja) 1988-01-14 1989-07-20 Mitsubishi Electric Corp 誤り訂正回路を有する半導体メモリ装置
US5008886A (en) * 1989-01-27 1991-04-16 Digital Equipment Corporation Read-modify-write operation
US5235693A (en) * 1989-01-27 1993-08-10 Digital Equipment Corporation Method and apparatus for reducing buffer storage in a read-modify-write operation
JPH0664918B2 (ja) 1989-05-25 1994-08-22 ローム株式会社 自己訂正機能を有する半導体記憶装置
JP2617026B2 (ja) 1989-12-22 1997-06-04 インターナショナル・ビジネス・マシーンズ・コーポレーション 障害余裕性メモリ・システム
US5307356A (en) 1990-04-16 1994-04-26 International Business Machines Corporation Interlocked on-chip ECC system
JP3215105B2 (ja) 1990-08-24 2001-10-02 富士通株式会社 メモリアクセス装置
US5233616A (en) 1990-10-01 1993-08-03 Digital Equipment Corporation Write-back cache with ECC protection
US5241503A (en) 1991-02-25 1993-08-31 Motorola, Inc. Dynamic random access memory with improved page-mode performance and method therefor having isolator between memory cells and sense amplifiers
US5274646A (en) 1991-04-17 1993-12-28 International Business Machines Corporation Excessive error correction control
US5289584A (en) 1991-06-21 1994-02-22 Compaq Computer Corp. Memory system with FIFO data input
WO1993004432A2 (en) 1991-08-16 1993-03-04 Multichip Technology High-performance dynamic memory system
US5369651A (en) * 1992-06-30 1994-11-29 Intel Corporation Multiplexed byte enable bus for partial word writes to ECC protected memory
US5519839A (en) 1992-10-02 1996-05-21 Compaq Computer Corp. Double buffering operations between the memory bus and the expansion bus of a computer system
US5430742A (en) * 1992-10-14 1995-07-04 Ast Research, Inc. Memory controller with ECC and data streaming control
US5519847A (en) 1993-06-30 1996-05-21 Intel Corporation Method of pipelining sequential writes in a flash memory
US5402389A (en) 1994-03-08 1995-03-28 Motorola, Inc. Synchronous memory having parallel output data paths
GB2289779B (en) 1994-05-24 1999-04-28 Intel Corp Method and apparatus for automatically scrubbing ECC errors in memory via hardware
US5535226A (en) 1994-05-31 1996-07-09 International Business Machines Corporation On-chip ECC status
US5592435A (en) 1994-06-03 1997-01-07 Intel Corporation Pipelined read architecture for memory
US5502835A (en) 1994-08-31 1996-03-26 Motorola, Inc. Method for synchronously accessing memory
US5524220A (en) 1994-08-31 1996-06-04 Vlsi Technology, Inc. Memory subsystems having look-ahead instruction prefetch buffers and intelligent posted write buffers for increasing the throughput of digital computer systems
JP3013714B2 (ja) 1994-09-28 2000-02-28 日本電気株式会社 半導体記憶装置
TW358907B (en) 1994-11-22 1999-05-21 Monolithic System Tech Inc A computer system and a method of using a DRAM array as a next level cache memory
US5513148A (en) 1994-12-01 1996-04-30 Micron Technology Inc. Synchronous NAND DRAM architecture
US5533194A (en) 1994-12-28 1996-07-02 International Business Machines Corporation Hardware-assisted high speed memory test apparatus and method
US5778237A (en) 1995-01-10 1998-07-07 Hitachi, Ltd. Data processor and single-chip microcomputer with changing clock frequency and operating voltage
US5687353A (en) * 1995-03-03 1997-11-11 Hal Computer Systems, Inc. Merging data using a merge code from a look-up table and performing ECC generation on the merged data
JP3272903B2 (ja) 1995-03-16 2002-04-08 株式会社東芝 誤り訂正検出回路と半導体記憶装置
US5671187A (en) 1995-06-07 1997-09-23 Texas Instruments Incorporated Storage circuit
US5615169A (en) 1995-08-31 1997-03-25 Monolithic System Technology, Inc. Method and structure for controlling internal operations of a DRAM array
JP3106947B2 (ja) 1996-02-28 2000-11-06 日本電気株式会社 不揮発性半導体記憶装置
US6065146A (en) 1996-10-21 2000-05-16 Texas Instruments Incorporated Error correcting memory
US5708624A (en) 1996-11-27 1998-01-13 Monolithic System Technology, Inc. Method and structure for controlling internal operations of a DRAM array
US5961655A (en) 1996-12-05 1999-10-05 Hewlett-Packard Company Opportunistic use of pre-corrected data to improve processor performance
US6052011A (en) 1997-11-10 2000-04-18 Tritech Microelectronics, Ltd. Fractional period delay circuit
JP3566051B2 (ja) 1997-11-14 2004-09-15 株式会社ルネサステクノロジ 位相の異なる複数のクロック信号を出力するクロック信号発生回路およびそれを用いたクロック位相制御回路
JP3199021B2 (ja) 1998-03-19 2001-08-13 日本電気株式会社 半導体メモリ装置、該半導体メモリ装置の検査方法及び使用方法
US6078547A (en) 1998-05-12 2000-06-20 Mosys, Inc. Method and structure for controlling operation of a DRAM array
US20020029365A1 (en) * 1998-12-17 2002-03-07 Yoshimichi Sato Information processing apparatus
JP4105819B2 (ja) 1999-04-26 2008-06-25 株式会社ルネサステクノロジ 記憶装置およびメモリカード
US6141272A (en) * 1999-09-02 2000-10-31 Micron Technology, Inc. Method and apparatus for programmable control signal generation for a semiconductor device
US6701480B1 (en) 2000-03-08 2004-03-02 Rockwell Automation Technologies, Inc. System and method for providing error check and correction in memory systems
US6799287B1 (en) 2000-05-01 2004-09-28 Hewlett-Packard Development Company, L.P. Method and apparatus for verifying error correcting codes
EP1316170A2 (de) 2000-06-07 2003-06-04 Conexant Systems, Inc. Verfahren und vorrichtung zur mediumzugriffssteuerung in einem kommunikationssystem über stromversorgungsleitungen
JP2002056671A (ja) 2000-08-14 2002-02-22 Hitachi Ltd ダイナミック型ｒａｍのデータ保持方法と半導体集積回路装置
US20030120858A1 (en) 2000-09-15 2003-06-26 Matrix Semiconductor, Inc. Memory devices and methods for use therewith
US7051264B2 (en) 2001-11-14 2006-05-23 Monolithic System Technology, Inc. Error correcting memory and method of operating same
US6563745B1 (en) 2001-12-14 2003-05-13 Matrix Semiconductor, Inc. Memory device and method for dynamic bit inversion
FR2840445B1 (fr) 2002-06-03 2004-09-10 St Microelectronics Sa Circuit memoire comportant un code correcteur d'erreur
US7124260B2 (en) 2002-08-26 2006-10-17 Micron Technology, Inc. Modified persistent auto precharge command protocol system and method for memory devices
US7206891B2 (en) * 2002-09-26 2007-04-17 Lsi Logic Corporation Multi-port memory controller having independent ECC encoders
US6781898B2 (en) 2002-10-30 2004-08-24 Broadcom Corporation Self-repairing built-in self test for linked list memories
US7099997B2 (en) 2003-02-27 2006-08-29 International Business Machines Corporation Read-modify-write avoidance using a boundary word storage mechanism
JP4278414B2 (ja) 2003-03-18 2009-06-17 株式会社ルネサステクノロジ 半導体記憶装置
US7099216B2 (en) 2003-09-05 2006-08-29 International Business Machines Corporation Single cycle read/write/writeback pipeline, full-wordline I/O DRAM architecture with enhanced write and single ended sensing
FR2864321B1 (fr) 2003-12-23 2007-01-19 St Microelectronics Sa Memoire dynamique a acces aleatoire ou dram comportant au moins deux registres tampons et procede de commande d'une telle memoire
US7116602B2 (en) * 2004-07-15 2006-10-03 Micron Technology, Inc. Method and system for controlling refresh to avoid memory cell data losses
US7483289B2 (en) 2004-08-02 2009-01-27 Stmicroelectronics Pvt. Ltd. Synchronous SRAM capable of faster read-modify-write operation
US7257762B2 (en) 2004-10-07 2007-08-14 Lsi Corporation Memory interface with write buffer and encoder
JP2006190425A (ja) 2005-01-07 2006-07-20 Nec Electronics Corp 半導体記憶装置
US7451380B2 (en) 2005-03-03 2008-11-11 International Business Machines Corporation Method for implementing enhanced vertical ECC storage in a dynamic random access memory
JP4703220B2 (ja) 2005-03-04 2011-06-15 株式会社東芝 半導体記憶装置

Also Published As

Publication number Publication date
ATE511139T1 (de) 2011-06-15
EP1815338B1 (de) 2010-08-11
WO2006057793A3 (en) 2007-05-31
EP1815338A4 (de) 2008-05-28
US20060123322A1 (en) 2006-06-08
WO2006057793A2 (en) 2006-06-01
US20060112321A1 (en) 2006-05-25
US7392456B2 (en) 2008-06-24
US7275200B2 (en) 2007-09-25
DE602005022916D1 (de) 2010-09-23
EP1815338A2 (de) 2007-08-08

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