IT1261411B - Metodo e circuiteria per l'uso di memorie aventi locazioni difettose erelativa apparecchiatura di produzione. - Google Patents

Metodo e circuiteria per l'uso di memorie aventi locazioni difettose erelativa apparecchiatura di produzione.

Info

Publication number
IT1261411B
IT1261411B ITRM930155A ITRM930155A IT1261411B IT 1261411 B IT1261411 B IT 1261411B IT RM930155 A ITRM930155 A IT RM930155A IT RM930155 A ITRM930155 A IT RM930155A IT 1261411 B IT1261411 B IT 1261411B
Authority
IT
Italy
Prior art keywords
memory
memories
locations
otp
recover
Prior art date
Application number
ITRM930155A
Other languages
English (en)
Inventor
Pasquale Pistilli
Original Assignee
Texas Instruments Italia Spa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Italia Spa filed Critical Texas Instruments Italia Spa
Priority to ITRM930155A priority Critical patent/IT1261411B/it
Publication of ITRM930155A0 publication Critical patent/ITRM930155A0/it
Priority to US08/209,580 priority patent/US5541938A/en
Priority to EP94301771A priority patent/EP0620524A3/en
Priority to JP6080844A priority patent/JPH07121451A/ja
Publication of ITRM930155A1 publication Critical patent/ITRM930155A1/it
Application granted granted Critical
Publication of IT1261411B publication Critical patent/IT1261411B/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/4402—Internal storage of test result, quality data, chip identification, repair information
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/88—Masking faults in memories by using spares or by reconfiguring with partially good memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Correction Of Errors (AREA)
  • Hardware Redundancy (AREA)

Abstract

Oggetto dell'invenzione è un sistema per l'uso di memorie dinamiche a semiconduttore aventi locazioni difettose, in cui tali memorie vengono inizialmente organizzate in banchi per formare una parola di informazione elementare e quindi vengono identificate tutte le locazioni omologhe di indirizzo che non sono affette da errori così da ottenere una mappatura, la quale viene memorizzata in una memoria non volatile (OTP) associata al banco di memoria, per dar luogo ad una tabella di transcodificazione; ed in cui l'utilizzatore esterno che deve recuperare i dati contenuti nei blocchi della memoria accederà a detta memoria non volatile (OTP) utilizzando degli indirizzi di memoria consecutivi (logici) forniti ad esso da una sezione intelligente del sistema. e recupererà da essa degli indirizzi transcodificati (fisici) che gli permetteranno di accedere direttamente ed immediatamente a detti blocchi di memoria.Nel sistema secondo l'invenzione, per ampliare il numero delle locazioni in cui sia possibile memorizzare informazioni, utilizzando anche zone affette da limitata difettosità, si applicano tecniche mirate alla applicazione per la correzione dell'errore (ECC).
ITRM930155A 1993-03-12 1993-03-12 Metodo e circuiteria per l'uso di memorie aventi locazioni difettose erelativa apparecchiatura di produzione. IT1261411B (it)

Priority Applications (4)

Application Number Priority Date Filing Date Title
ITRM930155A IT1261411B (it) 1993-03-12 1993-03-12 Metodo e circuiteria per l'uso di memorie aventi locazioni difettose erelativa apparecchiatura di produzione.
US08/209,580 US5541938A (en) 1993-03-12 1994-03-11 Method and apparatus for mapping memory as to operable and faulty locations
EP94301771A EP0620524A3 (en) 1993-03-12 1994-03-11 Improvements in or relating to memories and their manufacture
JP6080844A JPH07121451A (ja) 1993-03-12 1994-03-14 故障箇所を有するダイナミックメモリの使用システム

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ITRM930155A IT1261411B (it) 1993-03-12 1993-03-12 Metodo e circuiteria per l'uso di memorie aventi locazioni difettose erelativa apparecchiatura di produzione.

Publications (3)

Publication Number Publication Date
ITRM930155A0 ITRM930155A0 (it) 1993-03-12
ITRM930155A1 ITRM930155A1 (it) 1994-09-12
IT1261411B true IT1261411B (it) 1996-05-23

Family

ID=11401598

Family Applications (1)

Application Number Title Priority Date Filing Date
ITRM930155A IT1261411B (it) 1993-03-12 1993-03-12 Metodo e circuiteria per l'uso di memorie aventi locazioni difettose erelativa apparecchiatura di produzione.

Country Status (4)

Country Link
US (1) US5541938A (it)
EP (1) EP0620524A3 (it)
JP (1) JPH07121451A (it)
IT (1) IT1261411B (it)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU1934595A (en) * 1994-03-04 1995-09-18 Motorola, Inc. Remote meter reading power reduction method
WO1997011381A1 (fr) * 1995-09-22 1997-03-27 Advantest Corporation Controleur de memoire
IT1284244B1 (it) * 1996-08-05 1998-05-14 Texas Instruments Italia Spa Sistema per produrre moduli di memoria simm utilizzando chip di memoria aram e per il loro collaudo
US7054271B2 (en) 1996-12-06 2006-05-30 Ipco, Llc Wireless network system and method for providing same
US8982856B2 (en) 1996-12-06 2015-03-17 Ipco, Llc Systems and methods for facilitating wireless network communication, satellite-based wireless network systems, and aircraft-based wireless network systems, and related methods
US5915167A (en) * 1997-04-04 1999-06-22 Elm Technology Corporation Three dimensional structure memory
US6891838B1 (en) 1998-06-22 2005-05-10 Statsignal Ipc, Llc System and method for monitoring and controlling residential devices
US6914893B2 (en) 1998-06-22 2005-07-05 Statsignal Ipc, Llc System and method for monitoring and controlling remote devices
US6437692B1 (en) 1998-06-22 2002-08-20 Statsignal Systems, Inc. System and method for monitoring and controlling remote devices
US8410931B2 (en) 1998-06-22 2013-04-02 Sipco, Llc Mobile inventory unit monitoring systems and methods
CN1102271C (zh) * 1998-10-07 2003-02-26 国际商业机器公司 具有习惯用语处理功能的电子词典
US7650425B2 (en) 1999-03-18 2010-01-19 Sipco, Llc System and method for controlling communication between a host computer and communication devices associated with remote devices in an automated monitoring system
AU2001279241A1 (en) 2000-08-09 2002-02-18 Statsignal Systems, Inc. Systems and methods for providing remote monitoring of electricity consumption for an electric meter
US6725393B1 (en) * 2000-11-06 2004-04-20 Hewlett-Packard Development Company, L.P. System, machine, and method for maintenance of mirrored datasets through surrogate writes during storage-area network transients
ITRM20010298A1 (it) * 2001-05-31 2002-12-02 Micron Technology Inc Interfaccia di comando di utilizzatore con decodificatore programmabile.
US6678836B2 (en) * 2001-01-19 2004-01-13 Honeywell International, Inc. Simple fault tolerance for memory
US7346463B2 (en) 2001-08-09 2008-03-18 Hunt Technologies, Llc System for controlling electrically-powered devices in an electrical network
US7480501B2 (en) 2001-10-24 2009-01-20 Statsignal Ipc, Llc System and method for transmitting an emergency message over an integrated wireless network
US8489063B2 (en) 2001-10-24 2013-07-16 Sipco, Llc Systems and methods for providing emergency messages to a mobile device
US7424527B2 (en) 2001-10-30 2008-09-09 Sipco, Llc System and method for transmitting pollution information over an integrated wireless network
US7325157B2 (en) * 2003-11-03 2008-01-29 Samsung Electronics Co., Ltd Magnetic memory devices having selective error encoding capability based on fault probabilities
US7756086B2 (en) 2004-03-03 2010-07-13 Sipco, Llc Method for communicating in dual-modes
US8031650B2 (en) 2004-03-03 2011-10-04 Sipco, Llc System and method for monitoring remote devices with a dual-mode wireless communication protocol
WO2006081206A1 (en) 2005-01-25 2006-08-03 Sipco, Llc Wireless network protocol systems and methods
CN103390588B (zh) * 2012-05-09 2015-08-19 无锡华润上华半导体有限公司 一种基于otp存储器制作mrom存储器的方法
US10903858B2 (en) * 2015-05-27 2021-01-26 Quantum Corporation Dynamically variable error correcting code (ECC) system with hybrid rateless reed-solomon ECCs

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4653050A (en) * 1984-12-03 1987-03-24 Trw Inc. Fault-tolerant memory system
IT1201837B (it) * 1986-07-22 1989-02-02 Sgs Microelettronica Spa Sistema per la verifica della funzionalita' e delle caratteristiche di dispositivi a semiconduttore di tipo eprom durante il "burn-in"
US4939694A (en) * 1986-11-03 1990-07-03 Hewlett-Packard Company Defect tolerant self-testing self-repairing memory system
US5067105A (en) * 1987-11-16 1991-11-19 International Business Machines Corporation System and method for automatically configuring translation of logical addresses to a physical memory address in a computer memory system
US5077737A (en) * 1989-08-18 1991-12-31 Micron Technology, Inc. Method and apparatus for storing digital data in off-specification dynamic random access memory devices
EP0584864B1 (en) * 1992-08-21 1997-11-05 Koninklijke Philips Electronics N.V. A hardware-efficient method and device for encoding BCH codes and in particular Reed-Solomon codes

Also Published As

Publication number Publication date
US5541938A (en) 1996-07-30
EP0620524A3 (en) 1998-08-12
JPH07121451A (ja) 1995-05-12
ITRM930155A1 (it) 1994-09-12
ITRM930155A0 (it) 1993-03-12
EP0620524A2 (en) 1994-10-19

Similar Documents

Publication Publication Date Title
IT1261411B (it) Metodo e circuiteria per l'uso di memorie aventi locazioni difettose erelativa apparecchiatura di produzione.
GB2351822A (en) Memory system
KR930018593A (ko) 반도체 기억장치
TW451468B (en) Semiconductor memory device
KR970703596A (ko) 단일칩내 구현된 제어기와 메모리 디바이스 및 이를 실현하기에 적합한 메모리 구조 및 방법(Single chip controller-memory device and a memory architecture and methods suitable for implementing the same)
IT1256497B (it) Memoria di sola lettura programmabile e cancellabile elettricamente con un circuito di verifica e correzzione dell'errore
TW355843B (en) Semiconductor memory device
IT1255932B (it) Circuito di ridondanza di riga per un dispositivo di memoria a semiconduttore.
CN101641679A (zh) 用于系统管理的多级单元选择的多程序
IT1274925B (it) Architettura di memoria per dischi a stato solido
KR900012161A (ko) 집적된 매트릭스 메모리와 집적회로
TW274638B (en) A random access memory having a flexible array redundancy scheme
JPS56134390A (en) Rom element
EP0686980B1 (en) Semiconductor memory device having means for replacing defective memory cells
DE3872413D1 (de) Verfahren und anordnung zur adressierung von redundanten elementen eines integrierten speichers.
DE69321623D1 (de) Redundanzspeicherzellen mit Parallelprüffunktion enthaltendes Halbleiter-Speichergerät
CN105335296B (zh) 一种数据处理方法、装置及系统
JPH01180654A (ja) メモリ管理装置
US20090003098A1 (en) Method for Hiding Defective Memory Cells and Semiconductor Memories
CA2377765A1 (en) Data processors
TW397986B (en) Dynamic memory with two operation modes
ES2144284T3 (es) Memoria solo de lectura y procedimiento para la activacion de la misma.
EP0206655A3 (en) Method and apparatus for embedding data in an instruction stream
JPS5713562A (en) Control system of external memory
US6484277B1 (en) Integrated memory having a redundancy function

Legal Events

Date Code Title Description
0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19960119