DE3872413D1 - Verfahren und anordnung zur adressierung von redundanten elementen eines integrierten speichers. - Google Patents

Verfahren und anordnung zur adressierung von redundanten elementen eines integrierten speichers.

Info

Publication number
DE3872413D1
DE3872413D1 DE8888400388T DE3872413T DE3872413D1 DE 3872413 D1 DE3872413 D1 DE 3872413D1 DE 8888400388 T DE8888400388 T DE 8888400388T DE 3872413 T DE3872413 T DE 3872413T DE 3872413 D1 DE3872413 D1 DE 3872413D1
Authority
DE
Germany
Prior art keywords
column
row
address
bank
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8888400388T
Other languages
English (en)
Other versions
DE3872413T2 (de
Inventor
Jean-Marie Bernard Gaultier
Jean Devin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
SGS Thomson Microelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics SA filed Critical SGS Thomson Microelectronics SA
Application granted granted Critical
Publication of DE3872413D1 publication Critical patent/DE3872413D1/de
Publication of DE3872413T2 publication Critical patent/DE3872413T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/808—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a flexible replacement scheme
DE8888400388T 1987-03-03 1988-02-19 Verfahren und anordnung zur adressierung von redundanten elementen eines integrierten speichers. Expired - Fee Related DE3872413T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8702835A FR2611972B1 (fr) 1987-03-03 1987-03-03 Procede d'adressage d'elements redondants d'une memoire integree et dispositif permettant de mettre en oeuvre le procede

Publications (2)

Publication Number Publication Date
DE3872413D1 true DE3872413D1 (de) 1992-08-06
DE3872413T2 DE3872413T2 (de) 1992-12-03

Family

ID=9348528

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8888400388T Expired - Fee Related DE3872413T2 (de) 1987-03-03 1988-02-19 Verfahren und anordnung zur adressierung von redundanten elementen eines integrierten speichers.

Country Status (5)

Country Link
US (1) US4947375A (de)
EP (1) EP0282384B1 (de)
JP (1) JPS63302498A (de)
DE (1) DE3872413T2 (de)
FR (1) FR2611972B1 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2659165A1 (fr) * 1990-03-05 1991-09-06 Sgs Thomson Microelectronics Memoire ultra-rapide comportant un limiteur de la tension de drain des cellules.
FR2667193B1 (fr) * 1990-09-25 1993-07-02 Sgs Thomson Microelectronics Circuit de precharge pour la lecture de memoires.
JPH0831279B2 (ja) * 1990-12-20 1996-03-27 インターナショナル・ビジネス・マシーンズ・コーポレイション 冗長システム
JP3339641B2 (ja) * 1991-05-21 2002-10-28 日本テキサス・インスツルメンツ株式会社 半導体記憶装置
JPH05128893A (ja) * 1991-10-31 1993-05-25 Nec Ic Microcomput Syst Ltd 半導体集積回路
FR2683664A1 (fr) * 1991-11-13 1993-05-14 Sgs Thomson Microelectronics Memoire integree electriquement programmable a un seuil transistor.
FR2694119B1 (fr) * 1992-07-24 1994-08-26 Sgs Thomson Microelectronics Circuit de lecture pour mémoire, avec recharge et équilibrage avant lecture.
FR2714202B1 (fr) * 1993-12-22 1996-01-12 Sgs Thomson Microelectronics Mémoire en circuit intégré à temps de lecture amélioré.
GB2292236A (en) * 1995-04-04 1996-02-14 Memory Corp Plc Improved partial memory engine
JP3557022B2 (ja) * 1995-12-08 2004-08-25 株式会社東芝 半導体記憶装置
FR2758645B1 (fr) * 1997-01-22 2001-12-14 Sgs Thomson Microelectronics Dispositif et procede de programmation d'une memoire
US5835425A (en) * 1997-09-04 1998-11-10 Siemens Aktiengesellschaft Dimension programmable fusebanks and methods for making the same
US7003704B2 (en) * 2002-11-12 2006-02-21 International Business Machines Corporation Two-dimensional redundancy calculation

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3753244A (en) * 1971-08-18 1973-08-14 Ibm Yield enhancement redundancy technique
US4047163A (en) * 1975-07-03 1977-09-06 Texas Instruments Incorporated Fault-tolerant cell addressable array
US4228528B2 (en) * 1979-02-09 1992-10-06 Memory with redundant rows and columns
WO1980002889A1 (en) * 1979-06-15 1980-12-24 Fujitsu Ltd Semiconductor memory device
US4266285A (en) * 1979-06-28 1981-05-05 Honeywell Information Systems, Inc. Row selection circuits for memory circuits
US4346459A (en) * 1980-06-30 1982-08-24 Inmos Corporation Redundancy scheme for an MOS memory
JPS5948898A (ja) * 1982-09-10 1984-03-21 Hitachi Ltd 半導体記憶装置
US4654830A (en) * 1984-11-27 1987-03-31 Monolithic Memories, Inc. Method and structure for disabling and replacing defective memory in a PROM

Also Published As

Publication number Publication date
DE3872413T2 (de) 1992-12-03
US4947375A (en) 1990-08-07
FR2611972B1 (fr) 1989-05-19
EP0282384B1 (de) 1992-07-01
FR2611972A1 (fr) 1988-09-09
EP0282384A1 (de) 1988-09-14
JPS63302498A (ja) 1988-12-09

Similar Documents

Publication Publication Date Title
DE3872413T2 (de) Verfahren und anordnung zur adressierung von redundanten elementen eines integrierten speichers.
KR920006996A (ko) 용장 회로부 메모리 ic의 시험 장치
KR910002965B1 (ko) 여분 셀로 대치 가능한 반도체 메모리장치
ATE511188T1 (de) Vorrichtung und verfahren zum reparieren eines halbleiterspeichers
KR970703596A (ko) 단일칩내 구현된 제어기와 메모리 디바이스 및 이를 실현하기에 적합한 메모리 구조 및 방법(Single chip controller-memory device and a memory architecture and methods suitable for implementing the same)
US20060215432A1 (en) TCAM BIST with redundancy
KR100395031B1 (ko) 리던던트의 메모리 셀 유닛을 포함하는 집적 반도체 메모리
WO2002089147A3 (en) Circuit and method for memory test and repair
ES2036223T3 (es) Memorias y la comprobacion de las mismas.
KR920005798A (ko) 반도체 집적회로
FR2787233B1 (fr) Procede pour verifier l'integrite des circuits de decodage d'une memoire
ATE104465T1 (de) Integrierter halbleiterspeicher mit paralleltestmoeglichkeit und redundanzverfahren.
KR950025788A (ko) 용장성 메모리셀의 테스트 절차용으로 활용가능한 용장성 디코더를 구비한 반도체 메모리 장치
KR100404016B1 (ko) 집적 메모리의 결함 메모리 셀을 수리하기 위한 방법
KR920010653A (ko) 메모리 불량 해석 장치
KR970075939A (ko) 반도체 메모리 시험방법 및 장치
DE58909354D1 (de) Verfahren und Vorrichtung zum internen Paralleltest von Halbleiterspeichern.
KR930017042A (ko) 병렬 검사 기능을 갖는 용장 메모리 셀을 구비한 반도체 메모리 장치
KR890004326A (ko) 반도체 메모리장치
US5867435A (en) Fault repair method for a memory device
DE3862990D1 (de) Schaltungsanordnung und verfahren zum testen von speicherzellen.
KR930003170A (ko) 메모리회로의 테스트 방법 및 반도체집적회로장치
US6091650A (en) Redundancy for low remanence memory cells
KR950009745A (ko) 반도체 기억장치
US6538939B1 (en) Memory employing multiple enable/disable modes for redundant elements and testing method using same

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee