JP7330357B2 - 水素ブロッキング層を有する3次元メモリデバイスおよびその製作方法 - Google Patents
水素ブロッキング層を有する3次元メモリデバイスおよびその製作方法 Download PDFInfo
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Description
102 第1の半導体構造体
104 第2の半導体構造体
106 ボンディング界面
108 水素ブロッキング層
110 水素ブロッキング層
200 3Dメモリデバイス
201 3Dメモリデバイス
202 第1の半導体構造体
204 第2の半導体構造体
205 第2の半導体構造体
206 ボンディング界面
208 基板
210 メモリスタック
212 導電性層
214 誘電体層
216 3D NANDメモリストリング
218 メモリフィルム
220 半導体チャネル
222 プラグ
224 プラグ
226 相互接続層
228 ボンディング層
230 ボンディングコンタクト
232 ボンディング層
234 ボンディングコンタクト
236 相互接続層
238 デバイス層
240 トランジスタ
242 半導体層
246 水素ブロッキング層
248 パッドアウト相互接続層
250 コンタクト
251 水素ブロッキングスペーサ
254 接触パッド
256 不動態化層
258 水素ブロッキング層
260 ボンディングコンタクト
302 シリコン基板
304 トランジスタ
306 デバイス層
308 相互接続層
310 ボンディング層
312 ボンディングコンタクト
402 シリコン基板
404 メモリスタック
406 導電性層
408 誘電体層
410 3D NANDメモリストリング
412 プラグ
414 メモリフィルム
416 半導体層
418 プラグ
420 相互接続層
422 ボンディング層
424 ボンディングコンタクト
502 ボンディング界面
504 半導体層
506 水素ブロッキング層
508 誘電体層
509 パッドアウト相互接続層
510 コンタクト
511 水素ブロッキングスペーサ
512 パッドコンタクト
514 不動態化層
Claims (19)
- メモリデバイスであって、
メモリアレイと、
前記メモリアレイの上方の複数のロジックデバイスと、
前記ロジックデバイスの上方にあり、前記ロジックデバイスと接触している半導体層と、
前記半導体層の上方のパッドアウト相互接続層と、
垂直方向に前記半導体層と前記パッドアウト相互接続層との間のブロッキング層と
を含み、
前記半導体層は、垂直方向に前記複数のロジックデバイスと前記ブロッキング層との間にあり、
前記ブロッキング層は、高誘電率(高k)誘電材料を含む、メモリデバイス。 - 前記ブロッキング層の厚さは、約1nmから約100nmの間にある、請求項1に記載のメモリデバイス。
- 前記ブロッキング層は、横方向に延在し、前記半導体層を被覆している、請求項1に記載のメモリデバイス。
- 前記ブロッキング層は、前記メモリデバイスの製作の間に、前記ロジックデバイスから前記パッドアウト相互接続層の中への、または前記パッドアウト相互接続層を越える水素のガス放出を阻止するように構成されている、請求項1に記載のメモリデバイス。
- 前記メモリアレイの上方の第1のボンディング層であって、複数の第1のボンディングコンタクトを含む、第1のボンディング層と、
前記ロジックデバイスの下方の、および前記第1のボンディング層の上方の第2のボンディング層であって、複数の第2のボンディングコンタクトを含む、第2のボンディング層と、
垂直方向に前記第1のボンディング層と前記第2のボンディング層との間のボンディング界面であって、前記第1のボンディングコンタクトは、前記ボンディング界面において、前記第2のボンディングコンタクトと接触している、ボンディング界面と
をさらに含む、請求項1に記載のメモリデバイス。 - 前記メモリデバイスは、
垂直方向に前記メモリアレイと前記第1のボンディング層との間の第1の相互接続層と、
垂直方向に前記第2のボンディング層と前記ロジックデバイスとの間の第2の相互接続層と
をさらに含み、
前記ロジックデバイスは、前記第1および第2の相互接続層および前記第1および第2のボンディングコンタクトを通して、前記メモリアレイに電気的に接続されている、請求項5に記載のメモリデバイス。 - 前記メモリデバイスは、コンタクトであって、前記ブロッキング層および前記半導体層を通って垂直方向に延在し、前記パッドアウト相互接続層および前記第2の相互接続層を電気的に接続するコンタクトと、
前記コンタクトと前記ブロッキング層との間にブロッキングスペーサと、をさらに含む、請求項6に記載のメモリデバイス。 - 前記パッドアウト相互接続層の上方に不動態化層をさらに含む、請求項1に記載のメモリデバイス。
- 前記半導体層は、単結晶シリコンを含む、請求項1に記載のメモリデバイス。
- メモリデバイスであって、
第1のブロッキング層と、
前記第1のブロッキング層の上方の複数のロジックデバイスと、
前記ロジックデバイスの上方にあり、前記ロジックデバイスに接触している半導体層と、
前記半導体層の上方の第2のブロッキング層であって、前記半導体層は、垂直方向に前記複数のロジックデバイスと前記第2のブロッキング層との間にある、第2のブロッキング層と、
前記第2のブロッキング層の上方のパッドアウト相互接続層と
を含み、
前記第2のブロッキング層は、高誘電率(高k)誘電材料を含む、メモリデバイス。 - 前記第1のブロッキング層は、高誘電率(高k)誘電材料を含む、請求項10に記載のメモリデバイス。
- 前記第1および第2のブロッキング層は、横方向に延在し、垂直方向に前記ロジックデバイスをカプセル化している、請求項10に記載のメモリデバイス。
- 前記第1および第2のブロッキング層のそれぞれの厚さは、約1nmから約100nmの間にある、請求項10に記載のメモリデバイス。
- 前記メモリデバイスは、
複数の第1のボンディングコンタクトを含む、第1のボンディング層と、
前記ロジックデバイスの下方の、および前記第1のボンディング層の上方の第2のボンディング層であって、複数の第2のボンディングコンタクトを含む、第2のボンディング層と、
垂直方向に前記第1のボンディング層と前記第2のボンディング層との間のボンディング界面であって、前記第1のボンディングコンタクトは、前記ボンディング界面において、前記第2のボンディングコンタクトと接触している、ボンディング界面と
をさらに含む、請求項10に記載のメモリデバイス。 - 前記第1のブロッキング層は、垂直方向に前記第2のボンディング層と前記ロジックデバイスとの間にある、請求項14に記載のメモリデバイス。
- 前記メモリデバイスは、コンタクトをさらに含み、前記コンタクトは、前記第2のブロッキング層および前記半導体層を通って垂直方向に延在している、請求項14に記載のメモリデバイス。
- 前記コンタクトと前記第2のブロッキング層との間にブロッキングスペーサをさらに含む、請求項16に記載のメモリデバイス。
- 前記半導体層は、単結晶シリコンを含む、請求項10に記載のメモリデバイス。
- 前記パッドアウト相互接続層の上方に不動態化層をさらに含む、請求項10に記載のメモリデバイス。
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