JP2022541833A - 水素ブロッキング層を有する3次元メモリデバイスおよびその製作方法 - Google Patents
水素ブロッキング層を有する3次元メモリデバイスおよびその製作方法 Download PDFInfo
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- JP2022541833A JP2022541833A JP2022504247A JP2022504247A JP2022541833A JP 2022541833 A JP2022541833 A JP 2022541833A JP 2022504247 A JP2022504247 A JP 2022504247A JP 2022504247 A JP2022504247 A JP 2022504247A JP 2022541833 A JP2022541833 A JP 2022541833A
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Abstract
Description
102 第1の半導体構造体
104 第2の半導体構造体
106 ボンディング界面
108 水素ブロッキング層
110 水素ブロッキング層
200 3Dメモリデバイス
201 3Dメモリデバイス
202 第1の半導体構造体
204 第2の半導体構造体
205 第2の半導体構造体
206 ボンディング界面
208 基板
210 メモリスタック
212 導電性層
214 誘電体層
216 3D NANDメモリストリング
218 メモリフィルム
220 半導体チャネル
222 プラグ
224 プラグ
226 相互接続層
228 ボンディング層
230 ボンディングコンタクト
232 ボンディング層
234 ボンディングコンタクト
236 相互接続層
238 デバイス層
240 トランジスタ
242 半導体層
246 水素ブロッキング層
248 パッドアウト相互接続層
250 コンタクト
251 水素ブロッキングスペーサ
254 接触パッド
256 不動態化層
258 水素ブロッキング層
260 ボンディングコンタクト
302 シリコン基板
304 トランジスタ
306 デバイス層
308 相互接続層
310 ボンディング層
312 ボンディングコンタクト
402 シリコン基板
404 メモリスタック
406 導電性層
408 誘電体層
410 3D NANDメモリストリング
412 プラグ
414 メモリフィルム
416 半導体層
418 プラグ
420 相互接続層
422 ボンディング層
424 ボンディングコンタクト
502 ボンディング界面
504 半導体層
506 水素ブロッキング層
508 誘電体層
509 パッドアウト相互接続層
510 コンタクト
511 水素ブロッキングスペーサ
512 パッドコンタクト
514 不動態化層
Claims (36)
- 3次元(3D)メモリデバイスであって、
基板と、
前記基板の上方の交互配置された導電性層および誘電体層を含むメモリスタックと、
前記メモリスタックを通って垂直方向にそれぞれ延在するNANDメモリストリングのアレイと、
前記NANDメモリストリングのアレイの上方の複数のロジックプロセス互換型デバイスと、
前記ロジックプロセス互換型デバイスの上方にあり、前記ロジックプロセス互換型デバイスと接触している半導体層と、
前記半導体層の上方のパッドアウト相互接続層と、
垂直方向に前記半導体層と前記パッドアウト相互接続層との間の水素ブロッキング層であって、水素のガス放出を阻止するように構成されている、水素ブロッキング層と
を含む、3次元(3D)メモリデバイス。 - 前記水素ブロッキング層は、高誘電率(高k)誘電材料を含む、請求項1に記載の3Dメモリデバイス。
- 前記高k誘電材料は、酸化アルミニウムを含む、請求項2に記載の3Dメモリデバイス。
- 前記水素ブロッキング層の厚さは、約1nmから約100nmの間にある、請求項1から3のいずれか一項に記載の3Dメモリデバイス。
- 前記水素ブロッキング層は、横方向に延在し、前記半導体層を被覆している、請求項1から4のいずれか一項に記載の3Dメモリデバイス。
- 前記水素ブロッキング層は、前記3Dメモリデバイスの製作の間に、前記ロジックプロセス互換型デバイスから前記パッドアウト相互接続層の中へのまたは前記パッドアウト相互接続層を越える前記水素のガス放出を阻止するように構成されている、請求項1から5のいずれか一項に記載の3Dメモリデバイス。
- 前記NANDメモリストリングのアレイの上方の第1のボンディング層であって、複数の第1のボンディングコンタクトを含む、第1のボンディング層と、
前記ロジックプロセス互換型デバイスの下方および前記第1のボンディング層の上方の第2のボンディング層であって、複数の第2のボンディングコンタクトを含む、第2のボンディング層と、
垂直方向に前記第1のボンディング層と前記第2のボンディング層との間のボンディング界面であって、前記第1のボンディングコンタクトは、前記ボンディング界面において、前記第2のボンディングコンタクトと接触している、ボンディング界面と
をさらに含む、請求項1から6のいずれか一項に記載の3Dメモリデバイス。 - 前記3Dメモリデバイスは、
垂直方向に前記NANDメモリストリングのアレイと前記第1のボンディング層との間の第1の相互接続層と、
垂直方向に前記第2のボンディング層と前記ロジックプロセス互換型デバイスとの間の第2の相互接続層と
をさらに含み、
前記ロジックプロセス互換型デバイスは、前記第1および第2の相互接続層および前記第1および第2のボンディングコンタクトを通して、前記NANDメモリストリングのアレイに電気的に接続されている、請求項7に記載の3Dメモリデバイス。 - 前記3Dメモリデバイスは、コンタクトをさらに含み、前記コンタクトは、前記水素ブロッキング層および前記半導体層を通って垂直方向に延在し、前記パッドアウト相互接続層および前記第2の相互接続層を電気的に接続する、請求項8に記載の3Dメモリデバイス。
- 前記コンタクトと前記水素ブロッキング層との間に水素ブロッキングスペーサをさらに含む、請求項9に記載の3Dメモリデバイス。
- 前記半導体層は、単結晶シリコンを含む、請求項1から10のいずれか一項に記載の3Dメモリデバイス。
- 前記パッドアウト相互接続層の上方に不動態化層をさらに含む、請求項1から11のいずれか一項に記載の3Dメモリデバイス。
- 前記不動態化層は、窒化ケイ素を含む、請求項12に記載の3Dメモリデバイス。
- 3次元(3D)メモリデバイスであって、
基板と、
前記基板の上方の第1の水素ブロッキング層と、
前記第1の水素ブロッキング層の上方の複数のロジックプロセス互換型デバイスと、
前記ロジックプロセス互換型デバイスの上方にあり、前記ロジックプロセス互換型デバイスと接触している半導体層と、
前記半導体層の上方の第2の水素ブロッキング層と、
前記第2の水素ブロッキング層の上方のパッドアウト相互接続層と
を含み、
前記第1の水素ブロッキング層および前記第2の水素ブロッキング層は、前記3Dメモリデバイスの製作の間に、前記ロジックプロセス互換型デバイスからの水素のガス放出を阻止するように構成されている、3次元(3D)メモリデバイス。 - 前記第1および第2の水素ブロッキング層のそれぞれは、高誘電率(高k)誘電材料を含む、請求項14に記載の3Dメモリデバイス。
- 前記高k誘電材料は、酸化アルミニウムを含む、請求項15に記載の3Dメモリデバイス。
- 前記第1および第2の水素ブロッキング層のそれぞれの厚さは、約1nmから約100nmの間にある、請求項14から16のいずれか一項に記載の3Dメモリデバイス。
- 前記第1および第2の水素ブロッキング層は、横方向に延在し、垂直方向に前記ロジックプロセス互換型デバイスをカプセル化している、請求項14から17のいずれか一項に記載の3Dメモリデバイス。
- 前記3Dメモリデバイスは、
前記基板の上方の第1のボンディング層であって、複数の第1のボンディングコンタクトを含む、第1のボンディング層と、
前記ロジックプロセス互換型デバイスの下方のおよび前記第1のボンディング層の上方の第2のボンディング層であって、複数の第2のボンディングコンタクトを含む、第2のボンディング層と、
垂直方向に前記第1のボンディング層と前記第2のボンディング層との間のボンディング界面であって、前記第1のボンディングコンタクトは、前記ボンディング界面において、前記第2のボンディングコンタクトと接触している、ボンディング界面と
をさらに含む、請求項14から18のいずれか一項に記載の3Dメモリデバイス。 - 前記第1の水素ブロッキング層は、垂直方向に前記第2のボンディング層と前記ロジックプロセス互換型デバイスとの間にある、請求項19に記載の3Dメモリデバイス。
- 前記3Dメモリデバイスは、コンタクトをさらに含み、前記コンタクトは、前記第2の水素ブロッキング層および前記半導体層を通って垂直方向に延在している、請求項19または20に記載の3Dメモリデバイス。
- 前記コンタクトと前記第2の水素ブロッキング層との間に水素ブロッキングスペーサをさらに含む、請求項21に記載の3Dメモリデバイス。
- 前記半導体層は、単結晶シリコンを含む、請求項14から22のいずれか一項に記載の3Dメモリデバイス。
- 前記パッドアウト相互接続層の上方に不動態化層をさらに含む、請求項14から23のいずれか一項に記載の3Dメモリデバイス。
- 前記不動態化層は、窒化ケイ素を含む、請求項24に記載の3Dメモリデバイス。
- 3次元(3D)メモリデバイスを形成するための方法であって、
第1の基板の上方に、垂直方向にそれぞれ延在するNANDメモリストリングのアレイを形成するステップと、
第2の基板の上に複数のロジックプロセス互換型デバイスを形成するステップと、
前記第1の基板および前記第2の基板を向かい合った様式で結合するステップであって、前記ロジックプロセス互換型デバイスは、前記結合するステップの後に前記NANDメモリストリングのアレイの上方にある、ステップと、
前記第2の基板を薄くし、前記ロジックプロセス互換型デバイスの上方にあり、前記ロジックプロセス互換型デバイスと接触した半導体層を形成するステップと、
前記半導体層の上方に第1の水素ブロッキング層を形成するステップであって、前記第1の水素ブロッキング層は、高誘電率(高k)誘電材料を含む、ステップと
を含む、方法。 - 前記方法は、
前記第1の水素ブロッキング層の上方にパッドアウト相互接続層を形成するステップと、
前記ロジックプロセス互換型デバイスの中へ水素を拡散するために前記パッドアウト相互接続層をアニーリングするステップと
をさらに含み、
前記第1の水素ブロッキング層は、前記アニーリングするステップの後に、前記ロジックプロセス互換型デバイスから前記パッドアウト相互接続層の中への、または前記パッドアウト相互接続層を越える前記水素のガス放出を阻止する、請求項26に記載の方法。 - 前記方法は、前記アニーリングするステップの前に、前記パッドアウト相互接続層の上方に不動態化層を形成するステップをさらに含み、前記不動態化層は、水素に富む窒化ケイ素を含む、請求項27に記載の方法。
- 前記方法は、前記アニーリングするステップの前に、前記パッドアウト相互接続層の中へ水素を注入するステップをさらに含む、請求項27または28に記載の方法。
- 前記パッドアウト相互接続層を形成するステップの前に、前記パッドアウト相互接続層に電気的に接続されるように、前記第1の水素ブロッキング層および前記半導体層を通って垂直方向に延在するコンタクトを形成するステップをさらに含む、請求項27から29のいずれか一項に記載の方法。
- 前記コンタクトと前記第1の水素ブロッキング層との間に水素ブロッキングスペーサを形成するステップをさらに含む、請求項30に記載の方法。
- 前記方法は、前記第2の基板の上の前記ロジックプロセス互換型デバイスの上方に第2の水素ブロッキング層を形成するステップをさらに含み、前記第2の水素ブロッキング層は、高k誘電材料を含み、前記アニーリングするステップの後に、前記ロジックプロセス互換型デバイスからの前記水素のガス放出を阻止する、請求項27から31のいずれか一項に記載の方法。
- 前記第1の基板の上方の前記NANDメモリストリングのアレイの上方に第1の相互接続層を形成するステップと、
前記第1の相互接続層の上方に第1のボンディング層を形成するステップであって、前記第1のボンディング層は、複数の第1のボンディングコンタクトを含む、ステップと、
前記第2の基板の上の前記ロジックプロセス互換型デバイスの上方に第2の相互接続層を形成するステップと、
前記第2の相互接続層の上方に第2のボンディング層を形成するステップであって、前記第2のボンディング層は、複数の第2のボンディングコンタクトを含む、ステップと
をさらに含む、請求項26から32のいずれか一項に記載の方法。 - 前記結合するステップは、前記第1のボンディング層および前記第2のボンディング層のハイブリッドボンディングを含み、前記第1のボンディングコンタクトが、ボンディング界面において前記第2のボンディングコンタクトと接触しているようになっている、請求項33に記載の方法。
- 前記第1の水素ブロッキング層の前記高k誘電材料は、酸化アルミニウムを含む、請求項26から34のいずれか一項に記載の方法。
- 前記第1の水素ブロッキング層の厚さは、約1nmから約100nmの間にある、請求項26から35のいずれか一項に記載の方法。
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