CN1525485A - 三维结构存储器 - Google Patents
三维结构存储器 Download PDFInfo
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- CN1525485A CN1525485A CNA2003101026369A CN200310102636A CN1525485A CN 1525485 A CN1525485 A CN 1525485A CN A2003101026369 A CNA2003101026369 A CN A2003101026369A CN 200310102636 A CN200310102636 A CN 200310102636A CN 1525485 A CN1525485 A CN 1525485A
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Abstract
一种三维结构(3DS)存储器(100)使得能够将存储器电路(103)和控制逻辑(101)物理上分离到不同的层(103)上,致使可以分别地优化各个层。几个存储器电路(103)有一个控制逻辑(101)就够了,从而降低了成本。3DS存储器(100)的制造涉及到将存储器电路(103)减薄到厚度小于50微米以及将电路键合到电路叠层,同时仍然呈晶片衬底形式。采用了细粒高密度层间垂直总线互连(105)。3DS存储器(100)制造方法使得能够实现几种性能和物理尺寸效能,并且是用现有的半导体工艺技术实现的。
Description
本申请是1998年4月3日提交、申请号为98803836.6、发明名称为“三维结构存储器”的发明专利申请的分案申请。
技术领域
本发明涉及到叠层集成电路存储器。
背景技术
提高电子电路性能和降低其成本的制造方法,毫无例外地是提高电路集成度和减小相等数量的诸如晶体管或电容器之类的电子器件所占据的物理尺寸的方法。这些方法已经生产了每秒钟能够运行一亿次的成本低于1000美元的1996微处理器和数据存储时间小于50毫微秒的成本低于50美元的64兆位DRAM电路。这种电路的物理尺寸小于2Gm2。这些制造方法很大程度上支撑着主要工业化国家的经济生活标准,并在全球人民的日常生活中肯定会继续具有重大影响。
电路制造方法有二种主要形式:工艺集成和装配集成。历史上,这二种制造科目之间的界线是很清楚的,但随着MCM(多芯片模块)和倒装片管芯安装的使用的出现,这一清晰的分隔可能会很快地消失。(相对于例如封装形式中的集成电路,此处的术语“集成电路(IC)”主要是用于切自半导体晶片之类的电路衬底的单个管芯中的集成电路)。在初期的管芯形式中,大多数IC现在是单独封装的,但越来越多地使用MCM。MCM中的管芯通常用诸如金属丝键合、DCA(直接芯片安装)或FCA(倒装片安装)之类的常规IC管芯I/O互连键合方法,以平面形式被安装到电路衬底。
诸如DRAM、SRAM、快速EPROM、EEPROM、铁电存储器、GMR(巨磁阻)之类的集成电路存储器,具有共同的结构特性,即与控制电路单片集成在同一个具有存储器阵列电路的管芯上。对于大存储器电路,这样构成的(标准或常规的)结构即电路布局结构就在控制电路与存储器阵列电路之间产生了设计折中限制。制造过程中存储器单元电路的几何尺寸的减小已经导致了密度越来越高的存储器IC,但这种更高的存储器密度已经导致了以牺牲更大的IC面积为代价的更尖端的控制电路。更大的IC面积至少意味着单位IC的更高的制造成本(每个晶片的IC更少)以及更低的IC成品率(每个晶片可工作的IC更少),而在最坏的情况下,由于成本无竞争性或运行不可靠而导致无法制造的IC设计。
随着存储器密度的增大和单个存储器单元尺寸的减小,需要更多的控制电路。在诸如DRAM之类的某些情况下,存储器IC的控制电路所占IC面积的百分数接近或超过40%。一部分控制电路是读出放大器,它在读出操作过程中对存储器阵列电路中的存储器单元的状态、电位或电荷进行读出。读出放大器电路是控制电路的主要部分,改善读出放大器的灵敏度,以便读出甚至更小的存储器单元同时又防止读出放大器所用的面积变得太大,是对IC存储器设计者的一个永恒的挑战。
如果没有这一控制电路和存储器电路之间的限制或折中,则能够将控制电路制造成执行大量的额外功能,诸如对每个存储器单元进行多重存储状态的读出、通过更灵敏的读出放大器进行更快的存储器存取、超高速缓存、刷新、地址转换等等。但这一折中是目前所有制造厂家所制造的存储器IC的物理的和经济的现实。
DRAM电路的容量每代之间以4倍的因子增加,例如1兆位,4兆位,16兆位,64兆位DRAM。电路存储器容量的这一每代4倍的增大,已经导致了越来越大的DRAM电路面积。在引入新一代DRAM的时候,电路成品率太低,因而大量制造是不合算的。在新一代DRAM的实验性样品出现的日期与大量生产这种电路的日期之间,通常要几年。
在本发明人的美国专利5354695中,公开了以叠层即三维(3D)方式来装配管芯,此处列为参考。而且,还试图以3D方式装配存储器管芯。德克萨斯州Dallas的德州仪器公司、加州Costa Mesa的IrvineSemsors以及加州Scotts Valley的Cubic Memory公司,都已试图生产叠层即3D DRAM产品。在所有三种情况下,管芯形式的常规DRAM都被层叠起来,并沿电路叠层的外表面制作叠层中各个DRAM之间的互连。这些产品已经销售几年了,并已证明对于商业应用来说是太昂贵了,但由于其物理尺寸即脚印(footprint)小,故在空间及军事应用中已经得到了一些应用。
DRAM电路类型被认为是并常常被用作本说明书的样品,然而,本发明显然不局限于DRAM类型电路。诸如EEPROM(电可擦可编程只读存储器)、快速EPROM、铁电存储器、GMR(巨磁阻)或这些存储器单元的组合之类的存储器单元类型,无疑也能够用于本三维结构(3DS)方法来制作3DS存储器器件。
本发明还有下列其它的目的:
1.比之仅仅用单片电路集成方法常规制造的电路,存储器每兆位的制造成本降低几倍。
2.比之常规制造的存储器电路,性能高几倍。
3.比之常规制造的存储器电路,单位IC的存储器密度高许多倍。
4.设计者对电路面积尺寸因而对成本的更大的控制权。
5.用内部控制器对存储器单元进行电路的动态和静态自测试。
6.动态错误恢复和重构。
7.每个存储器单元的多层存储。
8.虚拟地址变换、地址分屏(address windowing)、诸如间接寻址或按内容寻址的各种寻址功能、模拟电路功能、以及各种图象加速和微处理器功能。
发明内容
本3DS存储器技术是一种叠层即3D电路装配技术。其特点包括:
1.存储器电路与控制逻辑,物理上分隔在不同的层上;
2.几个存储器电路用一个控制逻辑;
3.存储器电路被减薄到厚度小于约50微米,形成一个具有平坦的加工过的键合表面的基本上柔软的衬底,并在仍然处于晶片衬底形式的情况下,将电路键合到电路叠层;以及
4.采用细粒高密度层间垂直总线连接。
3DS存储器制造方法使得能够实现几种功能和物理尺寸效能,并用现有的半导体工艺技术加以实现。以DRAM电路作为例子,用0.25微米工艺制造的64兆位DRAM可以具有84mm2的管芯尺寸、存储器面积对管芯尺寸的比率为40%、和约为50ns的对8兆位存储的存取时间;用同样的0.25微米工艺制造的3DS DRAM IC将具有18.6mm2的管芯尺寸,采用17层DRAM阵列电路,存储器面积对管芯尺寸的比率为94.4%,而对64兆位存储的存取时间可望小于10ns。3DS DRAM IC制造方法代表了相对于常规DRAM IC制造方法的每兆位成本的可观的几倍的降低。换言之,3DS存储器制造方法在基本结构层面上代表了与所用的工艺制造技术无关的十分重要的成本节省方法。
附图说明
结合附图,从下列描述中可以进一步了解本发明。在这些附图中:
图1a是用方法A或方法B制造的3DS DRAM IC的示意图,显示了与常规IC管芯相同的I/O键合焊点的物理状态;
图1b是3DS存储器IC的剖面图,示出了几个减薄了的电路层之间的金属键合互连;
图1c是面朝下键合和互连在一个较大的常规IC或另一个3DS IC上的3DS DRAM IC的示意图;
图2a示出了具有一组数据线总线即一个端口的3DS DRAM阵列电路块的物理布局;
图2b示出了具有二组数据线总线即二个端口的3DS DRAM阵列电路块的物理布局;
图2c示出了部分典型存储器控制器电路的物理布局;
图3示出了3DS DRAM阵列电路的物理布局,示出了(64)3DS DRAM阵列块各部分;
图4是减薄了的衬底中的普通3DS垂直互连或连接线的剖面图;
图5示出了用来向下选择栅线读出或写入选择的3DS存储器多路复用器的布局。
具体实施方式
参照图1a和图1b,3DS(三维结构)存储器器件100是一个所有电路层之间具有细粒垂直互连的集成电路叠层。如从图2a和图2b可见,术语“细粒层间垂直互连”被用来表示穿透电路层的导体,它具有或不具有插入的器件元件,且标称间距小于100微米,更典型是小于10微米,但不限制小于2微米的间距。细粒层间互连也起将各个电路层键合到一起的作用。如图1b所示,虽然键合和互连层105a和105b等最好是金属,但如以下更充分地所述,也可以使用其它材料。
键合和互连层105a和105b等中的图形107a和107b等,确定了集成电路各层之间的垂直互连接触,并用来使这些接触彼此电隔离以及与其余的键合材料电隔离;此图形在键合层中取空洞或介电质填充的间隔的形式。
3DS存储器叠层通常被组织成控制器101和数目一般为9-32个的存储器阵列电路层103,但对层数没有特别的限制。控制器电路是标称电路厚度(通常为0.5mm或更厚),但各个存储器阵列电路层是减薄了的基本上柔软的净应力低的电路,其厚度小于50微米,通常小于10微米。在最终的存储器阵列电路层上制作常规I/O键合焊点,以便用于常规封装方法。可以使用诸如插入互连(公开在本发明人的美国专利5323035和5453404中)、DCA(直接芯片安装)或FCA(倒装片安装)方法之类的其它金属图形。
细粒层间垂直互连还可以用于3DS存储器管芯与常规管芯(其中常规管芯可以是图1c所示的控制器电路)之间的或3DS存储器管芯与另一个3DS存储器管芯之间的直接单个管芯键合;应该设想的是,待要键合到一起的各个芯片的面积(尺寸)可以不同,不必完全相同。更确切地说,参照图1c,3DS DRAM IC叠层100被面朝下键合并互连在一个较大的常规IC或另一个3DS IC 107上。3DS叠层100也可以只由具有DRAM控制器电路作为较大管芯部分的DRAM阵列电路组成。若DRAM控制器电路是较大管芯部分,则可能要求细粒垂直总线互连(在3DS DRAM IC叠层100的表面109处)将3DS DRAM阵列电路连接到DRAM控制器,否则较大晶粒的常规互连可能进入(图形化)到整平了的键合层中。
如图3所示,各个存储器阵列电路层包括由存储器阵列块301(标称面积小于5mm2)组成的存储器阵列电路300,且各个块由存储器单元(以与DRAM或EEPROM电路的单元阵列很相似的方式)、总线电极、以及按设计者的意思用来选择存储器阵列的特定行或列的启动栅组成。控制电路由通常在诸如常规DRAM之类的单片设计的典型存储器电路的外围可能找到的读出放大器、地址、控制和驱动逻辑组成。
细粒总线独立于各个存储器阵列层垂直连接控制器,使控制器能够将驱动(功率)或启动信号提供给任一层而不影响其它任何一层的状态。这使控制器能够独立地对各个存储器电路层进行测试、读出或写入。
图2a和图2b示出了诸如图3的块301的存储器阵列的可能块的布局的例子。虽然只示出了块的一部分,但在所示的实施例中,各个块呈现横向对称,致使可以从所示的部分确定整个块的布局。各个参考号后面的缩写“T”、“L”和“TL”分别被用来表示“上”、“左”和“左上”,表示图中未示出的相应元件。
参照图2a,块的核心部分200由大量的存储器单元组成。逻辑上说,存储器单元集合可以再分成各含有例如由64兆位存储器单元组成的8×8阵列的“宏单元”201。在核心的外围制作了细粒垂直互连,它包含以下参照图4更详细地描述的层间键合和总线接触金属化400。细粒垂直互连包括I/O功率和接地总线203TL、存储器电路层选择205T、存储器宏单元列选择207T、数据线209L和栅线多路复用器(“mux”)选择209TL。在所示实施例中,栅线多路复用器211T是4∶1多路复用器,用来在8列宽的存储器宏单元列中选择4列中的1个。相应的下侧4∶1多路复用器与上侧多路复用器211T组合形成等效8∶1多路复用器,用来从8栅线宽的存储器宏单元列中选择一个栅线。
图5示出了4∶1栅线总线多路复用器5 00的一种实现。栅线启动209TL(例如制作在金属层1中)分别控制晶体管501a-501d。耦合到晶体管的是各个栅线503a-503d。同时部分可看到的是耦合到相应4∶1多路复用器(未示出)的栅线505a-505d。当一个栅线启动被激活时,相应的栅线被耦合到多路复用器(例如制作在金属层2中)的输出线507。输出线通过线509(例如制作在金属层3中且相应于垂直总线互连的金属接触400)和钨栓511和513,被连接到一个或更多个垂直总线接触。钨栓513将线509连接到垂直互连(未示出)。
再次参照图2a,在存储器电路层的情况下,此层也可以包括来自控制器层启动信号205T的输出线启动(栅),对其可以提供I/O启动(栅)213。
要注意的是,在存储器层面处,各个存储器块301与每个其它的存储器块301是电隔离的。因此,各个存储器块的成品率几率是独立的。
同可以增加额外的栅线垂直互连一样,可以增加额外的读出/写入端口;额外的垂直互连能够以冗余的方式被采用,以便改善垂直互连成品率。3DS存储器电路能够被设计成具有一个或更多个数据读出和写入总线端口互连。参照图2b,存储器块301’被示为具有端口P0(209L)和另一个端口P1(209L’)。对垂直互连数目的唯一限制是这种垂直互连加在电路成本上的杂项开支(overhead)。细粒垂直互连方法在仅仅增加百分之几的管芯面积的情况下,使每个块能够有上千的互连。
作为一个例子,图2b所示的具有二个读出/写入端口并在0.35微米或0.15微米设计规则中完成的4兆位DRAM存储器块的垂直互连的杂项开支由接近5000个连接组成,并小于存储器阵列块总面积的6%。因此,3DS DRAM电路中的每个存储器阵列电路层的垂直互连杂项开支小于6%。这显著小于目前在单片DRAM电路设计中遇到的非存储器单元面积能够超过40%的情况。在完成了的3DS DRAM电路中,非存储器单元面积的百分比通常小于叠层结构中所有电路总面积的10%。
3DS存储器器件去耦通常在单片存储器电路的存储器单元邻近发现的控制功能,并将它们分离到控制电路。控制功能不出现在常规存储器IC中的各个存储器阵列层上,而只在控制电路中出现一次。这就产生了一个节省的办法,使几个存储器阵列层共用同一个控制逻辑,因而比常规存储器设计降低了高达二倍的单位存储器单元的净成本。
控制功能向分立控制电路的分离,使得这种功能可以有更大的面积(即等于一个或几个存储器阵列块的面积)。功能的这一物理分离还使二个用于控制逻辑和存储器阵列的非常不同的制造工艺能够分离,再次实现了比之用于常规存储器的更复杂的组合逻辑/存储器制造工艺的额外制造成本的节省。存储器阵列也可以在不考虑控制逻辑功能的工艺要求的工艺技术中制造。这导致能够以低于目前存储器电路的成本来设计性能更高的控制器功能。而且,也可以用较少的工艺步骤来制造存储器阵列电路,标称降低存储器电路制造成本30%-40%(例如,在DRAM阵列的情况下,对于CMOS,工艺技术能够被限制到NMOS或PMOS晶体管)。
因此,虽然用热扩散金属键合方法使存储器控制器衬底和存储器阵列衬底的足够平坦的表面键合是比较好的,但在本发明的较广泛的情况下,本发明试图用诸如各向异性导电环氧树脂粘合剂之类的各种常规表面键合方法来键合分立的存储器控制器和存储器阵列衬底,以便形成二者之间的互连以提供随机存取数据存储。
参照图2c,示出了部分示范性存储器控制电路的布局。层间键合和总线金属化的图形与前述图2a的相同。然而,提供了例如包括读出放大器和数据线缓冲器215的存储器控制器电路来代替大量的存储器单元。由于增大了管芯的可用面积,故多层逻辑可以与读出放大器和数据线缓冲器215一起制造。还示出了地址译码器、栅线和DRAM层选择逻辑217、刷新和自测试逻辑219、ECC逻辑221、开屏逻辑(windowinglogic)223等。要注意的是,除了通常在DRAM存储器控制器电路中的功能外,还提供了自测试逻辑、ECC逻辑和开屏逻辑。依赖于管芯尺寸或使用的控制器电路的数目,也可以提供任何大量的其它功能,例如包括虚拟存储器安排、诸如间接寻址或内容寻址之类的地址功能、数据压缩、数据解压缩、声频编码、声频译码、视频编码、视频译码、声音识别、手写体识别、功率安排、数据库处理、图象加速功能、微处理器功能(包括加入一个微处理器衬底)等。
3DS存储器电路管芯的尺寸不依赖于对一个单层上的存储器单元和控制功能逻辑的必要数目的这一限制。这使电路设计者能够减小3DS电路管芯的尺寸或选择对电路成品率最佳的管芯尺寸。3DS存储器电路管芯尺寸主要是用来制造最终3DS存储器电路的存储器阵列块的尺寸和数目以及存储器阵列层的数目的函数。(如下所述,19层的0.25微米工艺的3DS DRAM存储器电路的成品率可以呈现为大于90%。)选择3DS电路管芯尺寸的这一优点,使得能够比常规单片电路设计可以在制造中更早地使用更先进的工艺技术。这当然意味着比常规存储器电路额外的成本降低和功能提高。
3DS存储器器件的制造方法
3DS存储器电路有二种基本的制造方法。但此二种3DS存储器制造方法具有共同的目的,即大量电路衬底被热扩散金属键合(也称为热压键合)到坚固的支持件即公共衬底上,此公共衬底本身也可以是电路的元件层。
支持件即公共衬底可以是标准的半导体晶片、石英晶片或能够适应3DS电路工艺步骤、电路运行和所使用的工艺设备的任何材料组分构成的衬底。支持衬底的尺寸和形状是最大限度优化可获得的制造设备和方法的一种选择。通过各种方法将电路衬底键合到支持衬底,然后进行减薄。电路衬底可以制作在标准的单晶半导体衬底上,或作为多晶电路制作在诸如硅或石英之类的适当的衬底上。
多晶硅晶体管电路具有重要的成本节约选择余地,即加入一个分离层(膜),使其上制作了多晶硅电路的衬底能够分离并重新使用。多晶硅晶体管或TFT(薄膜晶体管)器件被广泛地使用,也不一定仅仅由硅制成。
利用通常是铝的二个金属表面的热扩散,将3DS存储器电路的各个电路层键合到一起。待要键合的电路的表面是光滑的且足够平整,正如未被加工的半导体晶片或已经用CMP(化学机械工艺)方法整平过的已被加工过的半导体晶片的表面情况那样,至少在待要键合的电路(制作在衬底上)的表面区域上,表面平整度小于1mm,最好是小于1000埃。待要键合的电路表面上的金属键合材料被图形化成彼此成镜象,从而确定图2a、图2b、图2c和图5所示的各个垂直互连接触。键合二个电路衬底的步骤导致在二个电路层即衬底之间同时形成垂直互连。
电路层的热扩散键合最好在具有受控压力和诸如含有少量H2O和O2的N2气氛的设备工作室中进行。键合设备对准待要键合的衬底的图形,然后用一组编程压力和用作键合材料的金属的类型所要求的一定时间的一种或更多种温度,将它们压到一起。键合材料的标称厚度在500-15000埃的范围内或更大,最佳厚度为1500埃。根据键合图形的设计,衬底键合的开始阶段最后在例如1-740乇的负压这样的低于标准压力的情况下进行。这样可以在键合表面之间留下一个内部负压,一旦回到外部大气压力,这进一步有助于形成键合并增强键合的可靠性。
最佳的键合材料是纯铝或铝的合金,但不局限于铝,例如可以包括在可接受的温度和制作时间内提供可接受的表面键合扩散能力的诸如Sn、Ti、In、Pb、Zn、Ni、Cu、Pt、Au之类的金属或这些金属的合金。键合材料不局限于金属,可以是诸如高导电多晶硅之类的键合材料的组合,其中有些是诸如二氧化硅那样不导电,且上述示范性键合材料选择不应该认为是对如何键合电路层的限制。
在金属键合材料形成表面天然氧化物的情况下,这种氧化物或阻止形成满意的键合,或者还可能增大键合所形成的垂直互连的电阻,必须清除此氧化物。键合设备提供了降低氧化物的能力,使键合材料的键合表面没有天然氧化物。组成降低表面氧化物的气氛的方法是众所周知的,并且有其它的方法来清除天然氧化物,例如溅射腐蚀、等离子体腐蚀或离子研磨腐蚀。在铝被用作键合材料的情况下,最好在键合之前清除键合表面上大约40埃的天然氧化铝薄膜。
3DS存储器电路的减薄了的(基本上柔软的)衬底电路层通常是存储器阵列电路,但减薄了的衬底电路层不局限于存储器电路。其它的电路层类型可以是控制器电路、诸如EEPROM之类的非易失存储器、包括微处理器逻辑的额外的逻辑、以及诸如支持图象或数据库处理的专用逻辑功能等。这些电路层类型的选择遵照电路设计的功能要求而不受3DS存储器制造工艺的限制。
与常规存储器电路制造中更普通地使用的由较高应力的氧化硅和氮化硅组成的介电质相反,最好用诸如低应力的二氧化硅和氮化硅介电质之类的低应力(低于5×108达因/cm2)介电质来制造减薄了的(基本上柔软的)衬底电路。在本发明人的美国专利5354695中,详细地讨论了这种低应力介电质,此处列为参考。具有常规应力水平的介电质可以用于3DS DRAM电路的装配中,但若叠层装配件包含几层以上,则装配件中的各个层必须平衡应力,使层的淀积膜的净应力小于5×108达因/cm2。比之使用各个淀积膜的应力不相等但淀积成产生较低的净平衡应力的方法,采用本来就应力低的淀积膜是较好的方法。
方法A,3DS存储器器件的制造工序
本制造工序假设几个电路层将被键合到一个公共即支持衬底并接着就地减薄。得到的3DS存储器电路的一个例子示于图1a。
1.将第二电路衬底的上侧对准并键合到公共衬底。
2A.将第二电路衬底的背侧即暴露的表面研磨到厚度小于50微米,然后抛光即平滑表面。此减薄了的衬底现在是基本上柔软的衬底。
在器件制造之前,也可以在半导体表面以下在第二衬底中包含一个厚度从小于1微米到几微米的腐蚀停止层。此腐蚀停止层可以是外延制作的诸如GeB之类的薄膜(在本发明人的美国专利5354695和5323035中描述,此处列为参考)或低密度的O2或N2注入层,以便正好在第二衬底的上侧上的器件层下面形成掩埋氧化物或氮化物势垒腐蚀停止层。在初步研磨衬底背侧的主要部分之后,再在化学浴液中对第二衬底背侧的其余部分进行选择性腐蚀,此腐蚀停止于外延层或注入层的表面。如有需要,可以再用抛光和RIE步骤来完成第二衬底的减薄。
作为变通,在器件制造之前,诸如注入到第二衬底的上侧表面中的H2之类的分离层可以用于热处理步骤,以便裂开第二衬底背侧的大部分,使之能够重新利用。
2B.第二电路衬底也可以是能够被专用化学脱模剂激活的诸如铝、钛、AlAs、KBr之类的分离层上的由多晶硅晶体管或TFT组成的电路。然后,在激活(溶解)分离层时,清除第二衬底的背侧,如有需要,则随之以互连半导体工艺步骤。
3.对第二电路衬底的减薄了的背侧进行加工,以便形成诸如图4所示的具有第二衬底的被键合表面侧的垂直互连。背侧加工通常包含介电质和金属淀积物的常规半导体工艺步骤、光刻和RIE,其顺序可以变化很大。背侧加工的完成还将导致相似于上侧键合材料图形的图形化金属层,从而方便额外电路衬底、诸如常规I/O IC键合焊点(金属丝键合)图形的端子图形、3DS存储器电路到另一个管芯(另一个3DS电路或常规管芯)的热扩散键合图形、或用来插入互连、常规DCA(直接芯片安装)或FCA(倒装片安装)的图形的后续键合。
更确切地说,参照图4,当制造有源电路器件时,热生长或淀积一个氧化物掩模401。然后,例如与多晶硅栅制作步骤同时,从高掺杂的多晶硅制作垂直总线接触403。作为变通,接触403也可以用金属制作。然后用常规工艺制作常规DRAM互连结构410。DRAM互连可以包括内部焊点405。晶片的“DRAM加工的”部分420包括各种介电层和金属层。淀积最终钝化层407,之后制作通孔409。然后用常规CMP工艺来获得平坦的表面411。再在最上面的金属层(例如第3金属层)中,对未示出的接触413和键合表面进行图形化。
在将第二衬底的背侧键合并减薄到硅(或其它半导体)衬底415的大约1-8mm之后,对准接触403,制作馈通线417。然后制作钝化层419和接触421。可以制作接触421以便形成接触413的镜象,使其它晶片得以键合。
4.若另一个电路层要键合到3DS电路叠层,则重复步骤1-3。
5A.然后将完成的3DS存储器衬底常规地锯成管芯(单个的),得到图1a所示类型的电路,并如常规集成电路那样进行封装。
5B.然后将完成的3DS存储器衬底的电路常规地锯开,并以相似于上述步骤1键合电路衬底的方式,单个地对准并热扩散键合(金属图形向下)到第二(常规IC)管芯或MCM衬底的表面。(常规管芯或MCM衬底可以具有比3DS存储器衬底更大的面积,并可以包括图象控制器、视频控制器或微处理器,使3DS被埋置成为另一个电路的一部分。)这一最后键合步骤通常包括3DS存储器电路与管芯或MCM衬底之间的细粒互连,但也可以使用常规的互连图形。3DS存储器电路还可以面朝上键合到管芯形式的常规IC或MCM衬底和用来形成常规I/O互连的金属丝键合。
方法B,3DS存储器器件的制造工序
本制造工序假设电路衬底首先被键合到一个传送衬底,进行减薄,然后键合到公共衬底成为电路叠层。然后分离传送衬底。此方法相对于方法A具有下述优点,即衬底在被键合到最终电路叠层之前能够被减薄,而且能够对衬底电路层同时进行减薄和垂直互连加工。
1.用脱模层即分离层将第二电路衬底键合到传送衬底。传送衬底可以具有高公差的平行表面(总厚度变化TTV小于1微米),并可以穿一系列的小孔以协助分离过程。分离层可以是平铺淀积的键合金属。不要求表面精确对准。
2.执行方法A的步骤2A或2B。
3.加工第二衬底的背侧,以形成图4所示的具有第二衬底的键合上侧表面的互连。背侧加工通常包含介电质和金属淀积物的常规半导体工艺步骤、光刻和RIE,其顺序可以变化很大。背侧加工的完成还将导致相似于公共衬底的键合材料图形的图形化金属层,从而方便额外电路层的后续键合。
4.将第二电路键合到公共衬底即支持衬底(3DS叠层),并借助于激活它与第二电路之间的分离层而分离传送衬底。
5.加工第二衬底现在暴露的上侧,以便形成后续衬底键合的互连或常规I/O键合(金属丝键合)焊点图形的端子图形、3DS存储器电路到另一个管芯(另一个3DS电路或常规管芯)的热扩散键合图形、或用于常规插入互连、DCA(直接芯片安装)或FCA(倒装片安装)的图形。若另一个电路层要键合到3DS电路叠层,则重复步骤1-4。
6.执行方法A的步骤5A或5B。
提高3DS存储器器件的成品率的方法
3DS电路可以被认为是一种垂直装配的MCM(多芯片模块),且其最终成品率为完成的3DS电路中各个组成电路(层)的成品率几率的乘积。3DS电路采用几种提高成品率的方法,这些方法在单个存储器IC中的组合应用中是叠加的。用在3DS存储器电路中的提高成品率的方法包括:小的存储器阵列块尺寸、通过物理地孤立即分离垂直总线互连而使存储器阵列块电隔离、备用内部存储器阵列块栅线、备用存储器阵列层(备用块间栅线)、备用控制器以及ECC(错误纠正码)。术语“备用”被用来表示用冗余的元件来替代。
存储器阵列块的选定的尺寸是3DS存储器电路成品率公式中的首要组成部分。各个存储器阵列块被单独地(唯一地)存取,并由控制器电路供电,因此,除了与不同存储器阵列层上的存储器阵列块之外,还与包括同一个存储器阵列层上的存储器阵列块的每个其它存储器阵列块,彼此物理上独立。存储器阵列块的尺寸通常小于5mm2,最好是小于3mm2,但不局限于具体的尺寸。存储器阵列块的尺寸、其NMOS或PMOS制造工艺的简化、以及它与其它存储器阵列块之间的物理独立性,为几乎所有的制造IC的工艺提供了大于99.5%的保守估计的标称成品率。这一成品率假定存储器阵列块中的诸如互连线断开或短路之类的大多数点缺陷或失效的存储器单元可以由块内或块间的冗余栅线备用(替代)。使完成的存储器阵列块无法使用的存储器阵列块中的大多数缺陷,导致用冗余存储器阵列层完全替代此块,否则就废弃此3DS电路。
在3DS DRAM电路例子中,存储器阵列块叠层的成品率由下列成品率公式计算:
Ys=((1-(1-Py)2)n)b
其中n是DRAM阵列的层数,b是每个DRAM阵列的块数,Py是小于3mm2的DRAM阵列块的有效成品率(几率)。假设在DRAM阵列块线和一个冗余DRAM阵列层中的栅线的DRAM阵列块冗余量为4%,并进一步假设每层的块数为64,叠层中的存储器阵列层数为17,且Py的有效值为0.995,则整个存储器阵列(包括所有存储器阵列块叠层)的叠层成品率Ys为97.47%。
然后将存储器阵列的叠层成品率Ys乘以控制器的成品率Yc。假设管芯尺寸小于50mm2,由0.5微米BiCMOS或混合信号工艺制造的控制器的合理Yc在65%-85%之间,则给出3DS存储器电路的净成品率在63.4%-82.8%之间。若冗余的控制器电路层被添加到3DS存储器叠层中,则成品率几率可以在85.7%-95.2%之间。
借助于可选地使用ECC逻辑,能够进一步提高存储器阵列块的有效成品率。ECC逻辑对某些数据位组的数据位错误进行纠正。运行ECC逻辑所必须的出错位组的各个位可以存储在垂直相关的块叠层中的任何一个存储器阵列层的冗余栅线上。如有需要,为了适应ECC出错位组各个位的存储,还可以将额外的存储器阵列层加入到电路中。
先进的3DS存储器器件控制器的能力
比之常规存储器电路,3DS存储器控制器电路由于控制器电路能够有额外的面积以及可以得到各种混合信号工艺制造技术,而可以具有各种优越的能力。某些这种能力是具有动态栅线地址分配的存储器单元的自测试、虚拟地址转换、可编程地址开屏或绘图、ECC、数据压缩和多层存储。
动态栅线地址分配是利用可编程栅来启动读出/写入操作的层和栅线。这使存储器存储的物理顺序能够分离或不同于存储的存储器的逻辑顺序。
对各代存储器器件进行的测试已经导致了明显增大了的测试成本。借助于组合足够的控制逻辑以执行各个存储器阵列块的内部测试(自测试),3DS存储器控制器降低了测试成本。按常规ATE方式的电路测试仅仅要求验证控制器电路的功能。内部测试的范围还被延伸到对应于各层上各个存储器阵列块的各个栅线的唯一地址的可编程(动态)分配。借助于重构(替代)在产品中使用3DS存储器电路之后失效的栅线的地址,在3DS存储器电路作为诊断工具和提高电路可靠性的方法的寿命期内的任何时候,都能够使用3DS控制器电路的自测试能力。
ECC是一种电路能力,即如果包括在控制器电路中,它被可编程信号能够启动或关断,或形成一种专用功能。
数据压缩逻辑能够提高可存储在3DS存储器阵列中的数据总量。存在着可用于此目的的各种各样的通常熟知的数据压缩方法。
较大的读出放大器具有较大的动态性能,并能够从存储器单元中进行更高速的读出操作。较大的读出放大器可望提供在每个存储器单元中存储多于一位的信息(多层存储)的能力;在诸如快速EPROM之类的非易失存储器电路中已经表现了这种能力。多层存储也已经被提出用于4千兆位DRAM一代的电路中。
对本技术领域熟练人员来说,显然,本发明可以体现在其它的具体形式中而不超越其构思和主旨特征。因此,此处公开的实施例被认为是说明性的而不是限制性的。本发明的范围由所附权利要求而不是由上述描述来表示,且其等效意义和范围内的改变都被认为包括在其中。
Claims (88)
1.一种叠层集成电路存储器,它包含:
其上制作有存储器电路和存储器控制器电路中的一个的基本上坚固的第一衬底;
至少一个其上制作有所述存储器电路和所述存储器控制器电路中的另一个并键合到第一衬底的基本上柔软的衬底;以及
将第一衬底和基本上柔软的衬底键合在一起的粘合剂,所述粘合剂具有与较高温度的半导体工艺相容的承受温度。
2.权利要求1的装置,其中的第一衬底上制作有存储器电路,并且是存储器电路衬底叠层的一部分,而第二衬底上制作有存储器控制器电路。
3.权利要求2的装置,其中第一和第二衬底是单个的管芯,第二衬底的面积大于第一衬底的面积。
4.权利要求3的装置,其中第二衬底上制作有与存储器控制器电路分隔的额外的电路。
5.权利要求4的装置,其中额外的电路是图象显示子系统的一部分。
6.权利要求4的装置,其中额外的电路包含微处理器。
7.权利要求1的装置,其中基本上柔软的衬底包括存储器I/O焊点。
8.权利要求7的装置,其中存储器电路制作在基本上柔软衬底的上表面附近,所述上表面被键合到第一衬底,而所述存储器I/O焊点制作在基本上柔软衬底的相反的底表面附近。
9.权利要求1的装置,其中存储器电路与存储器控制器电路由垂直互连耦合。
10.权利要求9的装置,其中所述垂直互连包括以小于100μm间距制作的细粒垂直互连。
11.权利要求10的装置,其中至少某些细粒垂直互连排列成二维。
12.权利要求10的装置,其中所述存储器电路包含存储器块的二维阵列,各个存储器块附近制作有细粒垂直互连阵列,形成将存储器块耦合到存储器控制器的第一端口。
13.权利要求12的装置,其中至少某些存储器块附近制作有细粒垂直互连阵列,形成将存储器块耦合到存储器控制器的第二端口。
14.权利要求1的装置,其中至少一个所述存储器电路提供了冗余存储器位置。
15.权利要求14的装置,还包含其上制作冗余存储器电路的额外的基本上柔软的衬底。
16.权利要求15的装置,其中存储器控制器电路包含ECC逻辑并被编程以便在冗余存储器电路中存储ECC出错位组。
17.权利要求14的装置,其中存储器控制器电路包含用来测试存储器电路的逻辑。
18.权利要求17的装置,其中存储器控制器电路被编程,以便用冗余存储器位置取代存储器电路中有缺陷的存储器位置。
19.权利要求1的装置,其中存储器控制器电路包含用来执行至少一个下列功能的逻辑:虚拟存储器管理、间接寻址、内容寻址、数据压缩、数据解压缩、图形加速、声频编码、声频译码、视频编码、视频译码、语音识别、手写体识别、电源管理、数据库处理。
20.权利要求1的装置,还包含其上制作有冗余存储器控制器的键合到基本上柔软的衬底的衬底。
21.权利要求1的装置,还包含其上制作有微处理器的键合到基本上柔软的衬底的衬底。
22.权利要求1的装置,其中的存储器控制器电路包含耦合到存储器电路的数据线的读出放大器。
23.权利要求22的装置,其中的读出放大器识别二个以上的信号电平,每个读出放大器产生多级输出信号。
24.权利要求22的装置,其中的读出放大器的尺寸做成使开关速度约为10ns或更小。
25.权利要求1的装置,其中所述存储器控制器电路采用特征在于特殊的淀积顺序的半导体工艺技术制造,并且所述存储器电路采用特征在于不同的淀积顺序的不同工艺技术制作。
26.权利要求25的装置,其中所述不同的工艺技术选自由DRAM、SRAM、FLASH、EPPOM、EEPROM、铁电和巨磁阻组成的组。
27.权利要求8的装置,其中所述上表面和所述基本上坚固的第一衬底都包含互连金属化和非互连金属化,并且通过热扩散键合来键合在一起,从而热扩散键合同时经由所述互连金属化实现的电互连以及经由所述非互连金属化实现的机械键合。
28.一种叠层集成电路存储器,它包含:
其上制作有存储器电路和存储器控制器电路中的一个的基本上坚固的第一衬底;
至少一个其上制作有所述存储器电路和所述存储器控制器电路中的另一个的基本上柔软的被键合到第一衬底的衬底;以及
进入并在第一衬底和基本上柔软的衬底之间延伸的、致密的细粒垂直互连二维阵列,互连在所述第一衬底和基本上柔软的衬底上形成的集成电路。
29.权利要求28的装置,其中的第一衬底上制作有存储器电路,并且是存储器电路衬底叠层的一部分,而第二衬底上制作有存储器控制器电路。
30.权利要求28的装置,其中基本上柔软的衬底包括存储器I/O焊点。
31.权利要求28的装置,其中存储器电路和存储器控制器电路通过垂直互连耦合。
32.权利要求28的装置,其中所述存储器电路中的至少一个提供冗余存储位置。
33.权利要求28的装置,其中存储器控制器电路包含用来执行至少一个下列功能的逻辑:虚拟存储器管理、间接寻址、内容寻址、数据压缩、数据解压缩、图形加速、声频编码、声频译码、视频编码、视频译码、语音识别、手写体识别、电源管理、数据库处理。
34.权利要求28的装置,还包含其上制作有冗余存储器控制器的键合到基本上柔软的衬底的第二衬底。
35.权利要求28的装置,还包含其上制作有微处理器的键合到基本上柔软的衬底的第二衬底。
36.权利要求28的装置,其中的存储器控制器电路包含耦合到存储器电路的数据线的读出放大器。
37.一种集成电路结构,它包含:
第一衬底;以及
键合到所述第一衬底上的第二衬底,从而在所述第一衬底和所述第二衬底之间形成导电路径,其中所述第二衬底是其上形成有电路的经减薄的衬底。
38.权利要求37的装置,其中第二衬底是经减薄的单晶半导体衬底和经减薄的多晶半导体衬底中的一种。
39.权利要求37的装置,其中在第二半导体上形成的电路是有源电路和无源电路中的一种。
40.权利要求37的装置,其中在第二衬底上形成的电路由有源电路和无源电路二者组成。
41.权利要求37的装置,其中第一衬底是其上形成有电路的衬底。
42.权利要求41的装置,其中第一衬底的电路是有源电路和无源电路中的一种。
43.权利要求41的装置,其中在第一衬底上形成的电路同时包括有源电路和无源电路。
44.权利要求37的装置,还包括其上形成有电路的至少一个额外的经减薄的衬底,所述电路键合到所述第二衬底或邻近的额外的经减薄的衬底中的一个上,从而在所述至少一个额外的经减薄的衬底和所述第二衬底或所述邻近的额外的经减薄的衬底中的一个之间形成导电路径。
45.权利要求44的装置,其中第一、第二和所述至少一个额外的经减薄的衬底之中的至少两个采用不同的工艺技术制造,其中所述不同的工艺技术选自由DRAM、SRAM、FLASH、EPPOM、EEPROM、铁电和巨磁阻组成的组。
46.权利要求4 4的装置,其中第一、第二和所述至少一个额外的经减薄的衬底中的至少一个包括微处理器。
47.权利要求44的装置,其中:
第一、第二和所述至少一个额外的经减薄的衬底中的至少一个衬底其上形成有存储器电路;以及
第一、第二和所述至少一个额外的经减薄的衬底中的至少一个衬底其上形成有逻辑电路,所述逻辑电路对其上形成有存储器电路的至少一个衬底进行测试。
48.权利要求44的装置,其中第一、第二和所述至少一个额外的经减薄的衬底中的至少一个衬底其上形成有存储器电路,所述存储器电路具有多个存储器位置,其中多个存储器位置中的至少一个存储器位置作为备用,并且其中来自其上形成有存储器电路的所述至少一个衬底上至少一个存储器位置的数据用来代替来自其上形成有存储器电路的所述至少一个衬底上有缺陷的存储器位置的数据。
49.权利要求44的装置,其中:
第一、第二和所述至少一个额外的经减薄的衬底中的至少一个衬底其上形成有存储器电路;以及
第一、第二和所述至少一个额外的经减薄的衬底中的至少一个衬底其上形成有逻辑电路,所述逻辑电路对其上形成有存储器电路的所述至少一个衬底进行可编程栅线地址分配。
50.权利要求44的装置,还包括横跨第一、第二和所述至少一个额外的经减薄的衬底中的所述至少一个衬底的多个内垂直互连。
51.权利要求4 4的装置,其中对在第一、第二和所述至少一个额外的经减薄的衬底中的至少两个的电路之间发送的数据进行信息处理。
52.权利要求44的装置,其中第一、第二和所述至少一个额外的经减薄的衬底中的至少一个具有重构电路。
53.权利要求44的装置,其中第一、第二和所述至少一个额外的经减薄的衬底中的至少一个其上形成有逻辑电路,用于执行至少一个下列功能的逻辑:虚拟存储器管理、ECC、间接寻址、内容寻址、数据压缩、数据解压缩、图形加速、声频编码、声频译码、视频编码、视频译码、语音识别、手写体识别、电源管理、数据库处理。
54.权利要求44的装置,还包括:
具有多个存储器存储单元、多个数据线和多个栅线的存储器阵列,每个存储器存储单元存储数据值,并具有响应接收来自多个栅线中的一个的栅控制信号而将数据值耦合到所述多个数据线中的一个的电路;
响应接收地址产生栅控制信号、包括用于将地址映射到栅线的装置的电路;以及
确定多个存储器单元中的一个是否有缺陷、并改变所述映射从而去除对多个存储单元中的所述有缺陷的一个的访问的控制器。
55.权利要求44的装置,还包括:
其上形成有逻辑电路的至少一个控制器衬底;
其上形成有存储器电路的至少一个存储器衬底;
在每一个存储器衬底上的多个数据线和多个栅线;
在每个存储器衬底上的存储单元阵列,每个存储单元存储数据值,并且具有响应选择多个栅线中的一个而将数据值耦合到所述多个数据线中的一个的电路;
启动用于存储器操作的栅线的栅线选择电路,其中所述栅线选择电路具有可编程栅以接收对所述多个栅线中的至少一个栅线的地址分配,并且其中对于各个可编程地址分配选择用于确定所述多个栅线中哪一个被选择的地址分配;以及
控制器衬底逻辑,所述控制器衬底逻辑确定存储器单元阵列中的一个存储单元是否有缺陷,并改变所述多个栅线的地址分配从而去除对导致有缺陷的存储单元将数据值耦合到所述多个数据线中的一个的访问。
56.权利要求55的装置,其中所述控制器衬底逻辑:
测试存储单元阵列以确定所述存储单元阵列中的一个是否有缺陷;并且
去除对导致所检测的有缺陷的存储单元将数据值耦合到所述多个数据线的栅线的地址分配的访问。
57.权利要求55中的装置,还包括:
可编程逻辑,从而在栅线导致所检测的有缺陷的存储单元将数据值耦合到所述多个数据线时防止使用来自所述多个数据线的数据值。
58.权利要求55的装置,其中存储单元阵列按物理次序排列在物理空间内,并且按逻辑次序排列在地址空间内,并且其中至少一个存储单元的物理次序不同于所述至少一个存储单元的逻辑次序。
59.权利要求55的装置,其中:
所述至少一个控制器衬底的逻辑电路由外部装置进行测试;并且
所述至少一个存储器衬底由所述至少一个控制器衬底的逻辑电路进行测试,其中所述测试实现所述存储单元阵列的基本部分的功能测试。
60.权利要求55的装置,其中所述至少一个控制器衬底的逻辑电路进行所述存储单元阵列的基本部分的功能测试。
61.权利要求55的装置,其中所述控制器衬底逻辑进一步配置成:
防止使用至少一个有缺陷的栅线;并且
由对采用备用栅线寻址的备用存储单元的访问代替对采用有缺陷的栅线寻址的存储单元的访问。
62.权利要求55的装置,其中控制器衬底逻辑进一步配置成防止使用至少一个有缺陷的栅线。
63.权利要求55的装置,其中所述至少一个控制器衬底的逻辑电路进行所述至少一个存储器衬底的所述存储单元阵列的全部功能测试。
64.权利要求37的装置,其中所述第一衬底是非半导体材料。
65.一种叠层集成电路存储器,它包含:
其上制作有存储器电路和存储器控制器电路中的一个的基本上坚固的第一衬底;以及
至少一个其上制作有所述存储器电路和所述存储器控制器电路中的另一个的基本上柔软的被键合到第一衬底的衬底。
66.权利要求65的装置,其中的第一衬底上制作有存储器电路,并且是存储器电路衬底叠层的一部分,而第二衬底上制作有存储器控制器电路。
67.权利要求66的装置,其中第一和第二衬底是单个的管芯,第二衬底的面积大于第一衬底的面积。
68.权利要求67的装置,其中第二衬底上制作有与存储器控制器电路分隔的额外的电路。
69.权利要求68的装置,其中额外的电路是图象显示子系统的一部分。
70.权利要求68的装置,其中额外的电路包含微处理器。
71.权利要求65的装置,其中基本上柔软的衬底包括存储器I/O焊点。
72.权利要求71的装置,其中存储器电路制作在柔软衬底的上表面附近,上表面被键合到第一衬底,而存储器I/O焊点制作在柔软衬底的相反的底表面附近。
73.权利要求65的装置,其中存储器电路与存储器控制器电路由垂直互连耦合。
74.权利要求73的装置,其中所述垂直互连包括以小于100μm间距制作的细粒垂直互连。
75.权利要求74的装置,其中至少某些细粒垂直互连排列成二维。
76.权利要求74的装置,其中所述存储器电路包含存储器块的二维阵列,各个存储器块附近制作有细粒垂直互连阵列,形成将存储器块耦合到存储器控制器的第一端口。
77.权利要求76的装置,其中至少某些存储器块附近制作有细粒垂直互连阵列,形成将存储器块耦合到存储器控制器的第二端口。
78.权利要求65的装置,其中至少一个所述存储器电路提供了冗余存储器位置。
79.权利要求78的装置,还包含其上制作冗余存储器电路的额外的基本上柔软的衬底。
80.权利要求79的装置,其中存储器控制器电路包含ECC逻辑并被编程以便在冗余存储器电路中存储ECC出错位组。
81.权利要求78的装置,其中存储器控制器电路包含用来测试存储器电路的逻辑。
82.权利要求81的装置,其中存储器控制器电路被编程,以便用冗余存储器位置取代存储器电路中有缺陷的存储器位置。
83.权利要求65的装置,其中存储器控制器电路包含用来执行至少一个下列功能的逻辑:虚拟存储器管理、间接寻址、内容寻址、数据压缩、数据解压缩、图形加速、声频编码、声频译码、视频编码、视频译码、语音识别、手写体识别、电源管理、数据库处理。
84.权利要求65的装置,还包含其上制作有冗余存储器控制器的键合到基本上柔软的衬底的第二衬底。
85.权利要求65的装置,还包含其上制作有微处理器的键合到基本上柔软的衬底的第二衬底。
86.权利要求65的装置,其中的存储器控制器电路包含耦合到存储器电路的数据线的读出放大器。
87.权利要求86的装置,其中的读出放大器识别二个以上的信号电平,每个读出放大器产生多级输出信号。
88.权利要求86的装置,其中的读出放大器的尺寸做成使开关速度约为10ns或更小。
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CN2003101026369A Expired - Fee Related CN1525485B (zh) | 1997-04-04 | 1998-04-03 | 叠层集成电路存储器 |
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- 1998-04-03 KR KR1020057018170A patent/KR100785821B1/ko not_active IP Right Cessation
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- 1998-04-03 WO PCT/US1998/006861 patent/WO1998045130A1/en not_active Application Discontinuation
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2000
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