TW201532235A - 使用重建晶圓與可測試之區域陣列之微小間距的焊孔陣列〈ｂｖａ〉 - Google Patents

使用重建晶圓與可測試之區域陣列之微小間距的焊孔陣列〈ｂｖａ〉 Download PDF

Info

Publication number
TW201532235A
TW201532235A TW104101608A TW104101608A TW201532235A TW 201532235 A TW201532235 A TW 201532235A TW 104101608 A TW104101608 A TW 104101608A TW 104101608 A TW104101608 A TW 104101608A TW 201532235 A TW201532235 A TW 201532235A
Authority
TW
Taiwan
Prior art keywords
microelectronic
connector
package
component
conductive
Prior art date
Application number
TW104101608A
Other languages
English (en)
Inventor
Rajesh Katkar
Original Assignee
Invensas Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Invensas Corp filed Critical Invensas Corp
Publication of TW201532235A publication Critical patent/TW201532235A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H01L21/566—Release layers for moulds, e.g. release layers, layers against residue during moulding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

本發明揭露一種針對同時製造複數微電子封裝之方法，其係藉由沿著載體上的複數微電子元件附著區域，以形成導電重分佈結構。複數附著區域係彼此相隔開以及覆蓋載體。方法也包含在相鄰的附著區域之間的導電連接器元件之形成。每一連接器元件係具有相鄰於第一端部或第二端部的載體以及位於微電子元件之一高度的另一端部。此方法也包含在連接器元件之一部分上形成密封體，並隨後將組件單一化成包含微電子元件的微電子單元。微電子單元之與重分佈結構相對設置之表面，其具有微電子元件之工作面以及連接器元件之自由端部，使得兩者能與微電子單元外部的裝置相連接。

Description

使用重建晶圓與可測試之區域陣列之微小間距的焊孔陣列(BVA)
本發明技術係相關於應用於微電子封裝的結構。
如複數半導體晶片之微電子裝置，通常需要許多輸入以及輸出連接至其他的電子元件。半導體晶片或其他類似裝置的輸入以及輸出接觸點通常設置為網格狀圖案，以實質上覆蓋裝置之表面(通常被稱為“區域陣列”)，或以延長列線設置，其可平行延伸且相鄰延伸至裝置的前表面的每個邊緣或前表面的中心內。通常，裝置(例如晶片)必須實體安裝於基板(例如印刷電路板)上，而裝置的接觸點必須電性連接電路板的導電體。
半導體晶片通常設置於封裝體內，以利於在製造過程中以及在將晶片安裝到外部基板(例如電路板或其他電路板)上的過程中處理晶片。例如，多個半導體晶片係設置在適合表面安裝(surface mounting)的封裝內。此型態的封裝已在各種應用中大量提出。最常見的，此類封裝包含通常被稱為“晶片載體(chip carrier)”的介電元件，其具有在介質上形成電鍍 的或蝕刻的金屬結構的端部。這些端部通常係例如藉由沿著其晶片載體延伸的細線路，以及藉由在晶片之接觸部以及端部或線路之間延伸的細導線或電線，以連接至其晶片的接觸點。在表面安裝操作上，封裝體係設置於電路板上，使得封裝上的每一端部係對準位於電路板上的相對應的接觸墊片。在端部以及接觸墊片之間提供焊料或另一接合材料。對組件加熱以熔化或“回流”焊料或以其他方式激活接合材料，使得封裝體可永久性接合在其位置上。
許多封裝體包含呈焊料球體型態的焊料塊，其直徑通常大約為0.1mm以及大約為0.8mm(5以及30mils)，其係附著至封裝之端部上。具有突出於其底部表面的焊料球體之陣列的封裝體通常被稱為球體柵格陣列或“BGA”封裝。其他被稱為平面柵格陣列或“LGA”的封裝體係藉由焊料所形成的薄膜或焊盤，以固定至基板上。此種型態的封裝體可以是相當薄的。通常被稱為“晶片級封裝”的特定封裝體所佔據電路板之一面積係相同於或僅稍微大於整合於封裝體內的元件之面積。其優勢在於可減少組件整體大小以及允許基板上的各種裝置之間使用短的相互連接，進而限制裝置之間的訊號傳輸時間，因此有利於組件進行高速操作。
封裝好的半導體晶片時常以“堆疊”排列，例如一封裝體係提供至電路板上，而另一封裝體係安裝至第一封裝體的頂面上。這些排列可允許多個不同的晶片安裝於電路板上的單一腳位內，並可更進一步藉由封裝體之間短的相互連接(interconnect)以進行高速的操作。通常，此種互聯距離係僅稍微大於其晶片的厚度。為了實現在晶片封裝體堆疊內互聯，必須在每一封裝體之兩側上提供用於機械連接以及電性連接的結構(除了最 上層封裝之外)。例如，藉由在安裝的晶片的基板之兩側上提供接觸墊片或焊盤，墊片係藉由多個導電孔或其相似物穿透連接至基板，以實現上述結構。焊料球體或其相似物已經用於將位於較低的基板之頂部上的多個接觸點之間的間隙橋接至位於較高的基板之底部上的多個接觸點。為了連接的多個接觸點，焊料球體必須高於晶片之高度。在美國專利公開文件，其公開號2010/0232129(以下簡稱’129公開文件)中，已經揭露上述的內容。
儘管在本領域的技術中已有上述的發展，但在微電子單元的製造以及測試上應當期望有更進一步的改進。
為解決上述問題，本發明提供一種微電子封裝。此微電子封裝係具有第一側面、第二側面、一微電子元件以及一覆蓋微電子元件之側壁的密封體。微電子封裝在其正面上可具有複數導電元件，這些導電元件可在封裝之第一側面上與微電子封裝外部的裝置相連接。微電子封裝可具有導電連接器元件，此導電連接器元件可具有與封裝之第一側面或第二側面相鄰的端部。連接器元件可在其第一端部以及第二端部之間與密封體相接觸，並可用以將位置低於第一側面的第一外部裝置電性耦接位於第二側面上方的第二外部裝置。
本發明再提供一種同時製造複數微電子封裝的方法，其可包含下列步驟：在載體上提供一導電重分配佈結構，並在平行載體之一表面的至少一第一方向上，提供彼此相隔開的複數微電子元件附著區域。本發明之方法可包含在相鄰的附著區域之間形成複數導電連接器元件。每一 連接器元件可具有第一端部、第二端部以及邊緣表面，第一端部可相鄰於載體，第二端部可位於該載體上方的一50微米之高度處。本發明之方法也可包含在連接器元件之邊緣表面之部分上形成介電密封體，並隨後將組件單一化成複數微電子單元。每一微電子單元可包含至少一微電子元件，任一微電子元件係與另一微電子元件上堆疊或側堆疊。微電子單元之與重分佈結構相對的表面係為微電子元件之正面，連接器元件之第二端部能與微電子單元外部的裝置相連接。
本發明再提供一種同時製造複數微電子封裝之方法，其可 包含下列步驟：在一載體上提供複數微電子元件附著區域，此複數微電子元件附著區域在平行於載體之表面的至少一第一方向上係彼此相隔開。接著，在相鄰的複數附著區域之間形成複數導電連接器元件。每一連接器元件可具有第一端部、第二端部以及邊緣表面。每一連接器元件之第一端部可相鄰於載體，而每一連接器之第二端部可位於該載體上方的50微米之高度處。此方法也可包含將複數微電子元件附著到載體上的個別附著區域上。 每一微電子元件係具有一正面、一背面以及複數側壁，此正面係具有接觸部且可面向載體。此方法可包含在連接器元件之邊緣表面之至少一部分上形成介電密封體。接著，可形成一導電重分佈結構，其係覆蓋密封體之相對於微電子元件之正面的至少一表面。重分佈結構可耦接連接器元件之第二端部，並可具有在第一方向或橫向方向上延伸的線路。單一化步驟係通常對複數微電子單元執行，每一微電子單元係包含一微電子元件。在每一產生的微電子單元內，微電子元件之第一表面以及連接器元件之第一端部可與微電子單元外部的裝置相連接。
8‧‧‧重建組件
10‧‧‧微電子單元
11‧‧‧第一側面
12‧‧‧微電子元件
13‧‧‧載體
14‧‧‧連接器元件
14A‧‧‧連接器元件
14B‧‧‧連接器元件
14C‧‧‧連接器元件
14D‧‧‧連接器元件
14E‧‧‧連接器元件
14F‧‧‧連接器元件
14G‧‧‧連接器元件
14H‧‧‧連接器元件
14I‧‧‧連接器元件
14J‧‧‧連接器元件
14K‧‧‧連接器元件
14L‧‧‧連接器元件
15‧‧‧側面
16‧‧‧密封體
17‧‧‧表面
18‧‧‧重分佈結構
19‧‧‧導電塊
20‧‧‧正面
21‧‧‧線路
22‧‧‧背面
23‧‧‧導電層
24‧‧‧側壁
26‧‧‧端部
27‧‧‧邊緣表面
28‧‧‧端部
28'‧‧‧端部
29‧‧‧導電元件
30‧‧‧導電端部
31‧‧‧區域陣列
32‧‧‧區域
33‧‧‧附著層
34‧‧‧自由端部
35‧‧‧導電接合塊
36‧‧‧切割線
42‧‧‧暫時膜
44‧‧‧模板
45‧‧‧模板
46‧‧‧腔體
50‧‧‧熱擴散片
52‧‧‧凹陷部分
54‧‧‧深度
55‧‧‧距離
56‧‧‧距離
57‧‧‧裝置
58‧‧‧寬度
60‧‧‧寬度
62‧‧‧寬度
64‧‧‧高度
100‧‧‧堆疊組件
110‧‧‧微電子封裝
118‧‧‧彎曲部
1100‧‧‧系統
1101‧‧‧殼體
1102‧‧‧電路板
1104‧‧‧電路板
1106‧‧‧元件
1108‧‧‧元件
1110‧‧‧元件
1111‧‧‧透鏡
本發明之上述及其他特徵及優勢將藉由參照附圖詳細說明其例示性實施例而變得更顯而易知，其中：第1A圖為本案較佳實施例之微電子單元之剖面圖。
第1B圖為第1A圖之實施例變化型的微電子單元之剖面圖。
第2圖為本案較佳重建組件之示例之俯視平面圖。
第3圖為相似於第1A圖的微電子單元之方法中之一階段。
第4圖為第1A圖之微電子單元之方法中之另一階段。
第5圖為第1A圖之微電子單元之方法中之另一階段。
第6圖為第1A圖之微電子單元之方法中之另一階段。
第7圖為第1B圖之微電子單元之方法中之一階段。
第8圖為第1B圖之微電子單元之方法中之另一階段。
第9圖為第1B圖之微電子單元之方法中之另一階段。
第10圖為本案較佳實施例之微電子單元之俯視圖。
第11A圖至第11D圖為本案較佳實施例之連接器元件以及密封體之變化型之剖面圖。
第12A圖至第12B圖為本案較佳實施例之微電子單元之形成密封層之方法中的一階段以及下一階段。
第12C圖為相對應於第12B圖之階段之放大剖面圖。
第13A圖至第13B圖為本案較佳實施例之載體之變動之剖面圖。
第14圖為本案較佳實施例之連接器元件以及密封體內之變動之剖面 圖。
第15A圖至第15B圖為本案較佳實施例之設置於堆疊組件內之微電子單元之剖面圖。
第16圖為本案較佳實施例之系統之示意剖面圖。
於此使用，詞彙“與/或”包含一或多個相關條列項目之任何或所有組合。當“至少其一”之敘述前綴於一元件清單前時，係修飾整個清單元件而非修飾清單中之個別元件。
本文所描述的處理步驟可用以形成在第1A圖以及第1B圖中的示例性微電子單元或封裝。如第1A圖以及第1B圖所示，示例性的無基板的封裝10可包含微電子元件12(見第2圖)、連接器元件14、密封體16以及重分佈結構18。微電子元件12可具有正面20或“工作面(active face)”、背面22以及在正面20以及背面22之間延伸的側壁24。正面20可位於微電子單元或封裝10的第一側面11上。如本發明所揭露的裝置，例如連接器元件、第一端部、第二端部、自由端部、導電元件、微電子元件等，元件“位於“裝置表面之敘述係指當裝置不與任何其他元件組裝時，導電元件係能與理論點相接觸，此理論點係在垂直於裝置之表面的方向上從裝置外部朝向裝置之表面移動。因此，位於微電子單元12之表面上的端部或其他導電元件可突出於此類表面；可與此類表面齊平；或可在基板上以孔洞或下陷處相對於此類表面凹陷。
連接器元件14可包含第一端部28(例如底端)、第二端部 26(例如頂端)以及在第一端部以及第二端部26之間垂直延伸的邊緣。第一端部28可包含由銅、鎳、鋁、錫、鈀或其他相似的導電材料或多個導電材料之組合所製成的導電元件29(例如墊片)。連接器元件14可呈圖案排列以形成區域陣列31，其可環繞微電子元件12以及具有網格狀外觀，例如第10圖中的其相對應的平面圖。區域陣列31可用密封體16填充，使得連接器元件14之自由端部34係位於密封體16之表面上。如第10圖所示，連接器元件之自由端部34可排列成網格或陣列，並曝露於介電密封體16之表面上。連接器元件14之自由端部34能以“自由”作為特徵，其不會電性連接或以其他方式接合微電子單元12內最接近自由端部34的其他導電體。換句話說，自由端部34能直接地或間接地電性連接微電子單元12外部的導電體。自由端部34如例可藉由密封體16或接合或電性連接另一導電體以維持在預設位置上，但如本文所描述，只要任何的此類元件不鄰近自由端部，就不意味著自由端部34不是“自由的”。如上所述，可決定第一端部或第二端部的配置為自由端部，例如在第1A圖中的第二端部26(例如頂端)係為自由端部，而在第1B圖中的第一端部(例如底端)係為自由端部34。在任一情況下，自由端部34以及微電子元件12之正面可位於封裝之相同側以及離開重分佈結構18的位置。相反地，相鄰於重分佈結構18的連接器元件之端部可以不是自由端部，因為這些端部係直接地或間接地電性耦接重分佈結構18。
如第10圖為連接器元件之自由端部34的示例性圖案，此 自由端部34係形成區域陣列31。在一示例中，區域陣列31可具有沿著微電子單元12之外圍部分環繞微電子元件12的多個列以及行。區域陣列31 可從微電子元件之邊緣朝向微電子單元10之邊緣向外延伸。區域陣列31可排列使得連接器元件14從微電子元件12之邊緣向外延伸的距離不小於距離55(例如此距離小於4mm)。區域陣列31也可排列使得連接器元件14從封裝的邊緣向內集中一短距離56(例如此距離少於4mm)。在一示例中，沒有連接器元件位於微電子元件12之邊緣的0.5mm距離範圍內以及微電子單元10之邊緣的0.5mm距離範圍內。
連接器元件14的數量(例如I/O連接)可取決於微電子單元 之一部分，此微電子單元所包含的連接器與連接器元件14相同之密度。此密度係相關於每一連接器之厚度以及連接器元件與另一個連接器元件之間的距離(例如間距)。取決於具體的結構，連接器元件可具有不同尺寸，例如打線接合的厚度可約為500μm，而焊料材料可具有較大的厚度。間距可介於0.05毫米(mm)以及4mm，較佳的間距範圍係介於0.1mm至0.6mm之間。 間距越低則I/O連接的密度越高。在一示例中，尺寸為14mmX14mm的微電子單元可具有約1440個連接器元件14，其為五列而彼此間距約為0.2mm。
請參閱第1A圖，在本發明之一示例中，連接器元件14之 第二端部26(例如頂端)可位於微電子單元12之第一側面11。在一實施例中，第二端部26可突出於封裝之表面的上方。如本文所述，導電元件係設置於“表面上方”或“覆蓋表面”的敘述係意指位於在遠離表面的正交方向上的區域上。元件係在一參考平面“上方”或”向上遠離”一參考平面係意指位於在遠離參考平面的正交方向上的區域上。元件在”向上的”方向移動係意指在朝向高於表面所定義的參考平面的方向。相反地，元件在”向 下的”方向移動係意指朝向低於表面所定義的參考平面的方向。先前項目的所有此類陳述以及意義並不以重力為參考，而是以元件的定義作為參考基準。
每一連接器元件14可電性連接上述重分佈結構。在一實施例中，連接器元件14及/或重分佈結構18與微電子元件12沒有電性連接。微電子元件12之背面可附著於附著區域32上的重分佈結構18上，其可被黏著層或黏著膜覆蓋。附著區域32可位於每一微電子單元之中心部分上。重分佈結構18可電性耦接或直接接觸連接器元件14之第一端部28(例如底端)。在一示例中，底端可以為導電墊片。
如第1B圖所示，在另一個示例性微電子單元中，連接器元件之第一端部28係與第二端部26相對設置，並可設置於微電子單元之第一側面11上以及相鄰於微電子元件12之工作面20。第二端部26(例如底端)可直接實體地及/或電性接觸重分佈結構18。重分佈結構18可藉由密封體16與微電子元件相隔開，密封體16可完整地覆蓋微電子元件12以及環繞背面以及所有的側壁。
如第2圖至第9圖中所示，係根據各種的形成階段以形成上述的微電子單元以及其他的變化型。在一些示例中，重分佈結構18可在連接器元件14之前形成，並電性耦接或接觸第一端部28(例如底端)。在另一示例中，重分佈結構18在連接器元件14之後形成，並與第二端部26(例如頂端)相接觸。
請參閱第2圖，製造之方法可利用重建組件方式(例如重建晶圓)。重建組件8可藉由在載體13上放置複數單一化的微電子元件12而 形成，以進一步處理。載體13可以為任何能在進行操作時機械地支撐複數微電子元件的結構(例如晶圓)。微電子元件12可直接地設置於載體上或可設置於先前在載體上形成的(複數)層上。微電子元件12可藉由黏著材料或真空，直接地或間接地與載體13相隔開以及附著於載體13上。形成重建晶圓時可同時處理複數微電子元件12，並接著進行單一化以形成個別封裝的微電子單元。
本發明之一態樣包含一種處理微電子單元之方法，其係藉 由在處理步驟中於較早期階段便形成重分佈結構18，其可產生相似於第1A圖的結構。如第3圖所示，在載體13上可提供暫時的附著層33(例如黏著層)以及導電端部30。暫時的附著層33可藉由在載體13上沉積黏著材料或附著黏著材料而形成。在一示例中，形成的複數導電端部30之步驟包含藉由圖案化導電材料進行消減，以形成個別的導電端部。另一示例中，複數導電端部可藉由額外處理而形成，例如藉由電鍍、沉積、打印等。導電端部端部可包含銅、鋁、鎳或任何其他的導電材料，例如但不限制為導電矩陣材料、導電性墨水、導電聚合物、導電性糊等。在一示例中，端部30可呈導電墊片的形態，其功能可作為微電子單元之表面上的封裝端部(例如球體柵格陣列(BGA))。
如第4圖所示，藉由形成介電層19以及電性耦接導電端部 30的線路21，可在載體13上建立重分佈結構18。重分佈結構18可由單一介電層(例如單一旋轉塗佈)形成或可包含多個介電層。在重分佈結構18之遠離載體13的表面上可以為導電元件29，在一示例中，可藉由形成另一導電層以及隨後將其圖案化，以形成導電元件29。此外，導電元件29可以為 墊片或導電塊(例如焊料球體)，其功能可作為焊孔陣列(Bond Via Array,BVA)之第一端部(例如底端)。
如第5圖所示，方法可包含形成附著區域32以及導電連接 器元件14。附著區域32可以為覆蓋載體的位置，微電子元件可設置於此載體上。微電子元件的設置可在形成連接器元件14之前或之後、可在形成密封體之前或之後，或可在單一化之前或之後。複數附著區域32可包含黏著墊片及/或黏著膜，並可形成在平行於載體之表面的至少一第一方向上彼此相隔開的區域上。
連接器元件14可在相鄰的複數附著區域32之間形成，並 可部分地或完全地環繞每一附著區域32。每一連接器元件可具有第一端部28、第二端部26以及在第一端部28以及第二端部26之間垂直延伸的邊緣表面27。第一端部28可相鄰於以及電性耦接於重分佈結構18，第二端部26可以為遠離重分佈結構18的自由端部。第一端部28可覆蓋以及電性耦接(例如結合或接合)導電元件29及/或第一端部可包含與其一體成形的導電元件29，如圖所示的第一端部28'。
在一示例中，連接器元件14可以為打線接合部，其係使用 打線接合工具以接合金屬接合表面(例如導電元件29)。在一示例中，形成打線接合部的方法可包含加熱線段之前端以及將其壓底線段接合的接受面，通常形成與導電元件29之表面相接合的球體或球狀底面。必須從接合工具拉出所需要的線段長度以形成打線接合部，接著在所期望的長度切斷或切割打線接合部。
另一個形成連接器元件14之技術可包含楔焊或針腳式接合。 楔焊可包含沿著接收面拖曳線之一部分以形成楔形物，此楔形物通常係平行於表面。如有必要，打線接合部所接合的楔形物可向上地彎曲，且在切割之前更可將線延長至所期望的長度或位置。在一具體的實施例中，用於形成打線接合部的線可具有圓柱形的橫截面。反之，從工具提供用以形成打線接合部的線或打線接合部所接合的楔形物可具有多邊形的橫截面，例如矩形或梯形。
如第6圖所示，微電子元件12可設置於附著區域32上以 及被介電密封體16圍繞。微電子元件12可在介電密封體16形成之前、之後或過程中附著於附著區域32上。每一微電子元件12可具有正面20、背面22以及在正面20以及背面22之間延伸的側壁24。正面20可以為主動或被動元件的工作面(例如接觸點)，背面22可具有或不具有主動或被動電性元件(例如接觸點)。在一示例中，附著區域可設置於重分佈結構18之表面上，微電子元件12可附著於面向載體的背面。因此，正面20可隔離以及面向遠離重分佈結構18以及載體13。
接著，微電子元件12可由密封體16圍繞，使得封裝係相 鄰於以及覆蓋微電子元件12所有的側壁。在此步驟中，在區域陣列31內，密封體也可形成於連接器元件之邊緣表面27之一部分上。介電密封體可具有平行於微電子元件12之正面20的主表面17，並位於基本上對準微電子元件12之高度的一高度(例如大於50mils)處。密封體之表面的位置高度也可高於、低於或近似於連接器元件14之第二端部26的高度。可允許第二端部突出於密封體16上方，或第二端部可相對於封裝之主表面17凹陷，或與封裝之主表面17齊平。下列的封裝步驟可以為另一個的或選擇性的單 一化處理步驟。例如，如第11C圖所示，位於微電子元件之正面上的接觸元件以及第二端部26可具有形成於其上(例如擠壓形成)的導電塊(例如焊料球體)。
在附著的以及消除處理完成之後，產生的重建組件可包含 大量作為連續或半連續結構的微電子單元，例如條狀、帶狀或板狀。儘管第6圖中並未在個別的微電子單元之間繪示可見的邊界，但微電子單元隨後可進行單一化，例如沿著切割線36進行單一化以及從載體13移出，以形成個別封裝的微電子元件，相似於第1A圖中所示的微電子單元。微電子單元可用以機械支撐以及將微電子元件電性連接另一個微電子結構，例如連接印刷電路板(“PCB”)，或連接其他封裝的微電子元件。在此類堆疊排列中，連接器元件14可承載多個電子訊號，每一電子訊號係具有不同的訊號電位，以允許不同的訊號由在單一堆疊中的相異的微電子元件進行處理。
本發明之另一態樣包含一種處理微電子單元之方法，此方 法係藉由在處理步驟中的後段形成重分佈結構18，以產生相似於第1B圖所示的結構。在此方法中的步驟以及結構可包含許多與上述方法相同的步驟。如第7圖所示，載體13可用以形成重建組件(例如重建晶圓)以及可包含附著區域32、微電子元件12、導電層23、導電元件29以及連接器元件14。如第4圖所示，在載體13上可直接提供與重分佈結構18相對設置的附著區域32。此外，可在設置於載體13上的中間層(例如導電層)上直接提供附著區域32。微電子元件12可表面朝下設置在附著區域上，使得正面係相鄰於載體。因此，背面22可隔離或面向遠離載體。可藉由形成另一導電 層(例如箔片)以及隨後將其圖案化，以形成導電元件29。在一示例中，導電元件29可以為墊片形態，其功能可作為微電子單元的封裝之兩端部以及連接器元件14之第一端部(例如底端)。如第5圖所示，連接器元件14可透過相同於上述的處理步驟而形成。
如第9圖所示，在上述的微電子元件12上以及連接器元件 14中可形成介電密封體16。然而，不同於第3圖至第8圖所述之示例，重分佈結構18可形成於密封體上方，並可直接與連接器元件14之第二端部相接觸。在這種情況下，雖然重分佈結構18可使用相似於第4圖的處理步驟而形成，但此重分佈結構18可遠離載體以及可形成重建組件之第二側面以及即將被單一化的微電子單元。在一示例中，在載體上可得到(例如曝露)重分佈結構18，其可允許區域陣列可電性耦接，以在較大的間距下進行測試的。
在此刻，重建組件可準備進行單一化，然而，在單一化步 驟之前也可發生另一處理步驟或選擇性的處理步驟。例如，如第11C圖所示，在連接器元件之端部上以及在微電子元件之接觸部上，可提供導電接合塊35(例如焊料球體)。在附加以及消減處理步驟完成之後，重建組件可沿著切割線36(第9圖)進行單一化以及從載體13中移出，以形成個別封裝的微電子元件，其相似於第1B圖中所示的微電子單元。如上所述，微電子單元可接著附著至印刷電路板上，或可成為微電子單元之堆疊的一部份。
如第11A圖至第11D圖所示，微電子單元10可在沒有形成 重分佈結構18的情況下形成，因此在最後的結構中可省略重分佈結構，連接器元件14可設置於微電子單元之兩側面。如第11A圖所示，微電子單元 10可具有第一側面15(例如頂部)以及與第一側面15對立之第二側面15(例如底部)以及微電子元件12。微電子元件12可具有位於連接器元件14旁邊的微電子單元10之第二側面15上的工作面20。可形成在微電子元件之第一表面以及第二表面之間垂直延伸的連接器元件14，此連接器元件14可站立平行於微電子元件之側壁。每一連接器元件可自由地電性連接其他的連接器元件及/或微電子元件。此可允許下層的或覆蓋的基板(例如PCB、中介層、另一微電子封裝)供應相互連接。
在一示例中，如第11D圖所示，連接器元件14H以及14I 可包含單一導電塊19。如連接器元件14H，導電塊可以為圓形的，或如連接器元件14I，導電塊可以延長為橢圓形。如連接器元件14J、14K及14L所示，每一導電塊也可包含一連串的堆疊導電塊。導電塊可由接合金屬形成或可包含接合金屬，例如錫、銦、焊料或金。此外，導電塊可由固化材料形成或可包含固化材料。在一些情況下，固化材料可允許在其上形成另一導電塊之前進行固化。在這種情況下，第一連接器端部以及第二連接器端部可分別為單一導電塊19之底部以及頂部，或當多個導電塊堆疊時，可分別為頂部導電塊以及底部導電塊。
請參閱第11B圖，微電子單元10也可包含相鄰於微電子元 件12的熱擴散片50。熱擴散片50可由導電層23之一部分組成，或可包含導電層23之一部分。在一示例中，熱擴散片50可直接地或間接地黏著至微電子元件12之背面上。熱擴散片50可佔據大於或小於微電子元件之背面的區域。
如第11A圖至第11D圖所示，在產生具有相異配置的微電 子單元的步驟中，密封體16在一示例中，如第11C圖所示，密封體可在微電子元件設置於重建組件上之前形成。密封體可在設置微電子元件之後形成，可允許密封體直接與微電子元件相接觸。在後者的示例中，介電密封體可覆蓋微電子元件之一大部份，並可環繞微電子元件所有的側壁以及背面(亦即微電子元件的六個側面中的五個)，如第11A圖所示。
在另一示例中，如第11B圖所示，密封體可環繞微電子元 件的側壁，但在僅水平方向上側向地從微電子元件向外延伸，而不覆蓋微電子元件12的正面或背面。如第11C圖所示，在一設計中，可將密封體形成，使其圍繞微電子元件，但在微電子元件的至少一側壁(例如所有的側壁)以及圍繞的密封體之間係具有大間隙17。
請參閱第12A圖至第12C圖所示，其為形成密封體16之 技術之示例，此技術可導致連接器元件14之未密封部分突出於密封體16之表面17外。如第12A圖所示，膜輔助成型技術可藉由設置於模板44以及腔體46之間的暫時膜42實施，其中組件包含基板、與其接合的連接器元件14以及可被接合的裝置，例如微電子元件。第12A圖為模具之第二模板45，其係與第一模板44相對立設置。
接著，如第12A圖至第12C圖所示，當模板44以及45聚 集在一起時，連接器元件14之自由端部34可突出至暫時膜42內。當模具化合物流入腔體46內形成密封體16時，模具化合物不會與連接器元件14之自由端部相接觸，因為這些自由端部被暫時膜42覆蓋。在此步驟之後，模板44與13係從密封層16移除，暫時膜42可從模具表面17移除，並留下突出於密封層16之表面17外的連接器元件14之自由端部。
膜輔助成型技術也可適用於大量製造。例如，在處理步驟 的一示例中，暫時膜之連續板之一部分可應用於模板。接著，密封層可形成於腔體46內，此腔體46之至少一部分係由模板所定義。接著，在模板44上的暫時膜42之目前部分可由具有暫時膜之連續板之另一部分的自動化裝置取代。
在膜輔助成型技術之變化型中，在形成密封層之前，水溶 性膜可設置於模板44之內表面上，以取代上述可移除的膜的使用。當模板移除時，可將水溶性膜沖洗掉，以便留下突出於上述的封裝層之表面17外的連接器元件14之端部。
密封體也可使用替代技術形成，例如密封體16可藉由完整 地覆蓋連接器元件14而形成，即連接器元件14包含封裝體之端部(例如端部26)。密封體可包含一犧牲部(例如層)，隨後可將此犧牲部移除以暴露第二端部。犧牲部可利用蝕刻、平坦化、磨光、磨削、濕噴砂(例如氧化鋁漿料)、拋光或其他相似方法移除。如此，可減少密封體之高度，以實現針對連接器元件14所期望的高度。
犧牲部(例如犧牲層)之平坦化可藉由將其高度降低而開始 進行，以使連接器元件14曝露於犧牲層之表面上。接著，平坦化處理步驟也可同時地平坦化犧牲層以及連接器元件14，使得犧牲層之高度連續地減少，而連接器元件14之高度也減少。一旦達到針對連接器元件14所期望的高度，可停止平坦化處理步驟。應當注意的是，連接器元件14可在此類的處理中初期形成，使得其高度係為不均勻，且其高度皆大於目標的均勻高度。在將連接器元件14平坦化處理成均勻的或下降的高度後，犧牲層可 例如藉由蝕刻或其相似方法進行移除。犧牲部可由與封裝相同或相異的材料形成，此材料可允許使用蝕刻液蝕刻以將其移除，而不會顯著地影響密封材料。在一示例中，犧牲層可由水溶性塑料製成。
請參閱第13A圖以及第13B圖，用於重建組件的載體可具 有基本上平整的平面，或表面可包含凹陷及/或凸起的附著區域。非平坦的附著區域可用以允許先前擠壓的微電子元件為載體上的可移除地附著面到。 如第13A圖所示，凹陷部分52可具有用以容納焊料凸塊56之厚度的深度54，例如深度可大於或可稍微小於焊料凸塊之厚度，後者可能會導致凸塊輕微變形。凹陷部分之寬度58可大於工作面之一部分的寬度60，此工作面之部分包含電性接觸點(例如墊片、焊料凸塊)。然而，凹陷寬度58可小於微電子元件12之寬度62，如此可允許微電子元件懸掛凹槽上方及/或橋接凹槽。
如第8圖中所示，在附著微電子元件12至第13A圖中的載 體13上之前或之後，可形成在導電元件14之端部上由導電元件29所提供的連接器元件14以及端部。接著，如第9圖中所示，一旦提供這些形體14、29以及微電子元件12，可提供密封體16以及更進一步提供重分佈層。如第13B圖所示，非平坦的附著區域可包含凸起部分以及凹陷部分。較佳地，微電子元件12可允許選擇性地設置於微電子單元內。在一示例中，微電子元件可在載體之表面上方稍微凸起一高度64，此外，可設置微電子元件，以使工作面或工作面上的凸塊之底部係沿著相同於連接器元件之自由端部34的平面。
如第14圖所示，上述任何的或所有的微電子單元以及方法 可包含任何的連接器元件在其底端以及端部之間產生各種橫向的位移的各種形態之組合。例如，如第14D圖以及上面示例所示，連接器元件14基本上可與設置於其個別的第一端部(例如底端)28上方的第二端部26直行，在此情況下，第一端部以及第二端部之間距可以為相同的。在一示例中，連接器元件14A可以直行，但第二端部26係設置於來自個別的第一端部28的側向上。在另一示例中，連接器元件(例如元件14B)可包含彎曲部118，其在第一端部28以及第二端部26之間導致一些輕微的橫向位移。在另一示例中，連接器元件(例如元件14C)包含具有呈彎曲狀形狀的彎曲部118，比起連接器元件14B，此彎曲部118係導致側向地設置且間隔個別底端28較大距離的第二端部26。
相對於連接器元件之第二端部26，連接器元件14之第一端 部28的橫向位移可能在第一端部28上產生連接器元件14之第一中心到中心的間距(第一間距)，此間距係相異於在連接器元件之第二端部26上的第二中心到中心的間距(第二間距)，第二間距係少於或大於第一間距。微電子單元10之複數導電端部30能以一第三中心到中心的間距進行設置，此間距可相同於或大於第一節距及/或第二節距。導電端部30可電性耦接所有的連接器元件14，或僅電性耦接連接器元件14之一部分。導電端部30可覆蓋微電子元件12及/或相鄰的密封體16，並可橫跨整體的側面或微電子單元10(例如封裝)之側面之大部份。在一示例中，第一端部以及第二端部之間距可具有相同的數值(例如240微米)，導電端部之間距則可以為較大的(例如400微米)。
如有必要，連接器元件14之彎曲部118可呈各種形態，以 實現連接器元件14之端部26所期望的位置。例如，彎曲部118可形成各種形態的S曲線，例如包含於打線接合部14B或平滑形態的打線接合部14C。 此外，彎曲部118可設於比端部26更接近底端28的位置，反之亦然。彎曲部118也可以為螺旋形或環形的形態，或可以為包含呈多個方向曲線的化合物，或可以為包含相異的形狀或特徵的曲線的化合物。
彎曲部118可例如在打線接合部的形成處理步驟中形成， 同時，打線部分可拉至所期望的長度。此步驟可使用現有的打線接合設備實施，可包含使用單一機器。
連接器元件14也可包含位於自由端部34(例如端部)上的導 電接合塊35(例如柱狀凸塊)。導電接合塊35可有助於提供與另一個導電元件的連接處。如元件14D至14G所示，導電塊可與沒有密封進內部的自由端部接合。導電塊可與自由端部接合，並允許沿著邊緣表面27以及允許除了自由端部外的接合。
請再次參閱第14圖，結構14D至14G可包含柱狀物或微 柱形態的連接器元件，此連接器元件係具有端部26以及邊緣表面。連接器元件14F至14G可具有截體圓錐型狀的錐形側壁。連接器元件14G可具有端部26，此端部26之橫截面係較寬於底端28以及端部26之間的一部分之橫截面，其中底端28以及端部26係為相互平行，邊緣表面係從底端28朝向每一其他的邊緣表面錐形延伸至端部26。如連接器元件14A所示，在此示例中，連接器元件14之底端28、或位於底端28上的導電元件或墊片可與連接器元件14一體成形，使得導電元件不會是個別被接合的相單一化的連接器元件14。
在另一實施例中，連接器元件可以為具有端部26的微柱 14G形態，此端部26係位於低於密封體16之主表面17的一高度處。為了暴露第二端部26，密封體16可包含已進行蝕刻的區域，反之，形成蝕刻區域以定義從表面17至少延伸至自由端部26的開孔或孔洞。孔洞可具有任何適合的形態以允許形成於孔洞內的連接器元件14G之端部26上進行電性連接，例如藉由在其內進行導電材料的沉積。在一示例中，導電接合塊35可沉積於孔洞內，並從端部26延伸至密封體16之主表面17上方，並遠離孔洞沿著表面17之部分進行延伸。
如第15A圖以及第15B圖所示，第1A圖或第1B圖所示的 微電子單元10可與其他元件組裝，例如位於單元10下方的較低的裝置57以及另一個位於單元10上方的微電子封裝110兩者“封裝層疊(PoP)”成堆疊組件100。在多個示例中，較低的裝置57可以為印刷電路板、中介層、微電子元件或微電子封裝，其中微電子元件12可以為附著至端部30上的倒裝晶片，並可透過微電子單元之連接器元件14延伸穿過微電子單元10與端部30電性連接。例如，微電子單元10可具有兩組不同節距的電性連接。第一連接組可包含在微電子元件12之正面上的導電元件，並可將微電子元件12電性耦接較低的裝置57。第二電性連接組可以為連接器元件14，此連接器元件14可將微電子封裝110與較低的裝置57電性耦接。在一實施例中，第一連接組可僅在微電子元件12以及較低的裝置57之間進行電性連接，第二連接組可僅在微電子封裝110以及較低的裝置57之間進行電性連接。此外，任一連接組之一部分可用以將封裝電性耦接較低的裝置57。
如第15A圖以及第15B圖所示，微電子單元10之重分佈 層18以及端部30可具有不同於較低裝置57之端部的間距，例如端部30可具有大於連接器元件之間距的一間距，此連接器元件係圍繞於微電子元件12外部的微電子單元10之周圍。在一示例中，在頂部可允許更寬鬆的間距以測試微電子單元10，並可允許微電子封裝110或裝置具有更寬鬆的間距以電性耦接單元之頂部30。
如第16圖所示，請一併參考第1A圖以及第1B圖、第10 圖至第11D圖以及第14圖至第15B圖，微電子封裝以及微電子組件可採用多樣化的電子系統之結構，如第16圖所示的系統1100。例如，根據本發明之另一實施例，系統1100包含複數模組或元件1106，例如微電子封裝及/或微電子組件，如上述的電子元件1108以及1110。
如示例性系統1100所示，系統可包含電路板、主機板或豎 式面板1102，例如可彎曲印刷電路板，電路板可包含多個導體1104(第16圖中僅繪示一個)，此導體1104可將模組或元件1106與另一模組或元件進行互聯。此電路板1102可與每一微電子封裝及/或系統1100所包含的微電子組件相互傳輸訊號。然而，其僅為示例性；可使用任何適合用以在模組或元件1106之間製造電性連接的結構。
在一具體的實施例中，系統1100也可包含處理器，例如半 導體晶片1108，使得每一模組或元件1106可在每一時脈週期並列傳輸數量N的資料位元，處理器可在每一時脈週期並列傳輸數量M的資料位元，M係大於或等於N。如第16圖，元件1108可以為半導體晶片，元件1110係為顯示螢幕，然而任何的其他元件也可使用於系統1100內。當然，所雖然第16圖僅繪示兩個用以明確說明的元件1108以及1110，但是系統1100可 包含任意數量的此類元件。
以虛線示意性地繪示，模組或元件1106以及元件1108以 及1110可安裝於共用殼體1101上，並可與另一模組或元件電性互聯以形成所期望的電路。殼體1101為可用型態的可攜式殼體，例如智慧型手機、平板電腦、電視或行動裝置以及可曝露於殼體之表面上的螢幕。在實施例中，結構1106包含光敏元件(例如影像晶片)、透鏡1111，或也可提供其他用以按一定路線發送光至結構上的光學裝置。此外，第16圖所繪示的簡化系統係僅為示例性；其他系統包含多個通常作為固定的結構的系統，例如可使用上述結構製成的桌上型電腦、路由器以及其相似物。
應當理解的是，在本發明中結構可包含其他配置，這些配 置係藉由封裝元件暴露連接器元件之一部分，例如在其端部表面上以及選擇性沿著其邊緣表面，此相似於本文所述的密封元件之表面之配置係遠離以及面向基板之表面的變化型。
在較佳實施例之詳細說明中所提出之具體實施例僅用以方便說明本發明之技術內容，而非將本發明狹義地限制於上述實施例，在不超出本發明之精神及以下申請專利範圍之情況，所做之種種變化實施，皆屬於本發明之範圍。
10‧‧‧微電子單元
11‧‧‧第一側面
12‧‧‧微電子元件
14‧‧‧連接器元件
16‧‧‧密封體
18‧‧‧重分佈結構
20‧‧‧正面
22‧‧‧背面
24‧‧‧側壁
26‧‧‧端部
28‧‧‧端部
29‧‧‧導電元件
30‧‧‧導電端部
31‧‧‧區域陣列
32‧‧‧區域
34‧‧‧自由端部

Claims (22)

  1. 一種同時製造複數微電子單元的方法，包含下列步驟：在一載體(Carrier)上提供一導電重分佈結構(Redistribution Structure)，並在平行該載體之一表面的至少一第一方向上，提供彼此相隔開的複數微電子元件附著區域(Microelectronic Element Attachment Regions)；在相鄰的複數附著區域之間形成複數導電連接器元件(Connector Elements)，每一連接器元件係具有一第一端部(End)、一第二端部以及在該第一端部以及該第二端部之間垂直延伸的複數邊緣表面(Edge surfaces)，每一連接器元件之該第一端部係與該重分佈結構相鄰，每一連接器之該第二端部位於該載體上方之一高度係大於50微米；在該複數連接器元件之相鄰複數邊緣表面之間形成一介電密封體(Encapsulation)；以及單一化複數微電子單元(Microelectronic units)，每一該複數微電子單元包含一微電子元件(Microelectronic element)，對立於該重分佈結構的該微電子單元之一側(Side)具有該微電子元件之第一表面(Face)以及該複數連接器元件之該第二端部，該第二端部係與該微電子單元外部之一裝置(Componet)相連接。
  2. 如申請專利範圍第1項所述之方法，其中形成該複數導電連接器元件之步驟包含：形成附著於該重分佈結構之複數墊上的複數打線接合部。
  3. 如申請專利範圍第1項所述之方法，其中形成該介電密封體之步驟包含：膜輔助成型，其中該連接器元件之該第二端部係突出於該密封體之一表面上方。
  4. 如申請專利範圍第1項所述之方法，其中形成該介電密封體之步驟包含：在該複數連接器元件之該第二端部上以及該複數微電子元件之相鄰的複數側壁上，形成該介電密封體；以及移除覆蓋該第二端部的該介電密封體。
  5. 一種同時製造複數微電子單元的方法，包含下列步驟：於一載體(Carrier)上提供複數微電子元件附著區域，該複數微電子元件附著區域在平行於該載體之一表面的至少一第一方向上係彼此相隔開；在相鄰的複數附著區域之間形成複數導電連接器元件(Connector elements)，每一該連接器元件係具有一第一端部、一第二端部以及複數邊緣表面，該複數邊緣表面係在該第一端部以及該第二端部之間垂直延伸，每一該連接器元件之該第一端部係與該載體相鄰，每一該連接器之該第二端部係位於該載體上方之高度係大於50微米；附著複數微電子元件(Microelectronic Elements)到該載體上的個別該附著區域上，每一微電子元件係具有一第一表面、一第二表面以及在該第 一表面以及該第二表面之間延伸的複數側壁，該第一表面係具有複數接觸部，該第一表面係面向該載體；在該複數連接器元件之相鄰的複數邊緣表面之間，形成一介電密封體(Encapsulation)；形成一導電重分佈結構(Redistribution Structure)以覆蓋該密封體之至少一表面，該封裝係與該微電子元件之該第一表面對立，該重分佈結構係耦接該複數連接器元件之該第二端部，並具有在該至少一第一方向上延伸的複數線路(Trace)；以及單一化複數微電子單元(Microelectronic Units)，每一複數微電子單元包含一微電子元件，該微電子單元之一側係具有該微電子元件之該第一表面，該複數連接器元件之第一端部係能與該微電子單元外部的一裝置相連接。
  6. 如申請專利範圍第5項所述之方法，其中形成該複數導電連接器元件之步驟包含：形成覆蓋該載體的一導電層；圖案化該導電層以形成複數墊；以及附著一打線接合部或形成一導電塊於該複數墊片上。
  7. 如申請專利範圍第5項所述之方法，其中形成該介電密封體之步驟包含：膜輔助成型，其中該連接器元件之該第二端部係係突出於該密封體之一表面上方。
  8. 如申請專利範圍第5項所述之方法，其中形成該介電密封體之步驟包含：形成該介電密封體於該複數連接器元件之該第二端部上，隨後將該介電密封體從該第二端部上移除。
  9. 如申請專利範圍第5項所述之方法，其中該複數導電連接器元件係自由電性連接該微電子元件。
  10. 一種具有相對立之一第一側面(Side)及一第二側面的微電子封裝(Package)，包含：一微電子元件，係具有相對立之一第一表面(Face)及一第二表面，以及複數側壁(Sidewalls)，每一側壁在該第一表面以及該第二表面之間延伸；一密封體(Encapsulation)，係相鄰於該微電子元件之該側壁，該密封體在該封裝之該第一側面以及該第二側面之間的一方向上係具有一厚度，其中該複數微電子元件之複數導電元件係位於該封裝之該第一側面上，用以電性耦接該微電子元件與該微電子封裝外部的一裝置；以及導電之複數連接器元件(Connector Elements)，係具有一第一端部(End)、遠離該第一端部的一第二端部以及在該第一端部以及該第二端部之 間延伸的一邊緣表面(Edge Surface)，其中該等端部之一係相鄰於該密封體之該第一側面，其他端部係相鄰於該封裝之該第二側面，該複數連接器元件係在該第一端部以及第二端部之間與該密封體(Encapsulation)接觸，該複數連接器元件係用以電性耦接相鄰於該第一側面的一第一外接裝置(External Component)與相鄰於該第二側面的一第二外接裝置。
  11. 如申請專利範圍第10項所述之微電子封裝，更包含：具有複數端部(Terminals)之一重分佈結構(Redistribution Structure)，該重分佈結構係與該封裝之該第二側面相鄰，並與該微電子元件之該第一表面相對立，該複數端部係側向地與該複數連接器元件之該複數第二端部間隔開來，每一該端部係電性耦接該複數連接器元件之該第二端部，該複數端部係透過該重分佈結構電性耦接相對應的複數連接器元件。
  12. 如申請專利範圍第11項所述之微電子封裝，其中一給定的連接器元件之該第一端部係與該重分佈結構相鄰，該給定的連接器之該第二端部係位於該封裝之該第一側面上，並突出於該密封體之該表面外。
  13. 如申請專利範圍第11項所述之微電子封裝，其中一給定的連接器元件之該第一端部係位於該封裝之該第一側面上，該給定的連接器元件之該第二端部係與該重分佈結構相鄰。
  14. 如申請專利範圍第10項所述之微電子封裝，其中一給定的連接器元件之該第一端部係位於該封裝之該第一側面上，該給定的連接器元件之該第二端部係位於該封裝之該第二側面上。
  15. 如申請專利範圍第10項所述之封裝，其中該複數導電連接器元件係自由電性連接該微電子元件。
  16. 如申請專利範圍第10項所述之微電子封裝，其中該複數導電元件包含：位於該微電子元件之該第一表面上的複數接觸部。
  17. 如申請專利範圍第10項所述之微電子封裝，其中該複數連接器元件係為複數打線接合部。
  18. 如申請專利範圍第17項所述之微電子封裝，其中該複數打線接合部之複數球體(Balls)係位於該複數第一端部上。
  19. 如申請專利範圍第10項所述之微電子封裝，更包含：形成於該微電子封裝之該第一側面上的複數導電接合塊(Conductive Joining Masses)，至少一導電接合塊係用以電性耦接該微電子元件與該第一外接裝置，至少一導電接合塊係用以件電性耦接該連接器元與該第一外接裝置。
  20. 如申請專利範圍第10項所述之微電子封裝，其中每一連接器元件包含一接合金屬塊(Bond Metal Mass)。
  21. 如申請專利範圍第10項所述之微電子封裝，其中每一連接器元件包含一焊料塊(Solder Mass)。
  22. 如申請專利範圍第21項所述之微電子封裝，其中每一連接器元件更包含：與該焊料塊相接合之一墊片(Pad)之至少一部分。
TW104101608A 2014-01-17 2015-01-16 使用重建晶圓與可測試之區域陣列之微小間距的焊孔陣列〈ｂｖａ〉 TW201532235A (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US14/157,790 US9583411B2 (en) 2014-01-17 2014-01-17 Fine pitch BVA using reconstituted wafer with area array accessible for testing

Publications (1)

Publication Number Publication Date
TW201532235A true TW201532235A (zh) 2015-08-16

Family

ID=52440889

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104101608A TW201532235A (zh) 2014-01-17 2015-01-16 使用重建晶圓與可測試之區域陣列之微小間距的焊孔陣列〈ｂｖａ〉

Country Status (4)

Country Link
US (5) US9583411B2 (zh)
KR (1) KR20160110970A (zh)
TW (1) TW201532235A (zh)
WO (1) WO2015109157A1 (zh)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101195786B1 (ko) 2008-05-09 2012-11-05 고쿠리츠 다이가쿠 호진 큐슈 코교 다이가쿠 칩 사이즈 양면 접속 패키지의 제조 방법
KR101128063B1 (ko) 2011-05-03 2012-04-23 테세라, 인코포레이티드 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리
US8404520B1 (en) 2011-10-17 2013-03-26 Invensas Corporation Package-on-package assembly with wire bond vias
US9583411B2 (en) * 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US9831214B2 (en) * 2014-06-18 2017-11-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device packages, packaging methods, and packaged semiconductor devices
US10177032B2 (en) * 2014-06-18 2019-01-08 Taiwan Semiconductor Manufacturing Company, Ltd. Devices, packaging devices, and methods of packaging semiconductor devices
US10804185B2 (en) * 2015-12-31 2020-10-13 Texas Instruments Incorporated Integrated circuit chip with a vertical connector
US10181447B2 (en) * 2017-04-21 2019-01-15 Invensas Corporation 3D-interconnect
US10541153B2 (en) * 2017-08-03 2020-01-21 General Electric Company Electronics package with integrated interconnect structure and method of manufacturing thereof
US10541209B2 (en) 2017-08-03 2020-01-21 General Electric Company Electronics package including integrated electromagnetic interference shield and method of manufacturing thereof
US11257803B2 (en) * 2018-08-25 2022-02-22 Octavo Systems Llc System in a package connectors
DE102019119714A1 (de) 2019-07-22 2021-01-28 Endress+Hauser Process Solutions Ag Verfahren zur Verifizierung des in einem Asset Management System eingetragenen Feldgerätebestands
US11239168B2 (en) * 2019-07-30 2022-02-01 Industrial Technology Research Institute Chip package structure
US11171127B2 (en) * 2019-08-02 2021-11-09 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor device and method of manufacturing semiconductor device
KR20220049423A (ko) * 2020-10-14 2022-04-21 에스케이하이닉스 주식회사 반도체 패키지 제조 방법

Family Cites Families (824)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2230663A (en) 1940-01-18 1941-02-04 Alden Milton Electric contact and wire assembly mechanism
US3004074A (en) 1954-08-03 1961-10-10 Universal Oil Prod Co Condensation of polyhalocycloalkadienes with cyclooctatetraene
US3004093A (en) 1958-06-03 1961-10-10 Union Carbide Corp Continuous process for making solid electrolyte batteries
DE1439262B2 (de) 1963-07-23 1972-03-30 Siemens AG, 1000 Berlin u. 8000 München Verfahren zum kontaktieren von halbleiterbauelementen durch thermokompression
US3358897A (en) 1964-03-31 1967-12-19 Tempress Res Co Electric lead wire bonding tools
US3430835A (en) 1966-06-07 1969-03-04 Westinghouse Electric Corp Wire bonding apparatus for microelectronic components
US3623649A (en) 1969-06-09 1971-11-30 Gen Motors Corp Wedge bonding tool for the attachment of semiconductor leads
DE2119567C2 (de) 1970-05-05 1983-07-14 International Computers Ltd., London Elektrische Verbindungsvorrichtung und Verfahren zu ihrer Herstellung
DE2228703A1 (de) 1972-06-13 1974-01-10 Licentia Gmbh Verfahren zum herstellen einer vorgegebenen lotschichtstaerke bei der fertigung von halbleiterbauelementen
JPS5338514Y2 (zh) 1974-10-17 1978-09-19
JPS5150661A (zh) 1974-10-30 1976-05-04 Hitachi Ltd
US4072816A (en) 1976-12-13 1978-02-07 International Business Machines Corporation Integrated circuit package
US4067104A (en) 1977-02-24 1978-01-10 Rockwell International Corporation Method of fabricating an array of flexible metallic interconnects for coupling microelectronics components
US4213556A (en) 1978-10-02 1980-07-22 General Motors Corporation Method and apparatus to detect automatic wire bonder failure
US4327860A (en) 1980-01-03 1982-05-04 Kulicke And Soffa Ind. Inc. Method of making slack free wire interconnections
US4422568A (en) 1981-01-12 1983-12-27 Kulicke And Soffa Industries, Inc. Method of making constant bonding wire tail lengths
US4437604A (en) 1982-03-15 1984-03-20 Kulicke & Soffa Industries, Inc. Method of making fine wire interconnections
JPS59189069A (ja) 1983-04-12 1984-10-26 Alps Electric Co Ltd 電気部品の端子のハンダ塗布装置
JPS59189069U (ja) 1983-06-02 1984-12-14 昭和アルミニウム株式会社 冷却装置
JPS61125062A (ja) 1984-11-22 1986-06-12 Hitachi Ltd ピン取付け方法およびピン取付け装置
US4667267A (en) 1985-01-22 1987-05-19 Rogers Corporation Decoupling capacitor for pin grid array package
US4604644A (en) 1985-01-28 1986-08-05 International Business Machines Corporation Solder interconnection structure for joining semiconductor devices to substrates that have improved fatigue life, and process for making
US4642889A (en) 1985-04-29 1987-02-17 Amp Incorporated Compliant interconnection and method therefor
JPS61269345A (ja) 1985-05-24 1986-11-28 Hitachi Ltd 半導体装置
US5917707A (en) 1993-11-16 1999-06-29 Formfactor, Inc. Flexible contact structure with an electrically conductive shell
US5476211A (en) 1993-11-16 1995-12-19 Form Factor, Inc. Method of manufacturing electrical contacts, using a sacrificial member
US4716049A (en) 1985-12-20 1987-12-29 Hughes Aircraft Company Compressive pedestal for microminiature connections
US4924353A (en) 1985-12-20 1990-05-08 Hughes Aircraft Company Connector system for coupling to an integrated circuit chip
JPS62158338A (ja) 1985-12-28 1987-07-14 Tanaka Denshi Kogyo Kk 半導体装置
US4793814A (en) 1986-07-21 1988-12-27 Rogers Corporation Electrical circuit board interconnect
US4695870A (en) 1986-03-27 1987-09-22 Hughes Aircraft Company Inverted chip carrier
JPS62226307A (ja) 1986-03-28 1987-10-05 Toshiba Corp ロボツト装置
US4771930A (en) 1986-06-30 1988-09-20 Kulicke And Soffa Industries Inc. Apparatus for supplying uniform tail lengths
JPH07122787B2 (ja) 1986-09-30 1995-12-25 カシオ計算機株式会社 連綿文字作成装置
JPS6397941A (ja) 1986-10-14 1988-04-28 Fuji Photo Film Co Ltd 感光材料
US4955523A (en) 1986-12-17 1990-09-11 Raychem Corporation Interconnection of electronic components
DE3703694A1 (de) 1987-02-06 1988-08-18 Dynapert Delvotec Gmbh Ball-bondverfahren und vorrichtung zur durchfuehrung derselben
US5138438A (en) 1987-06-24 1992-08-11 Akita Electronics Co. Ltd. Lead connections means for stacked tab packaged IC chips
JP2642359B2 (ja) 1987-09-11 1997-08-20 株式会社日立製作所 半導体装置
KR970003915B1 (ko) 1987-06-24 1997-03-22 미다 가쓰시게 반도체 기억장치 및 그것을 사용한 반도체 메모리 모듈
JPS6412769A (en) 1987-07-07 1989-01-17 Sony Corp Correction circuit for image distortion
US4804132A (en) 1987-08-28 1989-02-14 Difrancesco Louis Method for cold bonding
JPH0171162U (zh) 1987-10-29 1989-05-12
US4845354A (en) 1988-03-08 1989-07-04 International Business Machines Corporation Process control for laser wire bonding
JPH01313969A (ja) 1988-06-13 1989-12-19 Hitachi Ltd 半導体装置
US4998885A (en) 1989-10-27 1991-03-12 International Business Machines Corporation Elastomeric area array interposer
US5077598A (en) 1989-11-08 1991-12-31 Hewlett-Packard Company Strain relief flip-chip integrated circuit assembly with test fixturing
US5095187A (en) 1989-12-20 1992-03-10 Raychem Corporation Weakening wire supplied through a wire bonder
CA2034700A1 (en) 1990-01-23 1991-07-24 Masanori Nishiguchi Substrate for packaging a semiconductor device
AU645283B2 (en) 1990-01-23 1994-01-13 Sumitomo Electric Industries, Ltd. Substrate for packaging a semiconductor device
US5376403A (en) 1990-02-09 1994-12-27 Capote; Miguel A. Electrically conductive compositions and methods for the preparation and use thereof
US5948533A (en) 1990-02-09 1999-09-07 Ormet Corporation Vertically interconnected electronic assemblies and compositions useful therefor
US5083697A (en) 1990-02-14 1992-01-28 Difrancesco Louis Particle-enhanced joining of metal surfaces
US4975079A (en) 1990-02-23 1990-12-04 International Business Machines Corp. Connector assembly for chip testing
US4999472A (en) 1990-03-12 1991-03-12 Neinast James E Electric arc system for ablating a surface coating
US5241456A (en) 1990-07-02 1993-08-31 General Electric Company Compact high density interconnect structure
US5148266A (en) 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies having interposer and flexible lead
US5679977A (en) 1990-09-24 1997-10-21 Tessera, Inc. Semiconductor chip assemblies, methods of making same and components for same
US5148265A (en) 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies with fan-in leads
US5067382A (en) 1990-11-02 1991-11-26 Cray Computer Corporation Method and apparatus for notching a lead wire attached to an IC chip to facilitate severing the wire
KR940001149B1 (ko) 1991-04-16 1994-02-14 삼성전자 주식회사 반도체 장치의 칩 본딩 방법
JPH04346436A (ja) 1991-05-24 1992-12-02 Fujitsu Ltd バンプ製造方法とバンプ製造装置
US5316788A (en) 1991-07-26 1994-05-31 International Business Machines Corporation Applying solder to high density substrates
US5133495A (en) 1991-08-12 1992-07-28 International Business Machines Corporation Method of bonding flexible circuit to circuitized substrate to provide electrical connection therebetween
US5203075A (en) 1991-08-12 1993-04-20 Inernational Business Machines Method of bonding flexible circuit to cicuitized substrate to provide electrical connection therebetween using different solders
WO1993004375A1 (en) 1991-08-23 1993-03-04 Nchip, Inc. Burn-in technologies for unpackaged integrated circuits
US5220489A (en) 1991-10-11 1993-06-15 Motorola, Inc. Multicomponent integrated circuit package
US5238173A (en) 1991-12-04 1993-08-24 Kaijo Corporation Wire bonding misattachment detection apparatus and that detection method in a wire bonder
JP2931936B2 (ja) 1992-01-17 1999-08-09 株式会社日立製作所 半導体装置用リードフレームの製造方法及び半導体装置用リードフレーム並びに樹脂封止型半導体装置
US5241454A (en) 1992-01-22 1993-08-31 International Business Machines Corporation Mutlilayered flexible circuit package
US5831836A (en) 1992-01-30 1998-11-03 Lsi Logic Power plane for semiconductor device
US5222014A (en) 1992-03-02 1993-06-22 Motorola, Inc. Three-dimensional multi-chip pad array carrier
US5438224A (en) 1992-04-23 1995-08-01 Motorola, Inc. Integrated circuit package having a face-to-face IC chip arrangement
US5494667A (en) 1992-06-04 1996-02-27 Kabushiki Kaisha Hayahibara Topically applied hair restorer containing pine extract
US6054756A (en) 1992-07-24 2000-04-25 Tessera, Inc. Connection components with frangible leads and bus
JP3151219B2 (ja) 1992-07-24 2001-04-03 テツセラ，インコーポレイテッド 取り外し自在のリード支持体を備えた半導体接続構成体およびその製造方法
US5977618A (en) 1992-07-24 1999-11-02 Tessera, Inc. Semiconductor connection components and methods with releasable lead support
US5371654A (en) 1992-10-19 1994-12-06 International Business Machines Corporation Three dimensional high performance interconnection package
US20050062492A1 (en) 2001-08-03 2005-03-24 Beaman Brian Samuel High density integrated circuit apparatus, test probe and methods of use thereof
US6295729B1 (en) 1992-10-19 2001-10-02 International Business Machines Corporation Angled flying lead wire bonding process
JP2716336B2 (ja) 1993-03-10 1998-02-18 日本電気株式会社 集積回路装置
JPH06268101A (ja) 1993-03-17 1994-09-22 Hitachi Ltd 半導体装置及びその製造方法、電子装置、リ−ドフレ−ム並びに実装基板
US5340771A (en) 1993-03-18 1994-08-23 Lsi Logic Corporation Techniques for providing high I/O count connections to semiconductor dies
US7368924B2 (en) 1993-04-30 2008-05-06 International Business Machines Corporation Probe structure having a plurality of discrete insulated probe tips projecting from a support surface, apparatus for use thereof and methods of fabrication thereof
US5811982A (en) 1995-11-27 1998-09-22 International Business Machines Corporation High density cantilevered probe for electronic devices
US20030048108A1 (en) 1993-04-30 2003-03-13 Beaman Brian Samuel Structural design and processes to control probe position accuracy in a wafer test probe assembly
JPH06333931A (ja) 1993-05-20 1994-12-02 Nippondenso Co Ltd 半導体装置における微細電極の製造方法
JP2981385B2 (ja) 1993-09-06 1999-11-22 シャープ株式会社 チップ部品型ｌｅｄの構造及びその製造方法
US5346118A (en) 1993-09-28 1994-09-13 At&T Bell Laboratories Surface mount solder assembly of leadless integrated circuit packages to substrates
US6741085B1 (en) 1993-11-16 2004-05-25 Formfactor, Inc. Contact carriers (tiles) for populating larger substrates with spring contacts
US6835898B2 (en) 1993-11-16 2004-12-28 Formfactor, Inc. Electrical contact structures formed by configuring a flexible wire to have a springable shape and overcoating the wire with at least one layer of a resilient conductive material, methods of mounting the contact structures to electronic components, and applications for employing the contact structures
US5455390A (en) 1994-02-01 1995-10-03 Tessera, Inc. Microelectronics unit mounting with multiple lead bonding
KR100437437B1 (ko) 1994-03-18 2004-06-25 히다치 가세고교 가부시끼가이샤 반도체 패키지의 제조법 및 반도체 패키지
US5578869A (en) 1994-03-29 1996-11-26 Olin Corporation Components for housing an integrated circuit device
US5615824A (en) 1994-06-07 1997-04-01 Tessera, Inc. Soldering with resilient contacts
US5802699A (en) 1994-06-07 1998-09-08 Tessera, Inc. Methods of assembling microelectronic assembly with socket for engaging bump leads
JPH07335783A (ja) 1994-06-13 1995-12-22 Fujitsu Ltd 半導体装置及び半導体装置ユニット
US5468995A (en) 1994-07-05 1995-11-21 Motorola, Inc. Semiconductor device having compliant columnar electrical connections
US5989936A (en) 1994-07-07 1999-11-23 Tessera, Inc. Microelectronic assembly fabrication with terminal formation from a conductive layer
US6828668B2 (en) 1994-07-07 2004-12-07 Tessera, Inc. Flexible lead structures and methods of making same
US5518964A (en) 1994-07-07 1996-05-21 Tessera, Inc. Microelectronic mounting with multiple lead deformation and bonding
US6177636B1 (en) 1994-12-29 2001-01-23 Tessera, Inc. Connection components with posts
US6117694A (en) 1994-07-07 2000-09-12 Tessera, Inc. Flexible lead structures and methods of making same
US5688716A (en) 1994-07-07 1997-11-18 Tessera, Inc. Fan-out semiconductor chip assembly
US5656550A (en) 1994-08-24 1997-08-12 Fujitsu Limited Method of producing a semicondutor device having a lead portion with outer connecting terminal
US5659952A (en) 1994-09-20 1997-08-26 Tessera, Inc. Method of fabricating compliant interface for semiconductor chip
US5541567A (en) 1994-10-17 1996-07-30 International Business Machines Corporation Coaxial vias in an electronic substrate
US5495667A (en) 1994-11-07 1996-03-05 Micron Technology, Inc. Method for forming contact pins for semiconductor dice and interconnects
KR100394205B1 (ko) 1994-11-15 2003-08-06 폼팩터, 인크. 시험된 반도체 장치 및 시험된 반도체 장치의 제조방법
US6826827B1 (en) 1994-12-29 2004-12-07 Tessera, Inc. Forming conductive posts by selective removal of conductive material
JP2833522B2 (ja) 1995-04-27 1998-12-09 日本電気株式会社 半導体装置
US5736074A (en) 1995-06-30 1998-04-07 Micro Fab Technologies, Inc. Manufacture of coated spheres
US5971253A (en) 1995-07-31 1999-10-26 Tessera, Inc. Microelectronic component mounting with deformable shell terminals
US5872051A (en) 1995-08-02 1999-02-16 International Business Machines Corporation Process for transferring material to semiconductor chip conductive pads using a transfer substrate
US5874781A (en) 1995-08-16 1999-02-23 Micron Technology, Inc. Angularly offset stacked die multichip device and method of manufacture
US5886412A (en) 1995-08-16 1999-03-23 Micron Technology, Inc. Angularly offset and recessed stacked die multichip device
US5810609A (en) 1995-08-28 1998-09-22 Tessera, Inc. Socket for engaging bump leads on a microelectronic device and methods therefor
US5766987A (en) 1995-09-22 1998-06-16 Tessera, Inc. Microelectronic encapsulation methods and equipment
US6211572B1 (en) 1995-10-31 2001-04-03 Tessera, Inc. Semiconductor chip package with fan-in leads
JP3332308B2 (ja) 1995-11-07 2002-10-07 新光電気工業株式会社 半導体装置及びその製造方法
JPH09134934A (ja) 1995-11-07 1997-05-20 Sumitomo Metal Ind Ltd 半導体パッケージ及び半導体装置
US5718361A (en) 1995-11-21 1998-02-17 International Business Machines Corporation Apparatus and method for forming mold for metallic material
US5731709A (en) 1996-01-26 1998-03-24 Motorola, Inc. Method for testing a ball grid array semiconductor device and a device for such testing
US7166495B2 (en) 1996-02-20 2007-01-23 Micron Technology, Inc. Method of fabricating a multi-die semiconductor package assembly
US5994152A (en) 1996-02-21 1999-11-30 Formfactor, Inc. Fabricating interconnects and tips using sacrificial substrates
JP3146345B2 (ja) 1996-03-11 2001-03-12 アムコー テクノロジー コリア インコーポレーティド バンプチップスケール半導体パッケージのバンプ形成方法
US6000126A (en) 1996-03-29 1999-12-14 General Dynamics Information Systems, Inc. Method and apparatus for connecting area grid arrays to printed wire board
US6821821B2 (en) 1996-04-18 2004-11-23 Tessera, Inc. Methods for manufacturing resistors using a sacrificial layer
DE19618227A1 (de) 1996-05-07 1997-11-13 Herbert Streckfus Gmbh Verfahren und Vorrichtung zum Verlöten von elektronischen Bauelementen auf einer Leiterplatte
KR100186333B1 (ko) 1996-06-20 1999-03-20 문정환 칩 사이즈 반도체 패키지 및 그 제조방법
JPH1012769A (ja) 1996-06-24 1998-01-16 Ricoh Co Ltd 半導体装置およびその製造方法
JPH10135221A (ja) 1996-10-29 1998-05-22 Taiyo Yuden Co Ltd バンプ形成方法
KR100377033B1 (ko) 1996-10-29 2003-03-26 트러시 테크날러지스 엘엘시 Ｉｃ 및 그 제조방법
JPH10135220A (ja) 1996-10-29 1998-05-22 Taiyo Yuden Co Ltd バンプ形成方法
US6492719B2 (en) 1999-07-30 2002-12-10 Hitachi, Ltd. Semiconductor device
US5976913A (en) 1996-12-12 1999-11-02 Tessera, Inc. Microelectronic mounting with multiple lead deformation using restraining straps
US6225688B1 (en) 1997-12-11 2001-05-01 Tessera, Inc. Stacked microelectronic assembly and method therefor
US6133072A (en) 1996-12-13 2000-10-17 Tessera, Inc. Microelectronic connector with planar elastomer sockets
US6054337A (en) 1996-12-13 2000-04-25 Tessera, Inc. Method of making a compliant multichip package
US6121676A (en) 1996-12-13 2000-09-19 Tessera, Inc. Stacked microelectronic assembly and method therefor
US5736785A (en) 1996-12-20 1998-04-07 Industrial Technology Research Institute Semiconductor package for improving the capability of spreading heat
JP3400279B2 (ja) 1997-01-13 2003-04-28 株式会社新川 バンプ形成方法
US5898991A (en) 1997-01-16 1999-05-04 International Business Machines Corporation Methods of fabrication of coaxial vias and magnetic devices
US5839191A (en) 1997-01-24 1998-11-24 Unisys Corporation Vibrating template method of placing solder balls on the I/O pads of an integrated circuit package
JPH1118364A (ja) 1997-06-27 1999-01-22 Matsushita Electric Ind Co Ltd キャプスタンモータ
EP1030369B1 (en) 1997-08-19 2007-12-12 Hitachi, Ltd. Multichip module structure and method for manufacturing the same
CA2213590C (en) 1997-08-21 2006-11-07 Keith C. Carroll Flexible circuit connector and method of making same
JP3859318B2 (ja) 1997-08-29 2006-12-20 シチズン電子株式会社 電子回路のパッケージ方法
US6525414B2 (en) 1997-09-16 2003-02-25 Matsushita Electric Industrial Co., Ltd. Semiconductor device including a wiring board and semiconductor elements mounted thereon
JP3937265B2 (ja) 1997-09-29 2007-06-27 エルピーダメモリ株式会社 半導体装置
JP3262531B2 (ja) 1997-10-02 2002-03-04 インターナショナル・ビジネス・マシーンズ・コーポレーション 曲げられたフライング・リード・ワイヤ・ボンデイング・プロセス
JP2978861B2 (ja) 1997-10-28 1999-11-15 九州日本電気株式会社 モールドｂｇａ型半導体装置及びその製造方法
US6038136A (en) 1997-10-29 2000-03-14 Hestia Technologies, Inc. Chip package with molded underfill
JP3393800B2 (ja) 1997-11-05 2003-04-07 新光電気工業株式会社 半導体装置の製造方法
JPH11219984A (ja) 1997-11-06 1999-08-10 Sharp Corp 半導体装置パッケージおよびその製造方法ならびにそのための回路基板
US6222136B1 (en) 1997-11-12 2001-04-24 International Business Machines Corporation Printed circuit board with continuous connective bumps
US6002168A (en) 1997-11-25 1999-12-14 Tessera, Inc. Microelectronic component with rigid interposer
US6038133A (en) 1997-11-25 2000-03-14 Matsushita Electric Industrial Co., Ltd. Circuit component built-in module and method for producing the same
JPH11163022A (ja) 1997-11-28 1999-06-18 Sony Corp 半導体装置、その製造方法及び電子機器
US6124546A (en) 1997-12-03 2000-09-26 Advanced Micro Devices, Inc. Integrated circuit chip package and method of making the same
US6260264B1 (en) 1997-12-08 2001-07-17 3M Innovative Properties Company Methods for making z-axis electrical connections
US6052287A (en) 1997-12-09 2000-04-18 Sandia Corporation Silicon ball grid array chip carrier
US5973391A (en) 1997-12-11 1999-10-26 Read-Rite Corporation Interposer with embedded circuitry and method for using the same to package microelectronic units
JPH11220082A (ja) 1998-02-03 1999-08-10 Oki Electric Ind Co Ltd 半導体装置
JP3536650B2 (ja) 1998-02-27 2004-06-14 富士ゼロックス株式会社 バンプ形成方法および装置
JPH11260856A (ja) 1998-03-11 1999-09-24 Matsushita Electron Corp 半導体装置及びその製造方法並びに半導体装置の実装構造
US5933713A (en) 1998-04-06 1999-08-03 Micron Technology, Inc. Method of forming overmolded chip scale package and resulting product
US6222276B1 (en) 1998-04-07 2001-04-24 International Business Machines Corporation Through-chip conductors for low inductance chip-to-chip integration and off-chip connections
KR100260997B1 (ko) 1998-04-08 2000-07-01 마이클 디. 오브라이언 반도체패키지
US6329224B1 (en) 1998-04-28 2001-12-11 Tessera, Inc. Encapsulation of microelectronic assemblies
US6180881B1 (en) 1998-05-05 2001-01-30 Harlan Ruben Isaak Chip stack and method of making same
JPH11330134A (ja) 1998-05-12 1999-11-30 Hitachi Ltd ワイヤボンディング方法およびその装置並びに半導体装置
KR100266693B1 (ko) 1998-05-30 2000-09-15 김영환 적층가능한 비지에이 반도체 칩 패키지 및 그 제조방법
US5977640A (en) 1998-06-26 1999-11-02 International Business Machines Corporation Highly integrated chip-on-chip packaging
KR100265563B1 (ko) 1998-06-29 2000-09-15 김영환 볼 그리드 어레이 패키지 및 그의 제조 방법
US6414391B1 (en) 1998-06-30 2002-07-02 Micron Technology, Inc. Module assembly for stacked BGA packages with a common bus bar in the assembly
US6164523A (en) 1998-07-01 2000-12-26 Semiconductor Components Industries, Llc Electronic component and method of manufacture
US5854507A (en) 1998-07-21 1998-12-29 Hewlett-Packard Company Multiple chip assembly
US6399426B1 (en) 1998-07-21 2002-06-04 Miguel Albert Capote Semiconductor flip-chip package and method for the fabrication thereof
US6515355B1 (en) 1998-09-02 2003-02-04 Micron Technology, Inc. Passivation layer for packaged integrated circuits
JP2000091383A (ja) 1998-09-07 2000-03-31 Ngk Spark Plug Co Ltd 配線基板
US6194250B1 (en) 1998-09-14 2001-02-27 Motorola, Inc. Low-profile microelectronic package
US6158647A (en) 1998-09-29 2000-12-12 Micron Technology, Inc. Concave face wire bond capillary
US6684007B2 (en) 1998-10-09 2004-01-27 Fujitsu Limited Optical coupling structures and the fabrication processes
JP2000311915A (ja) 1998-10-14 2000-11-07 Texas Instr Inc <Ti> 半導体デバイス及びボンディング方法
JP3407275B2 (ja) 1998-10-28 2003-05-19 インターナショナル・ビジネス・マシーンズ・コーポレーション バンプ及びその形成方法
US6332270B2 (en) 1998-11-23 2001-12-25 International Business Machines Corporation Method of making high density integral test probe
US6255126B1 (en) 1998-12-02 2001-07-03 Formfactor, Inc. Lithographic contact elements
US6926796B1 (en) 1999-01-29 2005-08-09 Matsushita Electric Industrial Co., Ltd. Electronic parts mounting method and device therefor
US6206273B1 (en) 1999-02-17 2001-03-27 International Business Machines Corporation Structures and processes to create a desired probetip contact geometry on a wafer test probe
KR100319609B1 (ko) 1999-03-09 2002-01-05 김영환 와이어 어래이드 칩 사이즈 패키지 및 그 제조방법
US6177729B1 (en) 1999-04-03 2001-01-23 International Business Machines Corporation Rolling ball connector
US6211574B1 (en) 1999-04-16 2001-04-03 Advanced Semiconductor Engineering Inc. Semiconductor package with wire protection and method therefor
JP2000323516A (ja) 1999-05-14 2000-11-24 Fujitsu Ltd 配線基板の製造方法及び配線基板及び半導体装置
US6376769B1 (en) 1999-05-18 2002-04-23 Amerasia International Technology, Inc. High-density electronic package, and method for making same
US6258625B1 (en) 1999-05-18 2001-07-10 International Business Machines Corporation Method of interconnecting electronic components using a plurality of conductive studs
JP3398721B2 (ja) 1999-05-20 2003-04-21 アムコー テクノロジー コリア インコーポレーティド 半導体パッケージ及びその製造方法
US6238949B1 (en) 1999-06-18 2001-05-29 National Semiconductor Corporation Method and apparatus for forming a plastic chip on chip package module
JP4367730B2 (ja) 1999-06-25 2009-11-18 株式会社エンプラス Ｉｃソケット及び該ｉｃソケットのバネ手段
US6228687B1 (en) 1999-06-28 2001-05-08 Micron Technology, Inc. Wafer-level package and methods of fabricating
TW417839U (en) 1999-07-30 2001-01-01 Shen Ming Tung Stacked memory module structure and multi-layered stacked memory module structure using the same
JP5333337B2 (ja) 1999-08-12 2013-11-06 富士通セミコンダクター株式会社 半導体装置の製造方法
JP4526651B2 (ja) 1999-08-12 2010-08-18 富士通セミコンダクター株式会社 半導体装置
US6168965B1 (en) 1999-08-12 2001-01-02 Tower Semiconductor Ltd. Method for making backside illuminated image sensor
US6319764B1 (en) 1999-08-25 2001-11-20 Micron Technology, Inc. Method of forming haze-free BST films
EP1139705B1 (en) 1999-09-02 2006-11-22 Ibiden Co., Ltd. Printed wiring board and method of producing the same
US6867499B1 (en) 1999-09-30 2005-03-15 Skyworks Solutions, Inc. Semiconductor packaging
JP3513444B2 (ja) 1999-10-20 2004-03-31 株式会社新川 ピン状ワイヤ等の形成方法
JP2001127246A (ja) 1999-10-29 2001-05-11 Fujitsu Ltd 半導体装置
US6362525B1 (en) 1999-11-09 2002-03-26 Cypress Semiconductor Corp. Circuit structure including a passive element formed within a grid array substrate and method for making the same
JP3619410B2 (ja) 1999-11-18 2005-02-09 株式会社ルネサステクノロジ バンプ形成方法およびそのシステム
JP3798597B2 (ja) 1999-11-30 2006-07-19 富士通株式会社 半導体装置
JP3566156B2 (ja) 1999-12-02 2004-09-15 株式会社新川 ピン状ワイヤ等の形成方法
US6790757B1 (en) 1999-12-20 2004-09-14 Agere Systems Inc. Wire bonding method for copper interconnects in semiconductor devices
KR100426494B1 (ko) 1999-12-20 2004-04-13 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 이것의 제조방법
KR20010061849A (ko) 1999-12-29 2001-07-07 박종섭 웨이퍼 레벨 패키지
JP2001196407A (ja) 2000-01-14 2001-07-19 Seiko Instruments Inc 半導体装置および半導体装置の形成方法
US6710454B1 (en) 2000-02-16 2004-03-23 Micron Technology, Inc. Adhesive layer for an electronic apparatus having multiple semiconductor devices
JP2001319992A (ja) 2000-02-28 2001-11-16 Shinko Electric Ind Co Ltd 配線基板、半導体装置及びそれらの製造方法
JP2001339011A (ja) 2000-03-24 2001-12-07 Shinko Electric Ind Co Ltd 半導体装置およびその製造方法
JP3980807B2 (ja) 2000-03-27 2007-09-26 株式会社東芝 半導体装置及び半導体モジュール
JP2001274196A (ja) 2000-03-28 2001-10-05 Rohm Co Ltd 半導体装置
US6581276B2 (en) 2000-04-04 2003-06-24 Amerasia International Technology, Inc. Fine-pitch flexible connector, and method for making same
KR100583491B1 (ko) 2000-04-07 2006-05-24 앰코 테크놀로지 코리아 주식회사 반도체패키지 및 그 제조방법
US6578754B1 (en) 2000-04-27 2003-06-17 Advanpack Solutions Pte. Ltd. Pillar connections for semiconductor chips and method of manufacture
US6531335B1 (en) 2000-04-28 2003-03-11 Micron Technology, Inc. Interposers including upwardly protruding dams, semiconductor device assemblies including the interposers, and methods
JP2001326236A (ja) 2000-05-12 2001-11-22 Nec Kyushu Ltd 半導体装置の製造方法
JP2001326304A (ja) 2000-05-15 2001-11-22 Toshiba Corp 半導体装置及びその製造方法
US6522018B1 (en) 2000-05-16 2003-02-18 Micron Technology, Inc. Ball grid array chip packages having improved testing and stacking characteristics
US6647310B1 (en) 2000-05-30 2003-11-11 Advanced Micro Devices, Inc. Temperature control of an integrated circuit
US6717245B1 (en) 2000-06-02 2004-04-06 Micron Technology, Inc. Chip scale packages performed by wafer level processing
US6531784B1 (en) 2000-06-02 2003-03-11 Amkor Technology, Inc. Semiconductor package with spacer strips
US6395199B1 (en) 2000-06-07 2002-05-28 Graftech Inc. Process for providing increased conductivity to a material
US6560117B2 (en) 2000-06-28 2003-05-06 Micron Technology, Inc. Packaged microelectronic die assemblies and methods of manufacture
US6525413B1 (en) 2000-07-12 2003-02-25 Micron Technology, Inc. Die to die connection method and assemblies and packages including dice so connected
US6476583B2 (en) 2000-07-21 2002-11-05 Jomahip, Llc Automatic battery charging system for a battery back-up DC power supply
JP2002050871A (ja) 2000-08-02 2002-02-15 Casio Comput Co Ltd ビルドアップ回路基板およびその製造方法
SE517086C2 (sv) 2000-08-08 2002-04-09 Ericsson Telefon Ab L M Förfarande för säkring av lodkulor och eventuella komponenter, vilka är fästa på en och samma sida av ett substrat
US20020020898A1 (en) 2000-08-16 2002-02-21 Vu Quat T. Microelectronic substrates with integrated devices
US6462575B1 (en) 2000-08-28 2002-10-08 Micron Technology, Inc. Method and system for wafer level testing and burning-in semiconductor components
JP2002076250A (ja) 2000-08-29 2002-03-15 Nec Corp 半導体装置
US6614103B1 (en) 2000-09-01 2003-09-02 General Electric Company Plastic packaging of LED arrays
JP3874062B2 (ja) 2000-09-05 2007-01-31 セイコーエプソン株式会社 半導体装置
US6507104B2 (en) 2000-09-07 2003-01-14 Siliconware Precision Industries Co., Ltd. Semiconductor package with embedded heat-dissipating device
US7009297B1 (en) 2000-10-13 2006-03-07 Bridge Semiconductor Corporation Semiconductor chip assembly with embedded metal particle
US6423570B1 (en) 2000-10-18 2002-07-23 Intel Corporation Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby
US6538336B1 (en) 2000-11-14 2003-03-25 Rambus Inc. Wirebond assembly for high-speed integrated circuits
JP4505983B2 (ja) 2000-12-01 2010-07-21 日本電気株式会社 半導体装置
JP3798620B2 (ja) 2000-12-04 2006-07-19 富士通株式会社 半導体装置の製造方法
US6734539B2 (en) 2000-12-27 2004-05-11 Lucent Technologies Inc. Stacked module package
TW511405B (en) 2000-12-27 2002-11-21 Matsushita Electric Ind Co Ltd Device built-in module and manufacturing method thereof
KR100393102B1 (ko) 2000-12-29 2003-07-31 앰코 테크놀로지 코리아 주식회사 스택형 반도체패키지
AUPR244801A0 (en) 2001-01-10 2001-02-01 Silverbrook Research Pty Ltd A method and apparatus (WSM01)
US6388322B1 (en) 2001-01-17 2002-05-14 Aralight, Inc. Article comprising a mechanically compliant bump
US6653170B1 (en) 2001-02-06 2003-11-25 Charles W. C. Lin Semiconductor chip assembly with elongated wire ball bonded to chip and electrolessly plated to support circuit
US6472743B2 (en) 2001-02-22 2002-10-29 Siliconware Precision Industries, Co., Ltd. Semiconductor package with heat dissipating structure
KR100401020B1 (ko) 2001-03-09 2003-10-08 앰코 테크놀로지 코리아 주식회사 반도체칩의 스택킹 구조 및 이를 이용한 반도체패키지
JP2002280414A (ja) 2001-03-22 2002-09-27 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2002289769A (ja) 2001-03-26 2002-10-04 Matsushita Electric Ind Co Ltd 積層型半導体装置およびその製造方法
SG108245A1 (en) 2001-03-30 2005-01-28 Micron Technology Inc Ball grid array interposer, packages and methods
US6874910B2 (en) 2001-04-12 2005-04-05 Matsushita Electric Works, Ltd. Light source device using LED, and method of producing same
US7115986B2 (en) 2001-05-02 2006-10-03 Micron Technology, Inc. Flexible ball grid array chip scale packages
US6825552B2 (en) 2001-05-09 2004-11-30 Tessera, Inc. Connection components with anisotropic conductive material interconnection
TW544826B (en) 2001-05-18 2003-08-01 Nec Electronics Corp Flip-chip-type semiconductor device and manufacturing method thereof
US6930256B1 (en) 2002-05-01 2005-08-16 Amkor Technology, Inc. Integrated circuit substrate having laser-embedded conductive patterns and method therefor
US6900528B2 (en) 2001-06-21 2005-05-31 Micron Technology, Inc. Stacked mass storage flash memory package
US6754407B2 (en) 2001-06-26 2004-06-22 Intel Corporation Flip-chip package integrating optical and electrical devices and coupling to a waveguide on a board
US20030006494A1 (en) 2001-07-03 2003-01-09 Lee Sang Ho Thin profile stackable semiconductor package and method for manufacturing
US6486545B1 (en) 2001-07-26 2002-11-26 Amkor Technology, Inc. Pre-drilled ball grid array package
US6451626B1 (en) 2001-07-27 2002-09-17 Charles W.C. Lin Three-dimensional stacked semiconductor package
US6765287B1 (en) 2001-07-27 2004-07-20 Charles W. C. Lin Three-dimensional stacked semiconductor package
JP4023159B2 (ja) 2001-07-31 2007-12-19 ソニー株式会社 半導体装置の製造方法及び積層半導体装置の製造方法
JP3895952B2 (ja) 2001-08-06 2007-03-22 日本電気株式会社 半透過型液晶表示装置及びその製造方法
US6550666B2 (en) 2001-08-21 2003-04-22 Advanpack Solutions Pte Ltd Method for forming a flip chip on leadframe semiconductor package
US7605479B2 (en) 2001-08-22 2009-10-20 Tessera, Inc. Stacked chip assembly with encapsulant layer
US7176506B2 (en) 2001-08-28 2007-02-13 Tessera, Inc. High frequency chip packages with connecting elements
US6864166B1 (en) 2001-08-29 2005-03-08 Micron Technology, Inc. Method of manufacturing wire bonded microelectronic device assemblies
SG117395A1 (en) 2001-08-29 2005-12-29 Micron Technology Inc Wire bonded microelectronic device assemblies and methods of manufacturing same
US6787926B2 (en) 2001-09-05 2004-09-07 Taiwan Semiconductor Manufacturing Co., Ltd Wire stitch bond on an integrated circuit bond pad and method of making the same
US20030057544A1 (en) 2001-09-13 2003-03-27 Nathan Richard J. Integrated assembly protocol
US6476506B1 (en) 2001-09-28 2002-11-05 Motorola, Inc. Packaged semiconductor with multiple rows of bond pads and method therefor
DE10297316T5 (de) 2001-10-09 2004-12-09 Tessera, Inc., San Jose Gestapelte Baugruppen
US6977440B2 (en) 2001-10-09 2005-12-20 Tessera, Inc. Stacked packages
JP2003122611A (ja) 2001-10-11 2003-04-25 Oki Electric Ind Co Ltd データ提供方法及びサーバ装置
JP4257771B2 (ja) 2001-10-16 2009-04-22 シンジーテック株式会社 導電性ブレード
JP3875077B2 (ja) 2001-11-16 2007-01-31 富士通株式会社 電子デバイス及びデバイス接続方法
US20030094666A1 (en) 2001-11-16 2003-05-22 R-Tec Corporation Interposer
JP2003174124A (ja) 2001-12-04 2003-06-20 Sainekkusu:Kk 半導体装置の外部電極形成方法
KR100435813B1 (ko) 2001-12-06 2004-06-12 삼성전자주식회사 금속 바를 이용하는 멀티 칩 패키지와 그 제조 방법
JP2003197668A (ja) 2001-12-10 2003-07-11 Senmao Koochii Kofun Yugenkoshi 半導体パッケージ用のボンディングワイヤ及びその製造方法
JP3507059B2 (ja) 2002-06-27 2004-03-15 沖電気工業株式会社 積層マルチチップパッケージ
JP2003197669A (ja) 2001-12-28 2003-07-11 Seiko Epson Corp ボンディング方法及びボンディング装置
TW584950B (en) 2001-12-31 2004-04-21 Megic Corp Chip packaging structure and process thereof
TW548816B (en) 2002-01-23 2003-08-21 Via Tech Inc Formation method of conductor pillar
JP3935370B2 (ja) 2002-02-19 2007-06-20 セイコーエプソン株式会社 バンプ付き半導体素子の製造方法、半導体装置及びその製造方法、回路基板並びに電子機器
SG115456A1 (en) 2002-03-04 2005-10-28 Micron Technology Inc Semiconductor die packages with recessed interconnecting structures and methods for assembling the same
DE10209922A1 (de) 2002-03-07 2003-10-02 Infineon Technologies Ag Elektronisches Modul, Nutzen mit zu vereinzelnden elektronischen Modulen und Verfahren zu deren Herstellung
US6653723B2 (en) 2002-03-09 2003-11-25 Fujitsu Limited System for providing an open-cavity low profile encapsulated semiconductor package
KR100452819B1 (ko) 2002-03-18 2004-10-15 삼성전기주식회사 칩 패키지 및 그 제조방법
US6979230B2 (en) 2002-03-20 2005-12-27 Gabe Cherian Light socket
JP2003318327A (ja) 2002-04-22 2003-11-07 Mitsui Chemicals Inc プリント配線板および積層パッケージ
US7323767B2 (en) 2002-04-25 2008-01-29 Micron Technology, Inc. Standoffs for centralizing internals in packaging process
US7633765B1 (en) 2004-03-23 2009-12-15 Amkor Technology, Inc. Semiconductor package including a top-surface metal layer for implementing circuit features
US7078822B2 (en) 2002-06-25 2006-07-18 Intel Corporation Microelectronic device interconnects
US6906415B2 (en) 2002-06-27 2005-06-14 Micron Technology, Inc. Semiconductor device assemblies and packages including multiple semiconductor devices and methods
JP4601892B2 (ja) 2002-07-04 2010-12-22 ラムバス・インコーポレーテッド 半導体装置および半導体チップのバンプ製造方法
JP2004047702A (ja) 2002-07-11 2004-02-12 Toshiba Corp 半導体装置積層モジュール
US6756252B2 (en) 2002-07-17 2004-06-29 Texas Instrument Incorporated Multilayer laser trim interconnect method
US6987032B1 (en) 2002-07-19 2006-01-17 Asat Ltd. Ball grid array package and process for manufacturing same
US7943436B2 (en) 2002-07-29 2011-05-17 Synopsys, Inc. Integrated circuit devices and methods and apparatuses for designing integrated circuit devices
TW549592U (en) 2002-08-16 2003-08-21 Via Tech Inc Integrated circuit package with a balanced-part structure
AU2003265417A1 (en) 2002-08-16 2004-03-03 Tessera, Inc. Microelectronic packages with self-aligning features
US6740546B2 (en) 2002-08-21 2004-05-25 Micron Technology, Inc. Packaged microelectronic devices and methods for assembling microelectronic devices
US6964881B2 (en) 2002-08-27 2005-11-15 Micron Technology, Inc. Multi-chip wafer level system packages and methods of forming same
JP3765778B2 (ja) 2002-08-29 2006-04-12 ローム株式会社 ワイヤボンディング用キャピラリ及びこれを用いたワイヤボンディング方法
JP2004095799A (ja) 2002-08-30 2004-03-25 Toshiba Corp 半導体装置およびその製造方法
US20040041757A1 (en) 2002-09-04 2004-03-04 Ming-Hsiang Yang Light emitting diode display module with high heat-dispersion and the substrate thereof
US7294928B2 (en) 2002-09-06 2007-11-13 Tessera, Inc. Components, methods and assemblies for stacked packages
US7246431B2 (en) 2002-09-06 2007-07-24 Tessera, Inc. Methods of making microelectronic packages including folded substrates
US7071547B2 (en) 2002-09-11 2006-07-04 Tessera, Inc. Assemblies having stacked semiconductor chips and methods of making same
US7229906B2 (en) 2002-09-19 2007-06-12 Kulicke And Soffa Industries, Inc. Method and apparatus for forming bumps for semiconductor interconnections using a wire bonding machine
CN100380636C (zh) 2002-09-30 2008-04-09 先进互连技术有限公司 用于整体成型组件的热增强封装及其制造方法
US7045884B2 (en) 2002-10-04 2006-05-16 International Rectifier Corporation Semiconductor device package
US6906416B2 (en) 2002-10-08 2005-06-14 Chippac, Inc. Semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (BGA) package
US6989122B1 (en) 2002-10-17 2006-01-24 National Semiconductor Corporation Techniques for manufacturing flash-free contacts on a semiconductor package
TW567601B (en) 2002-10-18 2003-12-21 Siliconware Precision Industries Co Ltd Module device of stacked semiconductor package and method for fabricating the same
TWI221664B (en) 2002-11-07 2004-10-01 Via Tech Inc Structure of chip package and process thereof
US20050176233A1 (en) 2002-11-15 2005-08-11 Rajeev Joshi Wafer-level chip scale package and method for fabricating and using the same
JP2004172157A (ja) 2002-11-15 2004-06-17 Shinko Electric Ind Co Ltd 半導体パッケージおよびパッケージスタック半導体装置
JP2004172477A (ja) 2002-11-21 2004-06-17 Kaijo Corp ワイヤループ形状、そのワイヤループ形状を備えた半導体装置、ワイヤボンディング方法及び半導体製造装置
JP4464041B2 (ja) 2002-12-13 2010-05-19 キヤノン株式会社 柱状構造体、柱状構造体を有する電極、及びこれらの作製方法
JP2004200316A (ja) 2002-12-17 2004-07-15 Shinko Electric Ind Co Ltd 半導体装置
US20050161814A1 (en) 2002-12-27 2005-07-28 Fujitsu Limited Method for forming bumps, semiconductor device and method for manufacturing same, substrate processing apparatus, and semiconductor manufacturing apparatus
KR100621991B1 (ko) 2003-01-03 2006-09-13 삼성전자주식회사 칩 스케일 적층 패키지
JP2004221257A (ja) 2003-01-14 2004-08-05 Seiko Epson Corp ワイヤボンディング方法及びワイヤボンディング装置
WO2004077525A2 (en) 2003-02-25 2004-09-10 Tessera, Inc. Ball grid array with bumps
TW583757B (en) 2003-02-26 2004-04-11 Advanced Semiconductor Eng A structure of a flip-chip package and a process thereof
US20040217471A1 (en) 2003-02-27 2004-11-04 Tessera, Inc. Component and assemblies with ends offset downwardly
JP3885747B2 (ja) 2003-03-13 2007-02-28 株式会社デンソー ワイヤボンディング方法
JP2004343030A (ja) 2003-03-31 2004-12-02 North:Kk 配線回路基板とその製造方法とその配線回路基板を備えた回路モジュール
JP2004319892A (ja) 2003-04-18 2004-11-11 Renesas Technology Corp 半導体装置の製造方法
JP4199588B2 (ja) 2003-04-25 2008-12-17 テセラ・インターコネクト・マテリアルズ，インコーポレイテッド 配線回路基板の製造方法、及び、この配線回路基板を用いた半導体集積回路装置の製造方法
JP2004327855A (ja) 2003-04-25 2004-11-18 Nec Electronics Corp 半導体装置およびその製造方法
DE10320646A1 (de) 2003-05-07 2004-09-16 Infineon Technologies Ag Elektronisches Bauteil, sowie Systemträger und Nutzen zur Herstellung desselben
JP4145730B2 (ja) 2003-06-17 2008-09-03 松下電器産業株式会社 半導体内蔵モジュール
US20040262728A1 (en) 2003-06-30 2004-12-30 Sterrett Terry L. Modular device assemblies
KR100604821B1 (ko) 2003-06-30 2006-07-26 삼성전자주식회사 적층형 볼 그리드 어레이 패키지 및 그 제조방법
JP2005033141A (ja) 2003-07-11 2005-02-03 Sony Corp 半導体装置及びその製造方法、疑似ウェーハ及びその製造方法、並びに半導体装置の実装構造
US7227095B2 (en) 2003-08-06 2007-06-05 Micron Technology, Inc. Wire bonders and methods of wire-bonding
KR100537892B1 (ko) 2003-08-26 2005-12-21 삼성전자주식회사 칩 스택 패키지와 그 제조 방법
KR100546374B1 (ko) 2003-08-28 2006-01-26 삼성전자주식회사 센터 패드를 갖는 적층형 반도체 패키지 및 그 제조방법
US7372151B1 (en) 2003-09-12 2008-05-13 Asat Ltd. Ball grid array package and process for manufacturing same
JP2005093551A (ja) 2003-09-12 2005-04-07 Genusion:Kk 半導体装置のパッケージ構造およびパッケージ化方法
JP3999720B2 (ja) 2003-09-16 2007-10-31 沖電気工業株式会社 半導体装置およびその製造方法
US7061096B2 (en) 2003-09-24 2006-06-13 Silicon Pipe, Inc. Multi-surface IC packaging structures and methods for their manufacture
WO2005031861A1 (en) 2003-09-26 2005-04-07 Tessera, Inc. Structure and method of making capped chips including a flowable conductive medium
US7462936B2 (en) 2003-10-06 2008-12-09 Tessera, Inc. Formation of circuitry with modification of feature height
US7495179B2 (en) 2003-10-06 2009-02-24 Tessera, Inc. Components with posts and pads
JP4272968B2 (ja) 2003-10-16 2009-06-03 エルピーダメモリ株式会社 半導体装置および半導体チップ制御方法
JP2005126392A (ja) 2003-10-27 2005-05-19 Idemitsu Kosan Co Ltd 第三級カルボン酸組成物
JP4167965B2 (ja) 2003-11-07 2008-10-22 テセラ・インターコネクト・マテリアルズ，インコーポレイテッド 配線回路用部材の製造方法
KR100564585B1 (ko) 2003-11-13 2006-03-28 삼성전자주식회사 이중 스택된 ｂｇａ 패키지 및 다중 스택된 ｂｇａ 패키지
TWI227555B (en) 2003-11-17 2005-02-01 Advanced Semiconductor Eng Structure of chip package and the process thereof
KR100621992B1 (ko) 2003-11-19 2006-09-13 삼성전자주식회사 이종 소자들의 웨이퍼 레벨 적층 구조와 방법 및 이를이용한 시스템-인-패키지
JP2005183923A (ja) 2003-11-28 2005-07-07 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
US7345361B2 (en) 2003-12-04 2008-03-18 Intel Corporation Stackable integrated circuit packaging
JP2005175019A (ja) 2003-12-08 2005-06-30 Sharp Corp 半導体装置及び積層型半導体装置
JP5197961B2 (ja) 2003-12-17 2013-05-15 スタッツ・チップパック・インコーポレイテッド マルチチップパッケージモジュールおよびその製造方法
JP2005177641A (ja) 2003-12-19 2005-07-07 Nitto Denko Corp エアフィルタユニットおよびその製造方法、並びにエアフィルタユニット集合体
DE10360708B4 (de) 2003-12-19 2008-04-10 Infineon Technologies Ag Halbleitermodul mit einem Halbleiterstapel, Umverdrahtungsplatte, und Verfahren zur Herstellung derselben
JP4334996B2 (ja) 2003-12-24 2009-09-30 株式会社フジクラ 多層配線板用基材、両面配線板およびそれらの製造方法
JP3917133B2 (ja) 2003-12-26 2007-05-23 株式会社東芝 インターフェイスモジュール付ｌｓｉパッケージ及びそれに用いるインターポーザ、インターフェイスモジュール、接続モニタ回路、信号処理ｌｓｉ
US7495644B2 (en) 2003-12-26 2009-02-24 Semiconductor Energy Laboratory Co., Ltd. Display device and method for manufacturing display device
US6900530B1 (en) 2003-12-29 2005-05-31 Ramtek Technology, Inc. Stacked IC
US6917098B1 (en) 2003-12-29 2005-07-12 Texas Instruments Incorporated Three-level leadframe for no-lead packages
US7709968B2 (en) 2003-12-30 2010-05-04 Tessera, Inc. Micro pin grid array with pin motion isolation
US7176043B2 (en) 2003-12-30 2007-02-13 Tessera, Inc. Microelectronic packages and methods therefor
US8207604B2 (en) 2003-12-30 2012-06-26 Tessera, Inc. Microelectronic package comprising offset conductive posts on compliant layer
JP2005203497A (ja) 2004-01-14 2005-07-28 Toshiba Corp 半導体装置およびその製造方法
US20050173807A1 (en) 2004-02-05 2005-08-11 Jianbai Zhu High density vertically stacked semiconductor device
US8399972B2 (en) 2004-03-04 2013-03-19 Skyworks Solutions, Inc. Overmolded semiconductor package with a wirebond cage for EMI shielding
US7198987B1 (en) 2004-03-04 2007-04-03 Skyworks Solutions, Inc. Overmolded semiconductor package with an integrated EMI and RFI shield
US7095105B2 (en) 2004-03-23 2006-08-22 Texas Instruments Incorporated Vertically stacked semiconductor device
JP4484035B2 (ja) 2004-04-06 2010-06-16 セイコーエプソン株式会社 半導体装置の製造方法
US8092734B2 (en) 2004-05-13 2012-01-10 Aptina Imaging Corporation Covers for microelectronic imagers and methods for wafer-level packaging of microelectronics imagers
US7629695B2 (en) 2004-05-20 2009-12-08 Kabushiki Kaisha Toshiba Stacked electronic component and manufacturing method thereof
US6962864B1 (en) 2004-05-26 2005-11-08 National Chung Cheng University Wire-bonding method for chips with copper interconnects by introducing a thin layer
US7233057B2 (en) 2004-05-28 2007-06-19 Nokia Corporation Integrated circuit package with optimized mold shape
TWI255022B (en) 2004-05-31 2006-05-11 Via Tech Inc Circuit carrier and manufacturing process thereof
US7453157B2 (en) 2004-06-25 2008-11-18 Tessera, Inc. Microelectronic packages and methods therefor
TWI250596B (en) 2004-07-23 2006-03-01 Ind Tech Res Inst Wafer-level chip scale packaging method
JP3956965B2 (ja) 2004-09-07 2007-08-08 日立エーアイシー株式会社 チップ部品型発光装置及びそのための配線基板
US7290448B2 (en) 2004-09-10 2007-11-06 Yamaha Corporation Physical quantity sensor, lead frame, and manufacturing method therefor
CN1755929B (zh) 2004-09-28 2010-08-18 飞思卡尔半导体（中国）有限公司 形成半导体封装及其结构的方法
JP4385329B2 (ja) 2004-10-08 2009-12-16 Ｏｋｉセミコンダクタ株式会社 半導体装置の製造方法
US7595548B2 (en) 2004-10-08 2009-09-29 Yamaha Corporation Physical quantity sensor and manufacturing method therefor
JP4671802B2 (ja) 2004-10-18 2011-04-20 富士通株式会社 めっき方法、半導体装置の製造方法及び回路基板の製造方法
US20060087013A1 (en) 2004-10-21 2006-04-27 Etron Technology, Inc. Stacked multiple integrated circuit die package assembly
US8646675B2 (en) 2004-11-02 2014-02-11 Hid Global Gmbh Laying apparatus, contact-making apparatus, movement system, laying and contact-making unit, production system, method for production and a transponder unit
US8525314B2 (en) 2004-11-03 2013-09-03 Tessera, Inc. Stacked packaging improvements
TW200631111A (en) 2004-11-04 2006-09-01 Koninkl Philips Electronics Nv Nanotube-based circuit connection approach
US7750483B1 (en) 2004-11-10 2010-07-06 Bridge Semiconductor Corporation Semiconductor chip assembly with welded metal pillar and enlarged plated contact terminal
US7268421B1 (en) 2004-11-10 2007-09-11 Bridge Semiconductor Corporation Semiconductor chip assembly with welded metal pillar that includes enlarged ball bond
JP4917257B2 (ja) 2004-11-12 2012-04-18 浜松ホトニクス株式会社 レーザ加工方法
KR100674926B1 (ko) 2004-12-08 2007-01-26 삼성전자주식회사 메모리 카드 및 그 제조 방법
US7301770B2 (en) 2004-12-10 2007-11-27 International Business Machines Corporation Cooling apparatus, cooled electronic module, and methods of fabrication thereof employing thermally conductive, wire-bonded pin fins
JP4504798B2 (ja) 2004-12-16 2010-07-14 パナソニック株式会社 多段構成半導体モジュール
KR100843137B1 (ko) 2004-12-27 2008-07-02 삼성전자주식회사 반도체 소자 패키지
JP2006186086A (ja) 2004-12-27 2006-07-13 Itoo:Kk プリント基板のはんだ付け方法およびブリッジ防止用ガイド板
DE102005006333B4 (de) 2005-02-10 2007-10-18 Infineon Technologies Ag Halbleiterbauteil mit mehreren Bondanschlüssen und gebondeten Kontaktelementen unterschiedlicher Metallzusammensetzung und Verfahren zur Herstellung desselben
DE102005006995B4 (de) 2005-02-15 2008-01-24 Infineon Technologies Ag Halbleiterbauteil mit Kunstoffgehäuse und Außenanschlüssen sowie Verfahren zur Herstellung desselben
KR100867038B1 (ko) 2005-03-02 2008-11-04 삼성전기주식회사 커패시터 내장형 인쇄회로기판 및 그 제조방법
KR100630741B1 (ko) 2005-03-04 2006-10-02 삼성전자주식회사 다중 몰딩에 의한 적층형 반도체 패키지 및 그 제조방법
US7939934B2 (en) 2005-03-16 2011-05-10 Tessera, Inc. Microelectronic packages and methods therefor
US20060216868A1 (en) 2005-03-25 2006-09-28 Advanced Semiconductor Engineering Inc. Package structure and fabrication thereof
US7582963B2 (en) 2005-03-29 2009-09-01 Texas Instruments Incorporated Vertically integrated system-in-a-package
US7371676B2 (en) 2005-04-08 2008-05-13 Micron Technology, Inc. Method for fabricating semiconductor components with through wire interconnects
TWI284394B (en) 2005-05-12 2007-07-21 Advanced Semiconductor Eng Lid used in package structure and the package structure of having the same
JP2006324553A (ja) 2005-05-20 2006-11-30 Renesas Technology Corp 半導体装置及びその製造方法
US7528474B2 (en) 2005-05-31 2009-05-05 Stats Chippac Ltd. Stacked semiconductor package assembly having hollowed substrate
US7216794B2 (en) 2005-06-09 2007-05-15 Texas Instruments Incorporated Bond capillary design for ribbon wire bonding
JP4322844B2 (ja) 2005-06-10 2009-09-02 シャープ株式会社 半導体装置および積層型半導体装置
WO2007004137A2 (en) 2005-07-01 2007-01-11 Koninklijke Philips Electronics N.V. Electronic device
TWI294757B (en) 2005-07-06 2008-03-11 Delta Electronics Inc Circuit board with a through hole wire, and forming method thereof
US7476608B2 (en) 2005-07-14 2009-01-13 Hewlett-Packard Development Company, L.P. Electrically connecting substrate with electrical device
JP4787559B2 (ja) 2005-07-26 2011-10-05 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US7355289B2 (en) 2005-07-29 2008-04-08 Freescale Semiconductor, Inc. Packaged integrated circuit with enhanced thermal dissipation
TWI263313B (en) 2005-08-15 2006-10-01 Phoenix Prec Technology Corp Stack structure of semiconductor component embedded in supporting board
SG130055A1 (en) 2005-08-19 2007-03-20 Micron Technology Inc Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices
SG130066A1 (en) 2005-08-26 2007-03-20 Micron Technology Inc Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices
JP5522561B2 (ja) 2005-08-31 2014-06-18 マイクロン テクノロジー， インク． マイクロ電子デバイスパッケージ、積重ね型マイクロ電子デバイスパッケージ、およびマイクロ電子デバイスを製造する方法
US7675152B2 (en) 2005-09-01 2010-03-09 Texas Instruments Incorporated Package-on-package semiconductor assembly
US7485969B2 (en) 2005-09-01 2009-02-03 Micron Technology, Inc. Stacked microelectronic devices and methods for manufacturing microelectronic devices
US20070080360A1 (en) 2005-10-06 2007-04-12 Url Mirsky Microelectronic interconnect substrate and packaging techniques
KR101241650B1 (ko) 2005-10-19 2013-03-08 엘지이노텍 주식회사 엘이디 패키지
US8810031B2 (en) 2005-10-26 2014-08-19 Industrial Technology Research Institute Wafer-to-wafer stack with supporting pedestal
US7504716B2 (en) 2005-10-26 2009-03-17 Texas Instruments Incorporated Structure and method of molded QFN device suitable for miniaturization, multiple rows and stacking
JP2007123595A (ja) 2005-10-28 2007-05-17 Nec Corp 半導体装置及びその実装構造
TW200733272A (en) 2005-11-01 2007-09-01 Koninkl Philips Electronics Nv Methods of packaging a semiconductor die and die package formed by the methods
JP4530975B2 (ja) 2005-11-14 2010-08-25 株式会社新川 ワイヤボンディング方法
JP2007142042A (ja) 2005-11-16 2007-06-07 Sharp Corp 半導体パッケージとその製造方法，半導体モジュール，および電子機器
US7344917B2 (en) 2005-11-30 2008-03-18 Freescale Semiconductor, Inc. Method for packaging a semiconductor device
US7307348B2 (en) 2005-12-07 2007-12-11 Micron Technology, Inc. Semiconductor components having through wire interconnects (TWI)
US8058101B2 (en) 2005-12-23 2011-11-15 Tessera, Inc. Microelectronic packages and methods therefor
US7378726B2 (en) 2005-12-28 2008-05-27 Intel Corporation Stacked packages with interconnecting pins
JP4530984B2 (ja) 2005-12-28 2010-08-25 株式会社新川 ワイヤボンディング装置、ボンディング制御プログラム及びボンディング方法
WO2007083351A1 (ja) 2006-01-17 2007-07-26 Spansion Llc 半導体装置およびその製造方法
JP2007194436A (ja) 2006-01-19 2007-08-02 Elpida Memory Inc 半導体パッケージ、導電性ポスト付き基板、積層型半導体装置、半導体パッケージの製造方法及び積層型半導体装置の製造方法
US20070190747A1 (en) 2006-01-23 2007-08-16 Tessera Technologies Hungary Kft. Wafer level packaging to lidded chips
JP2007201254A (ja) 2006-01-27 2007-08-09 Ibiden Co Ltd 半導体素子内蔵基板、半導体素子内蔵型多層回路基板
JP2007208159A (ja) 2006-02-06 2007-08-16 Hitachi Ltd 半導体装置
SG135074A1 (en) 2006-02-28 2007-09-28 Micron Technology Inc Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices
TWI295115B (en) 2006-02-13 2008-03-21 Ind Tech Res Inst Encapsulation and methods thereof
JP2007234845A (ja) 2006-03-01 2007-09-13 Nec Corp 半導体装置
US7876180B2 (en) 2006-03-09 2011-01-25 Kyocera Corporation Waveguide forming apparatus, dielectric waveguide forming apparatus, pin structure, and high frequency circuit
JP4949719B2 (ja) 2006-04-07 2012-06-13 ラピスセミコンダクタ株式会社 半導体装置及びその製造方法
US7759782B2 (en) 2006-04-07 2010-07-20 Tessera, Inc. Substrate for a microelectronic package and method of fabricating thereof
US7390700B2 (en) 2006-04-07 2008-06-24 Texas Instruments Incorporated Packaged system of semiconductor chips having a semiconductor interposer
JP4821849B2 (ja) 2006-04-10 2011-11-24 株式会社村田製作所 複合基板及び複合基板の製造方法
JP5598787B2 (ja) 2006-04-17 2014-10-01 マイクロンメモリジャパン株式会社 積層型半導体装置の製造方法
US7659612B2 (en) 2006-04-24 2010-02-09 Micron Technology, Inc. Semiconductor components having encapsulated through wire interconnects (TWI)
US7242081B1 (en) 2006-04-24 2007-07-10 Advanced Semiconductor Engineering Inc. Stacked package structure
DE102006022360B4 (de) 2006-05-12 2009-07-09 Infineon Technologies Ag Abschirmvorrichtung
US7910385B2 (en) 2006-05-12 2011-03-22 Micron Technology, Inc. Method of fabricating microelectronic devices
US7780064B2 (en) 2006-06-02 2010-08-24 Asm Technology Singapore Pte Ltd Wire bonding method for forming low-loop profiles
JP4961848B2 (ja) 2006-06-12 2012-06-27 日本電気株式会社 金属ポストを有する配線基板、半導体装置及び半導体装置モジュールの製造方法
US20070290325A1 (en) 2006-06-16 2007-12-20 Lite-On Semiconductor Corporation Surface mounting structure and packaging method thereof
US7967062B2 (en) 2006-06-16 2011-06-28 International Business Machines Corporation Thermally conductive composite interface, cooled electronic assemblies employing the same, and methods of fabrication thereof
WO2008014633A1 (en) 2006-06-29 2008-02-07 Intel Corporation Apparatus, system, and method for wireless connection in integrated circuit packages
KR100792352B1 (ko) 2006-07-06 2008-01-08 삼성전기주식회사 패키지 온 패키지의 바텀기판 및 그 제조방법
JP2008016688A (ja) 2006-07-07 2008-01-24 Elpida Memory Inc 半導体装置の製造方法
US7612638B2 (en) 2006-07-14 2009-11-03 Taiwan Semiconductor Manufacturing Co., Ltd. Waveguides in integrated circuits
SG139573A1 (en) 2006-07-17 2008-02-29 Micron Technology Inc Microelectronic packages with leadframes, including leadframes configured for stacked die packages, and associated systems and methods
KR100800478B1 (ko) 2006-07-18 2008-02-04 삼성전자주식회사 적층형 반도체 패키지 및 그의 제조방법
US20080023805A1 (en) 2006-07-26 2008-01-31 Texas Instruments Incorporated Array-Processed Stacked Semiconductor Packages
JP5132101B2 (ja) 2006-07-27 2013-01-30 新光電気工業株式会社 スタックパッケージ構造体及びその製造に用いる単体パッケージと、それらの製造方法
US8048479B2 (en) 2006-08-01 2011-11-01 Qimonda Ag Method for placing material onto a target board by means of a transfer board
JP2008039502A (ja) 2006-08-03 2008-02-21 Alps Electric Co Ltd 接触子およびその製造方法
US7486525B2 (en) 2006-08-04 2009-02-03 International Business Machines Corporation Temporary chip attach carrier
KR100809696B1 (ko) 2006-08-08 2008-03-06 삼성전자주식회사 사이즈가 상이한 복수의 반도체 칩이 적층된 멀티 칩패키지 및 그 제조방법
US20080042265A1 (en) 2006-08-15 2008-02-21 Merilo Leo A Chip scale module package in bga semiconductor package
US7425758B2 (en) 2006-08-28 2008-09-16 Micron Technology, Inc. Metal core foldover package structures
US7560360B2 (en) 2006-08-30 2009-07-14 International Business Machines Corporation Methods for enhancing trench capacitance and trench capacitor
KR20080020069A (ko) 2006-08-30 2008-03-05 삼성전자주식회사 반도체 패키지 및 그 제조방법
KR100891516B1 (ko) 2006-08-31 2009-04-06 주식회사 하이닉스반도체 적층 가능한 에프비지에이 타입 반도체 패키지와 이를이용한 적층 패키지
US7683460B2 (en) 2006-09-22 2010-03-23 Infineon Technologies Ag Module with a shielding and/or heat dissipating element
KR100770934B1 (ko) 2006-09-26 2007-10-26 삼성전자주식회사 반도체 패키지와 그를 이용한 반도체 시스템 패키지
TWI336502B (en) 2006-09-27 2011-01-21 Advanced Semiconductor Eng Semiconductor package and semiconductor device and the method of making the same
US7901989B2 (en) 2006-10-10 2011-03-08 Tessera, Inc. Reconstituted wafer level stacking
TWI312561B (en) 2006-10-27 2009-07-21 Advanced Semiconductor Eng Structure of package on package and method for fabricating the same
KR100817073B1 (ko) 2006-11-03 2008-03-26 삼성전자주식회사 휨방지용 보강부재가 기판에 연결된 반도체 칩 스택 패키지
US8174119B2 (en) 2006-11-10 2012-05-08 Stats Chippac, Ltd. Semiconductor package with embedded die
US8193034B2 (en) 2006-11-10 2012-06-05 Stats Chippac, Ltd. Semiconductor device and method of forming vertical interconnect structure using stud bumps
WO2008065896A1 (fr) 2006-11-28 2008-06-05 Kyushu Institute Of Technology Procédé de fabrication d'un dispositif semi-conducteur ayant une structure d'électrode à double face et dispositif semi-conducteur fabriqué par le procédé
US7659617B2 (en) 2006-11-30 2010-02-09 Tessera, Inc. Substrate for a flexible microelectronic assembly and a method of fabricating thereof
US7537962B2 (en) 2006-12-22 2009-05-26 Stats Chippac Ltd. Method of fabricating a shielded stacked integrated circuit package system
JP2008166439A (ja) 2006-12-27 2008-07-17 Spansion Llc 半導体装置およびその製造方法
US8598717B2 (en) 2006-12-27 2013-12-03 Spansion Llc Semiconductor device and method for manufacturing the same
SG163530A1 (en) 2006-12-29 2010-08-30 United Test & Assembly Ct Lt Copper wire bonding on organic solderability preservative materials
KR100757345B1 (ko) 2006-12-29 2007-09-10 삼성전자주식회사 플립 칩 패키지 및 그의 제조 방법
US20080156518A1 (en) 2007-01-03 2008-07-03 Tessera, Inc. Alignment and cutting of microelectronic substrates
TWI332702B (en) 2007-01-09 2010-11-01 Advanced Semiconductor Eng Stackable semiconductor package and the method for making the same
JP5347222B2 (ja) 2007-01-10 2013-11-20 富士通株式会社 半導体装置の製造方法
US7719122B2 (en) 2007-01-11 2010-05-18 Taiwan Semiconductor Manufacturing Co., Ltd. System-in-package packaging for minimizing bond wire contamination and yield loss
KR100827667B1 (ko) 2007-01-16 2008-05-07 삼성전자주식회사 기판 내에 반도체 칩을 갖는 반도체 패키지 및 이를제조하는 방법
KR101057368B1 (ko) 2007-01-31 2011-08-18 후지쯔 세미컨덕터 가부시키가이샤 반도체 장치 및 그 제조 방법
JP4823089B2 (ja) 2007-01-31 2011-11-24 株式会社東芝 積層型半導体装置の製造方法
US8685792B2 (en) 2007-03-03 2014-04-01 Stats Chippac Ltd. Integrated circuit package system with interposer
CN101675516B (zh) 2007-03-05 2012-06-20 数字光学欧洲有限公司 具有通过过孔连接到前侧触头的后侧触头的芯片
US20080217708A1 (en) 2007-03-09 2008-09-11 Skyworks Solutions, Inc. Integrated passive cap in a system-in-package
JP5010316B2 (ja) 2007-03-16 2012-08-29 日本電気株式会社 金属ポストを有する配線基板、半導体装置
US7517733B2 (en) 2007-03-22 2009-04-14 Stats Chippac, Ltd. Leadframe design for QFN package with top terminal leads
WO2008117488A1 (ja) 2007-03-23 2008-10-02 Sanyo Electric Co., Ltd 半導体装置およびその製造方法
TWI335070B (en) 2007-03-23 2010-12-21 Advanced Semiconductor Eng Semiconductor package and the method of making the same
US8198716B2 (en) 2007-03-26 2012-06-12 Intel Corporation Die backside wire bond technology for single or stacked die package
JPWO2008120755A1 (ja) 2007-03-30 2010-07-15 日本電気株式会社 機能素子内蔵回路基板及びその製造方法、並びに電子機器
JP4926787B2 (ja) 2007-03-30 2012-05-09 アオイ電子株式会社 半導体装置の製造方法
US20080246126A1 (en) 2007-04-04 2008-10-09 Freescale Semiconductor, Inc. Stacked and shielded die packages with interconnects
US7800916B2 (en) 2007-04-09 2010-09-21 Endicott Interconnect Technologies, Inc. Circuitized substrate with internal stacked semiconductor chips, method of making same, electrical assembly utilizing same and information handling system utilizing same
US7589394B2 (en) 2007-04-10 2009-09-15 Ibiden Co., Ltd. Interposer
JP5003260B2 (ja) 2007-04-13 2012-08-15 日本電気株式会社 半導体装置およびその製造方法
US7994622B2 (en) 2007-04-16 2011-08-09 Tessera, Inc. Microelectronic packages having cavities for receiving microelectric elements
KR20080094251A (ko) 2007-04-19 2008-10-23 삼성전자주식회사 웨이퍼 레벨 패키지 및 그 제조방법
JP5601751B2 (ja) 2007-04-26 2014-10-08 スパンション エルエルシー 半導体装置
US20080280393A1 (en) 2007-05-09 2008-11-13 Taiwan Semiconductor Manufacturing Co., Ltd. Methods for forming package structures
US20080284045A1 (en) 2007-05-18 2008-11-20 Texas Instruments Incorporated Method for Fabricating Array-Molded Package-On-Package
TWI371809B (en) 2007-06-04 2012-09-01 Advanced Semiconductor Eng Wafer structure and method for fabricating the same
US7872335B2 (en) 2007-06-08 2011-01-18 Broadcom Corporation Lead frame-BGA package with enhanced thermal performance and I/O counts
JP2008306128A (ja) 2007-06-11 2008-12-18 Shinko Electric Ind Co Ltd 半導体装置およびその製造方法
KR100865125B1 (ko) 2007-06-12 2008-10-24 삼성전기주식회사 반도체 패키지 및 그 제조방법
US7576415B2 (en) 2007-06-15 2009-08-18 Advanced Semiconductor Engineering, Inc. EMI shielded semiconductor package
US20080308305A1 (en) 2007-06-15 2008-12-18 Ngk Spark Plug Co., Ltd. Wiring substrate with reinforcing member
JP5179787B2 (ja) 2007-06-22 2013-04-10 ラピスセミコンダクタ株式会社 半導体装置及びその製造方法
US7944034B2 (en) 2007-06-22 2011-05-17 Texas Instruments Incorporated Array molded package-on-package having redistribution lines
US8384199B2 (en) 2007-06-25 2013-02-26 Epic Technologies, Inc. Integrated conductive structures and fabrication methods thereof facilitating implementing a cell phone or other electronic system
US7911805B2 (en) 2007-06-29 2011-03-22 Tessera, Inc. Multilayer wiring element having pin interface
SG148901A1 (en) 2007-07-09 2009-01-29 Micron Technology Inc Packaged semiconductor assemblies and methods for manufacturing such assemblies
KR20090007120A (ko) 2007-07-13 2009-01-16 삼성전자주식회사 봉지부를 통하여 재배선을 달성하는 웨이퍼 레벨 적층형패키지 및 그 제조방법
US7781877B2 (en) 2007-08-07 2010-08-24 Micron Technology, Inc. Packaged integrated circuit devices with through-body conductive vias, and methods of making same
JP2009044110A (ja) 2007-08-13 2009-02-26 Elpida Memory Inc 半導体装置及びその製造方法
SG150396A1 (en) 2007-08-16 2009-03-30 Micron Technology Inc Microelectronic die packages with leadframes, including leadframe-based interposer for stacked die packages, and associated systems and methods
KR101329355B1 (ko) 2007-08-31 2013-11-20 삼성전자주식회사 적층형 반도체 패키지, 그 형성방법 및 이를 구비하는전자장치
KR101365621B1 (ko) 2007-09-04 2014-02-24 서울반도체 주식회사 열 방출 슬러그들을 갖는 발광 다이오드 패키지
JP2009064966A (ja) 2007-09-06 2009-03-26 Shinko Electric Ind Co Ltd 多層配線基板及びその製造方法ならびに半導体装置
US7808439B2 (en) 2007-09-07 2010-10-05 University Of Tennessee Reserch Foundation Substrate integrated waveguide antenna array
US9330945B2 (en) 2007-09-18 2016-05-03 Stats Chippac Ltd. Integrated circuit package system with multi-chip module
US8039960B2 (en) 2007-09-21 2011-10-18 Stats Chippac, Ltd. Solder bump with inner core pillar in semiconductor package
KR100902128B1 (ko) 2007-09-28 2009-06-09 삼성전기주식회사 방열 인쇄회로기판 및 반도체 칩 패키지
EP2206145A4 (en) 2007-09-28 2012-03-28 Tessera Inc FLIP-CHIP CONNECTION WITH DOUBLE POSTS
JP2009088254A (ja) 2007-09-28 2009-04-23 Toshiba Corp 電子部品パッケージ及び電子部品パッケージの製造方法
KR20090033605A (ko) 2007-10-01 2009-04-06 삼성전자주식회사 적층형 반도체 패키지, 그 형성방법 및 이를 구비하는전자장치
US7777351B1 (en) 2007-10-01 2010-08-17 Amkor Technology, Inc. Thin stacked interposer package
US20090091009A1 (en) 2007-10-03 2009-04-09 Corisis David J Stackable integrated circuit package
US8008183B2 (en) 2007-10-04 2011-08-30 Texas Instruments Incorporated Dual capillary IC wirebonding
US7834464B2 (en) 2007-10-09 2010-11-16 Infineon Technologies Ag Semiconductor chip package, semiconductor chip assembly, and method for fabricating a device
EP2213148A4 (en) 2007-10-10 2011-09-07 Tessera Inc ROBUST MULTILAYER WIRING ELEMENTS AND ASSEMBLIES INCLUDING MICROELECTRONIC ELEMENTS INCLUDED
TWI360207B (en) 2007-10-22 2012-03-11 Advanced Semiconductor Eng Chip package structure and method of manufacturing
TWI389220B (zh) 2007-10-22 2013-03-11 矽品精密工業股份有限公司 半導體封裝件及其製法
FR2923081B1 (fr) 2007-10-26 2009-12-11 3D Plus Procede d'interconnexion verticale de modules electroniques 3d par des vias.
GB0721957D0 (en) 2007-11-08 2007-12-19 Photonstar Led Ltd Ultra high thermal performance packaging for optoelectronics devices
JP2009123863A (ja) 2007-11-14 2009-06-04 Tessera Interconnect Materials Inc バンプ構造形成方法及びバンプ構造
WO2009067556A2 (en) 2007-11-19 2009-05-28 Nexxus Lighting, Inc. Apparatus and methods for thermal management of light emitting diodes
US20090127686A1 (en) 2007-11-21 2009-05-21 Advanced Chip Engineering Technology Inc. Stacking die package structure for semiconductor devices and method of the same
KR100886100B1 (ko) 2007-11-29 2009-02-27 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법
JP2009135398A (ja) 2007-11-29 2009-06-18 Ibiden Co Ltd 組合せ基板
US7902644B2 (en) 2007-12-07 2011-03-08 Stats Chippac Ltd. Integrated circuit package system for electromagnetic isolation
US7964956B1 (en) 2007-12-10 2011-06-21 Oracle America, Inc. Circuit packaging and connectivity
US7696631B2 (en) 2007-12-10 2010-04-13 International Business Machines Corporation Wire bonding personalization and discrete component attachment on wirebond pads
US8390117B2 (en) 2007-12-11 2013-03-05 Panasonic Corporation Semiconductor device and method of manufacturing the same
US7706144B2 (en) 2007-12-17 2010-04-27 Lynch Thomas W Heat dissipation system and related method
JP2009158593A (ja) 2007-12-25 2009-07-16 Tessera Interconnect Materials Inc バンプ構造およびその製造方法
US20090170241A1 (en) 2007-12-26 2009-07-02 Stats Chippac, Ltd. Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier
US20090166873A1 (en) 2007-12-27 2009-07-02 Advanced Chip Engineering Technology Inc. Inter-connecting structure for semiconductor device package and method of the same
JP4989614B2 (ja) 2007-12-28 2012-08-01 サムソン エルイーディー カンパニーリミテッド． 高出力ｌｅｄパッケージの製造方法
WO2009096950A1 (en) 2008-01-30 2009-08-06 Kulicke And Soffa Industries, Inc. Wire loop and method of forming the wire loop
US20090194829A1 (en) 2008-01-31 2009-08-06 Shine Chung MEMS Packaging Including Integrated Circuit Dies
US8120186B2 (en) 2008-02-15 2012-02-21 Qimonda Ag Integrated circuit and method
US8258015B2 (en) 2008-02-22 2012-09-04 Stats Chippac Ltd. Integrated circuit package system with penetrable film adhesive
US7956456B2 (en) 2008-02-27 2011-06-07 Texas Instruments Incorporated Thermal interface material design for enhanced thermal performance and improved package structural integrity
US8018065B2 (en) 2008-02-28 2011-09-13 Atmel Corporation Wafer-level integrated circuit package with top and bottom side electrical connections
US7919871B2 (en) 2008-03-21 2011-04-05 Stats Chippac Ltd. Integrated circuit package system for stackable devices
KR101501739B1 (ko) 2008-03-21 2015-03-11 삼성전자주식회사 반도체 패키지 제조 방법
US8525214B2 (en) 2008-03-25 2013-09-03 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base heat spreader with thermal via
US8072079B2 (en) 2008-03-27 2011-12-06 Stats Chippac, Ltd. Through hole vias at saw streets including protrusions or recesses for interconnection
CN101978490B (zh) 2008-03-31 2012-10-17 株式会社村田制作所 电子元器件组件及该电子元器件组件的制造方法
JP5043743B2 (ja) 2008-04-18 2012-10-10 ラピスセミコンダクタ株式会社 半導体装置の製造方法
US7741156B2 (en) 2008-05-27 2010-06-22 Stats Chippac, Ltd. Semiconductor device and method of forming through vias with reflowed conductive material
KR20090123680A (ko) 2008-05-28 2009-12-02 주식회사 하이닉스반도체 적층 반도체 패키지
US8093704B2 (en) 2008-06-03 2012-01-10 Intel Corporation Package on package using a bump-less build up layer (BBUL) package
US8021907B2 (en) 2008-06-09 2011-09-20 Stats Chippac, Ltd. Method and apparatus for thermally enhanced semiconductor package
CN102067310B (zh) 2008-06-16 2013-08-21 泰塞拉公司 带有边缘触头的晶片级芯片规模封装的堆叠及其制造方法
US7932170B1 (en) 2008-06-23 2011-04-26 Amkor Technology, Inc. Flip chip bump structure and fabrication method
DE102008048420A1 (de) 2008-06-27 2010-01-28 Qimonda Ag Chip-Anordnung und Verfahren zum Herstellen einer Chip-Anordnung
US7969009B2 (en) 2008-06-30 2011-06-28 Qualcomm Incorporated Through silicon via bridge interconnect
TWI473553B (zh) 2008-07-03 2015-02-11 Advanced Semiconductor Eng 晶片封裝結構
US7859033B2 (en) 2008-07-09 2010-12-28 Eastman Kodak Company Wafer level processing for backside illuminated sensors
JP5339800B2 (ja) 2008-07-10 2013-11-13 三菱電機株式会社 半導体装置の製造方法
TWI372453B (en) 2008-09-01 2012-09-11 Advanced Semiconductor Eng Copper bonding wire, wire bonding structure and method for processing and bonding a wire
TWI573201B (zh) 2008-07-18 2017-03-01 聯測總部私人有限公司 封裝結構性元件
US8923004B2 (en) 2008-07-31 2014-12-30 Micron Technology, Inc. Microelectronic packages with small footprints and associated methods of manufacturing
WO2010014103A1 (en) 2008-07-31 2010-02-04 Skyworks Solutions, Inc. Semiconductor package with integrated interference shielding and method of manufacture therof
US8004093B2 (en) 2008-08-01 2011-08-23 Stats Chippac Ltd. Integrated circuit package stacking system
US7800810B2 (en) 2008-08-06 2010-09-21 Spatial Photonics, Inc. Packaging and testing of multiple MEMS devices on a wafer
TW201007924A (en) 2008-08-07 2010-02-16 Advanced Semiconductor Eng Chip package structure
US20100044860A1 (en) 2008-08-21 2010-02-25 Tessera Interconnect Materials, Inc. Microelectronic substrate or element having conductive pads and metal posts joined thereto using bond layer
KR100997793B1 (ko) 2008-09-01 2010-12-02 주식회사 하이닉스반도체 반도체 패키지 및 이의 제조 방법
KR20100033012A (ko) 2008-09-19 2010-03-29 주식회사 하이닉스반도체 반도체 패키지 및 이를 갖는 적층 반도체 패키지
US7842541B1 (en) 2008-09-24 2010-11-30 Amkor Technology, Inc. Ultra thin package and fabrication method
US8237257B2 (en) 2008-09-25 2012-08-07 King Dragon International Inc. Substrate structure with die embedded inside and dual build-up layers over both side surfaces and method of the same
US8063475B2 (en) 2008-09-26 2011-11-22 Stats Chippac Ltd. Semiconductor package system with through silicon via interposer
WO2010041630A1 (ja) 2008-10-10 2010-04-15 日本電気株式会社 半導体装置及びその製造方法
JP5185062B2 (ja) 2008-10-21 2013-04-17 パナソニック株式会社 積層型半導体装置及び電子機器
MY149251A (en) 2008-10-23 2013-07-31 Carsem M Sdn Bhd Wafer-level package using stud bump coated with solder
KR101461630B1 (ko) 2008-11-06 2014-11-20 삼성전자주식회사 실장 높이는 축소되나, 솔더 접합 신뢰도는 개선되는 웨이퍼 레벨 칩 온 칩 패키지와, 패키지 온 패키지 및 그 제조방법
TW201023308A (en) 2008-12-01 2010-06-16 Advanced Semiconductor Eng Package-on-package device, semiconductor package and method for manufacturing the same
KR101011863B1 (ko) 2008-12-02 2011-01-31 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법
KR101015651B1 (ko) 2008-12-05 2011-02-22 삼성전기주식회사 칩 내장 인쇄회로기판 및 그 제조방법
JP2010135671A (ja) 2008-12-08 2010-06-17 Panasonic Corp 半導体装置及びその製造方法
US7642128B1 (en) 2008-12-12 2010-01-05 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
US7898083B2 (en) 2008-12-17 2011-03-01 Texas Instruments Incorporated Method for low stress flip-chip assembly of fine-pitch semiconductor devices
TWI499024B (zh) 2009-01-07 2015-09-01 Advanced Semiconductor Eng 堆疊式多封裝構造裝置、半導體封裝構造及其製造方法
US8012797B2 (en) 2009-01-07 2011-09-06 Advanced Semiconductor Engineering, Inc. Method for forming stackable semiconductor device packages including openings with conductive bumps of specified geometries
JP2010199528A (ja) 2009-01-27 2010-09-09 Tatsuta System Electronics Kk ボンディングワイヤ
JP2010177597A (ja) 2009-01-30 2010-08-12 Sanyo Electric Co Ltd 半導体モジュールおよび携帯機器
US20100200981A1 (en) 2009-02-09 2010-08-12 Advanced Semiconductor Engineering, Inc. Semiconductor package and method of manufacturing the same
US9142586B2 (en) 2009-02-24 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Pad design for backside illuminated image sensor
US8115283B1 (en) 2009-07-14 2012-02-14 Amkor Technology, Inc. Reversible top/bottom MEMS package
WO2010101163A1 (ja) 2009-03-04 2010-09-10 日本電気株式会社 機能素子内蔵基板及びそれを用いた電子デバイス
JP2010206007A (ja) 2009-03-04 2010-09-16 Nec Corp 半導体装置及びその製造方法
US8106498B2 (en) 2009-03-05 2012-01-31 Stats Chippac Ltd. Integrated circuit packaging system with a dual board-on-chip structure and method of manufacture thereof
DE102009001461A1 (de) 2009-03-11 2010-09-16 Robert Bosch Gmbh Verfahren zur Herstellung einer elektronischen Baugruppe
US8258010B2 (en) 2009-03-17 2012-09-04 Stats Chippac, Ltd. Making a semiconductor device having conductive through organic vias
US20100244276A1 (en) 2009-03-25 2010-09-30 Lsi Corporation Three-dimensional electronics package
US20110068478A1 (en) 2009-03-26 2011-03-24 Reza Argenty Pagaila Integrated circuit packaging system with package stacking and method of manufacture thereof
US8194411B2 (en) 2009-03-31 2012-06-05 Hong Kong Applied Science and Technology Research Institute Co. Ltd Electronic package with stacked modules with channels passing through metal layers of the modules
US8053814B2 (en) 2009-04-08 2011-11-08 International Business Machines Corporation On-chip embedded thermal antenna for chip cooling
US8039316B2 (en) 2009-04-14 2011-10-18 Stats Chippac Ltd. Integrated circuit packaging system with stacked integrated circuit and heat spreader with openings and method of manufacture thereof
JP2010251483A (ja) 2009-04-14 2010-11-04 Renesas Electronics Corp 半導体装置およびその製造方法
US20100289142A1 (en) 2009-05-15 2010-11-18 Il Kwon Shim Integrated circuit packaging system with coin bonded interconnects and method of manufacture thereof
US8020290B2 (en) 2009-06-14 2011-09-20 Jayna Sheats Processes for IC fabrication
TWI379367B (en) 2009-06-15 2012-12-11 Kun Yuan Technology Co Ltd Chip packaging method and structure thereof
US20120153444A1 (en) 2009-06-18 2012-06-21 Rohm Co., Ltd Semiconductor device
US20100327419A1 (en) 2009-06-26 2010-12-30 Sriram Muthukumar Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same
JP5214554B2 (ja) 2009-07-30 2013-06-19 ラピスセミコンダクタ株式会社 半導体チップ内蔵パッケージ及びその製造方法、並びに、パッケージ・オン・パッケージ型半導体装置及びその製造方法
US8183678B2 (en) 2009-08-04 2012-05-22 Amkor Technology Korea, Inc. Semiconductor device having an interposer
US20110209908A1 (en) 2009-08-06 2011-09-01 Advanced Chip Engineering Technology Inc. Conductor package structure and method of the same
KR101124102B1 (ko) 2009-08-24 2012-03-21 삼성전기주식회사 발광 소자 패키지용 기판 및 이를 포함하는 발광 소자 패키지
EP2290686A3 (en) 2009-08-28 2011-04-20 STMicroelectronics S.r.l. Method to perform electrical testing and assembly of electronic devices
US7923304B2 (en) 2009-09-10 2011-04-12 Stats Chippac Ltd. Integrated circuit packaging system with conductive pillars and method of manufacture thereof
US8264091B2 (en) 2009-09-21 2012-09-11 Stats Chippac Ltd. Integrated circuit packaging system with encapsulated via and method of manufacture thereof
US8008121B2 (en) 2009-11-04 2011-08-30 Stats Chippac, Ltd. Semiconductor package and method of mounting semiconductor die to opposite sides of TSV substrate
US8390108B2 (en) 2009-12-16 2013-03-05 Stats Chippac Ltd. Integrated circuit packaging system with stacking interconnect and method of manufacture thereof
US8169065B2 (en) 2009-12-22 2012-05-01 Epic Technologies, Inc. Stackable circuit structures and methods of fabrication thereof
TW201123387A (en) 2009-12-25 2011-07-01 xiang-hua Wang Thermal-electric separated metal PCB with a chip carrier.
TWI392066B (zh) 2009-12-28 2013-04-01 矽品精密工業股份有限公司 封裝結構及其製法
TWI395312B (zh) 2010-01-20 2013-05-01 矽品精密工業股份有限公司 具微機電元件之封裝結構及其製法
JP5550369B2 (ja) 2010-02-03 2014-07-16 新日鉄住金マテリアルズ株式会社 半導体用銅ボンディングワイヤとその接合構造
JP2011166051A (ja) 2010-02-15 2011-08-25 Panasonic Corp 半導体装置及び半導体装置の製造方法
US7990711B1 (en) 2010-02-24 2011-08-02 International Business Machines Corporation Double-face heat removal of vertically integrated chip-stacks utilizing combined symmetric silicon carrier fluid cavity and micro-channel cold plate
US7928552B1 (en) 2010-03-12 2011-04-19 Stats Chippac Ltd. Integrated circuit packaging system with multi-tier conductive interconnects and method of manufacture thereof
US9496152B2 (en) 2010-03-12 2016-11-15 STATS ChipPAC Pte. Ltd. Carrier system with multi-tier conductive posts and method of manufacture thereof
KR101667656B1 (ko) 2010-03-24 2016-10-20 삼성전자주식회사 패키지-온-패키지 형성방법
US8624374B2 (en) * 2010-04-02 2014-01-07 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof
US8278746B2 (en) 2010-04-02 2012-10-02 Advanced Semiconductor Engineering, Inc. Semiconductor device packages including connecting elements
US8564141B2 (en) 2010-05-06 2013-10-22 SK Hynix Inc. Chip unit and stack package having the same
US8558392B2 (en) 2010-05-14 2013-10-15 Stats Chippac, Ltd. Semiconductor device and method of forming interconnect structure and mounting semiconductor die in recessed encapsulant
US8288854B2 (en) 2010-05-19 2012-10-16 Advanced Semiconductor Engineering, Inc. Semiconductor package and method for making the same
US8217502B2 (en) 2010-06-08 2012-07-10 Stats Chippac Ltd. Integrated circuit packaging system with multipart conductive pillars and method of manufacture thereof
US20120001336A1 (en) 2010-07-02 2012-01-05 Texas Instruments Incorporated Corrosion-resistant copper-to-aluminum bonds
US8330272B2 (en) 2010-07-08 2012-12-11 Tessera, Inc. Microelectronic packages with dual or multiple-etched flip-chip connectors
KR20120007839A (ko) 2010-07-15 2012-01-25 삼성전자주식회사 적층형 반도체 패키지의 제조방법
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
JP5713598B2 (ja) 2010-07-20 2015-05-07 新光電気工業株式会社 ソケット及びその製造方法
US8791575B2 (en) 2010-07-23 2014-07-29 Tessera, Inc. Microelectronic elements having metallic pads overlying vias
US8847376B2 (en) 2010-07-23 2014-09-30 Tessera, Inc. Microelectronic elements with post-assembly planarization
US8796135B2 (en) 2010-07-23 2014-08-05 Tessera, Inc. Microelectronic elements with rear contacts connected with via first or via middle structures
KR101683814B1 (ko) 2010-07-26 2016-12-08 삼성전자주식회사 관통 전극을 구비하는 반도체 장치
US8580607B2 (en) 2010-07-27 2013-11-12 Tessera, Inc. Microelectronic packages with nanoparticle joining
US8304900B2 (en) 2010-08-11 2012-11-06 Stats Chippac Ltd. Integrated circuit packaging system with stacked lead and method of manufacture thereof
US8076184B1 (en) 2010-08-16 2011-12-13 Stats Chippac, Ltd. Semiconductor device and method of forming wafer-level multi-row etched leadframe with base leads and embedded semiconductor die
US8518746B2 (en) 2010-09-02 2013-08-27 Stats Chippac, Ltd. Semiconductor device and method of forming TSV semiconductor wafer with embedded semiconductor die
US8354297B2 (en) 2010-09-03 2013-01-15 Stats Chippac, Ltd. Semiconductor device and method of forming different height conductive pillars to electrically interconnect stacked laterally offset semiconductor die
US8080445B1 (en) 2010-09-07 2011-12-20 Stats Chippac, Ltd. Semiconductor device and method of forming WLP with semiconductor die embedded within penetrable encapsulant between TSV interposers
US20120063090A1 (en) 2010-09-09 2012-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Cooling mechanism for stacked die package and method of manufacturing the same
US8409922B2 (en) 2010-09-14 2013-04-02 Stats Chippac, Ltd. Semiconductor device and method of forming leadframe interposer over semiconductor die and TSV substrate for vertical electrical interconnect
US8415704B2 (en) 2010-09-22 2013-04-09 Ut-Battelle, Llc Close-packed array of light emitting devices
US8349735B2 (en) 2010-09-22 2013-01-08 Stats Chippac, Ltd. Semiconductor device and method of forming conductive TSV with insulating annular ring
US9224647B2 (en) 2010-09-24 2015-12-29 Stats Chippac, Ltd. Semiconductor device and method of forming TSV interposer with semiconductor die and build-up interconnect structure on opposing surfaces of the interposer
JP5616739B2 (ja) 2010-10-01 2014-10-29 新日鉄住金マテリアルズ株式会社 複層銅ボンディングワイヤの接合構造
US20120080787A1 (en) 2010-10-05 2012-04-05 Qualcomm Incorporated Electronic Package and Method of Making an Electronic Package
CN102024782B (zh) 2010-10-12 2012-07-25 北京大学 三维垂直互联结构及其制作方法
US8618646B2 (en) 2010-10-12 2013-12-31 Headway Technologies, Inc. Layered chip package and method of manufacturing same
JP2012104790A (ja) 2010-10-12 2012-05-31 Elpida Memory Inc 半導体装置
JP5591653B2 (ja) 2010-10-27 2014-09-17 東和精工株式会社 ラベル剥離機
US8263435B2 (en) 2010-10-28 2012-09-11 Stats Chippac, Ltd. Semiconductor device and method of stacking semiconductor die in mold laser package interconnected by bumps and conductive vias
US8697492B2 (en) 2010-11-02 2014-04-15 Tessera, Inc. No flow underfill
US8525318B1 (en) 2010-11-10 2013-09-03 Amkor Technology, Inc. Semiconductor device and fabricating method thereof
KR101075241B1 (ko) 2010-11-15 2011-11-01 테세라, 인코포레이티드 유전체 부재에 단자를 구비하는 마이크로전자 패키지
JPWO2012067177A1 (ja) 2010-11-17 2014-05-12 株式会社フジクラ 配線板及びその製造方法
KR20120056052A (ko) 2010-11-24 2012-06-01 삼성전자주식회사 반도체 패키지
US8502387B2 (en) 2010-12-09 2013-08-06 Stats Chippac Ltd. Integrated circuit packaging system with vertical interconnection and method of manufacture thereof
US8853558B2 (en) 2010-12-10 2014-10-07 Tessera, Inc. Interconnect structure
US8772817B2 (en) 2010-12-22 2014-07-08 Cree, Inc. Electronic device submounts including substrates with thermally conductive vias
US8736065B2 (en) 2010-12-22 2014-05-27 Intel Corporation Multi-chip package having a substrate with a plurality of vertically embedded die and a process of forming the same
KR101215271B1 (ko) 2010-12-29 2012-12-26 앰코 테크놀로지 코리아 주식회사 반도체 패키지 구조물 및 반도체 패키지 구조물의 제조 방법
US20120184116A1 (en) 2011-01-18 2012-07-19 Tyco Electronics Corporation Interposer
US8766436B2 (en) 2011-03-01 2014-07-01 Lsi Corporation Moisture barrier for a wire bond
US8508045B2 (en) 2011-03-03 2013-08-13 Broadcom Corporation Package 3D interconnection and method of making same
US8841765B2 (en) 2011-04-22 2014-09-23 Tessera, Inc. Multi-chip module with stacked face-down connected dies
US9508622B2 (en) 2011-04-28 2016-11-29 Freescale Semiconductor, Inc. Method for protecting copper wire bonds on aluminum pads of a semiconductor device from corrosion
KR101128063B1 (ko) 2011-05-03 2012-04-23 테세라, 인코포레이티드 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리
US8476115B2 (en) 2011-05-03 2013-07-02 Stats Chippac, Ltd. Semiconductor device and method of mounting cover to semiconductor die and interposer with adhesive material
US8618659B2 (en) 2011-05-03 2013-12-31 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US8633059B2 (en) 2011-05-11 2014-01-21 Stats Chippac Ltd. Integrated circuit packaging system with interconnect and method of manufacture thereof
US8669646B2 (en) 2011-05-31 2014-03-11 Broadcom Corporation Apparatus and method for grounding an IC package lid for EMI reduction
US9128123B2 (en) 2011-06-03 2015-09-08 Taiwan Semiconductor Manufacturing Company, Ltd. Interposer test structures and methods
US9117811B2 (en) 2011-06-13 2015-08-25 Tessera, Inc. Flip chip assembly and process with sintering material on metal bumps
US9006031B2 (en) 2011-06-23 2015-04-14 Stats Chippac, Ltd. Semiconductor device and method of forming EWLB package with standoff conductive layer over encapsulant bumps
KR20130007049A (ko) 2011-06-28 2013-01-18 삼성전자주식회사 쓰루 실리콘 비아를 이용한 패키지 온 패키지
US8476770B2 (en) 2011-07-07 2013-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and methods for forming through vias
US9449941B2 (en) 2011-07-07 2016-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Connecting function chips to a package to form package-on-package
US8816505B2 (en) 2011-07-29 2014-08-26 Tessera, Inc. Low stress vias
US8487421B2 (en) 2011-08-01 2013-07-16 Tessera, Inc. Microelectronic package with stacked microelectronic elements and method for manufacture thereof
US8937309B2 (en) 2011-08-08 2015-01-20 Micron Technology, Inc. Semiconductor die assemblies, semiconductor devices including same, and methods of fabrication
US20130037929A1 (en) 2011-08-09 2013-02-14 Kay S. Essig Stackable wafer level packages and related methods
US20130040423A1 (en) 2011-08-10 2013-02-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method of Multi-Chip Wafer Level Packaging
US9190297B2 (en) 2011-08-11 2015-11-17 Stats Chippac, Ltd. Semiconductor device and method of forming a stackable semiconductor package with vertically-oriented discrete electrical devices as interconnect structures
US8988895B2 (en) 2011-08-23 2015-03-24 Tessera, Inc. Interconnection elements with encased interconnects
US20130049218A1 (en) 2011-08-31 2013-02-28 Zhiwei Gong Semiconductor device packaging having pre-encapsulation through via formation
KR101800440B1 (ko) 2011-08-31 2017-11-23 삼성전자주식회사 다수의 반도체 칩들을 가진 반도체 패키지 및 그 형성 방법
US8816404B2 (en) 2011-09-16 2014-08-26 Stats Chippac, Ltd. Semiconductor device and method of forming stacked semiconductor die and conductive interconnect structure through an encapsulant
US9177832B2 (en) 2011-09-16 2015-11-03 Stats Chippac, Ltd. Semiconductor device and method of forming a reconfigured stackable wafer level package with vertical interconnect
KR101900423B1 (ko) 2011-09-19 2018-09-21 삼성전자주식회사 반도체 메모리 장치
KR20140085497A (ko) 2011-10-03 2014-07-07 인벤사스 코포레이션 직교 윈도가 있는 멀티-다이 와이어본드 어셈블리를 위한 스터브 최소화
KR101906408B1 (ko) 2011-10-04 2018-10-11 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US20130087915A1 (en) 2011-10-10 2013-04-11 Conexant Systems, Inc. Copper Stud Bump Wafer Level Package
US8404520B1 (en) 2011-10-17 2013-03-26 Invensas Corporation Package-on-package assembly with wire bond vias
US9105552B2 (en) 2011-10-31 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package devices and methods of packaging semiconductor dies
KR101297015B1 (ko) 2011-11-03 2013-08-14 주식회사 네패스 리드프레임을 이용한 팬-아웃 반도체 패키지 제조방법, 이에 의한 반도체 패키지 및 패키지 온 패키지
US9196588B2 (en) 2011-11-04 2015-11-24 Invensas Corporation EMI shield
US8916781B2 (en) 2011-11-15 2014-12-23 Invensas Corporation Cavities containing multi-wiring structures and devices
US8552556B1 (en) 2011-11-22 2013-10-08 Amkor Technology, Inc. Wafer level fan out package
US8912651B2 (en) 2011-11-30 2014-12-16 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package (PoP) structure including stud bulbs and method
TWI464031B (zh) 2011-12-14 2014-12-11 Univ Yuan Ze 抑制柯肯達爾孔洞形成於銲料與銅銲墊之間的方法
KR101924388B1 (ko) 2011-12-30 2018-12-04 삼성전자주식회사 재배선 구조를 갖는 반도체 패키지
US8680684B2 (en) 2012-01-09 2014-03-25 Invensas Corporation Stackable microelectronic package structures
US9258922B2 (en) 2012-01-18 2016-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. PoP structures including through-assembly via modules
US8686570B2 (en) 2012-01-20 2014-04-01 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-dimensional integrated circuit structures and methods of forming the same
KR20130090143A (ko) 2012-02-03 2013-08-13 삼성전자주식회사 패키지-온-패키지 타입의 반도체 패키지 및 그 제조방법
US8742576B2 (en) 2012-02-15 2014-06-03 Oracle International Corporation Maintaining alignment in a multi-chip module using a compressible structure
US8946757B2 (en) 2012-02-17 2015-02-03 Invensas Corporation Heat spreading substrate with embedded interconnects
US8372741B1 (en) 2012-02-24 2013-02-12 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9349706B2 (en) 2012-02-24 2016-05-24 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
DE102012203293B4 (de) 2012-03-02 2021-12-02 Robert Bosch Gmbh Halbleitermodul mit integriertem Wellenleiter für Radarsignale
US20130234317A1 (en) 2012-03-09 2013-09-12 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging Methods and Packaged Semiconductor Devices
US9082763B2 (en) 2012-03-15 2015-07-14 Taiwan Semiconductor Manufacturing Company, Ltd. Joint structure for substrates and methods of forming
US9842798B2 (en) 2012-03-23 2017-12-12 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a PoP device with embedded vertical interconnect units
KR20130111780A (ko) 2012-04-02 2013-10-11 삼성전자주식회사 Ｅｍｉ 차폐부를 갖는 반도체 장치
US9405064B2 (en) 2012-04-04 2016-08-02 Texas Instruments Incorporated Microstrip line of different widths, ground planes of different distances
US8922005B2 (en) 2012-04-11 2014-12-30 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for package on package devices with reversed stud bump through via interconnections
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US8978247B2 (en) 2012-05-22 2015-03-17 Invensas Corporation TSV fabrication using a removable handling structure
US9171790B2 (en) 2012-05-30 2015-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package devices and methods of packaging semiconductor dies
US20130323409A1 (en) 2012-05-31 2013-12-05 Skyworks Solutions, Inc. Systems and methods for controlling electromagnetic interference for integrated circuit modules
US8948712B2 (en) 2012-05-31 2015-02-03 Skyworks Solutions, Inc. Via density and placement in radio frequency shielding applications
US8981559B2 (en) 2012-06-25 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package devices and methods of packaging semiconductor dies
US8742597B2 (en) 2012-06-29 2014-06-03 Intel Corporation Package substrates with multiple dice
US8653626B2 (en) 2012-07-18 2014-02-18 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures including a capacitor and methods of forming the same
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US10115671B2 (en) 2012-08-03 2018-10-30 Snaptrack, Inc. Incorporation of passives and fine pitch through via for package on package
US8642393B1 (en) 2012-08-08 2014-02-04 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package devices and methods of forming same
US8828860B2 (en) 2012-08-30 2014-09-09 International Business Machines Corporation Double solder bumps on substrates for low temperature flip chip bonding
US9443797B2 (en) 2012-09-14 2016-09-13 STATS ChipPAC Pte. Ltd. Semiconductor device having wire studs as vertical interconnect in FO-WLP
US8963339B2 (en) 2012-10-08 2015-02-24 Qualcomm Incorporated Stacked multi-chip integrated circuit package
US8975726B2 (en) 2012-10-11 2015-03-10 Taiwan Semiconductor Manufacturing Company, Ltd. POP structures and methods of forming the same
KR101419597B1 (ko) 2012-11-06 2014-07-14 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US9418971B2 (en) 2012-11-08 2016-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package structure including a thermal isolation material and method of forming the same
US9412661B2 (en) 2012-11-21 2016-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming package-on-package structure
US9401338B2 (en) 2012-11-29 2016-07-26 Freescale Semiconductor, Inc. Electronic devices with embedded die interconnect structures, and methods of manufacture thereof
US8878353B2 (en) 2012-12-20 2014-11-04 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
US20140175657A1 (en) 2012-12-21 2014-06-26 Mihir A. Oka Methods to improve laser mark contrast on die backside film in embedded die packages
US8729714B1 (en) 2012-12-31 2014-05-20 Intel Mobile Communications GmbH Flip-chip wafer level package and methods thereof
US9378982B2 (en) 2013-01-31 2016-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Die package with openings surrounding end-portions of through package vias (TPVs) and package on package (PoP) using the die package
US9136254B2 (en) 2013-02-01 2015-09-15 Invensas Corporation Microelectronic package having wire bond vias and stiffening layer
US8940630B2 (en) 2013-02-01 2015-01-27 Invensas Corporation Method of making wire bond vias and microelectronic package having wire bond vias
US8907500B2 (en) 2013-02-04 2014-12-09 Invensas Corporation Multi-die wirebond packages with elongated windows
US20140225248A1 (en) 2013-02-13 2014-08-14 Qualcomm Incorporated Power distribution and thermal solution for direct stacked integrated circuits
US9209081B2 (en) 2013-02-21 2015-12-08 Freescale Semiconductor, Inc. Semiconductor grid array package
US20140239490A1 (en) 2013-02-26 2014-08-28 Unimicron Technology Corporation Packaging substrate and fabrication method thereof
US20140239479A1 (en) 2013-02-26 2014-08-28 Paul R Start Microelectronic package including an encapsulated heat spreader
US9461025B2 (en) 2013-03-12 2016-10-04 Taiwan Semiconductor Manfacturing Company, Ltd. Electric magnetic shielding structure in packages
US9299670B2 (en) 2013-03-14 2016-03-29 Freescale Semiconductor, Inc. Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof
US9788466B2 (en) 2013-04-16 2017-10-10 Skyworks Solutions, Inc. Apparatus and methods related to ground paths implemented with surface mount devices
KR20140126598A (ko) 2013-04-23 2014-10-31 삼성전자주식회사 반도체 패키지 및 그 제조 방법
DE112013003153T5 (de) 2013-06-28 2015-05-13 Intel IP Corporation Mikroelektromechanisches System (MEMS) auf anwendungspezifischer integrierter Schaltung (ASIC)
US9167710B2 (en) 2013-08-07 2015-10-20 Invensas Corporation Embedded packaging with preformed vias
US9685365B2 (en) 2013-08-08 2017-06-20 Invensas Corporation Method of forming a wire bond having a free end
KR102161173B1 (ko) 2013-08-29 2020-09-29 삼성전자주식회사 패키지 온 패키지 장치 및 이의 제조 방법
US20150076714A1 (en) 2013-09-16 2015-03-19 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US9373527B2 (en) 2013-10-30 2016-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. Chip on package structure and method
US9012263B1 (en) 2013-10-31 2015-04-21 Freescale Semiconductor, Inc. Method for treating a bond pad of a package substrate
US9379078B2 (en) 2013-11-07 2016-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. 3D die stacking structure with fine pitches
KR101631934B1 (ko) 2013-11-13 2016-06-21 앰코 테크놀로지 코리아 주식회사 반도체 패키지 구조물 및 그 제작 방법
US9379074B2 (en) 2013-11-22 2016-06-28 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9583456B2 (en) 2013-11-22 2017-02-28 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9263394B2 (en) 2013-11-22 2016-02-16 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9653442B2 (en) 2014-01-17 2017-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and methods of forming same
US9583411B2 (en) * 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
KR20150091932A (ko) 2014-02-04 2015-08-12 앰코 테크놀로지 코리아 주식회사 반도체 디바이스의 제조 방법 및 이에 따른 반도체 디바이스
US9224709B2 (en) 2014-02-13 2015-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device including an embedded surface mount device and method of forming the same
US9362161B2 (en) 2014-03-20 2016-06-07 Stats Chippac, Ltd. Semiconductor device and method of forming 3D dual side die embedded build-up semiconductor package
US9318452B2 (en) 2014-03-21 2016-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming the same
US9437459B2 (en) 2014-05-01 2016-09-06 Freescale Semiconductor, Inc. Aluminum clad copper structure of an electronic component package and a method of making an electronic component package with an aluminum clad copper structure
US20150340305A1 (en) 2014-05-20 2015-11-26 Freescale Semiconductor, Inc. Stacked die package with redistribution layer
US10325876B2 (en) 2014-06-25 2019-06-18 Nxp Usa, Inc. Surface finish for wirebonding
CN106662526B (zh) 2014-07-15 2020-04-14 富士胶片株式会社 探测系统及探测方法
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
KR101640341B1 (ko) 2015-02-04 2016-07-15 앰코 테크놀로지 코리아 주식회사 반도체 패키지
US9653428B1 (en) 2015-04-14 2017-05-16 Amkor Technology, Inc. Semiconductor package and fabricating method thereof
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires
US9490222B1 (en) 2015-10-12 2016-11-08 Invensas Corporation Wire bond wires for interference shielding
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding

Also Published As

Publication number Publication date
WO2015109157A1 (en) 2015-07-23
US20150206815A1 (en) 2015-07-23
US20170148696A1 (en) 2017-05-25
US10529636B2 (en) 2020-01-07
US20180082916A1 (en) 2018-03-22
US11990382B2 (en) 2024-05-21
KR20160110970A (ko) 2016-09-23
US11404338B2 (en) 2022-08-02
US9837330B2 (en) 2017-12-05
US9583411B2 (en) 2017-02-28
US20200144144A1 (en) 2020-05-07
US20230005804A1 (en) 2023-01-05

Similar Documents

Publication Publication Date Title
US11990382B2 (en) Fine pitch BVA using reconstituted wafer with area array accessible for testing
US10170412B2 (en) Substrate-less stackable package with wire-bond interconnect
TWI463635B (zh) 具有堆疊的微電子單元之微電子封裝及其製造方法
US8174109B2 (en) Electronic device and method of manufacturing same
KR101718011B1 (ko) 반도체 패키지 및 그 제조방법
JP4472682B2 (ja) イメージセンサのウエハレベルチップスケールパッケージの製造方法
KR100726892B1 (ko) 3차원 칩 적층 패키지 모듈 및 이의 제조방법
US10680033B2 (en) Chip packaging method and chip package
US20100127374A1 (en) Multi-stack semiconductor package, semiconductor module and electronic signal processing system including thereof
KR20180036947A (ko) 반도체 패키지용 상호 연결 구조체 및 상호 연결 구조체의 제조 방법
CN115148611A (zh) 2.5d封装结构及制备方法
JP2007142128A (ja) 半導体装置およびその製造方法
US20060141666A1 (en) Method for producing a module including an integrated circuit on a substrate and an integrated module manufactured thereby
TWI514483B (zh) 可堆疊半導體封裝構造之平板模封方法
TW201714234A (zh) 模封互連基板之面板組合構造及其製造方法