TW201532235A - 使用重建晶圓與可測試之區域陣列之微小間距的焊孔陣列〈bva〉 - Google Patents
使用重建晶圓與可測試之區域陣列之微小間距的焊孔陣列〈bva〉 Download PDFInfo
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- TW201532235A TW201532235A TW104101608A TW104101608A TW201532235A TW 201532235 A TW201532235 A TW 201532235A TW 104101608 A TW104101608 A TW 104101608A TW 104101608 A TW104101608 A TW 104101608A TW 201532235 A TW201532235 A TW 201532235A
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- microelectronic
- connector
- package
- component
- conductive
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Classifications
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Abstract
本發明揭露一種針對同時製造複數微電子封裝之方法,其係藉由沿著載體上的複數微電子元件附著區域,以形成導電重分佈結構。複數附著區域係彼此相隔開以及覆蓋載體。方法也包含在相鄰的附著區域之間的導電連接器元件之形成。每一連接器元件係具有相鄰於第一端部或第二端部的載體以及位於微電子元件之一高度的另一端部。此方法也包含在連接器元件之一部分上形成密封體,並隨後將組件單一化成包含微電子元件的微電子單元。微電子單元之與重分佈結構相對設置之表面,其具有微電子元件之工作面以及連接器元件之自由端部,使得兩者能與微電子單元外部的裝置相連接。
Description
本發明技術係相關於應用於微電子封裝的結構。
如複數半導體晶片之微電子裝置,通常需要許多輸入以及輸出連接至其他的電子元件。半導體晶片或其他類似裝置的輸入以及輸出接觸點通常設置為網格狀圖案,以實質上覆蓋裝置之表面(通常被稱為“區域陣列”),或以延長列線設置,其可平行延伸且相鄰延伸至裝置的前表面的每個邊緣或前表面的中心內。通常,裝置(例如晶片)必須實體安裝於基板(例如印刷電路板)上,而裝置的接觸點必須電性連接電路板的導電體。
半導體晶片通常設置於封裝體內,以利於在製造過程中以及在將晶片安裝到外部基板(例如電路板或其他電路板)上的過程中處理晶片。例如,多個半導體晶片係設置在適合表面安裝(surface mounting)的封裝內。此型態的封裝已在各種應用中大量提出。最常見的,此類封裝包含通常被稱為“晶片載體(chip carrier)”的介電元件,其具有在介質上形成電鍍
的或蝕刻的金屬結構的端部。這些端部通常係例如藉由沿著其晶片載體延伸的細線路,以及藉由在晶片之接觸部以及端部或線路之間延伸的細導線或電線,以連接至其晶片的接觸點。在表面安裝操作上,封裝體係設置於電路板上,使得封裝上的每一端部係對準位於電路板上的相對應的接觸墊片。在端部以及接觸墊片之間提供焊料或另一接合材料。對組件加熱以熔化或“回流”焊料或以其他方式激活接合材料,使得封裝體可永久性接合在其位置上。
許多封裝體包含呈焊料球體型態的焊料塊,其直徑通常大約為0.1mm以及大約為0.8mm(5以及30mils),其係附著至封裝之端部上。具有突出於其底部表面的焊料球體之陣列的封裝體通常被稱為球體柵格陣列或“BGA”封裝。其他被稱為平面柵格陣列或“LGA”的封裝體係藉由焊料所形成的薄膜或焊盤,以固定至基板上。此種型態的封裝體可以是相當薄的。通常被稱為“晶片級封裝”的特定封裝體所佔據電路板之一面積係相同於或僅稍微大於整合於封裝體內的元件之面積。其優勢在於可減少組件整體大小以及允許基板上的各種裝置之間使用短的相互連接,進而限制裝置之間的訊號傳輸時間,因此有利於組件進行高速操作。
封裝好的半導體晶片時常以“堆疊”排列,例如一封裝體係提供至電路板上,而另一封裝體係安裝至第一封裝體的頂面上。這些排列可允許多個不同的晶片安裝於電路板上的單一腳位內,並可更進一步藉由封裝體之間短的相互連接(interconnect)以進行高速的操作。通常,此種互聯距離係僅稍微大於其晶片的厚度。為了實現在晶片封裝體堆疊內互聯,必須在每一封裝體之兩側上提供用於機械連接以及電性連接的結構(除了最
上層封裝之外)。例如,藉由在安裝的晶片的基板之兩側上提供接觸墊片或焊盤,墊片係藉由多個導電孔或其相似物穿透連接至基板,以實現上述結構。焊料球體或其相似物已經用於將位於較低的基板之頂部上的多個接觸點之間的間隙橋接至位於較高的基板之底部上的多個接觸點。為了連接的多個接觸點,焊料球體必須高於晶片之高度。在美國專利公開文件,其公開號2010/0232129(以下簡稱’129公開文件)中,已經揭露上述的內容。
儘管在本領域的技術中已有上述的發展,但在微電子單元的製造以及測試上應當期望有更進一步的改進。
為解決上述問題,本發明提供一種微電子封裝。此微電子封裝係具有第一側面、第二側面、一微電子元件以及一覆蓋微電子元件之側壁的密封體。微電子封裝在其正面上可具有複數導電元件,這些導電元件可在封裝之第一側面上與微電子封裝外部的裝置相連接。微電子封裝可具有導電連接器元件,此導電連接器元件可具有與封裝之第一側面或第二側面相鄰的端部。連接器元件可在其第一端部以及第二端部之間與密封體相接觸,並可用以將位置低於第一側面的第一外部裝置電性耦接位於第二側面上方的第二外部裝置。
本發明再提供一種同時製造複數微電子封裝的方法,其可包含下列步驟:在載體上提供一導電重分配佈結構,並在平行載體之一表面的至少一第一方向上,提供彼此相隔開的複數微電子元件附著區域。本發明之方法可包含在相鄰的附著區域之間形成複數導電連接器元件。每一
連接器元件可具有第一端部、第二端部以及邊緣表面,第一端部可相鄰於載體,第二端部可位於該載體上方的一50微米之高度處。本發明之方法也可包含在連接器元件之邊緣表面之部分上形成介電密封體,並隨後將組件單一化成複數微電子單元。每一微電子單元可包含至少一微電子元件,任一微電子元件係與另一微電子元件上堆疊或側堆疊。微電子單元之與重分佈結構相對的表面係為微電子元件之正面,連接器元件之第二端部能與微電子單元外部的裝置相連接。
本發明再提供一種同時製造複數微電子封裝之方法,其可
包含下列步驟:在一載體上提供複數微電子元件附著區域,此複數微電子元件附著區域在平行於載體之表面的至少一第一方向上係彼此相隔開。接著,在相鄰的複數附著區域之間形成複數導電連接器元件。每一連接器元件可具有第一端部、第二端部以及邊緣表面。每一連接器元件之第一端部可相鄰於載體,而每一連接器之第二端部可位於該載體上方的50微米之高度處。此方法也可包含將複數微電子元件附著到載體上的個別附著區域上。
每一微電子元件係具有一正面、一背面以及複數側壁,此正面係具有接觸部且可面向載體。此方法可包含在連接器元件之邊緣表面之至少一部分上形成介電密封體。接著,可形成一導電重分佈結構,其係覆蓋密封體之相對於微電子元件之正面的至少一表面。重分佈結構可耦接連接器元件之第二端部,並可具有在第一方向或橫向方向上延伸的線路。單一化步驟係通常對複數微電子單元執行,每一微電子單元係包含一微電子元件。在每一產生的微電子單元內,微電子元件之第一表面以及連接器元件之第一端部可與微電子單元外部的裝置相連接。
8‧‧‧重建組件
10‧‧‧微電子單元
11‧‧‧第一側面
12‧‧‧微電子元件
13‧‧‧載體
14‧‧‧連接器元件
14A‧‧‧連接器元件
14B‧‧‧連接器元件
14C‧‧‧連接器元件
14D‧‧‧連接器元件
14E‧‧‧連接器元件
14F‧‧‧連接器元件
14G‧‧‧連接器元件
14H‧‧‧連接器元件
14I‧‧‧連接器元件
14J‧‧‧連接器元件
14K‧‧‧連接器元件
14L‧‧‧連接器元件
15‧‧‧側面
16‧‧‧密封體
17‧‧‧表面
18‧‧‧重分佈結構
19‧‧‧導電塊
20‧‧‧正面
21‧‧‧線路
22‧‧‧背面
23‧‧‧導電層
24‧‧‧側壁
26‧‧‧端部
27‧‧‧邊緣表面
28‧‧‧端部
28'‧‧‧端部
29‧‧‧導電元件
30‧‧‧導電端部
31‧‧‧區域陣列
32‧‧‧區域
33‧‧‧附著層
34‧‧‧自由端部
35‧‧‧導電接合塊
36‧‧‧切割線
42‧‧‧暫時膜
44‧‧‧模板
45‧‧‧模板
46‧‧‧腔體
50‧‧‧熱擴散片
52‧‧‧凹陷部分
54‧‧‧深度
55‧‧‧距離
56‧‧‧距離
57‧‧‧裝置
58‧‧‧寬度
60‧‧‧寬度
62‧‧‧寬度
64‧‧‧高度
100‧‧‧堆疊組件
110‧‧‧微電子封裝
118‧‧‧彎曲部
1100‧‧‧系統
1101‧‧‧殼體
1102‧‧‧電路板
1104‧‧‧電路板
1106‧‧‧元件
1108‧‧‧元件
1110‧‧‧元件
1111‧‧‧透鏡
本發明之上述及其他特徵及優勢將藉由參照附圖詳細說明其例示性實施例而變得更顯而易知,其中:第1A圖為本案較佳實施例之微電子單元之剖面圖。
第1B圖為第1A圖之實施例變化型的微電子單元之剖面圖。
第2圖為本案較佳重建組件之示例之俯視平面圖。
第3圖為相似於第1A圖的微電子單元之方法中之一階段。
第4圖為第1A圖之微電子單元之方法中之另一階段。
第5圖為第1A圖之微電子單元之方法中之另一階段。
第6圖為第1A圖之微電子單元之方法中之另一階段。
第7圖為第1B圖之微電子單元之方法中之一階段。
第8圖為第1B圖之微電子單元之方法中之另一階段。
第9圖為第1B圖之微電子單元之方法中之另一階段。
第10圖為本案較佳實施例之微電子單元之俯視圖。
第11A圖至第11D圖為本案較佳實施例之連接器元件以及密封體之變化型之剖面圖。
第12A圖至第12B圖為本案較佳實施例之微電子單元之形成密封層之方法中的一階段以及下一階段。
第12C圖為相對應於第12B圖之階段之放大剖面圖。
第13A圖至第13B圖為本案較佳實施例之載體之變動之剖面圖。
第14圖為本案較佳實施例之連接器元件以及密封體內之變動之剖面
圖。
第15A圖至第15B圖為本案較佳實施例之設置於堆疊組件內之微電子單元之剖面圖。
第16圖為本案較佳實施例之系統之示意剖面圖。
於此使用,詞彙“與/或”包含一或多個相關條列項目之任何或所有組合。當“至少其一”之敘述前綴於一元件清單前時,係修飾整個清單元件而非修飾清單中之個別元件。
本文所描述的處理步驟可用以形成在第1A圖以及第1B圖中的示例性微電子單元或封裝。如第1A圖以及第1B圖所示,示例性的無基板的封裝10可包含微電子元件12(見第2圖)、連接器元件14、密封體16以及重分佈結構18。微電子元件12可具有正面20或“工作面(active face)”、背面22以及在正面20以及背面22之間延伸的側壁24。正面20可位於微電子單元或封裝10的第一側面11上。如本發明所揭露的裝置,例如連接器元件、第一端部、第二端部、自由端部、導電元件、微電子元件等,元件“位於“裝置表面之敘述係指當裝置不與任何其他元件組裝時,導電元件係能與理論點相接觸,此理論點係在垂直於裝置之表面的方向上從裝置外部朝向裝置之表面移動。因此,位於微電子單元12之表面上的端部或其他導電元件可突出於此類表面;可與此類表面齊平;或可在基板上以孔洞或下陷處相對於此類表面凹陷。
連接器元件14可包含第一端部28(例如底端)、第二端部
26(例如頂端)以及在第一端部以及第二端部26之間垂直延伸的邊緣。第一端部28可包含由銅、鎳、鋁、錫、鈀或其他相似的導電材料或多個導電材料之組合所製成的導電元件29(例如墊片)。連接器元件14可呈圖案排列以形成區域陣列31,其可環繞微電子元件12以及具有網格狀外觀,例如第10圖中的其相對應的平面圖。區域陣列31可用密封體16填充,使得連接器元件14之自由端部34係位於密封體16之表面上。如第10圖所示,連接器元件之自由端部34可排列成網格或陣列,並曝露於介電密封體16之表面上。連接器元件14之自由端部34能以“自由”作為特徵,其不會電性連接或以其他方式接合微電子單元12內最接近自由端部34的其他導電體。換句話說,自由端部34能直接地或間接地電性連接微電子單元12外部的導電體。自由端部34如例可藉由密封體16或接合或電性連接另一導電體以維持在預設位置上,但如本文所描述,只要任何的此類元件不鄰近自由端部,就不意味著自由端部34不是“自由的”。如上所述,可決定第一端部或第二端部的配置為自由端部,例如在第1A圖中的第二端部26(例如頂端)係為自由端部,而在第1B圖中的第一端部(例如底端)係為自由端部34。在任一情況下,自由端部34以及微電子元件12之正面可位於封裝之相同側以及離開重分佈結構18的位置。相反地,相鄰於重分佈結構18的連接器元件之端部可以不是自由端部,因為這些端部係直接地或間接地電性耦接重分佈結構18。
如第10圖為連接器元件之自由端部34的示例性圖案,此
自由端部34係形成區域陣列31。在一示例中,區域陣列31可具有沿著微電子單元12之外圍部分環繞微電子元件12的多個列以及行。區域陣列31
可從微電子元件之邊緣朝向微電子單元10之邊緣向外延伸。區域陣列31可排列使得連接器元件14從微電子元件12之邊緣向外延伸的距離不小於距離55(例如此距離小於4mm)。區域陣列31也可排列使得連接器元件14從封裝的邊緣向內集中一短距離56(例如此距離少於4mm)。在一示例中,沒有連接器元件位於微電子元件12之邊緣的0.5mm距離範圍內以及微電子單元10之邊緣的0.5mm距離範圍內。
連接器元件14的數量(例如I/O連接)可取決於微電子單元
之一部分,此微電子單元所包含的連接器與連接器元件14相同之密度。此密度係相關於每一連接器之厚度以及連接器元件與另一個連接器元件之間的距離(例如間距)。取決於具體的結構,連接器元件可具有不同尺寸,例如打線接合的厚度可約為500μm,而焊料材料可具有較大的厚度。間距可介於0.05毫米(mm)以及4mm,較佳的間距範圍係介於0.1mm至0.6mm之間。
間距越低則I/O連接的密度越高。在一示例中,尺寸為14mmX14mm的微電子單元可具有約1440個連接器元件14,其為五列而彼此間距約為0.2mm。
請參閱第1A圖,在本發明之一示例中,連接器元件14之
第二端部26(例如頂端)可位於微電子單元12之第一側面11。在一實施例中,第二端部26可突出於封裝之表面的上方。如本文所述,導電元件係設置於“表面上方”或“覆蓋表面”的敘述係意指位於在遠離表面的正交方向上的區域上。元件係在一參考平面“上方”或”向上遠離”一參考平面係意指位於在遠離參考平面的正交方向上的區域上。元件在”向上的”方向移動係意指在朝向高於表面所定義的參考平面的方向。相反地,元件在”向
下的”方向移動係意指朝向低於表面所定義的參考平面的方向。先前項目的所有此類陳述以及意義並不以重力為參考,而是以元件的定義作為參考基準。
每一連接器元件14可電性連接上述重分佈結構。在一實施例中,連接器元件14及/或重分佈結構18與微電子元件12沒有電性連接。微電子元件12之背面可附著於附著區域32上的重分佈結構18上,其可被黏著層或黏著膜覆蓋。附著區域32可位於每一微電子單元之中心部分上。重分佈結構18可電性耦接或直接接觸連接器元件14之第一端部28(例如底端)。在一示例中,底端可以為導電墊片。
如第1B圖所示,在另一個示例性微電子單元中,連接器元件之第一端部28係與第二端部26相對設置,並可設置於微電子單元之第一側面11上以及相鄰於微電子元件12之工作面20。第二端部26(例如底端)可直接實體地及/或電性接觸重分佈結構18。重分佈結構18可藉由密封體16與微電子元件相隔開,密封體16可完整地覆蓋微電子元件12以及環繞背面以及所有的側壁。
如第2圖至第9圖中所示,係根據各種的形成階段以形成上述的微電子單元以及其他的變化型。在一些示例中,重分佈結構18可在連接器元件14之前形成,並電性耦接或接觸第一端部28(例如底端)。在另一示例中,重分佈結構18在連接器元件14之後形成,並與第二端部26(例如頂端)相接觸。
請參閱第2圖,製造之方法可利用重建組件方式(例如重建晶圓)。重建組件8可藉由在載體13上放置複數單一化的微電子元件12而
形成,以進一步處理。載體13可以為任何能在進行操作時機械地支撐複數微電子元件的結構(例如晶圓)。微電子元件12可直接地設置於載體上或可設置於先前在載體上形成的(複數)層上。微電子元件12可藉由黏著材料或真空,直接地或間接地與載體13相隔開以及附著於載體13上。形成重建晶圓時可同時處理複數微電子元件12,並接著進行單一化以形成個別封裝的微電子單元。
本發明之一態樣包含一種處理微電子單元之方法,其係藉
由在處理步驟中於較早期階段便形成重分佈結構18,其可產生相似於第1A圖的結構。如第3圖所示,在載體13上可提供暫時的附著層33(例如黏著層)以及導電端部30。暫時的附著層33可藉由在載體13上沉積黏著材料或附著黏著材料而形成。在一示例中,形成的複數導電端部30之步驟包含藉由圖案化導電材料進行消減,以形成個別的導電端部。另一示例中,複數導電端部可藉由額外處理而形成,例如藉由電鍍、沉積、打印等。導電端部端部可包含銅、鋁、鎳或任何其他的導電材料,例如但不限制為導電矩陣材料、導電性墨水、導電聚合物、導電性糊等。在一示例中,端部30可呈導電墊片的形態,其功能可作為微電子單元之表面上的封裝端部(例如球體柵格陣列(BGA))。
如第4圖所示,藉由形成介電層19以及電性耦接導電端部
30的線路21,可在載體13上建立重分佈結構18。重分佈結構18可由單一介電層(例如單一旋轉塗佈)形成或可包含多個介電層。在重分佈結構18之遠離載體13的表面上可以為導電元件29,在一示例中,可藉由形成另一導電層以及隨後將其圖案化,以形成導電元件29。此外,導電元件29可以為
墊片或導電塊(例如焊料球體),其功能可作為焊孔陣列(Bond Via Array,BVA)之第一端部(例如底端)。
如第5圖所示,方法可包含形成附著區域32以及導電連接
器元件14。附著區域32可以為覆蓋載體的位置,微電子元件可設置於此載體上。微電子元件的設置可在形成連接器元件14之前或之後、可在形成密封體之前或之後,或可在單一化之前或之後。複數附著區域32可包含黏著墊片及/或黏著膜,並可形成在平行於載體之表面的至少一第一方向上彼此相隔開的區域上。
連接器元件14可在相鄰的複數附著區域32之間形成,並
可部分地或完全地環繞每一附著區域32。每一連接器元件可具有第一端部28、第二端部26以及在第一端部28以及第二端部26之間垂直延伸的邊緣表面27。第一端部28可相鄰於以及電性耦接於重分佈結構18,第二端部26可以為遠離重分佈結構18的自由端部。第一端部28可覆蓋以及電性耦接(例如結合或接合)導電元件29及/或第一端部可包含與其一體成形的導電元件29,如圖所示的第一端部28'。
在一示例中,連接器元件14可以為打線接合部,其係使用
打線接合工具以接合金屬接合表面(例如導電元件29)。在一示例中,形成打線接合部的方法可包含加熱線段之前端以及將其壓底線段接合的接受面,通常形成與導電元件29之表面相接合的球體或球狀底面。必須從接合工具拉出所需要的線段長度以形成打線接合部,接著在所期望的長度切斷或切割打線接合部。
另一個形成連接器元件14之技術可包含楔焊或針腳式接合。
楔焊可包含沿著接收面拖曳線之一部分以形成楔形物,此楔形物通常係平行於表面。如有必要,打線接合部所接合的楔形物可向上地彎曲,且在切割之前更可將線延長至所期望的長度或位置。在一具體的實施例中,用於形成打線接合部的線可具有圓柱形的橫截面。反之,從工具提供用以形成打線接合部的線或打線接合部所接合的楔形物可具有多邊形的橫截面,例如矩形或梯形。
如第6圖所示,微電子元件12可設置於附著區域32上以
及被介電密封體16圍繞。微電子元件12可在介電密封體16形成之前、之後或過程中附著於附著區域32上。每一微電子元件12可具有正面20、背面22以及在正面20以及背面22之間延伸的側壁24。正面20可以為主動或被動元件的工作面(例如接觸點),背面22可具有或不具有主動或被動電性元件(例如接觸點)。在一示例中,附著區域可設置於重分佈結構18之表面上,微電子元件12可附著於面向載體的背面。因此,正面20可隔離以及面向遠離重分佈結構18以及載體13。
接著,微電子元件12可由密封體16圍繞,使得封裝係相
鄰於以及覆蓋微電子元件12所有的側壁。在此步驟中,在區域陣列31內,密封體也可形成於連接器元件之邊緣表面27之一部分上。介電密封體可具有平行於微電子元件12之正面20的主表面17,並位於基本上對準微電子元件12之高度的一高度(例如大於50mils)處。密封體之表面的位置高度也可高於、低於或近似於連接器元件14之第二端部26的高度。可允許第二端部突出於密封體16上方,或第二端部可相對於封裝之主表面17凹陷,或與封裝之主表面17齊平。下列的封裝步驟可以為另一個的或選擇性的單
一化處理步驟。例如,如第11C圖所示,位於微電子元件之正面上的接觸元件以及第二端部26可具有形成於其上(例如擠壓形成)的導電塊(例如焊料球體)。
在附著的以及消除處理完成之後,產生的重建組件可包含
大量作為連續或半連續結構的微電子單元,例如條狀、帶狀或板狀。儘管第6圖中並未在個別的微電子單元之間繪示可見的邊界,但微電子單元隨後可進行單一化,例如沿著切割線36進行單一化以及從載體13移出,以形成個別封裝的微電子元件,相似於第1A圖中所示的微電子單元。微電子單元可用以機械支撐以及將微電子元件電性連接另一個微電子結構,例如連接印刷電路板(“PCB”),或連接其他封裝的微電子元件。在此類堆疊排列中,連接器元件14可承載多個電子訊號,每一電子訊號係具有不同的訊號電位,以允許不同的訊號由在單一堆疊中的相異的微電子元件進行處理。
本發明之另一態樣包含一種處理微電子單元之方法,此方
法係藉由在處理步驟中的後段形成重分佈結構18,以產生相似於第1B圖所示的結構。在此方法中的步驟以及結構可包含許多與上述方法相同的步驟。如第7圖所示,載體13可用以形成重建組件(例如重建晶圓)以及可包含附著區域32、微電子元件12、導電層23、導電元件29以及連接器元件14。如第4圖所示,在載體13上可直接提供與重分佈結構18相對設置的附著區域32。此外,可在設置於載體13上的中間層(例如導電層)上直接提供附著區域32。微電子元件12可表面朝下設置在附著區域上,使得正面係相鄰於載體。因此,背面22可隔離或面向遠離載體。可藉由形成另一導電
層(例如箔片)以及隨後將其圖案化,以形成導電元件29。在一示例中,導電元件29可以為墊片形態,其功能可作為微電子單元的封裝之兩端部以及連接器元件14之第一端部(例如底端)。如第5圖所示,連接器元件14可透過相同於上述的處理步驟而形成。
如第9圖所示,在上述的微電子元件12上以及連接器元件
14中可形成介電密封體16。然而,不同於第3圖至第8圖所述之示例,重分佈結構18可形成於密封體上方,並可直接與連接器元件14之第二端部相接觸。在這種情況下,雖然重分佈結構18可使用相似於第4圖的處理步驟而形成,但此重分佈結構18可遠離載體以及可形成重建組件之第二側面以及即將被單一化的微電子單元。在一示例中,在載體上可得到(例如曝露)重分佈結構18,其可允許區域陣列可電性耦接,以在較大的間距下進行測試的。
在此刻,重建組件可準備進行單一化,然而,在單一化步
驟之前也可發生另一處理步驟或選擇性的處理步驟。例如,如第11C圖所示,在連接器元件之端部上以及在微電子元件之接觸部上,可提供導電接合塊35(例如焊料球體)。在附加以及消減處理步驟完成之後,重建組件可沿著切割線36(第9圖)進行單一化以及從載體13中移出,以形成個別封裝的微電子元件,其相似於第1B圖中所示的微電子單元。如上所述,微電子單元可接著附著至印刷電路板上,或可成為微電子單元之堆疊的一部份。
如第11A圖至第11D圖所示,微電子單元10可在沒有形成
重分佈結構18的情況下形成,因此在最後的結構中可省略重分佈結構,連接器元件14可設置於微電子單元之兩側面。如第11A圖所示,微電子單元
10可具有第一側面15(例如頂部)以及與第一側面15對立之第二側面15(例如底部)以及微電子元件12。微電子元件12可具有位於連接器元件14旁邊的微電子單元10之第二側面15上的工作面20。可形成在微電子元件之第一表面以及第二表面之間垂直延伸的連接器元件14,此連接器元件14可站立平行於微電子元件之側壁。每一連接器元件可自由地電性連接其他的連接器元件及/或微電子元件。此可允許下層的或覆蓋的基板(例如PCB、中介層、另一微電子封裝)供應相互連接。
在一示例中,如第11D圖所示,連接器元件14H以及14I
可包含單一導電塊19。如連接器元件14H,導電塊可以為圓形的,或如連接器元件14I,導電塊可以延長為橢圓形。如連接器元件14J、14K及14L所示,每一導電塊也可包含一連串的堆疊導電塊。導電塊可由接合金屬形成或可包含接合金屬,例如錫、銦、焊料或金。此外,導電塊可由固化材料形成或可包含固化材料。在一些情況下,固化材料可允許在其上形成另一導電塊之前進行固化。在這種情況下,第一連接器端部以及第二連接器端部可分別為單一導電塊19之底部以及頂部,或當多個導電塊堆疊時,可分別為頂部導電塊以及底部導電塊。
請參閱第11B圖,微電子單元10也可包含相鄰於微電子元
件12的熱擴散片50。熱擴散片50可由導電層23之一部分組成,或可包含導電層23之一部分。在一示例中,熱擴散片50可直接地或間接地黏著至微電子元件12之背面上。熱擴散片50可佔據大於或小於微電子元件之背面的區域。
如第11A圖至第11D圖所示,在產生具有相異配置的微電
子單元的步驟中,密封體16在一示例中,如第11C圖所示,密封體可在微電子元件設置於重建組件上之前形成。密封體可在設置微電子元件之後形成,可允許密封體直接與微電子元件相接觸。在後者的示例中,介電密封體可覆蓋微電子元件之一大部份,並可環繞微電子元件所有的側壁以及背面(亦即微電子元件的六個側面中的五個),如第11A圖所示。
在另一示例中,如第11B圖所示,密封體可環繞微電子元
件的側壁,但在僅水平方向上側向地從微電子元件向外延伸,而不覆蓋微電子元件12的正面或背面。如第11C圖所示,在一設計中,可將密封體形成,使其圍繞微電子元件,但在微電子元件的至少一側壁(例如所有的側壁)以及圍繞的密封體之間係具有大間隙17。
請參閱第12A圖至第12C圖所示,其為形成密封體16之
技術之示例,此技術可導致連接器元件14之未密封部分突出於密封體16之表面17外。如第12A圖所示,膜輔助成型技術可藉由設置於模板44以及腔體46之間的暫時膜42實施,其中組件包含基板、與其接合的連接器元件14以及可被接合的裝置,例如微電子元件。第12A圖為模具之第二模板45,其係與第一模板44相對立設置。
接著,如第12A圖至第12C圖所示,當模板44以及45聚
集在一起時,連接器元件14之自由端部34可突出至暫時膜42內。當模具化合物流入腔體46內形成密封體16時,模具化合物不會與連接器元件14之自由端部相接觸,因為這些自由端部被暫時膜42覆蓋。在此步驟之後,模板44與13係從密封層16移除,暫時膜42可從模具表面17移除,並留下突出於密封層16之表面17外的連接器元件14之自由端部。
膜輔助成型技術也可適用於大量製造。例如,在處理步驟
的一示例中,暫時膜之連續板之一部分可應用於模板。接著,密封層可形成於腔體46內,此腔體46之至少一部分係由模板所定義。接著,在模板44上的暫時膜42之目前部分可由具有暫時膜之連續板之另一部分的自動化裝置取代。
在膜輔助成型技術之變化型中,在形成密封層之前,水溶
性膜可設置於模板44之內表面上,以取代上述可移除的膜的使用。當模板移除時,可將水溶性膜沖洗掉,以便留下突出於上述的封裝層之表面17外的連接器元件14之端部。
密封體也可使用替代技術形成,例如密封體16可藉由完整
地覆蓋連接器元件14而形成,即連接器元件14包含封裝體之端部(例如端部26)。密封體可包含一犧牲部(例如層),隨後可將此犧牲部移除以暴露第二端部。犧牲部可利用蝕刻、平坦化、磨光、磨削、濕噴砂(例如氧化鋁漿料)、拋光或其他相似方法移除。如此,可減少密封體之高度,以實現針對連接器元件14所期望的高度。
犧牲部(例如犧牲層)之平坦化可藉由將其高度降低而開始
進行,以使連接器元件14曝露於犧牲層之表面上。接著,平坦化處理步驟也可同時地平坦化犧牲層以及連接器元件14,使得犧牲層之高度連續地減少,而連接器元件14之高度也減少。一旦達到針對連接器元件14所期望的高度,可停止平坦化處理步驟。應當注意的是,連接器元件14可在此類的處理中初期形成,使得其高度係為不均勻,且其高度皆大於目標的均勻高度。在將連接器元件14平坦化處理成均勻的或下降的高度後,犧牲層可
例如藉由蝕刻或其相似方法進行移除。犧牲部可由與封裝相同或相異的材料形成,此材料可允許使用蝕刻液蝕刻以將其移除,而不會顯著地影響密封材料。在一示例中,犧牲層可由水溶性塑料製成。
請參閱第13A圖以及第13B圖,用於重建組件的載體可具
有基本上平整的平面,或表面可包含凹陷及/或凸起的附著區域。非平坦的附著區域可用以允許先前擠壓的微電子元件為載體上的可移除地附著面到。
如第13A圖所示,凹陷部分52可具有用以容納焊料凸塊56之厚度的深度54,例如深度可大於或可稍微小於焊料凸塊之厚度,後者可能會導致凸塊輕微變形。凹陷部分之寬度58可大於工作面之一部分的寬度60,此工作面之部分包含電性接觸點(例如墊片、焊料凸塊)。然而,凹陷寬度58可小於微電子元件12之寬度62,如此可允許微電子元件懸掛凹槽上方及/或橋接凹槽。
如第8圖中所示,在附著微電子元件12至第13A圖中的載
體13上之前或之後,可形成在導電元件14之端部上由導電元件29所提供的連接器元件14以及端部。接著,如第9圖中所示,一旦提供這些形體14、29以及微電子元件12,可提供密封體16以及更進一步提供重分佈層。如第13B圖所示,非平坦的附著區域可包含凸起部分以及凹陷部分。較佳地,微電子元件12可允許選擇性地設置於微電子單元內。在一示例中,微電子元件可在載體之表面上方稍微凸起一高度64,此外,可設置微電子元件,以使工作面或工作面上的凸塊之底部係沿著相同於連接器元件之自由端部34的平面。
如第14圖所示,上述任何的或所有的微電子單元以及方法
可包含任何的連接器元件在其底端以及端部之間產生各種橫向的位移的各種形態之組合。例如,如第14D圖以及上面示例所示,連接器元件14基本上可與設置於其個別的第一端部(例如底端)28上方的第二端部26直行,在此情況下,第一端部以及第二端部之間距可以為相同的。在一示例中,連接器元件14A可以直行,但第二端部26係設置於來自個別的第一端部28的側向上。在另一示例中,連接器元件(例如元件14B)可包含彎曲部118,其在第一端部28以及第二端部26之間導致一些輕微的橫向位移。在另一示例中,連接器元件(例如元件14C)包含具有呈彎曲狀形狀的彎曲部118,比起連接器元件14B,此彎曲部118係導致側向地設置且間隔個別底端28較大距離的第二端部26。
相對於連接器元件之第二端部26,連接器元件14之第一端
部28的橫向位移可能在第一端部28上產生連接器元件14之第一中心到中心的間距(第一間距),此間距係相異於在連接器元件之第二端部26上的第二中心到中心的間距(第二間距),第二間距係少於或大於第一間距。微電子單元10之複數導電端部30能以一第三中心到中心的間距進行設置,此間距可相同於或大於第一節距及/或第二節距。導電端部30可電性耦接所有的連接器元件14,或僅電性耦接連接器元件14之一部分。導電端部30可覆蓋微電子元件12及/或相鄰的密封體16,並可橫跨整體的側面或微電子單元10(例如封裝)之側面之大部份。在一示例中,第一端部以及第二端部之間距可具有相同的數值(例如240微米),導電端部之間距則可以為較大的(例如400微米)。
如有必要,連接器元件14之彎曲部118可呈各種形態,以
實現連接器元件14之端部26所期望的位置。例如,彎曲部118可形成各種形態的S曲線,例如包含於打線接合部14B或平滑形態的打線接合部14C。
此外,彎曲部118可設於比端部26更接近底端28的位置,反之亦然。彎曲部118也可以為螺旋形或環形的形態,或可以為包含呈多個方向曲線的化合物,或可以為包含相異的形狀或特徵的曲線的化合物。
彎曲部118可例如在打線接合部的形成處理步驟中形成,
同時,打線部分可拉至所期望的長度。此步驟可使用現有的打線接合設備實施,可包含使用單一機器。
連接器元件14也可包含位於自由端部34(例如端部)上的導
電接合塊35(例如柱狀凸塊)。導電接合塊35可有助於提供與另一個導電元件的連接處。如元件14D至14G所示,導電塊可與沒有密封進內部的自由端部接合。導電塊可與自由端部接合,並允許沿著邊緣表面27以及允許除了自由端部外的接合。
請再次參閱第14圖,結構14D至14G可包含柱狀物或微
柱形態的連接器元件,此連接器元件係具有端部26以及邊緣表面。連接器元件14F至14G可具有截體圓錐型狀的錐形側壁。連接器元件14G可具有端部26,此端部26之橫截面係較寬於底端28以及端部26之間的一部分之橫截面,其中底端28以及端部26係為相互平行,邊緣表面係從底端28朝向每一其他的邊緣表面錐形延伸至端部26。如連接器元件14A所示,在此示例中,連接器元件14之底端28、或位於底端28上的導電元件或墊片可與連接器元件14一體成形,使得導電元件不會是個別被接合的相單一化的連接器元件14。
在另一實施例中,連接器元件可以為具有端部26的微柱
14G形態,此端部26係位於低於密封體16之主表面17的一高度處。為了暴露第二端部26,密封體16可包含已進行蝕刻的區域,反之,形成蝕刻區域以定義從表面17至少延伸至自由端部26的開孔或孔洞。孔洞可具有任何適合的形態以允許形成於孔洞內的連接器元件14G之端部26上進行電性連接,例如藉由在其內進行導電材料的沉積。在一示例中,導電接合塊35可沉積於孔洞內,並從端部26延伸至密封體16之主表面17上方,並遠離孔洞沿著表面17之部分進行延伸。
如第15A圖以及第15B圖所示,第1A圖或第1B圖所示的
微電子單元10可與其他元件組裝,例如位於單元10下方的較低的裝置57以及另一個位於單元10上方的微電子封裝110兩者“封裝層疊(PoP)”成堆疊組件100。在多個示例中,較低的裝置57可以為印刷電路板、中介層、微電子元件或微電子封裝,其中微電子元件12可以為附著至端部30上的倒裝晶片,並可透過微電子單元之連接器元件14延伸穿過微電子單元10與端部30電性連接。例如,微電子單元10可具有兩組不同節距的電性連接。第一連接組可包含在微電子元件12之正面上的導電元件,並可將微電子元件12電性耦接較低的裝置57。第二電性連接組可以為連接器元件14,此連接器元件14可將微電子封裝110與較低的裝置57電性耦接。在一實施例中,第一連接組可僅在微電子元件12以及較低的裝置57之間進行電性連接,第二連接組可僅在微電子封裝110以及較低的裝置57之間進行電性連接。此外,任一連接組之一部分可用以將封裝電性耦接較低的裝置57。
如第15A圖以及第15B圖所示,微電子單元10之重分佈
層18以及端部30可具有不同於較低裝置57之端部的間距,例如端部30可具有大於連接器元件之間距的一間距,此連接器元件係圍繞於微電子元件12外部的微電子單元10之周圍。在一示例中,在頂部可允許更寬鬆的間距以測試微電子單元10,並可允許微電子封裝110或裝置具有更寬鬆的間距以電性耦接單元之頂部30。
如第16圖所示,請一併參考第1A圖以及第1B圖、第10
圖至第11D圖以及第14圖至第15B圖,微電子封裝以及微電子組件可採用多樣化的電子系統之結構,如第16圖所示的系統1100。例如,根據本發明之另一實施例,系統1100包含複數模組或元件1106,例如微電子封裝及/或微電子組件,如上述的電子元件1108以及1110。
如示例性系統1100所示,系統可包含電路板、主機板或豎
式面板1102,例如可彎曲印刷電路板,電路板可包含多個導體1104(第16圖中僅繪示一個),此導體1104可將模組或元件1106與另一模組或元件進行互聯。此電路板1102可與每一微電子封裝及/或系統1100所包含的微電子組件相互傳輸訊號。然而,其僅為示例性;可使用任何適合用以在模組或元件1106之間製造電性連接的結構。
在一具體的實施例中,系統1100也可包含處理器,例如半
導體晶片1108,使得每一模組或元件1106可在每一時脈週期並列傳輸數量N的資料位元,處理器可在每一時脈週期並列傳輸數量M的資料位元,M係大於或等於N。如第16圖,元件1108可以為半導體晶片,元件1110係為顯示螢幕,然而任何的其他元件也可使用於系統1100內。當然,所雖然第16圖僅繪示兩個用以明確說明的元件1108以及1110,但是系統1100可
包含任意數量的此類元件。
以虛線示意性地繪示,模組或元件1106以及元件1108以
及1110可安裝於共用殼體1101上,並可與另一模組或元件電性互聯以形成所期望的電路。殼體1101為可用型態的可攜式殼體,例如智慧型手機、平板電腦、電視或行動裝置以及可曝露於殼體之表面上的螢幕。在實施例中,結構1106包含光敏元件(例如影像晶片)、透鏡1111,或也可提供其他用以按一定路線發送光至結構上的光學裝置。此外,第16圖所繪示的簡化系統係僅為示例性;其他系統包含多個通常作為固定的結構的系統,例如可使用上述結構製成的桌上型電腦、路由器以及其相似物。
應當理解的是,在本發明中結構可包含其他配置,這些配
置係藉由封裝元件暴露連接器元件之一部分,例如在其端部表面上以及選擇性沿著其邊緣表面,此相似於本文所述的密封元件之表面之配置係遠離以及面向基板之表面的變化型。
在較佳實施例之詳細說明中所提出之具體實施例僅用以方便說明本發明之技術內容,而非將本發明狹義地限制於上述實施例,在不超出本發明之精神及以下申請專利範圍之情況,所做之種種變化實施,皆屬於本發明之範圍。
10‧‧‧微電子單元
11‧‧‧第一側面
12‧‧‧微電子元件
14‧‧‧連接器元件
16‧‧‧密封體
18‧‧‧重分佈結構
20‧‧‧正面
22‧‧‧背面
24‧‧‧側壁
26‧‧‧端部
28‧‧‧端部
29‧‧‧導電元件
30‧‧‧導電端部
31‧‧‧區域陣列
32‧‧‧區域
34‧‧‧自由端部
Claims (22)
- 一種同時製造複數微電子單元的方法,包含下列步驟:在一載體(Carrier)上提供一導電重分佈結構(Redistribution Structure),並在平行該載體之一表面的至少一第一方向上,提供彼此相隔開的複數微電子元件附著區域(Microelectronic Element Attachment Regions);在相鄰的複數附著區域之間形成複數導電連接器元件(Connector Elements),每一連接器元件係具有一第一端部(End)、一第二端部以及在該第一端部以及該第二端部之間垂直延伸的複數邊緣表面(Edge surfaces),每一連接器元件之該第一端部係與該重分佈結構相鄰,每一連接器之該第二端部位於該載體上方之一高度係大於50微米;在該複數連接器元件之相鄰複數邊緣表面之間形成一介電密封體(Encapsulation);以及單一化複數微電子單元(Microelectronic units),每一該複數微電子單元包含一微電子元件(Microelectronic element),對立於該重分佈結構的該微電子單元之一側(Side)具有該微電子元件之第一表面(Face)以及該複數連接器元件之該第二端部,該第二端部係與該微電子單元外部之一裝置(Componet)相連接。
- 如申請專利範圍第1項所述之方法,其中形成該複數導電連接器元件之步驟包含:形成附著於該重分佈結構之複數墊上的複數打線接合部。
- 如申請專利範圍第1項所述之方法,其中形成該介電密封體之步驟包含:膜輔助成型,其中該連接器元件之該第二端部係突出於該密封體之一表面上方。
- 如申請專利範圍第1項所述之方法,其中形成該介電密封體之步驟包含:在該複數連接器元件之該第二端部上以及該複數微電子元件之相鄰的複數側壁上,形成該介電密封體;以及移除覆蓋該第二端部的該介電密封體。
- 一種同時製造複數微電子單元的方法,包含下列步驟:於一載體(Carrier)上提供複數微電子元件附著區域,該複數微電子元件附著區域在平行於該載體之一表面的至少一第一方向上係彼此相隔開;在相鄰的複數附著區域之間形成複數導電連接器元件(Connector elements),每一該連接器元件係具有一第一端部、一第二端部以及複數邊緣表面,該複數邊緣表面係在該第一端部以及該第二端部之間垂直延伸,每一該連接器元件之該第一端部係與該載體相鄰,每一該連接器之該第二端部係位於該載體上方之高度係大於50微米;附著複數微電子元件(Microelectronic Elements)到該載體上的個別該附著區域上,每一微電子元件係具有一第一表面、一第二表面以及在該第 一表面以及該第二表面之間延伸的複數側壁,該第一表面係具有複數接觸部,該第一表面係面向該載體;在該複數連接器元件之相鄰的複數邊緣表面之間,形成一介電密封體(Encapsulation);形成一導電重分佈結構(Redistribution Structure)以覆蓋該密封體之至少一表面,該封裝係與該微電子元件之該第一表面對立,該重分佈結構係耦接該複數連接器元件之該第二端部,並具有在該至少一第一方向上延伸的複數線路(Trace);以及單一化複數微電子單元(Microelectronic Units),每一複數微電子單元包含一微電子元件,該微電子單元之一側係具有該微電子元件之該第一表面,該複數連接器元件之第一端部係能與該微電子單元外部的一裝置相連接。
- 如申請專利範圍第5項所述之方法,其中形成該複數導電連接器元件之步驟包含:形成覆蓋該載體的一導電層;圖案化該導電層以形成複數墊;以及附著一打線接合部或形成一導電塊於該複數墊片上。
- 如申請專利範圍第5項所述之方法,其中形成該介電密封體之步驟包含:膜輔助成型,其中該連接器元件之該第二端部係係突出於該密封體之一表面上方。
- 如申請專利範圍第5項所述之方法,其中形成該介電密封體之步驟包含:形成該介電密封體於該複數連接器元件之該第二端部上,隨後將該介電密封體從該第二端部上移除。
- 如申請專利範圍第5項所述之方法,其中該複數導電連接器元件係自由電性連接該微電子元件。
- 一種具有相對立之一第一側面(Side)及一第二側面的微電子封裝(Package),包含:一微電子元件,係具有相對立之一第一表面(Face)及一第二表面,以及複數側壁(Sidewalls),每一側壁在該第一表面以及該第二表面之間延伸;一密封體(Encapsulation),係相鄰於該微電子元件之該側壁,該密封體在該封裝之該第一側面以及該第二側面之間的一方向上係具有一厚度,其中該複數微電子元件之複數導電元件係位於該封裝之該第一側面上,用以電性耦接該微電子元件與該微電子封裝外部的一裝置;以及導電之複數連接器元件(Connector Elements),係具有一第一端部(End)、遠離該第一端部的一第二端部以及在該第一端部以及該第二端部之 間延伸的一邊緣表面(Edge Surface),其中該等端部之一係相鄰於該密封體之該第一側面,其他端部係相鄰於該封裝之該第二側面,該複數連接器元件係在該第一端部以及第二端部之間與該密封體(Encapsulation)接觸,該複數連接器元件係用以電性耦接相鄰於該第一側面的一第一外接裝置(External Component)與相鄰於該第二側面的一第二外接裝置。
- 如申請專利範圍第10項所述之微電子封裝,更包含:具有複數端部(Terminals)之一重分佈結構(Redistribution Structure),該重分佈結構係與該封裝之該第二側面相鄰,並與該微電子元件之該第一表面相對立,該複數端部係側向地與該複數連接器元件之該複數第二端部間隔開來,每一該端部係電性耦接該複數連接器元件之該第二端部,該複數端部係透過該重分佈結構電性耦接相對應的複數連接器元件。
- 如申請專利範圍第11項所述之微電子封裝,其中一給定的連接器元件之該第一端部係與該重分佈結構相鄰,該給定的連接器之該第二端部係位於該封裝之該第一側面上,並突出於該密封體之該表面外。
- 如申請專利範圍第11項所述之微電子封裝,其中一給定的連接器元件之該第一端部係位於該封裝之該第一側面上,該給定的連接器元件之該第二端部係與該重分佈結構相鄰。
- 如申請專利範圍第10項所述之微電子封裝,其中一給定的連接器元件之該第一端部係位於該封裝之該第一側面上,該給定的連接器元件之該第二端部係位於該封裝之該第二側面上。
- 如申請專利範圍第10項所述之封裝,其中該複數導電連接器元件係自由電性連接該微電子元件。
- 如申請專利範圍第10項所述之微電子封裝,其中該複數導電元件包含:位於該微電子元件之該第一表面上的複數接觸部。
- 如申請專利範圍第10項所述之微電子封裝,其中該複數連接器元件係為複數打線接合部。
- 如申請專利範圍第17項所述之微電子封裝,其中該複數打線接合部之複數球體(Balls)係位於該複數第一端部上。
- 如申請專利範圍第10項所述之微電子封裝,更包含:形成於該微電子封裝之該第一側面上的複數導電接合塊(Conductive Joining Masses),至少一導電接合塊係用以電性耦接該微電子元件與該第一外接裝置,至少一導電接合塊係用以件電性耦接該連接器元與該第一外接裝置。
- 如申請專利範圍第10項所述之微電子封裝,其中每一連接器元件包含一接合金屬塊(Bond Metal Mass)。
- 如申請專利範圍第10項所述之微電子封裝,其中每一連接器元件包含一焊料塊(Solder Mass)。
- 如申請專利範圍第21項所述之微電子封裝,其中每一連接器元件更包含:與該焊料塊相接合之一墊片(Pad)之至少一部分。
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2014
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2015
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- 2015-01-16 KR KR1020167022186A patent/KR20160110970A/ko not_active Application Discontinuation
- 2015-01-16 TW TW104101608A patent/TW201532235A/zh unknown
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2017
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2020
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US9837330B2 (en) | 2017-12-05 |
KR20160110970A (ko) | 2016-09-23 |
US20150206815A1 (en) | 2015-07-23 |
US20180082916A1 (en) | 2018-03-22 |
US20230005804A1 (en) | 2023-01-05 |
US20170148696A1 (en) | 2017-05-25 |
US9583411B2 (en) | 2017-02-28 |
WO2015109157A1 (en) | 2015-07-23 |
US11990382B2 (en) | 2024-05-21 |
US20200144144A1 (en) | 2020-05-07 |
US10529636B2 (en) | 2020-01-07 |
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