JP2013520799A - 電子デバイス及びシステム、並びにその製造方法及び使用方法 - Google Patents
電子デバイス及びシステム、並びにその製造方法及び使用方法 Download PDFInfo
- Publication number
- JP2013520799A JP2013520799A JP2012554029A JP2012554029A JP2013520799A JP 2013520799 A JP2013520799 A JP 2013520799A JP 2012554029 A JP2012554029 A JP 2012554029A JP 2012554029 A JP2012554029 A JP 2012554029A JP 2013520799 A JP2013520799 A JP 2013520799A
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- region
- channel
- gate
- well
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 42
- 238000000034 method Methods 0.000 claims abstract description 138
- 239000002019 doping agent Substances 0.000 claims abstract description 121
- 239000000758 substrate Substances 0.000 claims description 48
- 229910052710 silicon Inorganic materials 0.000 claims description 30
- 239000010703 silicon Substances 0.000 claims description 30
- 230000008859 change Effects 0.000 claims description 22
- 230000005684 electric field Effects 0.000 claims description 22
- 238000002955 isolation Methods 0.000 claims description 22
- 230000005669 field effect Effects 0.000 claims description 21
- 230000004044 response Effects 0.000 claims description 14
- 238000000137 annealing Methods 0.000 claims description 6
- 238000002347 injection Methods 0.000 claims description 3
- 239000007924 injection Substances 0.000 claims description 3
- 230000006866 deterioration Effects 0.000 claims 1
- 230000008569 process Effects 0.000 abstract description 69
- 238000005516 engineering process Methods 0.000 abstract description 31
- 230000000694 effects Effects 0.000 abstract description 29
- 239000004065 semiconductor Substances 0.000 abstract description 23
- 238000013461 design Methods 0.000 abstract description 21
- 230000002829 reductive effect Effects 0.000 abstract description 18
- 108091006146 Channels Proteins 0.000 description 189
- 238000012216 screening Methods 0.000 description 59
- 239000010410 layer Substances 0.000 description 57
- 230000008901 benefit Effects 0.000 description 41
- 230000001976 improved effect Effects 0.000 description 33
- 238000010586 diagram Methods 0.000 description 32
- 125000004429 atom Chemical group 0.000 description 27
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 26
- 229910052751 metal Inorganic materials 0.000 description 22
- 239000002184 metal Substances 0.000 description 22
- 238000013459 approach Methods 0.000 description 21
- 230000001965 increasing effect Effects 0.000 description 20
- 239000000463 material Substances 0.000 description 16
- 230000006870 function Effects 0.000 description 15
- 230000003068 static effect Effects 0.000 description 15
- 239000007943 implant Substances 0.000 description 14
- 238000002513 implantation Methods 0.000 description 14
- 239000012212 insulator Substances 0.000 description 12
- 125000006850 spacer group Chemical group 0.000 description 12
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 10
- 229910052799 carbon Inorganic materials 0.000 description 10
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 230000002441 reversible effect Effects 0.000 description 9
- 238000004891 communication Methods 0.000 description 8
- 230000005012 migration Effects 0.000 description 8
- 238000013508 migration Methods 0.000 description 8
- 239000000203 mixture Substances 0.000 description 8
- 239000004189 Salinomycin Substances 0.000 description 7
- 230000036961 partial effect Effects 0.000 description 7
- 230000000295 complement effect Effects 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 229910052720 vanadium Inorganic materials 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 5
- 239000000969 carrier Substances 0.000 description 5
- 230000007423 decrease Effects 0.000 description 5
- 230000009977 dual effect Effects 0.000 description 5
- 238000007667 floating Methods 0.000 description 5
- 238000011065 in-situ storage Methods 0.000 description 5
- 238000012545 processing Methods 0.000 description 5
- 230000009467 reduction Effects 0.000 description 5
- 239000000523 sample Substances 0.000 description 5
- 239000008186 active pharmaceutical agent Substances 0.000 description 4
- 230000002411 adverse Effects 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 239000010408 film Substances 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- 125000005843 halogen group Chemical group 0.000 description 4
- 230000006872 improvement Effects 0.000 description 4
- 229910021332 silicide Inorganic materials 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 150000001768 cations Chemical class 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 230000018109 developmental process Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 230000000670 limiting effect Effects 0.000 description 3
- 238000007726 management method Methods 0.000 description 3
- 230000007246 mechanism Effects 0.000 description 3
- 229910001092 metal group alloy Inorganic materials 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 238000013500 data storage Methods 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910052735 hafnium Inorganic materials 0.000 description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012544 monitoring process Methods 0.000 description 2
- 230000035945 sensitivity Effects 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 230000001629 suppression Effects 0.000 description 2
- 239000003826 tablet Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 241000122205 Chamaeleonidae Species 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000927 Ge alloy Inorganic materials 0.000 description 1
- 229910003855 HfAlO Inorganic materials 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- 238000004566 IR spectroscopy Methods 0.000 description 1
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 238000010420 art technique Methods 0.000 description 1
- 229910052454 barium strontium titanate Inorganic materials 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000004069 differentiation Effects 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000003203 everyday effect Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- -1 laminates Substances 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 description 1
- 229910052451 lead zirconate titanate Inorganic materials 0.000 description 1
- HFGPZNIAWCZYJU-UHFFFAOYSA-N lead zirconate titanate Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ti+4].[Zr+4].[Pb+2] HFGPZNIAWCZYJU-UHFFFAOYSA-N 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000013178 mathematical model Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000001151 other effect Effects 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000008447 perception Effects 0.000 description 1
- 230000004043 responsiveness Effects 0.000 description 1
- 238000001004 secondary ion mass spectrometry Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 241000894007 species Species 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000008093 supporting effect Effects 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/82345—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/105—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with vertical doping variation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66537—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a self aligned punch through stopper or threshold implant under the gate region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7836—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a significant overlap between the lightly doped extension and the gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7838—Field effect transistors with field effect produced by an insulated gate without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- High Energy & Nuclear Physics (AREA)
- General Engineering & Computer Science (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
パスゲート(PG):W/L=70nm/40nm
プルダウン(PD):W/L=85nm/35nm
プルアップ(PU):W/L=65nm/35nm
この例は、45nmプロセスノードにおいて、x×y=0.72μm×0.475μm=0.342μm2の面積をもたらす。
Claims (32)
- 電界効果トランジスタであって:
バルクシリコン内のドープされたウェルと、
前記ドープされたウェルの上方に位置し、ドレインとソースとの間の導通を制御する、長さLgを有するゲートと、
5×1017原子/cm3より低いドーパント濃度を有するアンドープのチャネルであり、前記ドレインと前記ソースとの間且つ前記ゲートの下方に位置するアンドープのチャネルと、
前記ドープされたウェルに接触して前記ドープされたウェル上に位置し、且つ前記ゲートの下方Lg/3以上の深さ位置で、前記ゲートの下方に位置して、空乏深さを設定する遮蔽領域であり、前記アンドープのチャネルのドーパント濃度の10倍より高いドーパント濃度を有する遮蔽領域と、
を有する電界効果トランジスタ。 - 前記バルクシリコンは、前記遮蔽領域の下方に絶縁層を支持していない、請求項1に記載の電界効果トランジスタ。
- 前記遮蔽領域は、前記ドレインと前記ソースとの間に延在し、且つ前記ドレイン及び前記ソースそれぞれに接触している、請求項1又は2に記載の電界効果トランジスタ。
- 前記遮蔽領域は、前記ドレイン又は前記ソースに接触せずに、前記アンドープのチャネルの下方で延在している、請求項1又は2に記載の電界効果トランジスタ。
- 前記遮蔽領域のドーパント濃度の約1/50から1/2の間のドーパント濃度を有する閾値電圧調整領域を更に有し、該閾値電圧調整領域は、前記アンドープのチャネルと前記遮蔽領域との間に位置する、請求項1乃至3の何れかに記載の電界効果トランジスタ。
- 前記アンドープのチャネルは第1のエピタキシャル層として形成され、前記閾値電圧調整領域は第2のエピタキシャル層として形成されている、請求項1乃至4の何れかに記載の電界効果トランジスタ。
- 前記アンドープのチャネル及び前記閾値電圧調整領域は単一のエピタキシャル層から形成されている、請求項1乃至4の何れかに記載の電界効果トランジスタ。
- 電界効果トランジスタを製造する方法であって、
バルクシリコン内に、ドープされたウェルをドーピング形成する工程と、
前記ドープされたウェル内にドーパントを注入して、前記ドープされたウェルに接触した遮蔽領域を形成する工程と、
アンドープのチャネルをエピタキシャル成長させる工程であり、該アンドープのチャネルは、該アンドープのチャネルの下方で前記遮蔽領域がゲートの下方Lg/3以上の深さを有して空乏深さを設定するような厚さ、を有するように成長され、該アンドープのチャネルは、アニール後のドーパント濃度で、前記遮蔽領域のドーパント濃度の1/10未満のドーパント濃度を有する、工程と、
前記ドープされたウェル、前記遮蔽領域、及び前記アンドープのチャネルの上方に位置した、ドレインとソースとの間の導通を制御するための、長さLgを有するゲートを形成する工程と、
を有する方法。 - 前記アンドープのチャネルと前記遮蔽領域との間に位置し、且つ前記遮蔽領域のドーパント濃度の約1/50から1/2の間のドーパント濃度を有する閾値電圧調整領域、を形成する工程を更に有する請求項8に記載の方法。
- 前記アンドープのチャネルがアニール後のドーパント濃度で5×1017原子/cm3未満のドーパント濃度を有するように維持しながら、前記アンドープのチャネルを第1のエピタキシャル層にて形成し、且つ前記閾値電圧調整領域を第2のエピタキシャル層にて形成する工程、を有する請求項9に記載の方法。
- 前記遮蔽領域の注入領域は、複数の電界効果トランジスタに及ぶ連続したシート状である、請求項8乃至10の何れかに記載の方法。
- 前記アンドープのチャネルは、複数の電界効果トランジスタにわたって連続するようにエピタキシャル成長され、その後、該複数の電界効果トランジスタを分離するアイソレーション工程が行われる、請求項8乃至11の何れかに記載の方法。
- 電界効果トランジスタであって:
絶縁層を有しないバルクシリコン内のドープされたウェルと、
少なくとも部分的にゲートの下方及び前記ドープされたウェルの上方に延在するように配置された遮蔽領域と、
ソース及びドレインであり、これらの間に、アニール後のドーパント濃度で5×1017原子/cm3未満のドーパント濃度を有するアンドープのチャネル領域が延在している、ソース及びドレインと、
少なくとも所定の閾値電圧が前記ゲートに印加されたときに、前記ソースと前記ドレインとの間且つ前記ゲートと前記遮蔽領域との間に形成可能な深空乏化チャネル(DDC)であり、前記ゲートの近傍で該深空乏化チャネル内に形成される反転領域を横切って前記ソースと前記ドレインとの間の電流導通が可能にされる、深空乏化チャネルと、
を有し、
前記遮蔽領域は、前記ドープされたウェルと接触し、且つ前記アンドープのチャネル領域の前記アニール後のドーパント濃度の10倍より高いドーパント濃度を有する、
電界効果トランジスタ。 - 前記遮蔽領域は、前記ドレインと前記ソースとの間に延在し、且つ前記ドレイン及び前記ソースそれぞれに接触している、請求項13に記載の電界効果トランジスタ。
- 前記遮蔽領域のドーパント濃度の約1/50から1/2の間のドーパント濃度を有する閾値電圧調整領域を更に有し、該閾値電圧調整領域は、前記アンドープのチャネル領域と前記遮蔽領域との間に位置する、
請求項13又は14に記載の電界効果トランジスタ。 - トランジスタデバイスであって:
基板と、
前記基板上又は前記基板内に配置された遮蔽領域と、
前記遮蔽領域から所定の距離を置いて配置されたアンドープのチャネルと、
前記アンドープのチャネルの一方側に配置されたソース領域と、
前記アンドープのチャネルの反対側に配置されたドレイン領域と、
前記アンドープのチャネルの上方に配置されたゲート領域と
を有し、
前記アンドープのチャネルは、当該デバイスの閾値電圧より高い電圧の前記ゲート領域への印加時に、前記ソース領域から前記ドレイン領域まで、遮蔽領域を有しないドープされたチャネル構成と比較して高いキャリア移動度を提供する、
トランジスタデバイス。 - 前記アンドープのチャネルは、遮蔽領域を有しないドープされたチャネル構成を有するトランジスタに対して、最大120%の移動度向上を達成する、請求項16に記載のトランジスタデバイス。
- 前記アンドープのチャネルは、1.0MV/cm以下の低電界/低電力領域で、遮蔽領域を有しないドープされたチャネル構成と比較して高いキャリア移動度を提供する、請求項16に記載のトランジスタデバイス。
- 前記アンドープのチャネルは、およそ1.0MV/cmから0.4MV/cmの電界範囲で、およそ250cm2/Vsから400cm2/Vsの範囲内のキャリア移動度を提供する、請求項16に記載のトランジスタデバイス。
- 前記アンドープのチャネルと前記遮蔽領域との間に位置する閾値電圧調整領域、を更に有する請求項16に記載のトランジスタデバイス。
- トランジスタ回路であって:
第1の複数のトランジスタ素子であり、各トランジスタ素子が:
基板と、
前記基板上又は前記基板内に配置された遮蔽領域と、
前記遮蔽領域から所定の距離を置いて配置されたアンドープのチャネルと、
前記アンドープのチャネルの一方側に配置されたソース領域と、
前記アンドープのチャネルの反対側に配置されたドレイン領域と、
前記アンドープのチャネルの上方に配置されたゲート領域と
を有する、第1の複数のトランジスタ素子、
を有し、
前記第1の複数のトランジスタ素子は、各々がドープされたチャネルを有し且つ遮蔽領域を有しない同様のトランジスタ素子群、と比較して低い閾値電圧変動を有する、
トランジスタ回路。 - 前記第1の複数のトランジスタ素子は、前記低い閾値電圧変動により、各々がドープされたチャネルを有し且つ遮蔽領域を有しない同様のトランジスタ素子群と比較して低い動作電圧を用いて動作する、請求項21に記載のトランジスタ回路。
- 前記第1の複数のトランジスタ素子は、前記低い閾値電圧変動により、各々がドープされたチャネルを有し且つ遮蔽領域を有しない同様のトランジスタ素子群と比較して小さい電力を消費する、請求項21に記載のトランジスタ回路。
- 前記第1の複数のトランジスタ素子は、各々がドープされたチャネルを有し且つ遮蔽領域を有しない同様のトランジスタ素子群と比較して、ボディバイアス電圧の増大に伴う閾値電圧変動の悪化が小さい、請求項21に記載のトランジスタ回路。
- 前記第1の複数のトランジスタ素子は、各々がドープされたチャネルを有し且つ遮蔽領域を有しない同様のトランジスタ素子群と比較して、より大きくバイアス電圧に反応する閾値電圧を提供する、請求項21に記載のトランジスタ回路。
- トランジスタ回路であって:
複数のトランジスタ素子からなる第1のブロックと、
前記第1のブロックのトランジスタ素子から分離された、複数のトランジスタ素子からなる第2のブロックと
を有し、
各トランジスタ素子は:
基板と、
前記基板上又は前記基板内に配置された遮蔽領域と、
前記遮蔽領域から所定の距離を置いて配置されたアンドープのチャネルと、
前記アンドープのチャネルの一方側に配置されたソース領域と、
前記アンドープのチャネルの反対側に配置されたドレイン領域と、
前記アンドープのチャネルの上方に配置されたゲート領域と
を有し、
前記第1のブロックのトランジスタ素子は、第1のモードで動作可能であり、
前記第2のブロックのトランジスタ素子は、別の第2のモードで動作可能である、
トランジスタ回路。 - 前記第1及び第2のブロックのそれぞれに独立に、第1のバイアス電圧及び第2のバイアス電圧が印加される、請求項26に記載のトランジスタ回路。
- 前記第1のブロックは、前記第2のブロックとは異なる閾値電圧を有する、請求項26又は27に記載のトランジスタ回路。
- 前記第1及び第2のブロックの閾値電圧は、それらに印加されるバイアス電圧の変化に応答して調整される、請求項26乃至28の何れかに記載のトランジスタ回路。
- 前記第1のブロックの動作の前記第1のモード、及び前記第2のブロックの動作の前記第2のモードは、所定のバイアス電圧及び所定の動作電圧へのそれぞれの接続によって静的に設定される、請求項26乃至29の何れかに記載のトランジスタ回路。
- 前記第1及び第2のブロックに結合された制御回路であり、前記第1及び第2のブロックの各々のバイアス電圧及び動作電圧を調整することによって前記第1及び第2のモードを動的に調整するよう動作する制御回路、
を更に有する請求項26乃至29の何れかに記載のトランジスタ回路。 - 前記第1及び第2のモードは、スリープモード、ターボモード、低電力モード、及びレガシーモードのうちの何れか1つにされることができる、請求項26乃至31の何れかに記載のトランジスタ回路。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/708,497 US8273617B2 (en) | 2009-09-30 | 2010-02-18 | Electronic devices and systems, and methods for making and using the same |
US12/708,497 | 2010-02-18 | ||
PCT/US2011/025284 WO2011103318A1 (en) | 2010-02-18 | 2011-02-17 | Electronic devices and systems, and methods for making and using the same |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2013520799A true JP2013520799A (ja) | 2013-06-06 |
JP5934118B2 JP5934118B2 (ja) | 2016-06-15 |
Family
ID=43924267
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012554029A Active JP5934118B2 (ja) | 2010-02-18 | 2011-02-17 | 電子デバイス及びシステム、並びにその製造方法及び使用方法 |
JP2012554028A Active JP5838172B2 (ja) | 2010-02-18 | 2011-02-17 | 電界効果トランジスタ、それを支持するダイ、及び電界効果トランジスタの製造方法 |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012554028A Active JP5838172B2 (ja) | 2010-02-18 | 2011-02-17 | 電界効果トランジスタ、それを支持するダイ、及び電界効果トランジスタの製造方法 |
Country Status (5)
Country | Link |
---|---|
US (10) | US8273617B2 (ja) |
JP (2) | JP5934118B2 (ja) |
KR (3) | KR102068106B1 (ja) |
CN (2) | CN102918645B (ja) |
WO (2) | WO2011103314A1 (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015226059A (ja) * | 2014-05-23 | 2015-12-14 | 三重富士通セミコンダクター株式会社 | 埋込チャネル型深空乏化チャネルトランジスタ |
KR20160012560A (ko) * | 2014-07-24 | 2016-02-03 | 삼성전자주식회사 | 딜레이 셀 및 이를 적용하는 지연 동기 루프 회로와 위상 동기 루프 회로 |
JP2016032295A (ja) * | 2014-07-25 | 2016-03-07 | 三重富士通セミコンダクター株式会社 | 電源立ち上げ時のボディバイアス電圧を確立する集積回路デバイス及び方法 |
Families Citing this family (182)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8253195B2 (en) * | 2004-01-29 | 2012-08-28 | Enpirion, Inc. | Integrated circuit with a laterally diffused metal oxide semiconductor device and method of forming the same |
US8212317B2 (en) * | 2004-01-29 | 2012-07-03 | Enpirion, Inc. | Integrated circuit with a laterally diffused metal oxide semiconductor device and method of forming the same |
US8253196B2 (en) * | 2004-01-29 | 2012-08-28 | Enpirion, Inc. | Integrated circuit with a laterally diffused metal oxide semiconductor device and method of forming the same |
US8212316B2 (en) * | 2004-01-29 | 2012-07-03 | Enpirion, Inc. | Integrated circuit with a laterally diffused metal oxide semiconductor device and method of forming the same |
US8212315B2 (en) * | 2004-01-29 | 2012-07-03 | Enpirion, Inc. | Integrated circuit with a laterally diffused metal oxide semiconductor device and method of forming the same |
US8253197B2 (en) * | 2004-01-29 | 2012-08-28 | Enpirion, Inc. | Integrated circuit with a laterally diffused metal oxide semiconductor device and method of forming the same |
US7230302B2 (en) | 2004-01-29 | 2007-06-12 | Enpirion, Inc. | Laterally diffused metal oxide semiconductor device and method of forming the same |
US20110084356A1 (en) * | 2008-06-02 | 2011-04-14 | Nxp B.V. | Local buried layer forming method and semiconductor device having such a layer |
US8164969B2 (en) * | 2008-07-01 | 2012-04-24 | Jeng-Jye Shau | Ultra-low power hybrid circuits |
WO2011024213A1 (ja) * | 2009-08-25 | 2011-03-03 | 株式会社 東芝 | 不揮発性半導体記憶装置 |
US8273617B2 (en) | 2009-09-30 | 2012-09-25 | Suvolta, Inc. | Electronic devices and systems, and methods for making and using the same |
US8421162B2 (en) | 2009-09-30 | 2013-04-16 | Suvolta, Inc. | Advanced transistors with punch through suppression |
US20110079861A1 (en) * | 2009-09-30 | 2011-04-07 | Lucian Shifren | Advanced Transistors with Threshold Voltage Set Dopant Structures |
US8211784B2 (en) * | 2009-10-26 | 2012-07-03 | Advanced Ion Beam Technology, Inc. | Method for manufacturing a semiconductor device with less leakage current induced by carbon implant |
US8530286B2 (en) | 2010-04-12 | 2013-09-10 | Suvolta, Inc. | Low power semiconductor transistor structure and method of fabrication thereof |
US8569128B2 (en) | 2010-06-21 | 2013-10-29 | Suvolta, Inc. | Semiconductor structure and method of fabrication thereof with mixed metal types |
US8759872B2 (en) * | 2010-06-22 | 2014-06-24 | Suvolta, Inc. | Transistor with threshold voltage set notch and method of fabrication thereof |
JP5531848B2 (ja) * | 2010-08-06 | 2014-06-25 | 富士通セミコンダクター株式会社 | 半導体装置、半導体集積回路装置、SRAM、Dt−MOSトランジスタの製造方法 |
US20120038960A1 (en) * | 2010-08-13 | 2012-02-16 | Han Wui Then | Electro-optical logic techniques and circuits |
US8361872B2 (en) * | 2010-09-07 | 2013-01-29 | International Business Machines Corporation | High performance low power bulk FET device and method of manufacture |
US8378428B2 (en) * | 2010-09-29 | 2013-02-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal gate structure of a semiconductor device |
JP5605134B2 (ja) * | 2010-09-30 | 2014-10-15 | 富士通セミコンダクター株式会社 | 半導体装置及びその製造方法 |
US8377783B2 (en) | 2010-09-30 | 2013-02-19 | Suvolta, Inc. | Method for reducing punch-through in a transistor device |
US10629250B2 (en) * | 2010-11-16 | 2020-04-21 | Texas Instruments Incorporated | SRAM cell having an n-well bias |
US8404551B2 (en) * | 2010-12-03 | 2013-03-26 | Suvolta, Inc. | Source/drain extension control for advanced transistors |
US8461875B1 (en) * | 2011-02-18 | 2013-06-11 | Suvolta, Inc. | Digital circuits having improved transistors, and methods therefor |
US8525271B2 (en) * | 2011-03-03 | 2013-09-03 | Suvolta, Inc. | Semiconductor structure with improved channel stack and method for fabrication thereof |
US8400219B2 (en) | 2011-03-24 | 2013-03-19 | Suvolta, Inc. | Analog circuits having improved transistors, and methods therefor |
US8748270B1 (en) | 2011-03-30 | 2014-06-10 | Suvolta, Inc. | Process for manufacturing an improved analog transistor |
US8796048B1 (en) | 2011-05-11 | 2014-08-05 | Suvolta, Inc. | Monitoring and measurement of thin film layers |
US8999861B1 (en) | 2011-05-11 | 2015-04-07 | Suvolta, Inc. | Semiconductor structure with substitutional boron and method for fabrication thereof |
US8811068B1 (en) | 2011-05-13 | 2014-08-19 | Suvolta, Inc. | Integrated circuit devices and methods |
US8569156B1 (en) | 2011-05-16 | 2013-10-29 | Suvolta, Inc. | Reducing or eliminating pre-amorphization in transistor manufacture |
US8735987B1 (en) | 2011-06-06 | 2014-05-27 | Suvolta, Inc. | CMOS gate stack structures and processes |
US8995204B2 (en) | 2011-06-23 | 2015-03-31 | Suvolta, Inc. | Circuit devices and methods having adjustable transistor body bias |
US8416009B2 (en) * | 2011-07-13 | 2013-04-09 | International Business Machines Corporation | Solutions for controlling bulk bias voltage in an extremely thin silicon-on-insulator (ETSOI) integrated circuit chip |
US8629016B1 (en) | 2011-07-26 | 2014-01-14 | Suvolta, Inc. | Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer |
WO2013022753A2 (en) | 2011-08-05 | 2013-02-14 | Suvolta, Inc. | Semiconductor devices having fin structures and fabrication methods thereof |
US8748986B1 (en) | 2011-08-05 | 2014-06-10 | Suvolta, Inc. | Electronic device with controlled threshold voltage |
US8643108B2 (en) * | 2011-08-19 | 2014-02-04 | Altera Corporation | Buffered finFET device |
US8994123B2 (en) | 2011-08-22 | 2015-03-31 | Gold Standard Simulations Ltd. | Variation resistant metal-oxide-semiconductor field effect transistor (MOSFET) |
US8645878B1 (en) | 2011-08-23 | 2014-02-04 | Suvolta, Inc. | Porting a circuit design from a first semiconductor process to a second semiconductor process |
US8614128B1 (en) * | 2011-08-23 | 2013-12-24 | Suvolta, Inc. | CMOS structures and processes based on selective thinning |
US9214400B2 (en) * | 2011-08-31 | 2015-12-15 | Institute of Microelectronics, Chinese Academy of Sciences | Semiconductor device with back gate isolation regions and method for manufacturing the same |
US9054221B2 (en) * | 2011-08-31 | 2015-06-09 | Institute of Microelectronics, Chinese Academy of Sciences | Semiconductor device with a common back gate isolation region and method for manufacturing the same |
US8713511B1 (en) | 2011-09-16 | 2014-04-29 | Suvolta, Inc. | Tools and methods for yield-aware semiconductor manufacturing process target generation |
US8803242B2 (en) | 2011-09-19 | 2014-08-12 | Eta Semiconductor Inc. | High mobility enhancement mode FET |
US9236466B1 (en) | 2011-10-07 | 2016-01-12 | Mie Fujitsu Semiconductor Limited | Analog circuits having improved insulated gate transistors, and methods therefor |
US9287253B2 (en) | 2011-11-04 | 2016-03-15 | Synopsys, Inc. | Method and apparatus for floating or applying voltage to a well of an integrated circuit |
US8693235B2 (en) | 2011-12-06 | 2014-04-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for finFET SRAM arrays in integrated circuits |
US8582352B2 (en) * | 2011-12-06 | 2013-11-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for FinFET SRAM cells |
US8895327B1 (en) | 2011-12-09 | 2014-11-25 | Suvolta, Inc. | Tipless transistors, short-tip transistors, and methods and circuits therefor |
US8819603B1 (en) | 2011-12-15 | 2014-08-26 | Suvolta, Inc. | Memory circuits and methods of making and designing the same |
US8883600B1 (en) | 2011-12-22 | 2014-11-11 | Suvolta, Inc. | Transistor having reduced junction leakage and methods of forming thereof |
US8599623B1 (en) | 2011-12-23 | 2013-12-03 | Suvolta, Inc. | Circuits and methods for measuring circuit elements in an integrated circuit device |
JP5915194B2 (ja) * | 2012-01-17 | 2016-05-11 | 富士通セミコンダクター株式会社 | 半導体装置及びその製造方法 |
US8877619B1 (en) | 2012-01-23 | 2014-11-04 | Suvolta, Inc. | Process for manufacture of integrated circuits with different channel doping transistor architectures and devices therefrom |
US8970289B1 (en) | 2012-01-23 | 2015-03-03 | Suvolta, Inc. | Circuits and devices for generating bi-directional body bias voltages, and methods therefor |
US8735993B2 (en) * | 2012-01-31 | 2014-05-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET body contact and method of making same |
US9093550B1 (en) | 2012-01-31 | 2015-07-28 | Mie Fujitsu Semiconductor Limited | Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same |
US9406567B1 (en) | 2012-02-28 | 2016-08-02 | Mie Fujitsu Semiconductor Limited | Method for fabricating multiple transistor devices on a substrate with varying threshold voltages |
US9373684B2 (en) | 2012-03-20 | 2016-06-21 | Semiwise Limited | Method of manufacturing variation resistant metal-oxide-semiconductor field effect transistor (MOSFET) |
US8863064B1 (en) | 2012-03-23 | 2014-10-14 | Suvolta, Inc. | SRAM cell layout structure and devices therefrom |
US8759172B2 (en) * | 2012-04-18 | 2014-06-24 | International Business Machines Corporation | Etch stop layer formation in metal gate process |
US20130277747A1 (en) | 2012-04-24 | 2013-10-24 | Stmicroelectronics, Inc. | Transistor having a stressed body |
CN103456786B (zh) * | 2012-06-05 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Mos晶体管结构及其制造方法 |
US9299698B2 (en) | 2012-06-27 | 2016-03-29 | Mie Fujitsu Semiconductor Limited | Semiconductor structure with multiple transistors having various threshold voltages |
US8962434B2 (en) | 2012-07-10 | 2015-02-24 | International Business Machines Corporation | Field effect transistors with varying threshold voltages |
CN103545210B (zh) * | 2012-07-13 | 2015-12-02 | 中芯国际集成电路制造(上海)有限公司 | 深度耗尽沟道场效应晶体管及其制备方法 |
US9263568B2 (en) | 2012-07-28 | 2016-02-16 | Semiwise Limited | Fluctuation resistant low access resistance fully depleted SOI transistor with improved channel thickness control and reduced access resistance |
WO2014020403A1 (en) | 2012-07-28 | 2014-02-06 | Gold Standard Simulations Ltd. | Improved fluctuation resistant fdsoi transistors with charged subchannel and reduced access resistance |
US9190485B2 (en) | 2012-07-28 | 2015-11-17 | Gold Standard Simulations Ltd. | Fluctuation resistant FDSOI transistor with implanted subchannel |
US9269804B2 (en) | 2012-07-28 | 2016-02-23 | Semiwise Limited | Gate recessed FDSOI transistor with sandwich of active and etch control layers |
US9947773B2 (en) * | 2012-08-24 | 2018-04-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor arrangement with substrate isolation |
US8637955B1 (en) * | 2012-08-31 | 2014-01-28 | Suvolta, Inc. | Semiconductor structure with reduced junction leakage and method of fabrication thereof |
US9112057B1 (en) | 2012-09-18 | 2015-08-18 | Mie Fujitsu Semiconductor Limited | Semiconductor devices with dopant migration suppression and method of fabrication thereof |
US9041126B2 (en) | 2012-09-21 | 2015-05-26 | Mie Fujitsu Semiconductor Limited | Deeply depleted MOS transistors having a screening layer and methods thereof |
US8946050B2 (en) * | 2012-10-30 | 2015-02-03 | Globalfoundries Inc. | Double trench well formation in SRAM cells |
CN104854698A (zh) * | 2012-10-31 | 2015-08-19 | 三重富士通半导体有限责任公司 | 具有低变化晶体管外围电路的dram型器件以及相关方法 |
US8816754B1 (en) | 2012-11-02 | 2014-08-26 | Suvolta, Inc. | Body bias circuits and methods |
US9331182B2 (en) * | 2012-11-07 | 2016-05-03 | Institute of Microelectronics, Chinese Academy of Sciences | Semiconductor devices with a gate conductor formed as a spacer, and methods for manufacturing the same |
US9093997B1 (en) | 2012-11-15 | 2015-07-28 | Mie Fujitsu Semiconductor Limited | Slew based process and bias monitors and related methods |
CN103855134A (zh) | 2012-11-30 | 2014-06-11 | 英力股份有限公司 | 包括耦合至解耦合器件的半导体器件的装置 |
US9059206B2 (en) | 2012-12-10 | 2015-06-16 | International Business Machines Corporation | Epitaxial grown extremely shallow extension region |
US9070477B1 (en) | 2012-12-12 | 2015-06-30 | Mie Fujitsu Semiconductor Limited | Bit interleaved low voltage static random access memory (SRAM) and related methods |
US9112484B1 (en) | 2012-12-20 | 2015-08-18 | Mie Fujitsu Semiconductor Limited | Integrated circuit process and bias monitors and related methods |
US9093530B2 (en) * | 2012-12-28 | 2015-07-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin structure of FinFET |
JP6100535B2 (ja) * | 2013-01-18 | 2017-03-22 | ルネサスエレクトロニクス株式会社 | 半導体装置および半導体装置の製造方法 |
US8832619B2 (en) * | 2013-01-28 | 2014-09-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Analytical model for predicting current mismatch in metal oxide semiconductor arrays |
US9268885B1 (en) | 2013-02-28 | 2016-02-23 | Mie Fujitsu Semiconductor Limited | Integrated circuit device methods and models with predicted device metric variations |
US8994415B1 (en) | 2013-03-01 | 2015-03-31 | Suvolta, Inc. | Multiple VDD clock buffer |
US8988153B1 (en) | 2013-03-09 | 2015-03-24 | Suvolta, Inc. | Ring oscillator with NMOS or PMOS variation insensitivity |
US9299699B2 (en) * | 2013-03-13 | 2016-03-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-gate and complementary varactors in FinFET process |
US9299801B1 (en) | 2013-03-14 | 2016-03-29 | Mie Fujitsu Semiconductor Limited | Method for fabricating a transistor device with a tuned dopant profile |
US9825130B2 (en) * | 2013-03-14 | 2017-11-21 | Intel Corporation | Leakage reduction structures for nanowire transistors |
US9449967B1 (en) | 2013-03-15 | 2016-09-20 | Fujitsu Semiconductor Limited | Transistor array structure |
US9142674B2 (en) * | 2013-03-15 | 2015-09-22 | GlobalFoundries, Inc. | FINFET devices having a body contact and methods of forming the same |
US9112495B1 (en) * | 2013-03-15 | 2015-08-18 | Mie Fujitsu Semiconductor Limited | Integrated circuit device body bias circuits and methods |
FR3003685B1 (fr) * | 2013-03-21 | 2015-04-17 | St Microelectronics Crolles 2 | Procede de modification localisee des contraintes dans un substrat du type soi, en particulier fd soi, et dispositif correspondant |
US8952431B2 (en) * | 2013-05-09 | 2015-02-10 | International Business Machines Corporation | Stacked carbon-based FETs |
US9478571B1 (en) | 2013-05-24 | 2016-10-25 | Mie Fujitsu Semiconductor Limited | Buried channel deeply depleted channel transistor |
FR3007577B1 (fr) * | 2013-06-19 | 2015-08-07 | Commissariat Energie Atomique | Transistors avec differents niveaux de tensions de seuil et absence de distorsions entre nmos et pmos |
US9012276B2 (en) | 2013-07-05 | 2015-04-21 | Gold Standard Simulations Ltd. | Variation resistant MOSFETs with superior epitaxial properties |
US9209094B2 (en) | 2013-07-29 | 2015-12-08 | Globalfoundries Inc. | Fin field effect transistor with dielectric isolation and anchored stressor elements |
DE102014111781B4 (de) * | 2013-08-19 | 2022-08-11 | Korea Atomic Energy Research Institute | Verfahren zur elektrochemischen Herstellung einer Silizium-Schicht |
US8976575B1 (en) | 2013-08-29 | 2015-03-10 | Suvolta, Inc. | SRAM performance monitor |
US8975679B1 (en) | 2013-09-10 | 2015-03-10 | Gembedded Tech Ltd. | Single-poly non-volatile memory cell |
KR102137371B1 (ko) * | 2013-10-29 | 2020-07-27 | 삼성전자 주식회사 | 반도체 장치 및 이의 제조 방법 |
CN105900241B (zh) | 2013-11-22 | 2020-07-24 | 阿托梅拉公司 | 包括超晶格耗尽层堆叠的半导体装置和相关方法 |
US9536938B1 (en) | 2013-11-27 | 2017-01-03 | Altera Corporation | Semiconductor device including a resistor metallic layer and method of forming the same |
US9673192B1 (en) | 2013-11-27 | 2017-06-06 | Altera Corporation | Semiconductor device including a resistor metallic layer and method of forming the same |
US10020739B2 (en) | 2014-03-27 | 2018-07-10 | Altera Corporation | Integrated current replicator and method of operating the same |
CN104810396B (zh) | 2014-01-23 | 2018-02-06 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制造方法 |
US9379214B2 (en) | 2014-02-14 | 2016-06-28 | Semi Solutions Llc | Reduced variation MOSFET using a drain-extension-last process |
KR102279711B1 (ko) | 2014-03-11 | 2021-07-21 | 삼성전자주식회사 | 반도체 장치의 레이아웃 방법, 포토 마스크 및 이를 이용하여 제조된 반도체 장치 |
US9484205B2 (en) | 2014-04-07 | 2016-11-01 | International Business Machines Corporation | Semiconductor device having self-aligned gate contacts |
US10559469B2 (en) * | 2014-04-22 | 2020-02-11 | Texas Instruments Incorporated | Dual pocket approach in PFETs with embedded SI-GE source/drain |
US9087860B1 (en) * | 2014-04-29 | 2015-07-21 | Globalfoundries Inc. | Fabricating fin-type field effect transistor with punch-through stop region |
US9209172B2 (en) | 2014-05-08 | 2015-12-08 | International Business Machines Corporation | FinFET and fin-passive devices |
US9472628B2 (en) * | 2014-07-14 | 2016-10-18 | International Business Machines Corporation | Heterogeneous source drain region and extension region |
US20160043092A1 (en) * | 2014-08-08 | 2016-02-11 | Qualcomm Incorporated | Fin field-effect transistor static random access memory devices with p-channel metal-oxide-semiconductor pass gate transistors |
US9319013B2 (en) | 2014-08-19 | 2016-04-19 | Mie Fujitsu Semiconductor Limited | Operational amplifier input offset correction with transistor threshold voltage adjustment |
KR102277398B1 (ko) | 2014-09-17 | 2021-07-16 | 삼성전자주식회사 | 반도체 소자 및 이의 제조 방법 |
US11171215B2 (en) * | 2014-12-18 | 2021-11-09 | Silanna Asia Pte Ltd | Threshold voltage adjustment using adaptively biased shield plate |
US9859286B2 (en) * | 2014-12-23 | 2018-01-02 | International Business Machines Corporation | Low-drive current FinFET structure for improving circuit density of ratioed logic in SRAM devices |
KR102354463B1 (ko) | 2015-01-09 | 2022-01-24 | 삼성전자주식회사 | 레트로그레이드 채널을 갖는 반도체 소자 및 그 제조방법 |
US9805994B1 (en) | 2015-02-03 | 2017-10-31 | Pdf Solutions, Inc. | Mesh-style NCEM pads, and process for making semiconductor dies, chips, and wafers using in-line measurements from such pads |
US9799575B2 (en) | 2015-12-16 | 2017-10-24 | Pdf Solutions, Inc. | Integrated circuit containing DOEs of NCEM-enabled fill cells |
US10199283B1 (en) | 2015-02-03 | 2019-02-05 | Pdf Solutions, Inc. | Method for processing a semiconductor wager using non-contact electrical measurements indicative of a resistance through a stitch, where such measurements are obtained by scanning a pad comprised of at least three parallel conductive stripes using a moving stage with beam deflection to account for motion of the stage |
US10103627B2 (en) | 2015-02-26 | 2018-10-16 | Altera Corporation | Packaged integrated circuit including a switch-mode regulator and method of forming the same |
JP6513450B2 (ja) * | 2015-03-26 | 2019-05-15 | 三重富士通セミコンダクター株式会社 | 半導体装置 |
KR102293245B1 (ko) | 2015-03-27 | 2021-08-26 | 에스케이하이닉스 주식회사 | 반도체 소자 및 그 제조 방법 |
US9362407B1 (en) | 2015-03-27 | 2016-06-07 | International Business Machines Corporation | Symmetrical extension junction formation with low-K spacer and dual epitaxial process in FinFET device |
US10784372B2 (en) * | 2015-04-03 | 2020-09-22 | Magnachip Semiconductor, Ltd. | Semiconductor device with high voltage field effect transistor and junction field effect transistor |
US9978866B2 (en) * | 2015-04-22 | 2018-05-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor structure and manufacturing method thereof |
CN106126762A (zh) * | 2015-05-07 | 2016-11-16 | 飞思卡尔半导体公司 | 基于知晓封装状态的泄漏功耗减少 |
WO2016187042A1 (en) | 2015-05-15 | 2016-11-24 | Atomera Incorporated | Semiconductor devices with superlattice layers providing halo implant peak confinement and related methods |
US9899514B2 (en) * | 2015-05-21 | 2018-02-20 | Globalfoundries Singapore Pte. Ltd. | Extended drain metal-oxide-semiconductor transistor |
US9721790B2 (en) | 2015-06-02 | 2017-08-01 | Atomera Incorporated | Method for making enhanced semiconductor structures in single wafer processing chamber with desired uniformity control |
US11049939B2 (en) * | 2015-08-03 | 2021-06-29 | Semiwise Limited | Reduced local threshold voltage variation MOSFET using multiple layers of epi for improved device operation |
US9805987B2 (en) * | 2015-09-04 | 2017-10-31 | International Business Machines Corporation | Self-aligned punch through stopper liner for bulk FinFET |
KR102556027B1 (ko) * | 2015-09-10 | 2023-07-17 | 삼성디스플레이 주식회사 | 디스플레이장치 및 이의 제조방법 |
US10068918B2 (en) | 2015-09-21 | 2018-09-04 | Globalfoundries Inc. | Contacting SOI subsrates |
US9853101B2 (en) | 2015-10-07 | 2017-12-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained nanowire CMOS device and method of forming |
US10042967B2 (en) * | 2015-11-16 | 2018-08-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Electromigration sign-off methodology |
US9966435B2 (en) | 2015-12-09 | 2018-05-08 | Qualcomm Incorporated | Body tied intrinsic FET |
US9553093B1 (en) * | 2015-12-11 | 2017-01-24 | International Business Machines Corporation | Spacer for dual epi CMOS devices |
US10978438B1 (en) | 2015-12-16 | 2021-04-13 | Pdf Solutions, Inc. | IC with test structures and E-beam pads embedded within a contiguous standard cell area |
US10593604B1 (en) | 2015-12-16 | 2020-03-17 | Pdf Solutions, Inc. | Process for making semiconductor dies, chips, and wafers using in-line measurements obtained from DOEs of NCEM-enabled fill cells |
CN105652175B (zh) * | 2016-01-11 | 2018-07-13 | 北京大学 | 一种不同涨落源对器件电学特性影响幅度的提取方法 |
US10114919B2 (en) * | 2016-02-12 | 2018-10-30 | Globalfoundries Inc. | Placing and routing method for implementing back bias in FDSOI |
US9698266B1 (en) | 2016-03-09 | 2017-07-04 | International Business Machines Corporation | Semiconductor device strain relaxation buffer layer |
US9929063B1 (en) | 2016-04-04 | 2018-03-27 | Pdf Solutions, Inc. | Process for making an integrated circuit that includes NCEM-Enabled, tip-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates |
US9646961B1 (en) | 2016-04-04 | 2017-05-09 | Pdf Solutions, Inc. | Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, TS-short-configured, and metal-short-configured, NCEM-enabled fill cells |
US9905553B1 (en) | 2016-04-04 | 2018-02-27 | Pdf Solutions, Inc. | Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, GATECNT-short-configured, and metal-short-configured, NCEM-enabled fill cells |
US9755029B1 (en) | 2016-06-22 | 2017-09-05 | Qualcomm Incorporated | Switch device performance improvement through multisided biased shielding |
CN108093279A (zh) * | 2016-11-21 | 2018-05-29 | 新疆广电网络股份有限公司 | 一种面向电视、宽带、wifi终端“烟囱型”通风散热方法 |
US11437516B2 (en) * | 2016-11-28 | 2022-09-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Mechanisms for growing epitaxy structure of finFET device |
CN108231768A (zh) * | 2016-12-13 | 2018-06-29 | 钰创科技股份有限公司 | 具有晶闸管的存储器电路 |
US10592698B2 (en) * | 2017-03-01 | 2020-03-17 | International Business Machines Corporation | Analog-based multiple-bit chip security |
US9748153B1 (en) | 2017-03-29 | 2017-08-29 | Pdf Solutions, Inc. | Process for making and using a semiconductor wafer containing first and second does of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including tip-to-side short configure |
US9773774B1 (en) | 2017-03-30 | 2017-09-26 | Pdf Solutions, Inc. | Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including chamfer short configured fill cells, and the second DOE including corner short configured fill cells |
KR102324168B1 (ko) | 2017-06-21 | 2021-11-08 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
CN109119343A (zh) * | 2017-06-22 | 2019-01-01 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
US9786649B1 (en) | 2017-06-27 | 2017-10-10 | Pdf Solutions, Inc. | Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including via open configured fill cells, and the second DOE including stitch open configured fill cells |
US9768083B1 (en) | 2017-06-27 | 2017-09-19 | Pdf Solutions, Inc. | Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including snake open configured fill cells |
US9865583B1 (en) | 2017-06-28 | 2018-01-09 | Pdf Solutions, Inc. | Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including snake open configured fill cells, and the second DOE including stitch open configured fill cells |
US10096530B1 (en) | 2017-06-28 | 2018-10-09 | Pdf Solutions, Inc. | Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including stitch open configured fill cells |
US10211317B1 (en) | 2017-08-14 | 2019-02-19 | Globalfoundries Inc. | Vertical-transport field-effect transistors with an etched-through source/drain cavity |
US10050125B1 (en) | 2017-08-14 | 2018-08-14 | Globalfoundries Inc. | Vertical-transport field-effect transistors with an etched-through source/drain cavity |
US10290639B2 (en) * | 2017-09-12 | 2019-05-14 | Globalfoundries Inc. | VNW SRAM with trinity cross-couple PD/PU contact and method for producing the same |
US10014390B1 (en) | 2017-10-10 | 2018-07-03 | Globalfoundries Inc. | Inner spacer formation for nanosheet field-effect transistors with tall suspensions |
US11329099B2 (en) * | 2017-12-30 | 2022-05-10 | Integrated Silicon Solution, (Cayman) Inc. | Magnetic memory chip having nvm class and SRAM class MRAM elements on the same chip |
US10552563B2 (en) * | 2018-01-10 | 2020-02-04 | Qualcomm Incorporated | Digital design with bundled data asynchronous logic and body-biasing tuning |
US10636869B2 (en) * | 2018-03-09 | 2020-04-28 | Xilinx, Inc. | Mitigation for FinFET technology using deep isolation |
US10622491B2 (en) * | 2018-06-21 | 2020-04-14 | Qualcomm Incorporated | Well doping for metal oxide semiconductor (MOS) varactor |
US11276780B2 (en) | 2018-06-29 | 2022-03-15 | Intel Corporation | Transistor contact area enhancement |
US10665669B1 (en) | 2019-02-26 | 2020-05-26 | Globalfoundries Inc. | Insulative structure with diffusion break integral with isolation layer and methods to form same |
CN110136652B (zh) * | 2019-05-24 | 2020-10-16 | 深圳市华星光电半导体显示技术有限公司 | 一种goa电路及阵列基板 |
US11165021B2 (en) * | 2019-10-15 | 2021-11-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | RRAM device with improved performance |
US11373696B1 (en) | 2021-02-19 | 2022-06-28 | Nif/T, Llc | FFT-dram |
US20220302129A1 (en) * | 2021-03-10 | 2022-09-22 | Invention And Collaboration Laboratory Pte. Ltd. | SRAM Cell Structures |
Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0653496A (ja) * | 1992-06-02 | 1994-02-25 | Toshiba Corp | 半導体装置 |
JPH0697432A (ja) * | 1992-09-10 | 1994-04-08 | Hitachi Ltd | 半導体装置およびその製造方法 |
JPH06236967A (ja) * | 1992-12-14 | 1994-08-23 | Toshiba Corp | 半導体装置の製造方法 |
JPH08288508A (ja) * | 1995-04-14 | 1996-11-01 | Nec Corp | エピタキシャルチャネルmosトランジスタ及びその製造方法 |
JPH08293557A (ja) * | 1995-04-25 | 1996-11-05 | Hitachi Ltd | 半導体装置及びその製造方法 |
JPH11500873A (ja) * | 1995-12-15 | 1999-01-19 | フィリップス エレクトロニクス ネムローゼ フェンノートシャップ | SiGe層を具えた半導体電界効果デバイス |
JP2004087602A (ja) * | 2002-08-23 | 2004-03-18 | Fujitsu Ltd | 半導体集積回路装置 |
WO2004075295A1 (ja) * | 2003-02-19 | 2004-09-02 | Hitachi, Ltd. | 半導体集積回路装置 |
JP2006093507A (ja) * | 2004-09-27 | 2006-04-06 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP2006295131A (ja) * | 2005-03-17 | 2006-10-26 | Renesas Technology Corp | 半導体装置およびその製造方法 |
WO2007023979A1 (ja) * | 2005-08-22 | 2007-03-01 | Nec Corporation | Mosfetおよび半導体装置の製造方法 |
JP2007259463A (ja) * | 1996-11-21 | 2007-10-04 | Hitachi Ltd | 低電力プロセッサ |
JP2009170472A (ja) * | 2008-01-10 | 2009-07-30 | Sharp Corp | トランジスタ、半導体装置、半導体装置の製造方法 |
Family Cites Families (522)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US1487474A (en) | 1921-09-20 | 1924-03-18 | Rhodes Henry James | Casing for small cooking stoves |
US1681628A (en) | 1926-09-16 | 1928-08-21 | Schwarzkopf Erich | Electrocardiograph |
US1723750A (en) | 1927-10-27 | 1929-08-06 | William J Shore | Fuse-testing device |
US4021835A (en) * | 1974-01-25 | 1977-05-03 | Hitachi, Ltd. | Semiconductor device and a method for fabricating the same |
US3958266A (en) * | 1974-04-19 | 1976-05-18 | Rca Corporation | Deep depletion insulated gate field effect transistors |
US4000504A (en) | 1975-05-12 | 1976-12-28 | Hewlett-Packard Company | Deep channel MOS transistor |
US4276095A (en) | 1977-08-31 | 1981-06-30 | International Business Machines Corporation | Method of making a MOSFET device with reduced sensitivity of threshold voltage to source to substrate voltage variations |
US4242691A (en) | 1978-09-18 | 1980-12-30 | Mitsubishi Denki Kabushiki Kaisha | MOS Semiconductor device |
DE3069973D1 (en) * | 1979-08-25 | 1985-02-28 | Zaidan Hojin Handotai Kenkyu | Insulated-gate field-effect transistor |
EP0031237B1 (en) | 1979-12-19 | 1984-10-17 | National Research Development Corporation | Quinazoline derivatives, processes for their preparation, compositions containing them and their use as anti-cancer agents |
US4315781A (en) * | 1980-04-23 | 1982-02-16 | Hughes Aircraft Company | Method of controlling MOSFET threshold voltage with self-aligned channel stop |
JPS56155572A (en) | 1980-04-30 | 1981-12-01 | Sanyo Electric Co Ltd | Insulated gate field effect type semiconductor device |
FR2505676A1 (fr) | 1981-05-15 | 1982-11-19 | Rhone Poulenc Spec Chim | Catalyseurs constitues de silice contenant du fluor leur procede de preparation et leur application a la preparation de nitriles |
JPS5848936A (ja) | 1981-09-10 | 1983-03-23 | Fujitsu Ltd | 半導体装置の製造方法 |
US4518926A (en) | 1982-12-20 | 1985-05-21 | At&T Bell Laboratories | Gate-coupled field-effect transistor pair amplifier |
JPS59193066A (ja) * | 1983-04-15 | 1984-11-01 | Matsushita Electric Ind Co Ltd | Mos型半導体装置 |
JPS59193066U (ja) | 1983-06-08 | 1984-12-21 | 三菱電機株式会社 | エレベ−タの防犯テレビカメラ |
JPS6097432U (ja) | 1983-12-09 | 1985-07-03 | 株式会社小金井製作所 | 空気圧緩衝器 |
US4559091A (en) | 1984-06-15 | 1985-12-17 | Regents Of The University Of California | Method for producing hyperabrupt doping profiles in semiconductors |
US5060234A (en) | 1984-11-19 | 1991-10-22 | Max-Planck Gesellschaft Zur Forderung Der Wissenschaften | Injection laser with at least one pair of monoatomic layers of doping atoms |
US4617066A (en) | 1984-11-26 | 1986-10-14 | Hughes Aircraft Company | Process of making semiconductors having shallow, hyperabrupt doped regions by implantation and two step annealing |
US4578128A (en) * | 1984-12-03 | 1986-03-25 | Ncr Corporation | Process for forming retrograde dopant distributions utilizing simultaneous outdiffusion of dopants |
US4662061A (en) | 1985-02-27 | 1987-05-05 | Texas Instruments Incorporated | Method for fabricating a CMOS well structure |
JPH0237663Y2 (ja) | 1985-08-23 | 1990-10-11 | ||
JPH0770606B2 (ja) * | 1985-11-29 | 1995-07-31 | 株式会社日立製作所 | 半導体装置 |
JPS62128175A (ja) * | 1985-11-29 | 1987-06-10 | Hitachi Ltd | 半導体装置 |
GB8606748D0 (en) | 1986-03-19 | 1986-04-23 | Secr Defence | Monitoring surface layer growth |
US4780748A (en) | 1986-06-06 | 1988-10-25 | American Telephone & Telegraph Company, At&T Bell Laboratories | Field-effect transistor having a delta-doped ohmic contact |
DE3765844D1 (de) | 1986-06-10 | 1990-12-06 | Siemens Ag | Verfahren zum herstellen von hochintegrierten komplementaeren mos-feldeffekttransistorschaltungen. |
JPH0697432B2 (ja) | 1986-06-17 | 1994-11-30 | 松下電器産業株式会社 | 浮動小数点乗算回路 |
JPH0615661B2 (ja) | 1986-07-23 | 1994-03-02 | 昭和高分子株式会社 | 不飽和ポリエステル樹脂成形品 |
US5156990A (en) | 1986-07-23 | 1992-10-20 | Texas Instruments Incorporated | Floating-gate memory cell with tailored doping profile |
EP0274278B1 (en) | 1987-01-05 | 1994-05-25 | Seiko Instruments Inc. | MOS field effect transistor and method of manufacturing the same |
US5923985A (en) * | 1987-01-05 | 1999-07-13 | Seiko Instruments Inc. | MOS field effect transistor and its manufacturing method |
JPS63305566A (ja) | 1987-06-05 | 1988-12-13 | Nippon Telegr & Teleph Corp <Ntt> | 半導体装置およびその製造方法 |
GB2206010A (en) | 1987-06-08 | 1988-12-21 | Philips Electronic Associated | Differential amplifier and current sensing circuit including such an amplifier |
EP0312237A3 (en) | 1987-10-13 | 1989-10-25 | AT&T Corp. | Interface charge enhancement in delta-doped heterostructure |
US5156989A (en) | 1988-11-08 | 1992-10-20 | Siliconix, Incorporated | Complementary, isolated DMOS IC technology |
US5034337A (en) | 1989-02-10 | 1991-07-23 | Texas Instruments Incorporated | Method of making an integrated circuit that combines multi-epitaxial power transistors with logic/analog devices |
US4956311A (en) | 1989-06-27 | 1990-09-11 | National Semiconductor Corporation | Double-diffused drain CMOS process using a counterdoping technique |
US5208473A (en) * | 1989-11-29 | 1993-05-04 | Mitsubishi Denki Kabushiki Kaisha | Lightly doped MISFET with reduced latchup and punchthrough |
JP2822547B2 (ja) | 1990-03-06 | 1998-11-11 | 富士通株式会社 | 高電子移動度トランジスタ |
US5298435A (en) | 1990-04-18 | 1994-03-29 | National Semiconductor Corporation | Application of electronic properties of germanium to inhibit n-type or p-type diffusion in silicon |
KR920008834A (ko) | 1990-10-09 | 1992-05-28 | 아이자와 스스무 | 박막 반도체 장치 |
JPH04179160A (ja) | 1990-11-09 | 1992-06-25 | Hitachi Ltd | 半導体装置 |
JPH04186774A (ja) * | 1990-11-21 | 1992-07-03 | Hitachi Ltd | 半導体装置 |
JP2899122B2 (ja) | 1991-03-18 | 1999-06-02 | キヤノン株式会社 | 絶縁ゲートトランジスタ及び半導体集積回路 |
US5166765A (en) | 1991-08-26 | 1992-11-24 | At&T Bell Laboratories | Insulated gate field-effect transistor with pulse-shaped doping |
KR940006711B1 (ko) | 1991-09-12 | 1994-07-25 | 포항종합제철 주식회사 | 델타도핑 양자 우물전계 효과 트랜지스터의 제조방법 |
JP2851753B2 (ja) | 1991-10-22 | 1999-01-27 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
JP3146045B2 (ja) | 1992-01-06 | 2001-03-12 | 株式会社東芝 | 半導体装置及びその製造方法 |
JPH05183159A (ja) * | 1992-01-07 | 1993-07-23 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JPH05315598A (ja) | 1992-05-08 | 1993-11-26 | Fujitsu Ltd | 半導体装置 |
US5242847A (en) | 1992-07-27 | 1993-09-07 | North Carolina State University At Raleigh | Selective deposition of doped silion-germanium alloy on semiconductor substrate |
US5422508A (en) | 1992-09-21 | 1995-06-06 | Siliconix Incorporated | BiCDMOS structure |
JPH06151828A (ja) | 1992-10-30 | 1994-05-31 | Toshiba Corp | 半導体装置及びその製造方法 |
US5298763A (en) * | 1992-11-02 | 1994-03-29 | Motorola, Inc. | Intrinsically doped semiconductor structure and method for making |
US5298457A (en) | 1993-07-01 | 1994-03-29 | G. I. Corporation | Method of making semiconductor devices using epitaxial techniques to form Si/Si-Ge interfaces and inverting the material |
US5444008A (en) | 1993-09-24 | 1995-08-22 | Vlsi Technology, Inc. | High-performance punchthrough implant method for MOS/VLSI |
JPH07161974A (ja) * | 1993-12-03 | 1995-06-23 | Toshiba Corp | 半導体装置の製造方法 |
US5625568A (en) | 1993-12-22 | 1997-04-29 | Vlsi Technology, Inc. | Method and apparatus for compacting integrated circuits with standard cell architectures |
EP0698236B1 (en) | 1994-02-14 | 2000-05-10 | Koninklijke Philips Electronics N.V. | A reference circuit having a controlled temperature dependence |
KR0144959B1 (ko) | 1994-05-17 | 1998-07-01 | 김광호 | 반도체장치 및 제조방법 |
JPH07312423A (ja) | 1994-05-17 | 1995-11-28 | Hitachi Ltd | Mis型半導体装置 |
US5889315A (en) | 1994-08-18 | 1999-03-30 | National Semiconductor Corporation | Semiconductor structure having two levels of buried regions |
US5622880A (en) | 1994-08-18 | 1997-04-22 | Sun Microsystems, Inc. | Method of making a low power, high performance junction transistor |
US5818078A (en) | 1994-08-29 | 1998-10-06 | Fujitsu Limited | Semiconductor device having a regrowth crystal region |
US5559368A (en) | 1994-08-30 | 1996-09-24 | The Regents Of The University Of California | Dynamic threshold voltage mosfet having gate to body connection for ultra-low voltage operation |
JP2701762B2 (ja) * | 1994-11-28 | 1998-01-21 | 日本電気株式会社 | 半導体装置及びその製造方法 |
EP0717435A1 (en) | 1994-12-01 | 1996-06-19 | AT&T Corp. | Process for controlling dopant diffusion in a semiconductor layer and semiconductor layer formed thereby |
US6153920A (en) | 1994-12-01 | 2000-11-28 | Lucent Technologies Inc. | Process for controlling dopant diffusion in a semiconductor layer and semiconductor device formed thereby |
JPH08172187A (ja) | 1994-12-16 | 1996-07-02 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
JPH08250728A (ja) | 1995-03-10 | 1996-09-27 | Sony Corp | 電界効果型半導体装置及びその製造方法 |
US5608253A (en) * | 1995-03-22 | 1997-03-04 | Advanced Micro Devices Inc. | Advanced transistor structures with optimum short channel controls for high density/high performance integrated circuits |
US5552332A (en) | 1995-06-02 | 1996-09-03 | Motorola, Inc. | Process for fabricating a MOSFET device having reduced reverse short channel effects |
US5663583A (en) | 1995-06-06 | 1997-09-02 | Hughes Aircraft Company | Low-noise and power ALGaPSb/GaInAs HEMTs and pseudomorpohic HEMTs on GaAs substrate |
JP3462301B2 (ja) | 1995-06-16 | 2003-11-05 | 三菱電機株式会社 | 半導体装置及びその製造方法 |
JPH098296A (ja) | 1995-06-23 | 1997-01-10 | Hitachi Ltd | 半導体装置 |
US5624863A (en) | 1995-07-17 | 1997-04-29 | Micron Technology, Inc. | Semiconductor processing method of forming complementary N-type doped and P-type doped active regions within a semiconductor substrate |
US5754826A (en) | 1995-08-04 | 1998-05-19 | Synopsys, Inc. | CAD and simulation system for targeting IC designs to multiple fabrication processes |
KR0172793B1 (ko) * | 1995-08-07 | 1999-02-01 | 김주용 | 반도체소자의 제조방법 |
JPH0973784A (ja) | 1995-09-07 | 1997-03-18 | Nec Corp | 半導体装置及びその制御回路 |
US6127700A (en) * | 1995-09-12 | 2000-10-03 | National Semiconductor Corporation | Field-effect transistor having local threshold-adjust doping |
US5712501A (en) * | 1995-10-10 | 1998-01-27 | Motorola, Inc. | Graded-channel semiconductor device |
JPH09121049A (ja) | 1995-10-25 | 1997-05-06 | Sony Corp | 半導体装置 |
US5753555A (en) | 1995-11-22 | 1998-05-19 | Nec Corporation | Method for forming semiconductor device |
US5698884A (en) | 1996-02-07 | 1997-12-16 | Thunderbird Technologies, Inc. | Short channel fermi-threshold field effect transistors including drain field termination region and methods of fabricating same |
JP3420879B2 (ja) * | 1996-03-06 | 2003-06-30 | 沖電気工業株式会社 | pMOSの製造方法、及びCMOSの製造方法 |
JPH09270466A (ja) | 1996-04-01 | 1997-10-14 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
JPH1022462A (ja) | 1996-06-28 | 1998-01-23 | Sharp Corp | 半導体装置及びその製造方法 |
US5847419A (en) | 1996-09-17 | 1998-12-08 | Kabushiki Kaisha Toshiba | Si-SiGe semiconductor device and method of fabricating the same |
JPH10189766A (ja) | 1996-10-29 | 1998-07-21 | Hitachi Ltd | 半導体集積回路装置およびその製造方法ならびに半導体ウエハおよびその製造方法 |
JPH10135348A (ja) | 1996-11-05 | 1998-05-22 | Fujitsu Ltd | 電界効果型半導体装置 |
US5736419A (en) | 1996-11-12 | 1998-04-07 | National Semiconductor Corporation | Method of fabricating a raised source/drain MOSFET using self-aligned POCl3 for doping gate/source/drain regions |
JPH10163342A (ja) | 1996-12-04 | 1998-06-19 | Sharp Corp | 半導体装置 |
JPH10223853A (ja) | 1997-02-04 | 1998-08-21 | Mitsubishi Electric Corp | 半導体装置 |
DE19706789C2 (de) | 1997-02-20 | 1999-10-21 | Siemens Ag | CMOS-Schaltung mit teilweise dielektrisch isolierten Source-Drain-Bereichen und Verfahren zu ihrer Herstellung |
US5918129A (en) | 1997-02-25 | 1999-06-29 | Advanced Micro Devices, Inc. | Method of channel doping using diffusion from implanted polysilicon |
JPH10242153A (ja) | 1997-02-26 | 1998-09-11 | Hitachi Ltd | 半導体ウエハ、半導体ウエハの製造方法、半導体装置および半導体装置の製造方法 |
US5936868A (en) | 1997-03-06 | 1999-08-10 | Harris Corporation | Method for converting an integrated circuit design for an upgraded process |
JPH10270687A (ja) * | 1997-03-27 | 1998-10-09 | Mitsubishi Electric Corp | 電界効果トランジスタおよびその製造方法 |
US5923067A (en) | 1997-04-04 | 1999-07-13 | International Business Machines Corporation | 3-D CMOS-on-SOI ESD structure and method |
JP4253052B2 (ja) | 1997-04-08 | 2009-04-08 | 株式会社東芝 | 半導体装置 |
US6060345A (en) | 1997-04-21 | 2000-05-09 | Advanced Micro Devices, Inc. | Method of making NMOS and PMOS devices with reduced masking steps |
US6218895B1 (en) * | 1997-06-20 | 2001-04-17 | Intel Corporation | Multiple well transistor circuits having forward body bias |
US6218892B1 (en) | 1997-06-20 | 2001-04-17 | Intel Corporation | Differential circuits employing forward body bias |
US6194259B1 (en) * | 1997-06-27 | 2001-02-27 | Advanced Micro Devices, Inc. | Forming retrograde channel profile and shallow LLDD/S-D extensions using nitrogen implants |
US5923987A (en) | 1997-06-30 | 1999-07-13 | Sun Microsystems, Inc. | Method for forming MOS devices with retrograde pocket regions and counter dopant regions at the substrate surface |
US6723621B1 (en) * | 1997-06-30 | 2004-04-20 | International Business Machines Corporation | Abrupt delta-like doping in Si and SiGe films by UHV-CVD |
US5946214A (en) | 1997-07-11 | 1999-08-31 | Advanced Micro Devices | Computer implemented method for estimating fabrication yield for semiconductor integrated circuit including memory blocks with redundant rows and/or columns |
US5989963A (en) | 1997-07-21 | 1999-11-23 | Advanced Micro Devices, Inc. | Method for obtaining a steep retrograde channel profile |
JP3544833B2 (ja) | 1997-09-18 | 2004-07-21 | 株式会社東芝 | 半導体装置及びその製造方法 |
FR2769132B1 (fr) | 1997-09-29 | 2003-07-11 | Sgs Thomson Microelectronics | Amelioration de l'isolement entre alimentations d'un circuit analogique-numerique |
US5856003A (en) * | 1997-11-17 | 1999-01-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for forming pseudo buried layer for sub-micron bipolar or BiCMOS device |
JPH11163458A (ja) | 1997-11-26 | 1999-06-18 | Mitsui Chem Inc | 半導体レーザ装置 |
US6426260B1 (en) | 1997-12-02 | 2002-07-30 | Magepower Semiconductor Corp. | Switching speed improvement in DMO by implanting lightly doped region under gate |
US6271070B2 (en) | 1997-12-25 | 2001-08-07 | Matsushita Electronics Corporation | Method of manufacturing semiconductor device |
KR100339409B1 (ko) | 1998-01-14 | 2002-09-18 | 주식회사 하이닉스반도체 | 반도체소자및그의제조방법 |
US6088518A (en) | 1998-01-30 | 2000-07-11 | Aspec Technology, Inc. | Method and system for porting an integrated circuit layout from a reference process to a target process |
US6001695A (en) | 1998-03-02 | 1999-12-14 | Texas Instruments - Acer Incorporated | Method to form ultra-short channel MOSFET with a gate-side airgap structure |
US6096611A (en) | 1998-03-13 | 2000-08-01 | Texas Instruments - Acer Incorporated | Method to fabricate dual threshold CMOS circuits |
JP4278202B2 (ja) | 1998-03-27 | 2009-06-10 | 株式会社ルネサステクノロジ | 半導体装置の設計方法、半導体装置及び記録媒体 |
KR100265227B1 (ko) | 1998-06-05 | 2000-09-15 | 김영환 | 씨모스 트랜지스터의 제조 방법 |
US6072217A (en) | 1998-06-11 | 2000-06-06 | Sun Microsystems, Inc. | Tunable threshold SOI device using isolated well structure for back gate |
US6492232B1 (en) | 1998-06-15 | 2002-12-10 | Motorola, Inc. | Method of manufacturing vertical semiconductor device |
US6262461B1 (en) | 1998-06-22 | 2001-07-17 | Motorola, Inc. | Method and apparatus for creating a voltage threshold in a FET |
US5985705A (en) | 1998-06-30 | 1999-11-16 | Lsi Logic Corporation | Low threshold voltage MOS transistor and method of manufacture |
KR100292818B1 (ko) | 1998-07-02 | 2001-11-05 | 윤종용 | 모오스트랜지스터제조방법 |
US6320222B1 (en) | 1998-09-01 | 2001-11-20 | Micron Technology, Inc. | Structure and method for reducing threshold voltage variations due to dopant fluctuations |
US6143593A (en) | 1998-09-29 | 2000-11-07 | Conexant Systems, Inc. | Elevated channel MOSFET |
US6066533A (en) | 1998-09-29 | 2000-05-23 | Advanced Micro Devices, Inc. | MOS transistor with dual metal gate structure |
US20020008257A1 (en) | 1998-09-30 | 2002-01-24 | John P. Barnak | Mosfet gate electrodes having performance tuned work functions and methods of making same |
US6221724B1 (en) | 1998-11-06 | 2001-04-24 | Advanced Micro Devices, Inc. | Method of fabricating an integrated circuit having punch-through suppression |
US6084271A (en) | 1998-11-06 | 2000-07-04 | Advanced Micro Devices, Inc. | Transistor with local insulator structure |
US6380019B1 (en) * | 1998-11-06 | 2002-04-30 | Advanced Micro Devices, Inc. | Method of manufacturing a transistor with local insulator structure |
US6184112B1 (en) * | 1998-12-02 | 2001-02-06 | Advanced Micro Devices, Inc. | Method of forming a MOSFET transistor with a shallow abrupt retrograde dopant profile |
JP4193259B2 (ja) | 1999-01-07 | 2008-12-10 | 神鋼電機株式会社 | 部品整送装置 |
US6214654B1 (en) | 1999-01-27 | 2001-04-10 | Advanced Micro Devices, Inc. | Method for forming super-steep retrograded channel (SSRC) for CMOS transistor using rapid laser annealing to reduce thermal budget |
US6245618B1 (en) | 1999-02-03 | 2001-06-12 | Advanced Micro Devices, Inc. | Mosfet with localized amorphous region with retrograde implantation |
US6691311B1 (en) | 1999-02-12 | 2004-02-10 | Sony Corporation | Digital signal receiving apparatus and receiving method |
JP2000243958A (ja) | 1999-02-24 | 2000-09-08 | Toshiba Corp | 半導体装置およびその製造方法 |
US6060364A (en) | 1999-03-02 | 2000-05-09 | Advanced Micro Devices, Inc. | Fast Mosfet with low-doped source/drain |
US7145167B1 (en) | 2000-03-11 | 2006-12-05 | International Business Machines Corporation | High speed Ge channel heterostructures for field effect devices |
JP2000299462A (ja) | 1999-04-15 | 2000-10-24 | Toshiba Corp | 半導体装置及びその製造方法 |
US6928128B1 (en) | 1999-05-03 | 2005-08-09 | Rambus Inc. | Clock alignment circuit having a self regulating voltage supply |
US6232164B1 (en) | 1999-05-24 | 2001-05-15 | Taiwan Semiconductor Manufacturing Company | Process of making CMOS device structure having an anti-SCE block implant |
US6190979B1 (en) | 1999-07-12 | 2001-02-20 | International Business Machines Corporation | Method for fabricating dual workfunction devices on a semiconductor substrate using counter-doping and gapfill |
US6501131B1 (en) | 1999-07-22 | 2002-12-31 | International Business Machines Corporation | Transistors having independently adjustable parameters |
US6271547B1 (en) | 1999-08-06 | 2001-08-07 | Raytheon Company | Double recessed transistor with resistive layer |
US6235597B1 (en) | 1999-08-06 | 2001-05-22 | International Business Machines Corporation | Semiconductor structure having reduced silicide resistance between closely spaced gates and method of fabrication |
US6268640B1 (en) | 1999-08-12 | 2001-07-31 | International Business Machines Corporation | Forming steep lateral doping distribution at source/drain junctions |
US6444550B1 (en) | 1999-08-18 | 2002-09-03 | Advanced Micro Devices, Inc. | Laser tailoring retrograde channel profile in surfaces |
US6503801B1 (en) * | 1999-08-18 | 2003-01-07 | Advanced Micro Devices, Inc. | Non-uniform channel profile via enhanced diffusion |
US6426279B1 (en) | 1999-08-18 | 2002-07-30 | Advanced Micro Devices, Inc. | Epitaxial delta doping for retrograde channel profile |
DE19940362A1 (de) | 1999-08-25 | 2001-04-12 | Infineon Technologies Ag | MOS-Transistor und Verfahren zu dessen Herstellung |
US6162693A (en) | 1999-09-02 | 2000-12-19 | Micron Technology, Inc. | Channel implant through gate polysilicon |
US7091093B1 (en) | 1999-09-17 | 2006-08-15 | Matsushita Electric Industrial Co., Ltd. | Method for fabricating a semiconductor device having a pocket dopant diffused layer |
US6506640B1 (en) * | 1999-09-24 | 2003-01-14 | Advanced Micro Devices, Inc. | Multiple channel implantation to form retrograde channel profile and to engineer threshold voltage and sub-surface punch-through |
US6313489B1 (en) | 1999-11-16 | 2001-11-06 | Philips Electronics North America Corporation | Lateral thin-film silicon-on-insulator (SOI) device having a lateral drift region with a retrograde doping profile, and method of making such a device |
JP3371871B2 (ja) | 1999-11-16 | 2003-01-27 | 日本電気株式会社 | 半導体装置の製造方法 |
US6449749B1 (en) | 1999-11-18 | 2002-09-10 | Pdf Solutions, Inc. | System and method for product yield prediction |
US6541829B2 (en) * | 1999-12-03 | 2003-04-01 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
GB9929084D0 (en) | 1999-12-08 | 2000-02-02 | Regan Timothy J | Modification of integrated circuits |
US7638380B2 (en) | 2000-01-05 | 2009-12-29 | Agere Systems Inc. | Method for manufacturing a laterally diffused metal oxide semiconductor device |
US6633066B1 (en) * | 2000-01-07 | 2003-10-14 | Samsung Electronics Co., Ltd. | CMOS integrated circuit devices and substrates having unstrained silicon active layers |
US6297132B1 (en) | 2000-02-07 | 2001-10-02 | Chartered Semiconductor Manufacturing Ltd. | Process to control the lateral doping profile of an implanted channel region |
US6797994B1 (en) | 2000-02-14 | 2004-09-28 | Raytheon Company | Double recessed transistor |
US7015546B2 (en) * | 2000-02-23 | 2006-03-21 | Semiconductor Research Corporation | Deterministically doped field-effect devices and methods of making same |
US6326666B1 (en) | 2000-03-23 | 2001-12-04 | International Business Machines Corporation | DTCMOS circuit having improved speed |
US6548842B1 (en) * | 2000-03-31 | 2003-04-15 | National Semiconductor Corporation | Field-effect transistor for alleviating short-channel effects |
US6319799B1 (en) | 2000-05-09 | 2001-11-20 | Board Of Regents, The University Of Texas System | High mobility heterojunction transistor and method |
US6461928B2 (en) | 2000-05-23 | 2002-10-08 | Texas Instruments Incorporated | Methodology for high-performance, high reliability input/output devices and analog-compatible input/output and core devices using core device implants |
JP2001352057A (ja) * | 2000-06-09 | 2001-12-21 | Mitsubishi Electric Corp | 半導体装置、およびその製造方法 |
WO2002001641A1 (fr) | 2000-06-27 | 2002-01-03 | Matsushita Electric Industrial Co., Ltd. | Dispositif semi-conducteur |
DE10034942B4 (de) | 2000-07-12 | 2004-08-05 | Infineon Technologies Ag | Verfahren zur Erzeugung eines Halbleitersubstrats mit vergrabener Dotierung |
US6624488B1 (en) | 2000-08-07 | 2003-09-23 | Advanced Micro Devices, Inc. | Epitaxial silicon growth and usage of epitaxial gate insulator for low power, high performance devices |
JP2001068674A (ja) | 2000-08-10 | 2001-03-16 | Canon Inc | 絶縁ゲートトランジスタ及び半導体集積回路 |
US6503783B1 (en) | 2000-08-31 | 2003-01-07 | Micron Technology, Inc. | SOI CMOS device with reduced DIBL |
US6391752B1 (en) * | 2000-09-12 | 2002-05-21 | Taiwan Semiconductor Manufacturing, Co., Ltd. | Method of fabricating a silicon-on-insulator semiconductor device with an implanted ground plane |
US7064399B2 (en) | 2000-09-15 | 2006-06-20 | Texas Instruments Incorporated | Advanced CMOS using super steep retrograde wells |
US6891627B1 (en) | 2000-09-20 | 2005-05-10 | Kla-Tencor Technologies Corp. | Methods and systems for determining a critical dimension and overlay of a specimen |
US6617217B2 (en) | 2000-10-10 | 2003-09-09 | Texas Instruments Incorpated | Reduction in well implant channeling and resulting latchup characteristics in shallow trench isolation by implanting wells through nitride |
JP2002198529A (ja) | 2000-10-18 | 2002-07-12 | Hitachi Ltd | 半導体装置およびその製造方法 |
US6448590B1 (en) | 2000-10-24 | 2002-09-10 | International Business Machines Corporation | Multiple threshold voltage FET using multiple work-function gate materials |
JP3950294B2 (ja) | 2000-11-16 | 2007-07-25 | シャープ株式会社 | 半導体装置 |
DE10061191A1 (de) | 2000-12-08 | 2002-06-13 | Ihp Gmbh | Schichten in Substratscheiben |
US6300177B1 (en) | 2001-01-25 | 2001-10-09 | Chartered Semiconductor Manufacturing Inc. | Method to form transistors with multiple threshold voltages (VT) using a combination of different work function gate materials |
US6852602B2 (en) | 2001-01-31 | 2005-02-08 | Matsushita Electric Industrial Co., Ltd. | Semiconductor crystal film and method for preparation thereof |
JP2002237575A (ja) | 2001-02-08 | 2002-08-23 | Sharp Corp | 半導体装置及びその製造方法 |
US6551885B1 (en) * | 2001-02-09 | 2003-04-22 | Advanced Micro Devices, Inc. | Low temperature process for a thin film transistor |
US6797602B1 (en) | 2001-02-09 | 2004-09-28 | Advanced Micro Devices, Inc. | Method of manufacturing a semiconductor device with supersaturated source/drain extensions and metal silicide contacts |
US6787424B1 (en) | 2001-02-09 | 2004-09-07 | Advanced Micro Devices, Inc. | Fully depleted SOI transistor with elevated source and drain |
EP1421607A2 (en) | 2001-02-12 | 2004-05-26 | ASM America, Inc. | Improved process for deposition of semiconductor films |
US6821852B2 (en) | 2001-02-13 | 2004-11-23 | Micron Technology, Inc. | Dual doped gates |
KR100393216B1 (ko) | 2001-02-19 | 2003-07-31 | 삼성전자주식회사 | 엘디디 구조를 갖는 모오스 트랜지스터의 제조방법 |
US6432754B1 (en) | 2001-02-20 | 2002-08-13 | International Business Machines Corporation | Double SOI device with recess etch and epitaxy |
US6534373B1 (en) * | 2001-03-26 | 2003-03-18 | Advanced Micro Devices, Inc. | MOS transistor with reduced floating body effect |
JP3940565B2 (ja) * | 2001-03-29 | 2007-07-04 | 株式会社東芝 | 半導体装置及びその製造方法 |
JP2002299454A (ja) | 2001-04-02 | 2002-10-11 | Toshiba Corp | 論理回路設計方法、論理回路設計装置及び論理回路マッピング方法 |
US6576535B2 (en) | 2001-04-11 | 2003-06-10 | Texas Instruments Incorporated | Carbon doped epitaxial layer for high speed CB-CMOS |
US6693333B1 (en) * | 2001-05-01 | 2004-02-17 | Advanced Micro Devices, Inc. | Semiconductor-on-insulator circuit with multiple work functions |
US6620671B1 (en) | 2001-05-01 | 2003-09-16 | Advanced Micro Devices, Inc. | Method of fabricating transistor having a single crystalline gate conductor |
US6586817B1 (en) | 2001-05-18 | 2003-07-01 | Sun Microsystems, Inc. | Device including a resistive path to introduce an equivalent RC circuit |
US6489224B1 (en) | 2001-05-31 | 2002-12-03 | Sun Microsystems, Inc. | Method for engineering the threshold voltage of a device using buried wells |
US6822297B2 (en) | 2001-06-07 | 2004-11-23 | Texas Instruments Incorporated | Additional n-type LDD/pocket implant for improving short-channel NMOS ESD robustness |
US6500739B1 (en) | 2001-06-14 | 2002-12-31 | Taiwan Semiconductor Manufacturing Company | Formation of an indium retrograde profile via antimony ion implantation to improve NMOS short channel effect |
US6518673B2 (en) | 2001-06-15 | 2003-02-11 | Trw Inc. | Capacitor for signal propagation across ground plane boundaries in superconductor integrated circuits |
US6483375B1 (en) | 2001-06-28 | 2002-11-19 | Intel Corporation | Low power operation mechanism and method |
US6358806B1 (en) * | 2001-06-29 | 2002-03-19 | Lsi Logic Corporation | Silicon carbide CMOS channel |
JP4035354B2 (ja) | 2001-07-11 | 2008-01-23 | 富士通株式会社 | 電子回路設計方法及び装置、コンピュータプログラム及び記憶媒体 |
JP2003031803A (ja) * | 2001-07-19 | 2003-01-31 | Matsushita Electric Ind Co Ltd | 半導体装置とその製造方法 |
JP2003086706A (ja) | 2001-09-13 | 2003-03-20 | Sharp Corp | 半導体装置及びその製造方法、スタティック型ランダムアクセスメモリ装置並びに携帯電子機器 |
US20040207011A1 (en) | 2001-07-19 | 2004-10-21 | Hiroshi Iwata | Semiconductor device, semiconductor storage device and production methods therefor |
JP2003031813A (ja) | 2001-07-19 | 2003-01-31 | Matsushita Electric Ind Co Ltd | 半導体装置 |
US6444551B1 (en) | 2001-07-23 | 2002-09-03 | Taiwan Semiconductor Manufacturing Company | N-type buried layer drive-in recipe to reduce pits over buried antimony layer |
JP4381807B2 (ja) | 2001-09-14 | 2009-12-09 | パナソニック株式会社 | 半導体装置 |
AU2002349881A1 (en) | 2001-09-21 | 2003-04-01 | Amberwave Systems Corporation | Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same |
WO2003028106A2 (en) * | 2001-09-24 | 2003-04-03 | Amberwave Systems Corporation | Rf circuits including transistors having strained material layers |
US6751519B1 (en) | 2001-10-25 | 2004-06-15 | Kla-Tencor Technologies Corporation | Methods and systems for predicting IC chip yield |
US20050250289A1 (en) | 2002-10-30 | 2005-11-10 | Babcock Jeffrey A | Control of dopant diffusion from buried layers in bipolar integrated circuits |
US6521470B1 (en) | 2001-10-31 | 2003-02-18 | United Microelectronics Corp. | Method of measuring thickness of epitaxial layer |
US6770521B2 (en) | 2001-11-30 | 2004-08-03 | Texas Instruments Incorporated | Method of making multiple work function gates by implanting metals with metallic alloying additives |
US6760900B2 (en) | 2001-12-03 | 2004-07-06 | Anadigics Inc. | Integrated circuits with scalable design |
ITTO20011129A1 (it) | 2001-12-04 | 2003-06-04 | Infm Istituto Naz Per La Fisi | Metodo per la soppressione della diffusione anomala transiente di droganti in silicio. |
US6849528B2 (en) | 2001-12-12 | 2005-02-01 | Texas Instruments Incorporated | Fabrication of ultra shallow junctions from a solid source with fluorine implantation |
KR100794094B1 (ko) | 2001-12-28 | 2008-01-10 | 주식회사 하이닉스반도체 | 반도체 소자의 트랜지스터 제조 방법 |
US6662350B2 (en) | 2002-01-28 | 2003-12-09 | International Business Machines Corporation | FinFET layout generation |
US20030141033A1 (en) * | 2002-01-31 | 2003-07-31 | Tht Presses Inc. | Semi-solid molding method |
US7919791B2 (en) | 2002-03-25 | 2011-04-05 | Cree, Inc. | Doped group III-V nitride materials, and microelectronic devices and device precursor structures comprising same |
DE10214066B4 (de) * | 2002-03-28 | 2007-02-01 | Advanced Micro Devices, Inc., Sunnyvale | Halbleiterbauelement mit retrogradem Dotierprofil in einem Kanalgebiet und Verfahren zur Herstellung desselben |
WO2003083951A1 (en) | 2002-03-28 | 2003-10-09 | Advanced Micro Devices, Inc. | Semiconductor device having a retrograde dopant profile in a channel region and method for fabricating the same |
US6762469B2 (en) | 2002-04-19 | 2004-07-13 | International Business Machines Corporation | High performance CMOS device structure with mid-gap metal gate |
US6957163B2 (en) | 2002-04-24 | 2005-10-18 | Yoshiyuki Ando | Integrated circuits having post-silicon adjustment control |
KR100410574B1 (ko) | 2002-05-18 | 2003-12-18 | 주식회사 하이닉스반도체 | 데카보렌 도핑에 의한 초박형 에피채널을 갖는반도체소자의 제조 방법 |
KR100414736B1 (ko) | 2002-05-20 | 2004-01-13 | 주식회사 하이닉스반도체 | 반도체소자의 트랜지스터 형성방법 |
TWI290328B (en) | 2002-05-23 | 2007-11-21 | Nof Corp | Transparent conductive laminated film and touch panel |
US6893947B2 (en) * | 2002-06-25 | 2005-05-17 | Freescale Semiconductor, Inc. | Advanced RF enhancement-mode FETs with improved gate properties |
US7673273B2 (en) | 2002-07-08 | 2010-03-02 | Tier Logic, Inc. | MPGA products based on a prototype FPGA |
US6849492B2 (en) | 2002-07-08 | 2005-02-01 | Micron Technology, Inc. | Method for forming standard voltage threshold and low voltage threshold MOSFET devices |
US6743291B2 (en) | 2002-07-09 | 2004-06-01 | Chartered Semiconductor Manufacturing Ltd. | Method of fabricating a CMOS device with integrated super-steep retrograde twin wells using double selective epitaxial growth |
JP4463482B2 (ja) | 2002-07-11 | 2010-05-19 | パナソニック株式会社 | Misfet及びその製造方法 |
US7112856B2 (en) | 2002-07-12 | 2006-09-26 | Samsung Electronics Co., Ltd. | Semiconductor device having a merged region and method of fabrication |
US6869854B2 (en) | 2002-07-18 | 2005-03-22 | International Business Machines Corporation | Diffused extrinsic base and method for fabrication |
JP4020730B2 (ja) | 2002-08-26 | 2007-12-12 | シャープ株式会社 | 半導体装置およびその製造方法 |
KR100464935B1 (ko) * | 2002-09-17 | 2005-01-05 | 주식회사 하이닉스반도체 | 불화붕소화합물 도핑에 의한 초박형 에피채널을 갖는반도체소자의 제조 방법 |
JP2004119513A (ja) * | 2002-09-24 | 2004-04-15 | Toshiba Corp | 半導体装置及びその製造方法 |
US7226843B2 (en) | 2002-09-30 | 2007-06-05 | Intel Corporation | Indium-boron dual halo MOSFET |
US6743684B2 (en) | 2002-10-11 | 2004-06-01 | Texas Instruments Incorporated | Method to produce localized halo for MOS transistor |
US6864135B2 (en) | 2002-10-31 | 2005-03-08 | Freescale Semiconductor, Inc. | Semiconductor fabrication process using transistor spacers of differing widths |
DE10251308B4 (de) | 2002-11-04 | 2007-01-18 | Advanced Micro Devices, Inc., Sunnyvale | Integrierte geschaltete Kondensatorschaltung und Verfahren |
US6660605B1 (en) | 2002-11-12 | 2003-12-09 | Texas Instruments Incorporated | Method to fabricate optimal HDD with dual diffusion process to optimize transistor drive current junction capacitance, tunneling current and channel dopant loss |
JP3769262B2 (ja) | 2002-12-20 | 2006-04-19 | 株式会社東芝 | ウェーハ平坦度評価方法、その評価方法を実行するウェーハ平坦度評価装置、その評価方法を用いたウェーハの製造方法、その評価方法を用いたウェーハ品質保証方法、その評価方法を用いた半導体デバイスの製造方法、およびその評価方法によって評価されたウェーハを用いた半導体デバイスの製造方法 |
KR100486609B1 (ko) * | 2002-12-30 | 2005-05-03 | 주식회사 하이닉스반도체 | 이중 도핑구조의 초박형 에피채널 피모스트랜지스터 및그의 제조 방법 |
US7205758B1 (en) | 2004-02-02 | 2007-04-17 | Transmeta Corporation | Systems and methods for adjusting threshold voltage |
JP2006512767A (ja) | 2003-01-02 | 2006-04-13 | ピー・デイ・エフ ソリユーシヨンズ インコーポレイテツド | 歩留まり改善 |
US6963090B2 (en) | 2003-01-09 | 2005-11-08 | Freescale Semiconductor, Inc. | Enhancement mode metal-oxide-semiconductor field effect transistor |
JP2004214578A (ja) * | 2003-01-09 | 2004-07-29 | Matsushita Electric Ind Co Ltd | 半導体装置 |
KR100499159B1 (ko) | 2003-02-28 | 2005-07-01 | 삼성전자주식회사 | 리세스 채널을 갖는 반도체장치 및 그 제조방법 |
US20040175893A1 (en) | 2003-03-07 | 2004-09-09 | Applied Materials, Inc. | Apparatuses and methods for forming a substantially facet-free epitaxial film |
KR100989006B1 (ko) | 2003-03-13 | 2010-10-20 | 크로스텍 캐피탈, 엘엘씨 | 씨모스 이미지센서의 제조방법 |
US7615802B2 (en) | 2003-03-19 | 2009-11-10 | Siced Electronics Development Gmbh & Co. Kg | Semiconductor structure comprising a highly doped conductive channel region and method for producing a semiconductor structure |
SE0300924D0 (sv) * | 2003-03-28 | 2003-03-28 | Infineon Technologies Wireless | A method to provide a triple well in an epitaxially based CMOS or BiCMOS process |
EP1611602A1 (en) | 2003-03-28 | 2006-01-04 | Koninklijke Philips Electronics N.V. | Method for epitaxial deposition of an n-doped silicon layer |
US7294877B2 (en) * | 2003-03-28 | 2007-11-13 | Nantero, Inc. | Nanotube-on-gate FET structures and applications |
EP1612861B1 (en) * | 2003-04-10 | 2018-10-03 | Fujitsu Semiconductor Limited | Semiconductor device and its manufacturing method |
JP4469139B2 (ja) | 2003-04-28 | 2010-05-26 | シャープ株式会社 | 化合物半導体fet |
US7176137B2 (en) | 2003-05-09 | 2007-02-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for multiple spacer width control |
US7638841B2 (en) | 2003-05-20 | 2009-12-29 | Fairchild Semiconductor Corporation | Power semiconductor devices and methods of manufacture |
US6794235B1 (en) | 2003-06-05 | 2004-09-21 | Texas Instruments Incorporated | Method of manufacturing a semiconductor device having a localized halo implant |
WO2004112145A1 (ja) | 2003-06-10 | 2004-12-23 | Fujitsu Limited | パンチスルー耐性を向上させた半導体集積回路装置およびその製造方法、低電圧トランジスタと高電圧トランジスタとを含む半導体集積回路装置 |
US6808994B1 (en) | 2003-06-17 | 2004-10-26 | Micron Technology, Inc. | Transistor structures and processes for forming same |
US20060273299A1 (en) | 2003-06-26 | 2006-12-07 | Rj Mears, Llc | Method for making a semiconductor device including a dopant blocking superlattice |
US7036098B2 (en) | 2003-06-30 | 2006-04-25 | Sun Microsystems, Inc. | On-chip signal state duration measurement and adjustment |
US7260562B2 (en) | 2003-06-30 | 2007-08-21 | Intel Corporation | Solutions for constraint satisfaction problems requiring multiple constraints |
EP1519421A1 (en) * | 2003-09-25 | 2005-03-30 | Interuniversitair Microelektronica Centrum Vzw | Multiple gate semiconductor device and method for forming same |
EP1647046A2 (en) | 2003-07-23 | 2006-04-19 | ASM America, Inc. | DEPOSITION OF SiGE ON SILICON-ON-INSULATOR STRUCTURES AND BULK SUBSTRATES |
JP2007504660A (ja) | 2003-09-03 | 2007-03-01 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | ダブルゲート電界効果トランジスタ装置を製造する方法、及びそのようなダブルゲート電界効果トランジスタ装置 |
US6930007B2 (en) | 2003-09-15 | 2005-08-16 | Texas Instruments Incorporated | Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance |
JP4186774B2 (ja) | 2003-09-25 | 2008-11-26 | 沖電気工業株式会社 | 情報抽出装置,情報抽出方法,およびプログラム |
US7127687B1 (en) | 2003-10-14 | 2006-10-24 | Sun Microsystems, Inc. | Method and apparatus for determining transistor sizes |
US7109099B2 (en) | 2003-10-17 | 2006-09-19 | Chartered Semiconductor Manufacturing Ltd. | End of range (EOR) secondary defect engineering using substitutional carbon doping |
US7274076B2 (en) | 2003-10-20 | 2007-09-25 | Micron Technology, Inc. | Threshold voltage adjustment for long channel transistors |
US7141468B2 (en) | 2003-10-27 | 2006-11-28 | Texas Instruments Incorporated | Application of different isolation schemes for logic and embedded memory |
US7057216B2 (en) | 2003-10-31 | 2006-06-06 | International Business Machines Corporation | High mobility heterojunction complementary field effect transistors and methods thereof |
US7132323B2 (en) | 2003-11-14 | 2006-11-07 | International Business Machines Corporation | CMOS well structure and method of forming the same |
US6927137B2 (en) | 2003-12-01 | 2005-08-09 | Texas Instruments Incorporated | Forming a retrograde well in a transistor to enhance performance of the transistor |
US7279743B2 (en) | 2003-12-02 | 2007-10-09 | Vishay-Siliconix | Closed cell trench metal-oxide-semiconductor field effect transistor |
JP2007515066A (ja) | 2003-12-18 | 2007-06-07 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | 固相エピタキシャル再成長を用いて接合の漏損を低減させた半導体基板及び同半導体基板の生産方法 |
US7045456B2 (en) | 2003-12-22 | 2006-05-16 | Texas Instruments Incorporated | MOS transistor gates with thin lower metal silicide and methods for making the same |
US7111185B2 (en) | 2003-12-23 | 2006-09-19 | Micron Technology, Inc. | Synchronization device with delay line control circuit to control amount of delay added to input signal and tuning elements to receive signal form delay circuit |
DE10360874B4 (de) * | 2003-12-23 | 2009-06-04 | Infineon Technologies Ag | Feldeffekttransistor mit Heteroschichtstruktur sowie zugehöriges Herstellungsverfahren |
US7015741B2 (en) | 2003-12-23 | 2006-03-21 | Intel Corporation | Adaptive body bias for clock skew compensation |
US7005333B2 (en) | 2003-12-30 | 2006-02-28 | Infineon Technologies Ag | Transistor with silicon and carbon layer in the channel region |
JP4903055B2 (ja) * | 2003-12-30 | 2012-03-21 | フェアチャイルド・セミコンダクター・コーポレーション | パワー半導体デバイスおよびその製造方法 |
KR100597460B1 (ko) * | 2003-12-31 | 2006-07-05 | 동부일렉트로닉스 주식회사 | 반도체 소자의 트랜지스터 및제조방법 |
JP4744807B2 (ja) * | 2004-01-06 | 2011-08-10 | パナソニック株式会社 | 半導体集積回路装置 |
US6917237B1 (en) | 2004-03-02 | 2005-07-12 | Intel Corporation | Temperature dependent regulation of threshold voltage |
US7089515B2 (en) | 2004-03-09 | 2006-08-08 | International Business Machines Corporation | Threshold voltage roll-off compensation using back-gated MOSFET devices for system high-performance and low standby power |
US7176530B1 (en) | 2004-03-17 | 2007-02-13 | National Semiconductor Corporation | Configuration and fabrication of semiconductor structure having n-channel channel-junction field-effect transistor |
US7089513B2 (en) | 2004-03-19 | 2006-08-08 | International Business Machines Corporation | Integrated circuit design for signal integrity, avoiding well proximity effects |
US7564105B2 (en) | 2004-04-24 | 2009-07-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Quasi-plannar and FinFET-like transistors on bulk silicon |
US7402207B1 (en) | 2004-05-05 | 2008-07-22 | Advanced Micro Devices, Inc. | Method and apparatus for controlling the thickness of a selective epitaxial growth layer |
JP4795653B2 (ja) | 2004-06-15 | 2011-10-19 | ルネサスエレクトロニクス株式会社 | 半導体記憶装置 |
US7562233B1 (en) | 2004-06-22 | 2009-07-14 | Transmeta Corporation | Adaptive control of operating and body bias voltages |
US7221021B2 (en) * | 2004-06-25 | 2007-05-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming high voltage devices with retrograde well |
US7491988B2 (en) * | 2004-06-28 | 2009-02-17 | Intel Corporation | Transistors with increased mobility in the channel zone and method of fabrication |
US7169675B2 (en) | 2004-07-07 | 2007-01-30 | Chartered Semiconductor Manufacturing, Ltd | Material architecture for the fabrication of low temperature transistor |
US7462908B2 (en) * | 2004-07-14 | 2008-12-09 | International Rectifier Corporation | Dynamic deep depletion field effect transistor |
US7186622B2 (en) | 2004-07-15 | 2007-03-06 | Infineon Technologies Ag | Formation of active area using semiconductor growth process without STI integration |
US7119381B2 (en) | 2004-07-30 | 2006-10-10 | Freescale Semiconductor, Inc. | Complementary metal-oxide-semiconductor field effect transistor structure having ion implant in only one of the complementary devices |
US7071103B2 (en) | 2004-07-30 | 2006-07-04 | International Business Machines Corporation | Chemical treatment to retard diffusion in a semiconductor overlayer |
US7846822B2 (en) | 2004-07-30 | 2010-12-07 | The Board Of Trustees Of The University Of Illinois | Methods for controlling dopant concentration and activation in semiconductor structures |
DE102004037087A1 (de) | 2004-07-30 | 2006-03-23 | Advanced Micro Devices, Inc., Sunnyvale | Selbstvorspannende Transistorstruktur und SRAM-Zellen mit weniger als sechs Transistoren |
US7002214B1 (en) * | 2004-07-30 | 2006-02-21 | International Business Machines Corporation | Ultra-thin body super-steep retrograde well (SSRW) FET devices |
JP4469677B2 (ja) | 2004-08-04 | 2010-05-26 | パナソニック株式会社 | 半導体装置およびその製造方法 |
JP4664631B2 (ja) | 2004-08-05 | 2011-04-06 | 株式会社東芝 | 半導体装置及びその製造方法 |
US7189627B2 (en) * | 2004-08-19 | 2007-03-13 | Texas Instruments Incorporated | Method to improve SRAM performance and stability |
US20060049464A1 (en) | 2004-09-03 | 2006-03-09 | Rao G R Mohan | Semiconductor devices with graded dopant regions |
US8106481B2 (en) * | 2004-09-03 | 2012-01-31 | Rao G R Mohan | Semiconductor devices with graded dopant regions |
US7425460B2 (en) | 2004-09-17 | 2008-09-16 | California Institute Of Technology | Method for implementation of back-illuminated CMOS or CCD imagers |
US7095094B2 (en) | 2004-09-29 | 2006-08-22 | Agere Systems Inc. | Multiple doping level bipolar junctions transistors and method for forming |
US7332439B2 (en) * | 2004-09-29 | 2008-02-19 | Intel Corporation | Metal gate transistors with epitaxial source and drain regions |
US7268049B2 (en) | 2004-09-30 | 2007-09-11 | International Business Machines Corporation | Structure and method for manufacturing MOSFET with super-steep retrograded island |
JP4604637B2 (ja) | 2004-10-07 | 2011-01-05 | ソニー株式会社 | 半導体装置および半導体装置の製造方法 |
KR100652381B1 (ko) * | 2004-10-28 | 2006-12-01 | 삼성전자주식회사 | 다수의 나노 와이어 채널을 구비한 멀티 브릿지 채널 전계효과 트랜지스터 및 그 제조방법 |
US7226833B2 (en) | 2004-10-29 | 2007-06-05 | Freescale Semiconductor, Inc. | Semiconductor device structure and method therefor |
DE102004053761A1 (de) | 2004-11-08 | 2006-05-18 | Robert Bosch Gmbh | Halbleitereinrichtung und Verfahren für deren Herstellung |
US7402872B2 (en) | 2004-11-18 | 2008-07-22 | Intel Corporation | Method for forming an integrated circuit |
US20060113591A1 (en) | 2004-11-30 | 2006-06-01 | Chih-Hao Wan | High performance CMOS devices and methods for making same |
US7105399B1 (en) | 2004-12-07 | 2006-09-12 | Advanced Micro Devices, Inc. | Selective epitaxial growth for tunable channel thickness |
KR100642407B1 (ko) | 2004-12-29 | 2006-11-08 | 주식회사 하이닉스반도체 | 반도체 메모리 소자의 셀 트랜지스터 제조 방법 |
KR100613294B1 (ko) * | 2004-12-30 | 2006-08-21 | 동부일렉트로닉스 주식회사 | 단채널 효과가 개선되는 모스 전계효과 트랜지스터 및 그제조 방법 |
US20060154428A1 (en) | 2005-01-12 | 2006-07-13 | International Business Machines Corporation | Increasing doping of well compensating dopant region according to increasing gate length |
US7193279B2 (en) | 2005-01-18 | 2007-03-20 | Intel Corporation | Non-planar MOS structure with a strained channel region |
US20060166417A1 (en) * | 2005-01-27 | 2006-07-27 | International Business Machines Corporation | Transistor having high mobility channel and methods |
US7531436B2 (en) | 2005-02-14 | 2009-05-12 | Texas Instruments Incorporated | Highly conductive shallow junction formation |
US7404114B2 (en) | 2005-02-15 | 2008-07-22 | International Business Machines Corporation | System and method for balancing delay of signal communication paths through well voltage adjustment |
US20060203581A1 (en) | 2005-03-10 | 2006-09-14 | Joshi Rajiv V | Efficient method and computer program for modeling and improving static memory performance across process variations and environmental conditions |
US7407850B2 (en) | 2005-03-29 | 2008-08-05 | Texas Instruments Incorporated | N+ poly on high-k dielectric for semiconductor devices |
JP4493536B2 (ja) | 2005-03-30 | 2010-06-30 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
US7170120B2 (en) * | 2005-03-31 | 2007-01-30 | Intel Corporation | Carbon nanotube energy well (CNEW) field effect transistor |
US7338817B2 (en) | 2005-03-31 | 2008-03-04 | Intel Corporation | Body bias compensation for aged transistors |
US7271079B2 (en) * | 2005-04-06 | 2007-09-18 | International Business Machines Corporation | Method of doping a gate electrode of a field effect transistor |
US7605429B2 (en) | 2005-04-15 | 2009-10-20 | International Business Machines Corporation | Hybrid crystal orientation CMOS structure for adaptive well biasing and for power and performance enhancement |
US7446380B2 (en) | 2005-04-29 | 2008-11-04 | International Business Machines Corporation | Stabilization of flatband voltages and threshold voltages in hafnium oxide based silicon transistors for CMOS |
US7441211B1 (en) | 2005-05-06 | 2008-10-21 | Blaze Dfm, Inc. | Gate-length biasing for digital circuit optimization |
US20060273379A1 (en) * | 2005-06-06 | 2006-12-07 | Alpha & Omega Semiconductor, Ltd. | MOSFET using gate work function engineering for switching applications |
US7354833B2 (en) * | 2005-06-10 | 2008-04-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for improving threshold voltage stability of a MOS device |
US20070040222A1 (en) * | 2005-06-15 | 2007-02-22 | Benjamin Van Camp | Method and apparatus for improved ESD performance |
US7190050B2 (en) | 2005-07-01 | 2007-03-13 | Synopsys, Inc. | Integrated circuit on corrugated substrate |
JP2007013025A (ja) | 2005-07-04 | 2007-01-18 | Matsushita Electric Ind Co Ltd | 電界効果型トランジスタおよびその製造方法 |
US7735452B2 (en) * | 2005-07-08 | 2010-06-15 | Mks Instruments, Inc. | Sensor for pulsed deposition monitoring and control |
JP2007023979A (ja) | 2005-07-21 | 2007-02-01 | Nissan Motor Co Ltd | 車両駆動スリップ制御装置 |
JP4800700B2 (ja) | 2005-08-01 | 2011-10-26 | ルネサスエレクトロニクス株式会社 | 半導体装置およびそれを用いた半導体集積回路 |
US7409651B2 (en) | 2005-08-05 | 2008-08-05 | International Business Machines Corporation | Automated migration of analog and mixed-signal VLSI design |
US7314794B2 (en) | 2005-08-08 | 2008-01-01 | International Business Machines Corporation | Low-cost high-performance planar back-gate CMOS |
US7307471B2 (en) | 2005-08-26 | 2007-12-11 | Texas Instruments Incorporated | Adaptive voltage control and body bias for performance and energy optimization |
US7838369B2 (en) | 2005-08-29 | 2010-11-23 | National Semiconductor Corporation | Fabrication of semiconductor architecture having field-effect transistors especially suitable for analog applications |
JP2007073578A (ja) | 2005-09-05 | 2007-03-22 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2007103863A (ja) | 2005-10-07 | 2007-04-19 | Nec Electronics Corp | 半導体デバイス |
US7569873B2 (en) | 2005-10-28 | 2009-08-04 | Dsm Solutions, Inc. | Integrated circuit using complementary junction field effect transistor and MOS transistor in silicon and silicon alloys |
US7465642B2 (en) | 2005-10-28 | 2008-12-16 | International Business Machines Corporation | Methods for forming semiconductor structures with buried isolation collars |
JP4256381B2 (ja) | 2005-11-09 | 2009-04-22 | 株式会社東芝 | 半導体装置 |
US8255843B2 (en) | 2005-11-14 | 2012-08-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing strained-silicon semiconductor device |
US7462538B2 (en) | 2005-11-15 | 2008-12-09 | Infineon Technologies Ag | Methods of manufacturing multiple gate CMOS transistors having different gate dielectric materials |
US7759206B2 (en) | 2005-11-29 | 2010-07-20 | International Business Machines Corporation | Methods of forming semiconductor devices using embedded L-shape spacers |
EP2469584A1 (en) | 2005-12-09 | 2012-06-27 | Semequip, Inc. | Method of implanting ions |
WO2007078802A2 (en) | 2005-12-22 | 2007-07-12 | Asm America, Inc. | Epitaxial deposition of doped semiconductor materials |
KR100657130B1 (ko) | 2005-12-27 | 2006-12-13 | 동부일렉트로닉스 주식회사 | 반도체 소자 및 그 제조 방법 |
US7633134B2 (en) | 2005-12-29 | 2009-12-15 | Jaroslav Hynecek | Stratified photodiode for high resolution CMOS image sensor implemented with STI technology |
US7485536B2 (en) * | 2005-12-30 | 2009-02-03 | Intel Corporation | Abrupt junction formation by atomic layer epitaxy of in situ delta doped dopant diffusion barriers |
JP5145691B2 (ja) | 2006-02-23 | 2013-02-20 | セイコーエプソン株式会社 | 半導体装置 |
US20070212861A1 (en) | 2006-03-07 | 2007-09-13 | International Business Machines Corporation | Laser surface annealing of antimony doped amorphized semiconductor region |
US7380225B2 (en) | 2006-03-14 | 2008-05-27 | International Business Machines Corporation | Method and computer program for efficient cell failure rate estimation in cell arrays |
JP5283827B2 (ja) * | 2006-03-30 | 2013-09-04 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
US7351637B2 (en) | 2006-04-10 | 2008-04-01 | General Electric Company | Semiconductor transistors having reduced channel widths and methods of fabricating same |
US7681628B2 (en) | 2006-04-12 | 2010-03-23 | International Business Machines Corporation | Dynamic control of back gate bias in a FinFET SRAM cell |
US7348629B2 (en) * | 2006-04-20 | 2008-03-25 | International Business Machines Corporation | Metal gated ultra short MOSFET devices |
US20070257315A1 (en) | 2006-05-04 | 2007-11-08 | International Business Machines Corporation | Ion implantation combined with in situ or ex situ heat treatment for improved field effect transistors |
KR100703986B1 (ko) | 2006-05-22 | 2007-04-09 | 삼성전자주식회사 | 동작 특성과 플리커 노이즈 특성이 향상된 아날로그트랜지스터를 구비하는 반도체 소자 및 그 제조 방법 |
JPWO2007136102A1 (ja) | 2006-05-23 | 2009-10-01 | 日本電気株式会社 | 集積回路、及び半導体装置の製造方法 |
US7384835B2 (en) | 2006-05-25 | 2008-06-10 | International Business Machines Corporation | Metal oxide field effect transistor with a sharp halo and a method of forming the transistor |
US7941776B2 (en) | 2006-05-26 | 2011-05-10 | Open-Silicon Inc. | Method of IC design optimization via creation of design-specific cells from post-layout patterns |
JP5073968B2 (ja) | 2006-05-31 | 2012-11-14 | 住友化学株式会社 | 化合物半導体エピタキシャル基板およびその製造方法 |
US7503020B2 (en) | 2006-06-19 | 2009-03-10 | International Business Machines Corporation | IC layout optimization to improve yield |
US7469164B2 (en) | 2006-06-26 | 2008-12-23 | Nanometrics Incorporated | Method and apparatus for process control with in-die metrology |
US7538412B2 (en) * | 2006-06-30 | 2009-05-26 | Infineon Technologies Austria Ag | Semiconductor device with a field stop zone |
GB0613289D0 (en) | 2006-07-04 | 2006-08-16 | Imagination Tech Ltd | Synchronisation of execution threads on a multi-threaded processor |
JP5090451B2 (ja) | 2006-07-31 | 2012-12-05 | アプライド マテリアルズ インコーポレイテッド | 炭素含有シリコンエピタキシャル層の形成方法 |
US7496862B2 (en) | 2006-08-29 | 2009-02-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for automatically modifying integrated circuit layout |
TW200821417A (en) | 2006-09-07 | 2008-05-16 | Sumco Corp | Semiconductor substrate for solid state imaging device, solid state imaging device, and method for manufacturing them |
US20080067589A1 (en) * | 2006-09-20 | 2008-03-20 | Akira Ito | Transistor having reduced channel dopant fluctuation |
US7764137B2 (en) | 2006-09-28 | 2010-07-27 | Suvolta, Inc. | Circuit and method for generating electrical solutions with junction field effect transistors |
JP2008085253A (ja) | 2006-09-29 | 2008-04-10 | Oki Electric Ind Co Ltd | 半導体装置の製造方法 |
US7683442B1 (en) * | 2006-09-29 | 2010-03-23 | Burr James B | Raised source/drain with super steep retrograde channel |
US8137179B2 (en) | 2006-11-08 | 2012-03-20 | Igt | Gaming device having expanding and rolling wild symbols |
US7642150B2 (en) | 2006-11-08 | 2010-01-05 | Varian Semiconductor Equipment Associates, Inc. | Techniques for forming shallow junctions |
US7750374B2 (en) | 2006-11-14 | 2010-07-06 | Freescale Semiconductor, Inc | Process for forming an electronic device including a transistor having a metal gate electrode |
US7741200B2 (en) | 2006-12-01 | 2010-06-22 | Applied Materials, Inc. | Formation and treatment of epitaxial layer containing silicon and carbon |
US7696000B2 (en) * | 2006-12-01 | 2010-04-13 | International Business Machines Corporation | Low defect Si:C layer with retrograde carbon profile |
US7821066B2 (en) | 2006-12-08 | 2010-10-26 | Michael Lebby | Multilayered BOX in FDSOI MOSFETS |
US7897495B2 (en) | 2006-12-12 | 2011-03-01 | Applied Materials, Inc. | Formation of epitaxial layer containing silicon and carbon |
US8217423B2 (en) | 2007-01-04 | 2012-07-10 | International Business Machines Corporation | Structure and method for mobility enhanced MOSFETs with unalloyed silicide |
US7416605B2 (en) | 2007-01-08 | 2008-08-26 | Freescale Semiconductor, Inc. | Anneal of epitaxial layer in a semiconductor device |
KR100819562B1 (ko) | 2007-01-15 | 2008-04-08 | 삼성전자주식회사 | 레트로그레이드 영역을 갖는 반도체소자 및 그 제조방법 |
US20080169516A1 (en) | 2007-01-17 | 2008-07-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor devices for alleviating well proximity effects |
KR100862113B1 (ko) | 2007-01-22 | 2008-10-09 | 삼성전자주식회사 | 공정 변화에 대한 정보를 이용하여 공급전압/공급주파수를제어할 수 있는 장치와 방법 |
US7644377B1 (en) | 2007-01-31 | 2010-01-05 | Hewlett-Packard Development Company, L.P. | Generating a configuration of a system that satisfies constraints contained in models |
KR100836767B1 (ko) | 2007-02-05 | 2008-06-10 | 삼성전자주식회사 | 높은 전압을 제어하는 모스 트랜지스터를 포함하는 반도체소자 및 그 형성 방법 |
KR101312259B1 (ko) * | 2007-02-09 | 2013-09-25 | 삼성전자주식회사 | 박막 트랜지스터 및 그 제조방법 |
US7781288B2 (en) | 2007-02-21 | 2010-08-24 | International Business Machines Corporation | Semiconductor structure including gate electrode having laterally variable work function |
US7818702B2 (en) | 2007-02-28 | 2010-10-19 | International Business Machines Corporation | Structure incorporating latch-up resistant semiconductor device structures on hybrid substrates |
US7831873B1 (en) | 2007-03-07 | 2010-11-09 | Xilinx, Inc. | Method and apparatus for detecting sudden temperature/voltage changes in integrated circuits |
US7602017B2 (en) | 2007-03-13 | 2009-10-13 | Fairchild Semiconductor Corporation | Short channel LV, MV, and HV CMOS devices |
US7598142B2 (en) | 2007-03-15 | 2009-10-06 | Pushkar Ranade | CMOS device with dual-epi channels and self-aligned contacts |
JP2008235568A (ja) | 2007-03-20 | 2008-10-02 | Toshiba Corp | 半導体装置およびその製造方法 |
US8394687B2 (en) | 2007-03-30 | 2013-03-12 | Intel Corporation | Ultra-abrupt semiconductor junction profile |
US7496867B2 (en) | 2007-04-02 | 2009-02-24 | Lsi Corporation | Cell library management for power optimization |
US7737472B2 (en) | 2007-04-05 | 2010-06-15 | Panasonic Corporation | Semiconductor integrated circuit device |
CN101030602B (zh) | 2007-04-06 | 2012-03-21 | 上海集成电路研发中心有限公司 | 一种可减小短沟道效应的mos晶体管及其制作方法 |
US7692220B2 (en) | 2007-05-01 | 2010-04-06 | Suvolta, Inc. | Semiconductor device storage cell structure, method of operation, and method of manufacture |
US7586322B1 (en) | 2007-05-02 | 2009-09-08 | Altera Corporation | Test structure and method for measuring mismatch and well proximity effects |
US20080272409A1 (en) | 2007-05-03 | 2008-11-06 | Dsm Solutions, Inc.; | JFET Having a Step Channel Doping Profile and Method of Fabrication |
US7604399B2 (en) | 2007-05-31 | 2009-10-20 | Siemens Energy, Inc. | Temperature monitor for bus structure flex connector |
US20080315206A1 (en) | 2007-06-19 | 2008-12-25 | Herner S Brad | Highly Scalable Thin Film Transistor |
US7759714B2 (en) * | 2007-06-26 | 2010-07-20 | Hitachi, Ltd. | Semiconductor device |
CN101720463B (zh) | 2007-06-28 | 2012-09-26 | 萨格昂泰克以色列有限公司 | 基于设计规则和用户约束的半导体布图修正方法 |
US7651920B2 (en) * | 2007-06-29 | 2010-01-26 | Infineon Technologies Ag | Noise reduction in semiconductor device using counter-doping |
KR100934789B1 (ko) | 2007-08-29 | 2009-12-31 | 주식회사 동부하이텍 | 반도체 소자 및 그 제조 방법 |
US7895546B2 (en) | 2007-09-04 | 2011-02-22 | Lsi Corporation | Statistical design closure |
US7795677B2 (en) * | 2007-09-05 | 2010-09-14 | International Business Machines Corporation | Nanowire field-effect transistors |
JP2009064860A (ja) * | 2007-09-05 | 2009-03-26 | Renesas Technology Corp | 半導体装置 |
JP5242103B2 (ja) | 2007-09-07 | 2013-07-24 | ルネサスエレクトロニクス株式会社 | 半導体集積回路のレイアウト方法 |
US7675317B2 (en) | 2007-09-14 | 2010-03-09 | Altera Corporation | Integrated circuits with adjustable body bias and power supply circuitry |
US7926018B2 (en) | 2007-09-25 | 2011-04-12 | Synopsys, Inc. | Method and apparatus for generating a layout for a transistor |
US8053340B2 (en) | 2007-09-27 | 2011-11-08 | National University Of Singapore | Method for fabricating semiconductor devices with reduced junction diffusion |
US7704844B2 (en) * | 2007-10-04 | 2010-04-27 | International Business Machines Corporation | High performance MOSFET |
US8329564B2 (en) | 2007-10-26 | 2012-12-11 | International Business Machines Corporation | Method for fabricating super-steep retrograde well MOSFET on SOI or bulk silicon substrate, and device fabricated in accordance with the method |
US7948008B2 (en) | 2007-10-26 | 2011-05-24 | Micron Technology, Inc. | Floating body field-effect transistors, and methods of forming floating body field-effect transistors |
DE102007052220B4 (de) | 2007-10-31 | 2015-04-09 | Globalfoundries Inc. | Verfahren zur Dotierstoffprofileinstellung für MOS-Bauelemente durch Anpassen einer Abstandshalterbreite vor der Implantation |
JP5528667B2 (ja) * | 2007-11-28 | 2014-06-25 | ルネサスエレクトロニクス株式会社 | 半導体装置および半導体装置の制御方法 |
US7994573B2 (en) | 2007-12-14 | 2011-08-09 | Fairchild Semiconductor Corporation | Structure and method for forming power devices with carbon-containing region |
US7745270B2 (en) | 2007-12-28 | 2010-06-29 | Intel Corporation | Tri-gate patterning using dual layer gate stack |
US7622341B2 (en) | 2008-01-16 | 2009-11-24 | International Business Machines Corporation | Sige channel epitaxial development for high-k PFET manufacturability |
DE102008006961A1 (de) | 2008-01-31 | 2009-08-27 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zum Erzeugen eines verformten Kanalgebiets in einem Transistor durch eine tiefe Implantation einer verformungsinduzierenden Sorte unter das Kanalgebiet |
DE102008007029B4 (de) | 2008-01-31 | 2014-07-03 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | Betrieb einer elektronischen Schaltung mit körpergesteuertem Doppelkanaltransistor und SRAM-Zelle mit körpergesteuertem Doppelkanaltransistor |
JP2011512677A (ja) | 2008-02-14 | 2011-04-21 | マックスパワー・セミコンダクター・インコーポレイテッド | 半導体素子構造及び関連プロセス |
FR2928028B1 (fr) | 2008-02-27 | 2011-07-15 | St Microelectronics Crolles 2 | Procede de fabrication d'un dispositif semi-conducteur a grille enterree et circuit integre correspondant. |
US7867835B2 (en) | 2008-02-29 | 2011-01-11 | Chartered Semiconductor Manufacturing Ltd. | Integrated circuit system for suppressing short channel effects |
US7750682B2 (en) | 2008-03-10 | 2010-07-06 | International Business Machines Corporation | CMOS back-gated keeper technique |
US7968440B2 (en) | 2008-03-19 | 2011-06-28 | The Board Of Trustees Of The University Of Illinois | Preparation of ultra-shallow semiconductor junctions using intermediate temperature ramp rates and solid interfaces for defect engineering |
KR101502033B1 (ko) | 2008-04-11 | 2015-03-12 | 삼성전자주식회사 | Adc의 전류 제어 회로 및 방법 |
EP2112686B1 (en) | 2008-04-22 | 2011-10-12 | Imec | Method for fabricating a dual workfunction semiconductor device made thereof |
JP2009267159A (ja) | 2008-04-25 | 2009-11-12 | Sumco Techxiv株式会社 | 半導体ウェーハの製造装置及び方法 |
JP5173582B2 (ja) * | 2008-05-19 | 2013-04-03 | 株式会社東芝 | 半導体装置 |
US8225255B2 (en) | 2008-05-21 | 2012-07-17 | International Business Machines Corporation | Placement and optimization of process dummy cells |
DE102008026213B3 (de) | 2008-05-30 | 2009-09-24 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Durchlassstromerhöhung in Transistoren durch asymmetrische Amorphisierungsimplantation |
FR2932609B1 (fr) | 2008-06-11 | 2010-12-24 | Commissariat Energie Atomique | Transistor soi avec plan de masse et grille auto-alignes et oxyde enterre d'epaisseur variable |
US8471307B2 (en) | 2008-06-13 | 2013-06-25 | Texas Instruments Incorporated | In-situ carbon doped e-SiGeCB stack for MOS transistor |
US8129797B2 (en) | 2008-06-18 | 2012-03-06 | International Business Machines Corporation | Work function engineering for eDRAM MOSFETs |
US20100012988A1 (en) * | 2008-07-21 | 2010-01-21 | Advanced Micro Devices, Inc. | Metal oxide semiconductor devices having implanted carbon diffusion retardation layers and methods for fabricating the same |
US7951678B2 (en) | 2008-08-12 | 2011-05-31 | International Business Machines Corporation | Metal-gate high-k reference structure |
DE102008045037B4 (de) | 2008-08-29 | 2010-12-30 | Advanced Micro Devices, Inc., Sunnyvale | Statischer RAM-Zellenaufbau und Mehrfachkontaktschema zum Anschluss von Doppelkanaltransistoren |
US7927943B2 (en) * | 2008-09-12 | 2011-04-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for tuning a work function of high-k metal gate devices |
WO2010036621A2 (en) | 2008-09-25 | 2010-04-01 | Applied Materials, Inc. | Defect-free junction formation using octadecaborane self-amorphizing implants |
US20100100856A1 (en) | 2008-10-17 | 2010-04-22 | Anurag Mittal | Automated optimization of an integrated circuit layout using cost functions associated with circuit performance characteristics |
JP5519140B2 (ja) | 2008-10-28 | 2014-06-11 | ルネサスエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
US7824986B2 (en) * | 2008-11-05 | 2010-11-02 | Micron Technology, Inc. | Methods of forming a plurality of transistor gates, and methods of forming a plurality of transistor gates having at least two different work functions |
US8103983B2 (en) | 2008-11-12 | 2012-01-24 | International Business Machines Corporation | Electrically-driven optical proximity correction to compensate for non-optical effects |
US8170857B2 (en) | 2008-11-26 | 2012-05-01 | International Business Machines Corporation | In-situ design method and system for improved memory yield |
DE102008059501B4 (de) | 2008-11-28 | 2012-09-20 | Advanced Micro Devices, Inc. | Technik zur Verbesserung des Dotierstoffprofils und der Kanalleitfähigkeit durch Millisekunden-Ausheizprozesse |
US20100148153A1 (en) | 2008-12-16 | 2010-06-17 | Hudait Mantu K | Group III-V devices with delta-doped layer under channel region |
US7960238B2 (en) | 2008-12-29 | 2011-06-14 | Texas Instruments Incorporated | Multiple indium implant methods and devices and integrated circuits therefrom |
DE102008063427B4 (de) | 2008-12-31 | 2013-02-28 | Advanced Micro Devices, Inc. | Verfahren zum selektiven Herstellen eines Transistors mit einem eingebetteten verformungsinduzierenden Material mit einer graduell geformten Gestaltung |
JP5350815B2 (ja) * | 2009-01-22 | 2013-11-27 | 株式会社東芝 | 半導体装置 |
US7829402B2 (en) | 2009-02-10 | 2010-11-09 | General Electric Company | MOSFET devices and methods of making |
US20100207182A1 (en) | 2009-02-13 | 2010-08-19 | International Business Machines Corporation | Implementing Variable Threshold Voltage Transistors |
US8048791B2 (en) | 2009-02-23 | 2011-11-01 | Globalfoundries Inc. | Method of forming a semiconductor device |
US8163619B2 (en) | 2009-03-27 | 2012-04-24 | National Semiconductor Corporation | Fabrication of semiconductor structure having asymmetric field-effect transistor with tailored pocket portion along source/drain zone |
US8178430B2 (en) | 2009-04-08 | 2012-05-15 | International Business Machines Corporation | N-type carrier enhancement in semiconductors |
US8214190B2 (en) | 2009-04-13 | 2012-07-03 | International Business Machines Corporation | Methodology for correlated memory fail estimations |
US7943457B2 (en) | 2009-04-14 | 2011-05-17 | International Business Machines Corporation | Dual metal and dual dielectric integration for metal high-k FETs |
JP2010258264A (ja) | 2009-04-27 | 2010-11-11 | Toshiba Corp | 半導体集積回路装置およびその設計方法 |
US8183107B2 (en) | 2009-05-27 | 2012-05-22 | Globalfoundries Inc. | Semiconductor devices with improved local matching and end resistance of RX based resistors |
US8173499B2 (en) | 2009-06-12 | 2012-05-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of fabricating a gate stack integration of complementary MOS device |
US8227307B2 (en) | 2009-06-24 | 2012-07-24 | International Business Machines Corporation | Method for removing threshold voltage adjusting layer with external acid diffusion process |
CN101661889B (zh) | 2009-08-15 | 2011-09-07 | 北京大学深圳研究生院 | 一种部分耗尽的绝缘层上硅mos晶体管的制作方法 |
US8236661B2 (en) | 2009-09-28 | 2012-08-07 | International Business Machines Corporation | Self-aligned well implant for improving short channel effects control, parasitic capacitance, and junction leakage |
CN102034865B (zh) | 2009-09-30 | 2012-07-04 | 中国科学院微电子研究所 | 半导体器件及其制造方法 |
US8421162B2 (en) | 2009-09-30 | 2013-04-16 | Suvolta, Inc. | Advanced transistors with punch through suppression |
US20110079861A1 (en) * | 2009-09-30 | 2011-04-07 | Lucian Shifren | Advanced Transistors with Threshold Voltage Set Dopant Structures |
US8273617B2 (en) * | 2009-09-30 | 2012-09-25 | Suvolta, Inc. | Electronic devices and systems, and methods for making and using the same |
EP2309544B1 (en) * | 2009-10-06 | 2019-06-12 | IMEC vzw | Tunnel field effect transistor with improved subthreshold swing |
US8552795B2 (en) | 2009-10-22 | 2013-10-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Substrate bias control circuit for system on chip |
WO2011062788A1 (en) | 2009-11-17 | 2011-05-26 | Suvolta, Inc. | Electronic devices and systems, and methods for making and using the same |
US8114761B2 (en) | 2009-11-30 | 2012-02-14 | Applied Materials, Inc. | Method for doping non-planar transistors |
US8598003B2 (en) | 2009-12-21 | 2013-12-03 | Intel Corporation | Semiconductor device having doped epitaxial region and its methods of fabrication |
TWI404209B (zh) | 2009-12-31 | 2013-08-01 | Univ Nat Chiao Tung | 高電子遷移率電晶體及其製作方法 |
US8343818B2 (en) | 2010-01-14 | 2013-01-01 | International Business Machines Corporation | Method for forming retrograded well for MOSFET |
US8697521B2 (en) | 2010-01-21 | 2014-04-15 | International Business Machines Corporation | Structure and method for making low leakage and low mismatch NMOSFET |
US8048810B2 (en) | 2010-01-29 | 2011-11-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for metal gate N/P patterning |
US8288798B2 (en) | 2010-02-10 | 2012-10-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Step doping in extensions of III-V family semiconductor devices |
US20110212590A1 (en) | 2010-02-26 | 2011-09-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | High temperature implantation method for stressor formation |
US8436422B2 (en) | 2010-03-08 | 2013-05-07 | Sematech, Inc. | Tunneling field-effect transistor with direct tunneling for enhanced tunneling current |
US8385147B2 (en) | 2010-03-30 | 2013-02-26 | Silicon Storage Technology, Inc. | Systems and methods of non-volatile memory sensing including selective/differential threshold voltage features |
US8530286B2 (en) | 2010-04-12 | 2013-09-10 | Suvolta, Inc. | Low power semiconductor transistor structure and method of fabrication thereof |
US8176461B1 (en) | 2010-05-10 | 2012-05-08 | Xilinx, Inc. | Design-specific performance specification based on a yield for programmable integrated circuits |
US8201122B2 (en) | 2010-05-25 | 2012-06-12 | International Business Machines Corporation | Computing resistance sensitivities with respect to geometric parameters of conductors with arbitrary shapes |
JP5614877B2 (ja) | 2010-05-28 | 2014-10-29 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US8759872B2 (en) | 2010-06-22 | 2014-06-24 | Suvolta, Inc. | Transistor with threshold voltage set notch and method of fabrication thereof |
US8361872B2 (en) * | 2010-09-07 | 2013-01-29 | International Business Machines Corporation | High performance low power bulk FET device and method of manufacture |
JP2012060016A (ja) | 2010-09-10 | 2012-03-22 | Renesas Electronics Corp | 半導体装置の評価方法、評価装置、及びシミュレーション方法 |
US8450169B2 (en) | 2010-11-29 | 2013-05-28 | International Business Machines Corporation | Replacement metal gate structures providing independent control on work function and gate leakage current |
US8466473B2 (en) | 2010-12-06 | 2013-06-18 | International Business Machines Corporation | Structure and method for Vt tuning and short channel control with high k/metal gate MOSFETs |
US8656339B2 (en) | 2010-12-22 | 2014-02-18 | Advanced Micro Devices, Inc. | Method for analyzing sensitivity and failure probability of a circuit |
US8299562B2 (en) | 2011-03-28 | 2012-10-30 | Nanya Technology Corporation | Isolation structure and device structure including the same |
US8324059B2 (en) | 2011-04-25 | 2012-12-04 | United Microelectronics Corp. | Method of fabricating a semiconductor structure |
US8735987B1 (en) | 2011-06-06 | 2014-05-27 | Suvolta, Inc. | CMOS gate stack structures and processes |
US8645878B1 (en) | 2011-08-23 | 2014-02-04 | Suvolta, Inc. | Porting a circuit design from a first semiconductor process to a second semiconductor process |
TWI522548B (zh) | 2012-09-13 | 2016-02-21 | Famosa Corp | The electronic control damping structure of fitness equipment |
JP6236967B2 (ja) | 2013-07-31 | 2017-11-29 | ブラザー工業株式会社 | 端末装置とプリンタ |
EP3098671B1 (fr) | 2015-05-27 | 2019-10-09 | Montres Breguet S.A. | Mécanisme d'affichage de phase de lune d'horlogerie |
-
2010
- 2010-02-18 US US12/708,497 patent/US8273617B2/en active Active
-
2011
- 2011-02-17 JP JP2012554029A patent/JP5934118B2/ja active Active
- 2011-02-17 KR KR1020177033340A patent/KR102068106B1/ko active IP Right Grant
- 2011-02-17 WO PCT/US2011/025278 patent/WO2011103314A1/en active Application Filing
- 2011-02-17 WO PCT/US2011/025284 patent/WO2011103318A1/en active Application Filing
- 2011-02-17 JP JP2012554028A patent/JP5838172B2/ja active Active
- 2011-02-17 KR KR1020127024299A patent/KR20130004909A/ko active Application Filing
- 2011-02-17 CN CN201180019743.8A patent/CN102918645B/zh active Active
- 2011-02-17 KR KR1020127024293A patent/KR101922735B1/ko active IP Right Grant
- 2011-02-17 CN CN201180019710.3A patent/CN102844869B/zh active Active
-
2012
- 2012-07-19 US US13/553,593 patent/US8541824B2/en active Active
- 2012-09-14 US US13/616,859 patent/US8604530B2/en active Active
- 2012-09-14 US US13/616,053 patent/US8604527B2/en active Active
-
2013
- 2013-11-18 US US14/082,931 patent/US8975128B2/en active Active
-
2015
- 2015-03-09 US US14/642,156 patent/US10074568B2/en active Active
-
2016
- 2016-08-19 US US15/241,337 patent/US10224244B2/en active Active
-
2017
- 2017-01-04 US US15/398,471 patent/US10217668B2/en active Active
-
2018
- 2018-09-12 US US16/129,518 patent/US11062950B2/en active Active
-
2021
- 2021-06-10 US US17/343,756 patent/US11887895B2/en active Active
Patent Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0653496A (ja) * | 1992-06-02 | 1994-02-25 | Toshiba Corp | 半導体装置 |
JPH0697432A (ja) * | 1992-09-10 | 1994-04-08 | Hitachi Ltd | 半導体装置およびその製造方法 |
JPH06236967A (ja) * | 1992-12-14 | 1994-08-23 | Toshiba Corp | 半導体装置の製造方法 |
JPH08288508A (ja) * | 1995-04-14 | 1996-11-01 | Nec Corp | エピタキシャルチャネルmosトランジスタ及びその製造方法 |
JPH08293557A (ja) * | 1995-04-25 | 1996-11-05 | Hitachi Ltd | 半導体装置及びその製造方法 |
JPH11500873A (ja) * | 1995-12-15 | 1999-01-19 | フィリップス エレクトロニクス ネムローゼ フェンノートシャップ | SiGe層を具えた半導体電界効果デバイス |
JP2007259463A (ja) * | 1996-11-21 | 2007-10-04 | Hitachi Ltd | 低電力プロセッサ |
JP2004087602A (ja) * | 2002-08-23 | 2004-03-18 | Fujitsu Ltd | 半導体集積回路装置 |
WO2004075295A1 (ja) * | 2003-02-19 | 2004-09-02 | Hitachi, Ltd. | 半導体集積回路装置 |
JP2006093507A (ja) * | 2004-09-27 | 2006-04-06 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP2006295131A (ja) * | 2005-03-17 | 2006-10-26 | Renesas Technology Corp | 半導体装置およびその製造方法 |
WO2007023979A1 (ja) * | 2005-08-22 | 2007-03-01 | Nec Corporation | Mosfetおよび半導体装置の製造方法 |
JP2009170472A (ja) * | 2008-01-10 | 2009-07-30 | Sharp Corp | トランジスタ、半導体装置、半導体装置の製造方法 |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015226059A (ja) * | 2014-05-23 | 2015-12-14 | 三重富士通セミコンダクター株式会社 | 埋込チャネル型深空乏化チャネルトランジスタ |
KR20160012560A (ko) * | 2014-07-24 | 2016-02-03 | 삼성전자주식회사 | 딜레이 셀 및 이를 적용하는 지연 동기 루프 회로와 위상 동기 루프 회로 |
KR102101836B1 (ko) * | 2014-07-24 | 2020-04-17 | 삼성전자 주식회사 | 딜레이 셀 및 이를 적용하는 지연 동기 루프 회로와 위상 동기 루프 회로 |
JP2016032295A (ja) * | 2014-07-25 | 2016-03-07 | 三重富士通セミコンダクター株式会社 | 電源立ち上げ時のボディバイアス電圧を確立する集積回路デバイス及び方法 |
JP2020120402A (ja) * | 2014-07-25 | 2020-08-06 | ユナイテッド・セミコンダクター・ジャパン株式会社 | 集積回路デバイス |
Also Published As
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6371823B2 (ja) | 電界効果トランジスタ及びその製造方法 | |
US11887895B2 (en) | Electronic devices and systems, and methods for making and using the same | |
WO2011062788A1 (en) | Electronic devices and systems, and methods for making and using the same | |
JP6042501B2 (ja) | 電界効果トランジスタの製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20140206 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20141027 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20141111 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20150210 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20150310 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20150714 |
|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A711 Effective date: 20150817 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20151113 |
|
A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20151120 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20160126 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20160314 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20160412 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20160506 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5934118 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |