US6521470B1 - Method of measuring thickness of epitaxial layer - Google Patents

Method of measuring thickness of epitaxial layer Download PDF

Info

Publication number
US6521470B1
US6521470B1 US10145696 US14569602A US6521470B1 US 6521470 B1 US6521470 B1 US 6521470B1 US 10145696 US10145696 US 10145696 US 14569602 A US14569602 A US 14569602A US 6521470 B1 US6521470 B1 US 6521470B1
Authority
US
Grant status
Grant
Patent type
Prior art keywords
layer
thickness
non
single crystal
epitaxial
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
US10145696
Inventor
Ching-Fu Lin
Hua-Chou Tseng
Teng-Chi Yang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
United Microelectronics Corp
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Grant date

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H01L22/24Optical enhancement of defects or not directly visible states, e.g. selective electrolytic deposition, bubbles in liquids, light emission, colour change

Abstract

A method of measuring the thickness of an epitaxial layer is disclosed. The method is particularly useful in measuring the epitaxial layer with a doping concentration lower than or similar to the substrate on which the epitaxial layer is formed. The method uses a non-single crystal layer previously formed on the substrate before forming the epitaxial layer over the substrate so that the portion of the epitaxial layer on the non-single crystal layer will be polycrystal. To obtain the thickness of the epitaxial layer, thicknesses of the polycrystal layer and the non-single crystal layer as well as the thickness difference between the polycrystal layer plus the non-single crystal layer and the epitaxial layer are measured. The thickness of the epitaxial layer equals the result of the total thickness of the polycrystal layer plus the non-single crystal layer minus the thickness difference between the polycrystal layer plus the non-single crystal layer and the epitaxial layer.

Description

This application claims the benefit of Ser. No. 60/336,395, filed Oct. 31, 2001.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method of measuring the thickness of an epitaxial layer, and more particularly to an in-line method of measuring the thickness of an epitaxial layer.

2. Description of the Related Art

As is well known, it is important in the fabrication of semiconductor devices to know the thickness of an epitaxial layer on a semiconductor wafer. Different methods are known within the prior art for measuring or determining the thickness of an epitaxial layer including methods based upon IR interference physical optic theory. In accordance with such theory, IR energy is directed onto a wafer and is reflected from the surface of the epitaxial layer and from the interface between the epitaxial layer and the underlying substrate. The IR energy is directed as an incident beam onto a small area of the wafer at a position where the epitaxial thickness is to be measured. Such incident beam is divided to form two reflected beams. One beam is reflected from the surface of the epitaxial layer and the other beam is reflected from the epitaxial layer/substrate interface. The two reflected beams interface with each other in such a manner that the epitaxial thickness can be determined by spectral reflectance and interferometric methods.

The spectral reflectance method is based on the phenomena that the degree of optical interference between the two reflected beams cyclically varies at each wavelength across a spectrum. The variation produces a series of maxima and minima reflectance values in accordance with the degree of constructive and destructive interference at the different wavelengths. Such method generally involves measuring the spectral reflectance and then calculating the thickness using the reflectance at two different maxima or minima.

In the interferometric method, an interferometer is used to generate an interferogram from the two reflected beams. The interferogram includes a center burst or peak and two side bursts or peaks created as a result of displacement of the interferometer mirror. In a perfect system, the interferometer would be symmetrical and the degree of mirror displacement between two positions corresponding to two of the bursts or peaks, is proportional to the epitaxial thickness. In actual practice however, the interferogram is asymmetrical and a double Fourier Transform and other mathematical manipulations are performed to create an idealized interferogram from which the thickness is calculated as a function of mirror displacement between the side peaks.

However, when the difference of doping concentrations between the epitaxial layer and the substrate which are the same material such as silicon is negligible or the doping concentration of the epitaxial layer is lower than the doping concentration of the substrate, the optical methods such as the Fourier-Transform Infrared Spectroscopy (FTIR) method set forth and other conventional electrical methods such as the four point probe method will not be suitable anymore.

Therefore, it is necessary to provide a new method to solve the problems mentioned above, and the method of the present invention is just the one.

SUMMARY OF THE INVENTION

It is therefore an object of the invention to provide a new method of measuring the thickness of an epitaxial layer that are always available particularly when the doping concentration of the epitaxial layer is lower than or the same as the doping concentration of the substrate.

It is another object of this invention to provide a new in-line method of measuring the thickness of an epitaxial layer when the materials of the epitaxial layer and the substrate are the same.

It is a further object of this invention to provide a new method of measuring the thickness of an epitaxial layer and the growth rate ratio of a polycrystal layer to a single crystal layer.

To achieve these objects, and in accordance with the purpose of the invention, the invention uses a method of measuring the thickness of an epitaxial layer. The method comprises the steps: an ousubstrate having a non-single crystal layer thereon, wherein the non-single crystal layer only covers a portion of the substrate; forming an epitaxial layer over the substrate and the non-single crystal layer, wherein the portion of the epitaxial layer on the non-single crystal layer grows into a polycrystal layer; measuring the thickness of the polycrystal layer and the thickness of the non-single crystal layer; and measuring the thickness difference between the polycrystal layer plus the non-single crystal layer and the epitaxial layer, thereby the thickness of said epitaxial layer equals to the result of the total thickness of the polycrystal layer plus the non-single crystal layer minus the thickness difference between the polycrystal layer plus the non-single crystal layer and the epitaxial layer.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:

FIG. 1 shows a cross-sectional view of a substrate having a non-single crystal layer thereon; and

FIG. 2 shows a result of forming an epitaxial layer over the structure shown in FIG. 1.

DESCRIPTION OF THE PREFERRED EMBODIMENT

It is to be understood and appreciated that the process steps and structures described below do not cover a complete process flow. The present invention can be practiced in conjunction with various integrated circuit fabrication techniques that are used in the art, and only so much of the commonly practiced process steps are included herein as are necessary to provide an understanding of the present invention.

The present invention will be described in detail with reference to the accompanying drawings. It should be noted that the drawings are in greatly simplified form and they are not drawn to scale. Moreover, dimensions have been exaggerated in order to provide a clear illustration and understanding of the present invention.

Referring to FIG. 1, a substrate 100 having a layer 102 thereon is shown. The substrate 100 comprises, but is not limited to: a silicon substrate with a <100>crystallographic orientation. The substrate can also comprise other semiconductor substrate such as diamond-like carbon as well as germanium, gallium arsenide and indium arsenide. The layer 102 comprises a non-single crystal layer such as a polycrystal layer. The layer 102 can be a conductive layer such as a polysilicon layer or a dielectric layer such as a silicon dioxide layer or a silicon nitride layer. The thickness of the layer 102, for example, can be preferably from about 100 angstrom to about 200 angstrom but it can be thicker or thinner.

Referring to FIG. 2, an epitaxial layer 104 is formed over the substrate 100 and the layer 102. The material of the epitaxial layer 104 should be the same with the material of the substrate 100. For example, if the substrate 100 is a silicon substrate with a <100>crystallographic orientation, the epitaxial layer 104 should be an epitaxial silicon layer with a <100>crystallographic orientation. Because the layer 102 is a non-single crystal layer such as a polycrystal layer, the portion of the epitaxial layer on said non-single crystal layer 102 grows into a polycrystal layer 106 rather than a single crystal layer with a crystallographic orientation the same as the substrate. Accordingly, the polycrystal layer 106 will be a polysilicon layer if the epitaxial layer 104 is an epitaxial silicon layer. Usually, the substrate 100 such as a silicon substrate is doped and the epitaxial layer 104 is also in-situ doped with the same dopant as the substrate 100 being doped. Particularly, the thickness of the epitaxial layer 104 is difficult to find when the dopant concentration of the epitaxial layer 104 is lower or nearly the same with the dopant concentration of the substrate 100.

To find out the thickness of the epitaxial layer 104 tepi, the thickness of the polycrystal layer 106 tpoly and the thickness of the layer 102 tA must be determined. tpoly and tA can be obtained by using conventional optical methods. Typically, one can use an Ellisometer to measure tpoly and tA by the reflection or absorption of the laser light beam emitting onto the layer 102 and the polycrystal layer 106. The Ellisometer employs maximizing of internal reflection or absorption of laser light into a light transmittable layer of material. The intensity of remaining light emanating outwardly through or from the upper surface is monitored. Thickness and planarity are determinable therefrom.

The thickness difference tΔ between the epitaxial layer 104 and the layer 102 plus the polycrystal layer 106 can be measured by using a probe-based surface characterization or metrology instrument such as a profiler. The profiler utilizes atomic force to detect the vertical position of its probe while the probe scans across the surfaces of the epitaxial layer 104 and the polycrystal layer 106 thereby tΔ can be obtained. The thickness of the epitaxial layer 104 tepi can be obtained by the following equation: tepi=tpoly+tA−tΔ. The growth rate ratio tpoly/tepi can be also obtained.

Other embodiments of the invention will appear to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with the true scope and spirit of the invention being indicated by the following claims.

Claims (19)

What is claim is:
1. A method of measuring the thickness of an epitaxial layer, said method comprising:
providing a substrate having a non-single crystal layer thereon, wherein said non-single crystal layer only covers a portion of said substrate;
forming an epitaxial layer over said substrate and said non-single crystal layer, wherein the portion of said epitaxial layer on said non-single crystal layer grows into a polycrystal layer;
measuring the thickness of said polycrystal layer and the thickness of said non-single crystal layer; and
measuring the thickness difference between said polycrystal layer plus said non-single crystal layer and said epitaxial layer, thereby the thickness of said epitaxial layer equals to the result of the total thickness of said polycrystal layer plus said non-single crystal layer minus the thickness difference between said polycrystal layer plus said non-single crystal layer and said epitaxial layer.
2. The method according to claim 1, wherein said substrate comprises a silicon substrate.
3. The method according to claim 1, wherein said substrate comprises a GaAs substrate.
4. The method according to claim 1, wherein said non-single crystal layer comprises a polycrystal layer.
5. The method according to claim 1, wherein the thickness of said polycrystal layer and the thickness of said non-single crystal layer are measured by using a ellisometer.
6. The method according to claim 1, wherein the thickness difference between said polycrystal layer plus said non-single crystal layer and said epitaxial layer is measured by using a profiler.
7. A method of measuring the thickness of an epitaxial layer, said method comprising:
providing a substrate having a dielectric layer thereon, wherein said dielectric layer only covers a portion of said substrate;
forming an epitaxial layer over said substrate and said dielectric layer, wherein the portion of said epitaxial layer on said dielectric layer grows into a polycrystal layer;
measuring the thickness of said polycrystal layer and the thickness of said dielectric layer; and
measuring the thickness difference between said polycrystal layer plus said dielectric layer and said epitaxial layer, thereby the thickness of said epitaxial layer equals to the result of the total thickness of said polycrystal layer plus said dielectric layer minus the thickness difference between said polycrystal layer plus said dielectric layer and said epitaxial layer.
8. The method according to claim 7, wherein said substrate comprises a silicon substrate.
9. The method according to claim 7, wherein said substrate comprises a GaAs substrate.
10. The method according to claim 7, wherein said dielectric layer comprises a polycrystal layer.
11. The method according to claim 7, wherein the thickness of said polycrystal layer and the thickness of said dielectric layer are measured by using a ellisometer.
12. The method according to claim 7, wherein the thickness difference between said polycrystal layer plus said dielectric layer and said epitaxial layer is measured by using a profiler.
13. A method of measuring the thickness of an epitaxial layer, said method comprising:
providing a silicon substrate having a non-single crystal layer thereon, wherein said non-single crystal layer only covers a portion of said substrate;
forming an epitaxial silicon layer over said silicon substrate and said non-single crystal layer, wherein the portion of said epitaxial silicon layer on said non-single crystal layer grows into a polysilicon layer;
measuring the thickness of said polysilicon layer and the thickness of said non-single crystal layer; and
measuring the thickness difference between said polysilicon layer plus said non-single crystal layer and said epitaxial silicon layer, thereby the thickness of said epitaxial silicon layer equals to the result of the total thickness of said polysilicon layer plus said non-single crystal layer minus the thickness difference between said polysilicon layer plus said non-single crystal layer and said epitaxial silicon layer.
14. The method according to claim 13, wherein said non-single crystal layer comprises a dielectric layer.
15. The method according to claim 14, wherein said dielectric layer comprises a silicon dioxide layer.
16. The method according to claim 14, wherein dielectric layer comprises a silicon nitride layer.
17. The method according to claim 14, wherein the thickness difference between said polysilicon layer plus said non-single crystal layer and said epitaxial silicon layer is measured by using a profiler.
18. The method according to claim 13, wherein said non-single crystal layer comprises a polysilicon layer.
19. The method according to claim 13, wherein the thickness of said polysilicon layer and the thickness of said non-single crystal layer are measured by using a ellisometer.
US10145696 2001-10-31 2002-05-16 Method of measuring thickness of epitaxial layer Active US6521470B1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US33639501 true 2001-10-31 2001-10-31
US10145696 US6521470B1 (en) 2001-10-31 2002-05-16 Method of measuring thickness of epitaxial layer

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10145696 US6521470B1 (en) 2001-10-31 2002-05-16 Method of measuring thickness of epitaxial layer
CN 02146939 CN1205457C (en) 2001-10-31 2002-10-25 Method of measuring built crystal layer thickness

Publications (1)

Publication Number Publication Date
US6521470B1 true US6521470B1 (en) 2003-02-18

Family

ID=26843218

Family Applications (1)

Application Number Title Priority Date Filing Date
US10145696 Active US6521470B1 (en) 2001-10-31 2002-05-16 Method of measuring thickness of epitaxial layer

Country Status (2)

Country Link
US (1) US6521470B1 (en)
CN (1) CN1205457C (en)

Cited By (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110121404A1 (en) * 2009-09-30 2011-05-26 Lucian Shifren Advanced transistors with punch through suppression
US8404551B2 (en) 2010-12-03 2013-03-26 Suvolta, Inc. Source/drain extension control for advanced transistors
US8461875B1 (en) 2011-02-18 2013-06-11 Suvolta, Inc. Digital circuits having improved transistors, and methods therefor
US8525271B2 (en) 2011-03-03 2013-09-03 Suvolta, Inc. Semiconductor structure with improved channel stack and method for fabrication thereof
US8530286B2 (en) 2010-04-12 2013-09-10 Suvolta, Inc. Low power semiconductor transistor structure and method of fabrication thereof
US8569128B2 (en) 2010-06-21 2013-10-29 Suvolta, Inc. Semiconductor structure and method of fabrication thereof with mixed metal types
US8569156B1 (en) 2011-05-16 2013-10-29 Suvolta, Inc. Reducing or eliminating pre-amorphization in transistor manufacture
US8599623B1 (en) 2011-12-23 2013-12-03 Suvolta, Inc. Circuits and methods for measuring circuit elements in an integrated circuit device
US8614128B1 (en) 2011-08-23 2013-12-24 Suvolta, Inc. CMOS structures and processes based on selective thinning
US8629016B1 (en) 2011-07-26 2014-01-14 Suvolta, Inc. Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer
US8637955B1 (en) 2012-08-31 2014-01-28 Suvolta, Inc. Semiconductor structure with reduced junction leakage and method of fabrication thereof
US8645878B1 (en) 2011-08-23 2014-02-04 Suvolta, Inc. Porting a circuit design from a first semiconductor process to a second semiconductor process
US8713511B1 (en) 2011-09-16 2014-04-29 Suvolta, Inc. Tools and methods for yield-aware semiconductor manufacturing process target generation
US8735987B1 (en) 2011-06-06 2014-05-27 Suvolta, Inc. CMOS gate stack structures and processes
US8748986B1 (en) 2011-08-05 2014-06-10 Suvolta, Inc. Electronic device with controlled threshold voltage
US8748270B1 (en) 2011-03-30 2014-06-10 Suvolta, Inc. Process for manufacturing an improved analog transistor
US8759872B2 (en) 2010-06-22 2014-06-24 Suvolta, Inc. Transistor with threshold voltage set notch and method of fabrication thereof
US8796048B1 (en) 2011-05-11 2014-08-05 Suvolta, Inc. Monitoring and measurement of thin film layers
US8811068B1 (en) 2011-05-13 2014-08-19 Suvolta, Inc. Integrated circuit devices and methods
US8816754B1 (en) 2012-11-02 2014-08-26 Suvolta, Inc. Body bias circuits and methods
US8819603B1 (en) 2011-12-15 2014-08-26 Suvolta, Inc. Memory circuits and methods of making and designing the same
US8863064B1 (en) 2012-03-23 2014-10-14 Suvolta, Inc. SRAM cell layout structure and devices therefrom
US8877619B1 (en) 2012-01-23 2014-11-04 Suvolta, Inc. Process for manufacture of integrated circuits with different channel doping transistor architectures and devices therefrom
US8883600B1 (en) 2011-12-22 2014-11-11 Suvolta, Inc. Transistor having reduced junction leakage and methods of forming thereof
US8895327B1 (en) 2011-12-09 2014-11-25 Suvolta, Inc. Tipless transistors, short-tip transistors, and methods and circuits therefor
US8970289B1 (en) 2012-01-23 2015-03-03 Suvolta, Inc. Circuits and devices for generating bi-directional body bias voltages, and methods therefor
US8995204B2 (en) 2011-06-23 2015-03-31 Suvolta, Inc. Circuit devices and methods having adjustable transistor body bias
US8999861B1 (en) 2011-05-11 2015-04-07 Suvolta, Inc. Semiconductor structure with substitutional boron and method for fabrication thereof
US9041126B2 (en) 2012-09-21 2015-05-26 Mie Fujitsu Semiconductor Limited Deeply depleted MOS transistors having a screening layer and methods thereof
US9054219B1 (en) 2011-08-05 2015-06-09 Mie Fujitsu Semiconductor Limited Semiconductor devices having fin structures and fabrication methods thereof
US9070477B1 (en) 2012-12-12 2015-06-30 Mie Fujitsu Semiconductor Limited Bit interleaved low voltage static random access memory (SRAM) and related methods
US9093997B1 (en) 2012-11-15 2015-07-28 Mie Fujitsu Semiconductor Limited Slew based process and bias monitors and related methods
US9093550B1 (en) 2012-01-31 2015-07-28 Mie Fujitsu Semiconductor Limited Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same
US9112484B1 (en) 2012-12-20 2015-08-18 Mie Fujitsu Semiconductor Limited Integrated circuit process and bias monitors and related methods
US9112057B1 (en) 2012-09-18 2015-08-18 Mie Fujitsu Semiconductor Limited Semiconductor devices with dopant migration suppression and method of fabrication thereof
US9236466B1 (en) 2011-10-07 2016-01-12 Mie Fujitsu Semiconductor Limited Analog circuits having improved insulated gate transistors, and methods therefor
US9268885B1 (en) 2013-02-28 2016-02-23 Mie Fujitsu Semiconductor Limited Integrated circuit device methods and models with predicted device metric variations
US9299698B2 (en) 2012-06-27 2016-03-29 Mie Fujitsu Semiconductor Limited Semiconductor structure with multiple transistors having various threshold voltages
US9299801B1 (en) 2013-03-14 2016-03-29 Mie Fujitsu Semiconductor Limited Method for fabricating a transistor device with a tuned dopant profile
US9319013B2 (en) 2014-08-19 2016-04-19 Mie Fujitsu Semiconductor Limited Operational amplifier input offset correction with transistor threshold voltage adjustment
US9406567B1 (en) 2012-02-28 2016-08-02 Mie Fujitsu Semiconductor Limited Method for fabricating multiple transistor devices on a substrate with varying threshold voltages
US9431068B2 (en) 2012-10-31 2016-08-30 Mie Fujitsu Semiconductor Limited Dynamic random access memory (DRAM) with low variation transistor peripheral circuits
US9478571B1 (en) 2013-05-24 2016-10-25 Mie Fujitsu Semiconductor Limited Buried channel deeply depleted channel transistor
US9710006B2 (en) 2014-07-25 2017-07-18 Mie Fujitsu Semiconductor Limited Power up body bias circuits and methods
US10014387B2 (en) 2016-02-18 2018-07-03 Mie Fujitsu Semiconductor Limited Semiconductor structure with multiple transistors having various threshold voltages

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4912087A (en) * 1988-04-15 1990-03-27 Ford Motor Company Rapid thermal annealing of superconducting oxide precursor films on Si and SiO2 substrates
JPH0296640A (en) * 1988-10-03 1990-04-09 Dainippon Screen Mfg Co Ltd Method for measuring dispersion of refractive index and thickness of film
JPH02206146A (en) * 1989-02-06 1990-08-15 Oki Electric Ind Co Ltd Measurement of film thickness of semiconductor device
JPH0395405A (en) * 1989-09-07 1991-04-19 Seiko Instr Inc Preparing method of working curve for measuring film thickness by fluorescence x-ray
JPH04316347A (en) * 1991-04-15 1992-11-06 Oki Electric Ind Co Ltd Method of measuring film thickness of semiconductor device
US5375064A (en) * 1993-12-02 1994-12-20 Hughes Aircraft Company Method and apparatus for moving a material removal tool with low tool accelerations
US5449638A (en) * 1994-06-06 1995-09-12 United Microelectronics Corporation Process on thickness control for silicon-on-insulator technology
US5604581A (en) * 1994-10-07 1997-02-18 On-Line Technologies, Inc. Film thickness and free carrier concentration analysis method and apparatus
US5705423A (en) * 1994-11-14 1998-01-06 Shin-Etsu Handotai Co., Ltd. Epitaxial wafer
JPH11288884A (en) * 1998-04-01 1999-10-19 Advantest Corp Mbe apparatus and film thickness measuring method of epitaxially grown film
US6030887A (en) * 1998-02-26 2000-02-29 Memc Electronic Materials, Inc. Flattening process for epitaxial semiconductor wafers
US6045626A (en) * 1997-07-11 2000-04-04 Tdk Corporation Substrate structures for electronic devices
JP2001264022A (en) * 2000-03-21 2001-09-26 Nok Corp Instrument and method for measuring liquid film thickness

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4912087A (en) * 1988-04-15 1990-03-27 Ford Motor Company Rapid thermal annealing of superconducting oxide precursor films on Si and SiO2 substrates
JPH0296640A (en) * 1988-10-03 1990-04-09 Dainippon Screen Mfg Co Ltd Method for measuring dispersion of refractive index and thickness of film
JPH02206146A (en) * 1989-02-06 1990-08-15 Oki Electric Ind Co Ltd Measurement of film thickness of semiconductor device
JPH0395405A (en) * 1989-09-07 1991-04-19 Seiko Instr Inc Preparing method of working curve for measuring film thickness by fluorescence x-ray
JPH04316347A (en) * 1991-04-15 1992-11-06 Oki Electric Ind Co Ltd Method of measuring film thickness of semiconductor device
US5375064A (en) * 1993-12-02 1994-12-20 Hughes Aircraft Company Method and apparatus for moving a material removal tool with low tool accelerations
US5449638A (en) * 1994-06-06 1995-09-12 United Microelectronics Corporation Process on thickness control for silicon-on-insulator technology
US5604581A (en) * 1994-10-07 1997-02-18 On-Line Technologies, Inc. Film thickness and free carrier concentration analysis method and apparatus
US5705423A (en) * 1994-11-14 1998-01-06 Shin-Etsu Handotai Co., Ltd. Epitaxial wafer
US6045626A (en) * 1997-07-11 2000-04-04 Tdk Corporation Substrate structures for electronic devices
US6030887A (en) * 1998-02-26 2000-02-29 Memc Electronic Materials, Inc. Flattening process for epitaxial semiconductor wafers
JPH11288884A (en) * 1998-04-01 1999-10-19 Advantest Corp Mbe apparatus and film thickness measuring method of epitaxially grown film
JP2001264022A (en) * 2000-03-21 2001-09-26 Nok Corp Instrument and method for measuring liquid film thickness

Cited By (87)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8421162B2 (en) 2009-09-30 2013-04-16 Suvolta, Inc. Advanced transistors with punch through suppression
US9263523B2 (en) 2009-09-30 2016-02-16 Mie Fujitsu Semiconductor Limited Advanced transistors with punch through suppression
US9508800B2 (en) 2009-09-30 2016-11-29 Mie Fujitsu Semiconductor Limited Advanced transistors with punch through suppression
US20110121404A1 (en) * 2009-09-30 2011-05-26 Lucian Shifren Advanced transistors with punch through suppression
US9865596B2 (en) 2010-04-12 2018-01-09 Mie Fujitsu Semiconductor Limited Low power semiconductor transistor structure and method of fabrication thereof
US8530286B2 (en) 2010-04-12 2013-09-10 Suvolta, Inc. Low power semiconductor transistor structure and method of fabrication thereof
US9496261B2 (en) 2010-04-12 2016-11-15 Mie Fujitsu Semiconductor Limited Low power semiconductor transistor structure and method of fabrication thereof
US8569128B2 (en) 2010-06-21 2013-10-29 Suvolta, Inc. Semiconductor structure and method of fabrication thereof with mixed metal types
US9224733B2 (en) 2010-06-21 2015-12-29 Mie Fujitsu Semiconductor Limited Semiconductor structure and method of fabrication thereof with mixed metal types
US9418987B2 (en) 2010-06-22 2016-08-16 Mie Fujitsu Semiconductor Limited Transistor with threshold voltage set notch and method of fabrication thereof
US9922977B2 (en) 2010-06-22 2018-03-20 Mie Fujitsu Semiconductor Limited Transistor with threshold voltage set notch and method of fabrication thereof
US8759872B2 (en) 2010-06-22 2014-06-24 Suvolta, Inc. Transistor with threshold voltage set notch and method of fabrication thereof
US8563384B2 (en) 2010-12-03 2013-10-22 Suvolta, Inc. Source/drain extension control for advanced transistors
US8404551B2 (en) 2010-12-03 2013-03-26 Suvolta, Inc. Source/drain extension control for advanced transistors
US8686511B2 (en) 2010-12-03 2014-04-01 Suvolta, Inc. Source/drain extension control for advanced transistors
US9006843B2 (en) 2010-12-03 2015-04-14 Suvolta, Inc. Source/drain extension control for advanced transistors
US9985631B2 (en) 2011-02-18 2018-05-29 Mie Fujitsu Semiconductor Limited Digital circuits having improved transistors, and methods therefor
US9680470B2 (en) 2011-02-18 2017-06-13 Mie Fujitsu Semiconductor Limited Digital circuits having improved transistors, and methods therefor
US8461875B1 (en) 2011-02-18 2013-06-11 Suvolta, Inc. Digital circuits having improved transistors, and methods therefor
US9838012B2 (en) 2011-02-18 2017-12-05 Mie Fujitsu Semiconductor Limited Digital circuits having improved transistors, and methods therefor
US9184750B1 (en) 2011-02-18 2015-11-10 Mie Fujitsu Semiconductor Limited Digital circuits having improved transistors, and methods therefor
US8525271B2 (en) 2011-03-03 2013-09-03 Suvolta, Inc. Semiconductor structure with improved channel stack and method for fabrication thereof
US9111785B2 (en) 2011-03-03 2015-08-18 Mie Fujitsu Semiconductor Limited Semiconductor structure with improved channel stack and method for fabrication thereof
US9093469B2 (en) 2011-03-30 2015-07-28 Mie Fujitsu Semiconductor Limited Analog transistor
US8748270B1 (en) 2011-03-30 2014-06-10 Suvolta, Inc. Process for manufacturing an improved analog transistor
US8999861B1 (en) 2011-05-11 2015-04-07 Suvolta, Inc. Semiconductor structure with substitutional boron and method for fabrication thereof
US8796048B1 (en) 2011-05-11 2014-08-05 Suvolta, Inc. Monitoring and measurement of thin film layers
US8811068B1 (en) 2011-05-13 2014-08-19 Suvolta, Inc. Integrated circuit devices and methods
US9966130B2 (en) 2011-05-13 2018-05-08 Mie Fujitsu Semiconductor Limited Integrated circuit devices and methods
US9362291B1 (en) 2011-05-13 2016-06-07 Mie Fujitsu Semiconductor Limited Integrated circuit devices and methods
US9741428B2 (en) 2011-05-13 2017-08-22 Mie Fujitsu Semiconductor Limited Integrated circuit devices and methods
US8937005B2 (en) 2011-05-16 2015-01-20 Suvolta, Inc. Reducing or eliminating pre-amorphization in transistor manufacture
US8569156B1 (en) 2011-05-16 2013-10-29 Suvolta, Inc. Reducing or eliminating pre-amorphization in transistor manufacture
US9514940B2 (en) 2011-05-16 2016-12-06 Mie Fujitsu Semiconductor Limited Reducing or eliminating pre-amorphization in transistor manufacture
US9793172B2 (en) 2011-05-16 2017-10-17 Mie Fujitsu Semiconductor Limited Reducing or eliminating pre-amorphization in transistor manufacture
US8735987B1 (en) 2011-06-06 2014-05-27 Suvolta, Inc. CMOS gate stack structures and processes
US9281248B1 (en) 2011-06-06 2016-03-08 Mie Fujitsu Semiconductor Limited CMOS gate stack structures and processes
US8995204B2 (en) 2011-06-23 2015-03-31 Suvolta, Inc. Circuit devices and methods having adjustable transistor body bias
US8629016B1 (en) 2011-07-26 2014-01-14 Suvolta, Inc. Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer
US8653604B1 (en) 2011-07-26 2014-02-18 Suvolta, Inc. Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer
US8916937B1 (en) 2011-07-26 2014-12-23 Suvolta, Inc. Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer
US8748986B1 (en) 2011-08-05 2014-06-10 Suvolta, Inc. Electronic device with controlled threshold voltage
US9054219B1 (en) 2011-08-05 2015-06-09 Mie Fujitsu Semiconductor Limited Semiconductor devices having fin structures and fabrication methods thereof
US8963249B1 (en) 2011-08-05 2015-02-24 Suvolta, Inc. Electronic device with controlled threshold voltage
US8614128B1 (en) 2011-08-23 2013-12-24 Suvolta, Inc. CMOS structures and processes based on selective thinning
US9391076B1 (en) 2011-08-23 2016-07-12 Mie Fujitsu Semiconductor Limited CMOS structures and processes based on selective thinning
US8645878B1 (en) 2011-08-23 2014-02-04 Suvolta, Inc. Porting a circuit design from a first semiconductor process to a second semiconductor process
US9117746B1 (en) 2011-08-23 2015-08-25 Mie Fujitsu Semiconductor Limited Porting a circuit design from a first semiconductor process to a second semiconductor process
US8806395B1 (en) 2011-08-23 2014-08-12 Suvolta, Inc. Porting a circuit design from a first semiconductor process to a second semiconductor process
US8713511B1 (en) 2011-09-16 2014-04-29 Suvolta, Inc. Tools and methods for yield-aware semiconductor manufacturing process target generation
US9236466B1 (en) 2011-10-07 2016-01-12 Mie Fujitsu Semiconductor Limited Analog circuits having improved insulated gate transistors, and methods therefor
US8895327B1 (en) 2011-12-09 2014-11-25 Suvolta, Inc. Tipless transistors, short-tip transistors, and methods and circuits therefor
US8819603B1 (en) 2011-12-15 2014-08-26 Suvolta, Inc. Memory circuits and methods of making and designing the same
US8883600B1 (en) 2011-12-22 2014-11-11 Suvolta, Inc. Transistor having reduced junction leakage and methods of forming thereof
US9368624B2 (en) 2011-12-22 2016-06-14 Mie Fujitsu Semiconductor Limited Method for fabricating a transistor with reduced junction leakage current
US9196727B2 (en) 2011-12-22 2015-11-24 Mie Fujitsu Semiconductor Limited High uniformity screen and epitaxial layers for CMOS devices
US8599623B1 (en) 2011-12-23 2013-12-03 Suvolta, Inc. Circuits and methods for measuring circuit elements in an integrated circuit device
US8877619B1 (en) 2012-01-23 2014-11-04 Suvolta, Inc. Process for manufacture of integrated circuits with different channel doping transistor architectures and devices therefrom
US8970289B1 (en) 2012-01-23 2015-03-03 Suvolta, Inc. Circuits and devices for generating bi-directional body bias voltages, and methods therefor
US9093550B1 (en) 2012-01-31 2015-07-28 Mie Fujitsu Semiconductor Limited Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same
US9385047B2 (en) 2012-01-31 2016-07-05 Mie Fujitsu Semiconductor Limited Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same
US9406567B1 (en) 2012-02-28 2016-08-02 Mie Fujitsu Semiconductor Limited Method for fabricating multiple transistor devices on a substrate with varying threshold voltages
US8863064B1 (en) 2012-03-23 2014-10-14 Suvolta, Inc. SRAM cell layout structure and devices therefrom
US9812550B2 (en) 2012-06-27 2017-11-07 Mie Fujitsu Semiconductor Limited Semiconductor structure with multiple transistors having various threshold voltages
US9299698B2 (en) 2012-06-27 2016-03-29 Mie Fujitsu Semiconductor Limited Semiconductor structure with multiple transistors having various threshold voltages
US8637955B1 (en) 2012-08-31 2014-01-28 Suvolta, Inc. Semiconductor structure with reduced junction leakage and method of fabrication thereof
US9105711B2 (en) 2012-08-31 2015-08-11 Mie Fujitsu Semiconductor Limited Semiconductor structure with reduced junction leakage and method of fabrication thereof
US9112057B1 (en) 2012-09-18 2015-08-18 Mie Fujitsu Semiconductor Limited Semiconductor devices with dopant migration suppression and method of fabrication thereof
US9041126B2 (en) 2012-09-21 2015-05-26 Mie Fujitsu Semiconductor Limited Deeply depleted MOS transistors having a screening layer and methods thereof
US9431068B2 (en) 2012-10-31 2016-08-30 Mie Fujitsu Semiconductor Limited Dynamic random access memory (DRAM) with low variation transistor peripheral circuits
US9154123B1 (en) 2012-11-02 2015-10-06 Mie Fujitsu Semiconductor Limited Body bias circuits and methods
US8816754B1 (en) 2012-11-02 2014-08-26 Suvolta, Inc. Body bias circuits and methods
US9319034B2 (en) 2012-11-15 2016-04-19 Mie Fujitsu Semiconductor Limited Slew based process and bias monitors and related methods
US9093997B1 (en) 2012-11-15 2015-07-28 Mie Fujitsu Semiconductor Limited Slew based process and bias monitors and related methods
US9070477B1 (en) 2012-12-12 2015-06-30 Mie Fujitsu Semiconductor Limited Bit interleaved low voltage static random access memory (SRAM) and related methods
US9112484B1 (en) 2012-12-20 2015-08-18 Mie Fujitsu Semiconductor Limited Integrated circuit process and bias monitors and related methods
US9276561B2 (en) 2012-12-20 2016-03-01 Mie Fujitsu Semiconductor Limited Integrated circuit process and bias monitors and related methods
US9268885B1 (en) 2013-02-28 2016-02-23 Mie Fujitsu Semiconductor Limited Integrated circuit device methods and models with predicted device metric variations
US9299801B1 (en) 2013-03-14 2016-03-29 Mie Fujitsu Semiconductor Limited Method for fabricating a transistor device with a tuned dopant profile
US9577041B2 (en) 2013-03-14 2017-02-21 Mie Fujitsu Semiconductor Limited Method for fabricating a transistor device with a tuned dopant profile
US9893148B2 (en) 2013-03-14 2018-02-13 Mie Fujitsu Semiconductor Limited Method for fabricating a transistor device with a tuned dopant profile
US9786703B2 (en) 2013-05-24 2017-10-10 Mie Fujitsu Semiconductor Limited Buried channel deeply depleted channel transistor
US9478571B1 (en) 2013-05-24 2016-10-25 Mie Fujitsu Semiconductor Limited Buried channel deeply depleted channel transistor
US9991300B2 (en) 2013-05-24 2018-06-05 Mie Fujitsu Semiconductor Limited Buried channel deeply depleted channel transistor
US9710006B2 (en) 2014-07-25 2017-07-18 Mie Fujitsu Semiconductor Limited Power up body bias circuits and methods
US9319013B2 (en) 2014-08-19 2016-04-19 Mie Fujitsu Semiconductor Limited Operational amplifier input offset correction with transistor threshold voltage adjustment
US10014387B2 (en) 2016-02-18 2018-07-03 Mie Fujitsu Semiconductor Limited Semiconductor structure with multiple transistors having various threshold voltages

Also Published As

Publication number Publication date Type
CN1459618A (en) 2003-12-03 application
CN1205457C (en) 2005-06-08 grant

Similar Documents

Publication Publication Date Title
Cocorullo et al. Temperature dependence of the thermo-optic coefficient in crystalline silicon between room temperature and 550 K at the wavelength of 1523 nm
US6290864B1 (en) Fluoride gas etching of silicon with improved selectivity
US6297880B1 (en) Apparatus for analyzing multi-layer thin film stacks on semiconductors
US5741070A (en) Apparatus for real-time semiconductor wafer temperature measurement based on a surface roughness characteristic of the wafer
US5985681A (en) Method of producing bonded substrate with silicon-on-insulator structure
US5392124A (en) Method and apparatus for real-time, in-situ endpoint detection and closed loop etch process control
US6116779A (en) Method for determining the temperature of semiconductor substrates from bandgap spectra
US6815228B2 (en) Film thickness measuring method of member to be processed using emission spectroscopy and processing method of the member using the measuring method
US6485872B1 (en) Method and apparatus for measuring the composition and other properties of thin films utilizing infrared radiation
US5841931A (en) Methods of forming polycrystalline semiconductor waveguides for optoelectronic integrated circuits, and devices formed thereby
McMarr et al. Spectroscopic ellipsometry: A new tool for nondestructive depth profiling and characterization of interfaces
US6177995B1 (en) Polarimeter and corresponding measuring method
US7893703B2 (en) Systems and methods for controlling deposition of a charge on a wafer for measurement of one or more electrical properties of the wafer
US4367044A (en) Situ rate and depth monitor for silicon etching
US5362356A (en) Plasma etching process control
US5354575A (en) Ellipsometric approach to anti-reflection coatings of semiconductor laser amplifiers
US5494697A (en) Process for fabricating a device using an ellipsometric technique
US20040032593A1 (en) Process endpoint detection method using broadband reflectometry
US6174081B1 (en) Specular reflection optical bandgap thermometry
US4211488A (en) Optical testing of a semiconductor
US6465265B2 (en) Analysis of interface layer characteristics
US5739909A (en) Measurement and control of linewidths in periodic structures using spectroscopic ellipsometry
US4953982A (en) Method and apparatus for endpoint detection in a semiconductor wafer etching system
US4989972A (en) Low reflectivity surface relief gratings for photodetectors
US5724144A (en) Process monitoring and thickness measurement from the back side of a semiconductor body

Legal Events

Date Code Title Description
AS Assignment

Owner name: UNITED MICROELECTRONICS CORP., TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LIN, CHING-FU;TSENG, HUA-CHOU;YANG, TENG-CHI;REEL/FRAME:012907/0442

Effective date: 20010727

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12