JPH02206146A - Measurement of film thickness of semiconductor device - Google Patents

Measurement of film thickness of semiconductor device

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Publication number
JPH02206146A
JPH02206146A JP2688389A JP2688389A JPH02206146A JP H02206146 A JPH02206146 A JP H02206146A JP 2688389 A JP2688389 A JP 2688389A JP 2688389 A JP2688389 A JP 2688389A JP H02206146 A JPH02206146 A JP H02206146A
Authority
JP
Japan
Prior art keywords
layer
measurement
pattern
film thickness
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2688389A
Other languages
Japanese (ja)
Inventor
Isao Sato
功 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP2688389A priority Critical patent/JPH02206146A/en
Publication of JPH02206146A publication Critical patent/JPH02206146A/en
Pending legal-status Critical Current

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  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Length Measuring Devices With Unspecified Measuring Means (AREA)

Abstract

PURPOSE:To measure a film thickness of an epitaxial growth layer highly accurately and easily by a method wherein a pattern for measurement use, a deposition layer and an opening part are formed according to a process and are utilized. CONSTITUTION:A dielectric layer other than a pattern 23 for measurement use is removed; after that, a deposition layer 25 composed of a single-crystal silicon layer to which n-type impurities have been added, i.e. an epitaxial growth layer, is formed on a semiconductor substrate 21; then, the deposition layer 25 on the pattern 23, for measurement use, composed of a silicon oxide film is transformed into a polycrystalline silicon layer 26. Then, the polycrystalline silicon layer 25 is dry-etched; an opening part 27 reaching the pattern 23 for measurement use is formed; in succession, the pattern 23, for measurement use, exposed inside the opening part 27 is etched by using a hydrofluoric-acid-based solution; the opening part 27 reaches the semiconductor substrate 21. After that, a difference in level on the surface is measured by using a contact-type surface difference-in-level meter while this meter is scanned on the deposition layer 25 including the opening part 27, e.g. in a direction of an arrow C. Thereby, a film thickness of the deposition layer can be measured by using a highly accurate and easy means.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は半導体装置の膜厚測定方法、特にエピタキシャ
ル成長層に対する膜厚測定方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for measuring the thickness of a semiconductor device, and particularly to a method of measuring the thickness of an epitaxially grown layer.

(従来の技術) 従来、このような分野の技術に関するものとしては、例
えばエピタキシャル膜厚計がある。この膜厚計は赤外線
を応用したものであり、再現性良くエピタキシャル成長
層の膜厚を測定できるので、広く用いられている。
(Prior Art) Conventionally, as a technology related to such a field, there is an epitaxial film thickness meter, for example. This film thickness meter uses infrared rays and is widely used because it can measure the thickness of an epitaxially grown layer with good reproducibility.

しかし、前記膜厚計は高濃度のシリコン基板上にエピタ
キシャル成長層を形成した場合でないと高濃度に測定で
きないという不具合があった。また、この膜厚計はエピ
タキシャル成長層側に上方拡散された位置からエピタキ
シャル成長層表面までを測定するので、元のシリコン基
板とエピタキシャル成長層との界面を正確に測定できな
いという不具合もあった。
However, the film thickness meter has a problem in that it cannot measure high concentrations unless an epitaxially grown layer is formed on a high concentration silicon substrate. Furthermore, since this film thickness meter measures from the position upwardly diffused to the epitaxial growth layer side to the surface of the epitaxial growth layer, there was also a problem in that the interface between the original silicon substrate and the epitaxial growth layer could not be accurately measured.

上記不具合を解決する膜厚測定技術としては、特公昭5
9−17536号公報に記載されている測定方法がある
。この文献は、単結晶シリコン基板中にP形拡散領域を
形成した場合のその拡散領域深さを測定する方法につい
て述べているが、この測定方法を利用してエピタキシャ
ル成長層の膜厚測定を行なうことが可能であり、以下に
その測定方法を説明する。
As a film thickness measurement technology that solves the above problems,
There is a measuring method described in Japanese Patent No. 9-17536. This document describes a method for measuring the depth of a P-type diffusion region when a P-type diffusion region is formed in a single-crystal silicon substrate. is possible, and the measurement method will be explained below.

第2図(a)〜(e)は前記文献の方法を用いた従来の
エピタキシャル成長層の膜厚測定方法を示すものであり
、同図(a)〜(d)は試料片の製造工程、及び同図(
e)のその試料片による測定方法をそれぞれ示すもので
ある。
FIGS. 2(a) to 2(e) show a conventional method for measuring the thickness of an epitaxially grown layer using the method described in the above-mentioned document, and FIGS. 2(a) to 2(d) show the manufacturing process of a sample piece, and Same figure (
The method of measuring e) using the sample piece is shown respectively.

第2図(a)〜(d)において、それぞれ左側の図は試
料片の正面断面図を示し、これに対応する右側の図はそ
れぞれ正面断面図のA−A線断面を示す側面断面図であ
る。先ず第2図(a)に示すように、単結晶シリコンか
ら成る半導体基板1の全表面に膜厚1000人程度0シ
リコン酸化膜から成る誘電体層2を形成する。続いて第
2図(b)に示す如く、誘電体層2の表面上に不純物を
添加しない多結晶シリコン層3を気相成長法で育成する
In FIGS. 2(a) to 2(d), the figures on the left side each show a front sectional view of the sample piece, and the corresponding figures on the right side are side sectional views showing the cross section taken along line A-A of the front sectional view. be. First, as shown in FIG. 2(a), a dielectric layer 2 made of a silicon oxide film having a thickness of approximately 1000 yen is formed on the entire surface of a semiconductor substrate 1 made of single crystal silicon. Subsequently, as shown in FIG. 2(b), a polycrystalline silicon layer 3 to which no impurities are added is grown on the surface of the dielectric layer 2 by vapor phase growth.

次に第2図(C)に示すように、多結晶シリコン層3に
ドライエツチングを施し、誘電体層2に達する複数の開
口4をストライプ状に形成する。
Next, as shown in FIG. 2(C), polycrystalline silicon layer 3 is dry etched to form a plurality of openings 4 in stripes reaching dielectric layer 2. Then, as shown in FIG.

その後、開口4内に露出した誘電体層2をぶつ酸系溶液
に浸してエツチング除去し、開口4を半導体基板1に到
達せしめる。これにより、半導体基板1上には、半導体
基板1の露出面5と多結晶シリコン層3の露出面6がス
トライプ状に存在することになる。
Thereafter, the dielectric layer 2 exposed in the opening 4 is immersed in a diluted acid solution and removed by etching, allowing the opening 4 to reach the semiconductor substrate 1. Thereby, on the semiconductor substrate 1, the exposed surface 5 of the semiconductor substrate 1 and the exposed surface 6 of the polycrystalline silicon layer 3 are present in a stripe shape.

次いで第2図(d)の如く、半導体基板1上の全面にエ
ピタキシャル成長を行なわしめる。これにより半導体基
板1の露出面5上にはエピタキシャル成長層7が形成さ
れ、多結晶シリコン層3の露出面6上には多結晶シリコ
ン層8が形成される。
Next, as shown in FIG. 2(d), epitaxial growth is performed on the entire surface of the semiconductor substrate 1. As a result, an epitaxial growth layer 7 is formed on the exposed surface 5 of the semiconductor substrate 1, and a polycrystalline silicon layer 8 is formed on the exposed surface 6 of the polycrystalline silicon layer 3.

このようにして、膜厚測定用の試料片9が製造される。In this way, the sample piece 9 for film thickness measurement is manufactured.

その後、試料片9のエピタキシャル成長層7に対する膜
厚測定は、第2図(e)のように行なわれる。第2図(
e)は試料片9の側面断面図とその平面図を示している
Thereafter, the film thickness of the epitaxially grown layer 7 of the sample piece 9 is measured as shown in FIG. 2(e). Figure 2 (
e) shows a side sectional view and a plan view of the sample piece 9.

先ず、半径Rの円盤形砥石10をその回転軸がエピタキ
シャル成長層7及び多結晶シリコン層8のストライプに
対して直交するように配置し、回転研磨を行なって溝1
1を形成する。これによりエピタキシャル成長層7の表
面には研磨端部12a、12bが形成され、多結晶シリ
コン層8の表面には研磨端部13a、13bが形成され
る。また、溝11内には各層が露出し、半導体基板1と
エピタキシャル成長層7の界面14a、14b、及び半
導体基板1と誘電体層2の界面15a、15bも露出す
る。
First, a disk-shaped grindstone 10 with a radius R is arranged so that its rotation axis is perpendicular to the stripes of the epitaxial growth layer 7 and the polycrystalline silicon layer 8, and rotational polishing is performed to form the grooves 1.
form 1. As a result, polished end portions 12a, 12b are formed on the surface of epitaxial growth layer 7, and polished end portions 13a, 13b are formed on the surface of polycrystalline silicon layer 8. Further, each layer is exposed in the groove 11, and the interfaces 14a and 14b between the semiconductor substrate 1 and the epitaxial growth layer 7 and the interfaces 15a and 15b between the semiconductor substrate 1 and the dielectric layer 2 are also exposed.

ここに、研磨端部12a、12b、13a、13bは観
察可能であるが、界面14a、14bは単結晶シリコン
同士の界面であるため、観察不可能である。一方界面1
5a、15bは、誘電体層2を成すシリコン酸化膜が干
渉色を有するもので光学的に観察可能である。それ故、
研磨端部12aと界面15a間もしくは研磨端部12b
と界面15b間の距離1、及び界面15aと界面15b
間の距離mを測定する。そして、これらの距離ρmと前
記砥石10の半径Rを次式 %式% に代入することにより、エピタキシャル成長層7の膜厚
dを算出することができる。
Here, the polished ends 12a, 12b, 13a, and 13b can be observed, but the interfaces 14a and 14b are not observable because they are interfaces between single crystal silicon. On the other hand, interface 1
5a and 15b, the silicon oxide film forming the dielectric layer 2 has an interference color and can be observed optically. Therefore,
Between the polished end 12a and the interface 15a or between the polished end 12b
and the distance 1 between the interface 15b and the interface 15a and the interface 15b.
Measure the distance m between. The film thickness d of the epitaxial growth layer 7 can be calculated by substituting these distances ρm and the radius R of the grindstone 10 into the following formula %.

こうした測定方法は、半導体基板1とエピタキシャル成
長層7の界面14a、14bからエピタキシャル成長層
7表面までを比較的簡易にかつ正確に測定できるので、
今日に至るまで広く用いられている。
Such a measurement method can relatively easily and accurately measure the area from the interfaces 14a and 14b between the semiconductor substrate 1 and the epitaxial growth layer 7 to the surface of the epitaxial growth layer 7.
It is widely used to this day.

(発明が解決しようとする課題) しかしながら、上記構成の半導体装置の膜厚測定方法で
は、実際のデバイスを形成するウェハ(以下、本ウェハ
という)のエピタキシャル成長工程において、本ウェハ
とは別個の試料片9を同時処理により形成する。即ち、
半導体基板↑の誘電体層2上に多結晶シリコンN3を形
成して試料片9を調整し、研磨を行なった後に膜厚測定
を行なうので、次のような問題点を生じ−その解決が困
難であった。
(Problem to be Solved by the Invention) However, in the method for measuring the film thickness of a semiconductor device having the above configuration, in the epitaxial growth process of a wafer (hereinafter referred to as the main wafer) that forms an actual device, a sample piece separate from the main wafer is 9 is formed by simultaneous processing. That is,
Since polycrystalline silicon N3 is formed on the dielectric layer 2 of the semiconductor substrate ↑, the sample piece 9 is prepared, and the film thickness is measured after polishing, the following problems occur, which are difficult to solve. Met.

(1) 本ウェハと試料片つとでは、エピタキシャル成
長層7を成長させる面積が異なるため一所謂ローディン
グ効果を生じ、双方におけるエピタキシャル成長層7の
膜厚に差異を生じる。それ故、試料片9で測定された膜
厚が必ずしも木ウェハの膜厚に一致しないおそれがある
(1) Since the areas on which the epitaxial growth layer 7 is grown are different between this wafer and the sample piece, a so-called loading effect occurs, resulting in a difference in the film thickness of the epitaxial growth layer 7 on both sides. Therefore, there is a possibility that the film thickness measured on the sample piece 9 does not necessarily match the film thickness of the wooden wafer.

(2) 前記ローディング効果を防止するため、ウェハ
を用いて試料片9を形成する場合には、装置の処理能力
上の問題が生じる。即ち、1回にエピタキシャル成長を
行なえる容量は装置によって決定されるので、本ウェハ
の処理能力が低下してしまう。
(2) When forming the sample piece 9 using a wafer in order to prevent the loading effect, a problem arises in terms of the throughput of the apparatus. That is, since the capacity that can be epitaxially grown at one time is determined by the equipment, the throughput of the wafer is reduced.

(3) 試料片9を実デバイスと共に本ウェハ上に形成
しなとしても、その膜厚測定に際しては研磨等の関係か
ら試料片9を本ウェハから切り出さねばならず、その本
ウェハは使用不能な無駄になってしまう。従って、試料
片9を別個に調製する必要がある上に、ストライプ状の
多結晶シリコン層3の形成作業や研磨作業が必要なので
、膜厚測定に多大な工数を費やさねばならない。
(3) Even if the sample piece 9 is not formed on the actual wafer together with the actual device, the sample piece 9 must be cut out from the actual wafer due to polishing etc. when measuring its film thickness, and the actual wafer may become unusable. It will be wasted. Therefore, it is necessary to separately prepare the sample piece 9, and it is also necessary to perform the formation and polishing operations of the striped polycrystalline silicon layer 3, so that a large number of man-hours must be spent on measuring the film thickness.

本発明は、前記従来技術がもっていた課題として、試料
片で測定された膜厚が必ずしも実際の膜厚に一致しない
点、処理装置の能力上の問題を生じる点、及び膜厚測定
に多大な工数を要する点について解決した半導体装置の
膜厚測定方法を提供するものである。
The present invention addresses the problems that the prior art had, such as the fact that the film thickness measured on a sample piece does not necessarily match the actual film thickness, problems that arise in the performance of processing equipment, and the fact that film thickness measurement requires a great deal of effort. The present invention provides a method for measuring film thickness of a semiconductor device that solves the problem of requiring a lot of man-hours.

(課題を解決するための手段〉 本発明は前記課題を解決するために、半導体基板の表面
に測定用誘電体パターンを含む所定パターンの誘電体層
を形成する工程と、前記測定用誘電体パターンを残し他
の前記誘電体層を除去する工程と、前記半導体基板及び
前記測定用誘電体パターンの露出表面に堆積層を成長さ
せる工程と、前記測定用誘電体パターン上の前記堆積層
にエツチングを施し、前記測定用誘電体パターンに達し
かつその測定用誘電体パターンの表面積より小さな開口
面積を有する開口部を形成する工程と、前記開口部内に
露出した前記測定用誘電体パターンにエツチングを施し
、前記開口部を前記半導体基板に到達させる工程と、前
記堆積層の表面に対する前記開口部の深さを表面段差計
により計測し、前記堆積層の膜厚を検出する固定とによ
り、半導体装置の膜厚測定を行なうようにしたものであ
る。
(Means for Solving the Problems) In order to solve the above problems, the present invention provides a step of forming a dielectric layer of a predetermined pattern including a dielectric pattern for measurement on the surface of a semiconductor substrate, and removing the remaining dielectric layer, growing a deposited layer on exposed surfaces of the semiconductor substrate and the measurement dielectric pattern, and etching the deposited layer on the measurement dielectric pattern. forming an opening that reaches the measurement dielectric pattern and has an opening area smaller than the surface area of the measurement dielectric pattern; etching the measurement dielectric pattern exposed within the opening; A film of a semiconductor device is formed by making the opening reach the semiconductor substrate, measuring the depth of the opening with respect to the surface of the deposited layer using a surface level difference meter, and detecting the thickness of the deposited layer. It is designed to measure thickness.

(作用) 本発明によれば、以上のように半導体装置の膜厚測定方
法を構成したので、半導体基板上りこ測定用誘電体パタ
ーンを形成した後その上に堆積層を成長させ、堆積層と
測定用誘電体パターンに開口を形成することによって膜
厚測定部を形成し、その膜厚測定部を表面段差計で計測
することは、従来の測定方法におけるストライプ状の多
結晶シリコン層の形成及び研磨作業を不要ならしめ、膜
厚測定部を半導体装置製造用の本ウェハ上にその製造工
程に従って形成することを可能ならしめる。
(Function) According to the present invention, since the method for measuring the film thickness of a semiconductor device is configured as described above, after forming a dielectric pattern for measuring the thickness of a semiconductor substrate, a deposited layer is grown on the dielectric pattern. Forming a film thickness measurement part by forming an opening in a dielectric pattern for measurement and measuring the film thickness measurement part with a surface step meter is a method that can be used to form a striped polycrystalline silicon layer in the conventional measurement method. This eliminates the need for polishing work and makes it possible to form a film thickness measuring section on a wafer for manufacturing semiconductor devices according to the manufacturing process.

それ故、本ウェハ上に半導体装置と同一条件で膜厚測定
部を形成できるので、高精度な膜厚測定が可能となる。
Therefore, since the film thickness measurement section can be formed on the wafer under the same conditions as the semiconductor device, highly accurate film thickness measurement is possible.

また、前記膜厚測定部は本ウェハ上の素子形成領域以外
の箇所における形成を可能ならしめ、素子形成領域に悪
影響を及ぼすことはない。それ故、本ウェハを無駄にし
たり、本ウェハの処理能力の低下を来たすこともなくな
る。さらに、試料片を単独に製作することを不要ならし
め、膜厚測定を簡易化するように働く。
Further, the film thickness measurement section enables formation on the wafer at a location other than the element formation area, and does not adversely affect the element formation area. Therefore, there is no need to waste the wafer or reduce the throughput of the wafer. Furthermore, it serves to eliminate the need to manufacture a separate sample piece, thereby simplifying film thickness measurement.

従って、前記課題を解決することができる。Therefore, the above problem can be solved.

(実施例) 第1図(a)〜(f>は本発明の実施例における半導体
装置の膜厚測定方法を示す工程図である。
(Example) FIGS. 1(a) to 1(f) are process diagrams showing a method for measuring film thickness of a semiconductor device in an example of the present invention.

以下、図の順番に従い、バイポーラ形半導体装置の場合
について説明する。
The case of a bipolar semiconductor device will be described below in accordance with the order of the figures.

先ず第1図(a)において、P形の単結晶シリコンから
成る半導体基板21−の全表面にシリコン酸化膜から成
る誘電体層22を形成する。ここに、半導体基板21は
バイポーラ形半導体装置を形成するための本ウェハであ
り、例えば図中Bで示す領域はバイポーラ素子形成領域
である。また、図中Gで示す領域は、バイポーラ素子形
成領域外のグリッドライン領域である。
First, in FIG. 1(a), a dielectric layer 22 made of a silicon oxide film is formed on the entire surface of a semiconductor substrate 21- made of P-type single crystal silicon. Here, the semiconductor substrate 21 is a main wafer for forming a bipolar type semiconductor device, and for example, the area indicated by B in the figure is a bipolar element forming area. Furthermore, the region indicated by G in the figure is a grid line region outside the bipolar element forming region.

次いで第1図(b)に示すように、誘電体層22にパタ
ーニングを施し、バイポーラ素子形成領域Bに所定の素
子形成用パターンを形成する。その際使用するマスクに
膜厚測定用のパターンを形成しておき、素子形成用パタ
ーンの形成と同時に、グリッドライン領域Gに測定用誘
電体パターン(以下、単に測定用パターンという)23
を形成する。
Next, as shown in FIG. 1(b), the dielectric layer 22 is patterned to form a predetermined element formation pattern in the bipolar element formation region B. Then, as shown in FIG. A pattern for film thickness measurement is formed on the mask used at that time, and at the same time as the element formation pattern is formed, a dielectric pattern for measurement (hereinafter simply referred to as a measurement pattern) 23 is placed in the grid line area G.
form.

続いて第1図(C)に示す如く、埋込み層形成のために
半導体基板21露出面上にn形不純物添加の液体を塗布
し、例えばアンチモンシリカフィルムを形成する。その
後、この半導体基板2]に熱処理を施し、n形拡散領域
24を形成する。
Subsequently, as shown in FIG. 1C, a liquid doped with n-type impurities is applied onto the exposed surface of the semiconductor substrate 21 to form a buried layer, such as an antimony silica film. Thereafter, this semiconductor substrate 2] is subjected to heat treatment to form an n-type diffusion region 24.

次に第1図(d)の如く、測定用パターン23以外の誘
電体層22を除去した後、半導体基板21上にn形不純
物添加の単結晶シリコン層から成る堆積層25、即ちエ
ピタキシャル成長層を形成する。このとき、シリコン酸
化膜から成る測定用パターン2B上の堆積層25は、多
結晶シリコン層26となる。その際、多結晶シリコン層
26の表面付近には凹凸が生じる。
Next, as shown in FIG. 1(d), after removing the dielectric layer 22 other than the measurement pattern 23, a deposited layer 25 made of a single crystal silicon layer doped with n-type impurities, that is, an epitaxially grown layer, is formed on the semiconductor substrate 21. Form. At this time, the deposited layer 25 on the measurement pattern 2B made of a silicon oxide film becomes a polycrystalline silicon layer 26. At this time, irregularities occur near the surface of the polycrystalline silicon layer 26.

その後第1図(e)のように、多結晶シリコン層26上
に既知のホトリソグラフィ技術を用いてレジストパター
ンを形成し、そのレジストをマスクとして多結晶シリコ
ンM26にドライエツチングを施す。これにより、測定
用パターン23に達する開口部27を形成する。その際
、開口部27の開口面積は測定用パターン23の表面積
より小さくなるように設定し、開口部27が測定用パタ
ーン23の表面積内に収まる31:うにする。続いて、
開口部27内に露出した測定用パターン23に対してぶ
つ酸系溶液によるエツチングを施し、開口部27を半導
体基板21に到達せしめる。その後、例えば図示しない
接触型の表面段差計を用い、開口部27を含む堆積層2
5上を例えば矢印Cで示す方向に走査し、表面段差を計
測する。これにより後述の如く、堆積層25即ちエピタ
キシャル成長層の膜厚が測定される。
Thereafter, as shown in FIG. 1(e), a resist pattern is formed on the polycrystalline silicon layer 26 using a known photolithography technique, and the polycrystalline silicon M26 is dry-etched using the resist as a mask. As a result, an opening 27 reaching the measurement pattern 23 is formed. At this time, the opening area of the opening 27 is set to be smaller than the surface area of the measurement pattern 23, so that the opening 27 falls within the surface area of the measurement pattern 23. continue,
The measurement pattern 23 exposed in the opening 27 is etched using a fluoric acid solution, and the opening 27 is made to reach the semiconductor substrate 21 . Thereafter, the deposited layer 2 including the opening 27 is
5 is scanned, for example, in the direction shown by arrow C, and the surface level difference is measured. As a result, the thickness of the deposited layer 25, that is, the epitaxially grown layer, is measured as described later.

これ以降は第1図(f>に示すように、通常のバイポー
ラ型半導体装置の製造工程に準じて必要な処理を施す。
Thereafter, as shown in FIG. 1(f>), necessary processing is performed in accordance with the manufacturing process of a normal bipolar semiconductor device.

その際、開口部27及び測定用パターン23等はグリッ
ドライン領域Gに設けられているので、バイポーラ型半
導体装置の製造工程に何ら悪影響を与えることはない。
At this time, since the opening 27, the measurement pattern 23, etc. are provided in the grid line region G, there is no adverse effect on the manufacturing process of the bipolar semiconductor device.

次に、第3図を用いて前述の表面段差計によるエピタキ
シャル成長層の膜厚測定方法について詳細に説明する。
Next, a method for measuring the thickness of an epitaxially grown layer using the above-mentioned surface step meter will be described in detail with reference to FIG.

第3図は表面段差計から出力されたデータ例を示す出力
データ図である。
FIG. 3 is an output data diagram showing an example of data output from the surface level difference meter.

前述のように例えば表面段差計を第1図(e)の矢印C
方向に走査させた場合、表面段差計からは第3図に示す
ような出力データが得られる。即ち、開口部27周囲の
多結晶シリコン層26表面を走査させた場合には、その
凹凸に応じて出力データにも凹凸を生じるが、単結晶シ
リコン層の堆積層25表面を走査させた場合には、平坦
な出力データが得られる。それ故、凹凸頂部から開口部
27内底面までの深さHlと、堆積層25表面から凹凸
頂部までの高さH2を計測することにより、第3図に示
すように堆積層25即ちエピタキシャル成長層の膜厚T
が測定される。
As mentioned above, for example, the surface level difference meter can be
When scanning in this direction, output data as shown in FIG. 3 is obtained from the surface level difference meter. That is, when the surface of the polycrystalline silicon layer 26 around the opening 27 is scanned, the output data also has irregularities corresponding to the irregularities, but when the surface of the deposited layer 25 of the single crystal silicon layer is scanned, gives flat output data. Therefore, by measuring the depth Hl from the top of the unevenness to the inner bottom surface of the opening 27 and the height H2 from the surface of the deposited layer 25 to the top of the unevenness, it is possible to determine the depth of the deposited layer 25, that is, the epitaxially grown layer, as shown in FIG. Film thickness T
is measured.

゛以上のように、本実施例においては、半導体装置を形
成するための本ウェハ上に半導体装置製造工程に従って
測定用パターン23、堆積層25及び開口部27を形成
し、これらを利用してエピタキシャル成長層の膜厚Tを
計測することができる。
゛As described above, in this example, the measurement pattern 23, the deposited layer 25, and the opening 27 are formed on the main wafer for forming the semiconductor device according to the semiconductor device manufacturing process, and these are used to perform epitaxial growth. The thickness T of the layer can be measured.

それ故、実際に製造される半導体装置に対応したエピタ
キシャル成長層の膜厚Tを高精度かつ容易に測定できる
上に、本ウェハはそのまま半導体装置の製造に用いられ
るもので無駄を生じることがない。また、本ウェハとは
別個に測定用試料片を製作することが不要となるので、
試料片製作に係わる複雑な手間が省ける。しかも従来に
おけるような研磨作業等も不要となるので、作業性の向
上及び測定工数の大幅削減を図ることとができる。
Therefore, the film thickness T of the epitaxial growth layer corresponding to the semiconductor device actually manufactured can be easily measured with high precision, and the wafer can be used as is for manufacturing the semiconductor device, so there is no waste. In addition, since it is not necessary to manufacture a measurement sample piece separately from the wafer,
The complicated labor involved in preparing sample pieces can be eliminated. Moreover, polishing work and the like as in the conventional method are not required, so that workability can be improved and the number of measurement steps can be significantly reduced.

さらに、本ウェハをそのまま膜厚測定に用いることによ
り、エピタキシャル成長層の形成に係わる処理能力が向
上するという利点もある。
Furthermore, by using this wafer as it is for film thickness measurement, there is an advantage that the throughput associated with the formation of the epitaxial growth layer is improved.

なお、本発明は図示の実施例に限定されず、種々の変形
が可能であり、例えば次のような変形例が挙げられる。
Note that the present invention is not limited to the illustrated embodiment, and can be modified in various ways, such as the following modifications.

i) 第1図ではバイポーラ形半導体装置における膜厚
測定方法を示したが、ユニポーラ形半導体装置例えばM
OSトランジスタ等に対しても適用可能である。
i) Figure 1 shows a method for measuring film thickness in a bipolar semiconductor device;
It is also applicable to OS transistors and the like.

ii)  膜厚測定用の測定部を本ウェハのグリッドラ
イン領域Gに設けることとしたが、これに限らず半導体
素子の形成領域以外なら何処に設けてもよい。また、敢
えて本ウェハ上に設けず、別個の試料片を同様の方法で
製作、測定することも勿論可能である。
ii) Although the measuring section for film thickness measurement is provided in the grid line region G of the wafer, the present invention is not limited to this, and may be provided anywhere other than the semiconductor element formation region. Furthermore, it is of course possible to fabricate and measure a separate sample piece in a similar manner without intentionally providing it on the main wafer.

iii )  堆積層25はエピタキシャル成長層とし
たが、ある程度の膜厚を有するものであるならば、エピ
タキシャル成長層以外の膜厚測定に本発明の測定方法を
利用することができる。
iii) Although the deposited layer 25 is an epitaxially grown layer, the measuring method of the present invention can be used to measure the thickness of a layer other than an epitaxially grown layer as long as it has a certain thickness.

iv)  前記実施例で示した半導体基板21、誘電体
層22及び堆積層25等の材質は例示のもののみに限ら
ず、他の材質であっても本発明の適用が可能である。
iv) The materials of the semiconductor substrate 21, dielectric layer 22, deposited layer 25, etc. shown in the above embodiments are not limited to those illustrated, but the present invention can be applied to other materials as well.

(発明の効果) 以上詳細に説明したように本発明によれば、半導体基板
上に測定用誘電体パターンを形成した後堆積層を成長さ
せ、その堆積層及び測定用誘電体パターンに開口部を形
成し、堆積層表面に対する開口部の深さを表面段差計で
計測することによって堆積層の膜厚を測定する膜厚測定
方法としたので、前記測定用誘電体パターン、堆積層及
び開口部を半導体装置製造用の本ウェハ上にその製造工
程に従って形成することが可能となる。
(Effects of the Invention) As described above in detail, according to the present invention, after forming a dielectric pattern for measurement on a semiconductor substrate, a deposited layer is grown, and openings are formed in the deposited layer and the dielectric pattern for measurement. The thickness of the deposited layer is measured by measuring the depth of the opening with respect to the surface of the deposited layer using a surface step meter. It becomes possible to form the semiconductor device on the wafer for manufacturing the semiconductor device according to the manufacturing process.

それ故、実際の半導体装置に対応した堆積層の膜厚を高
精度かつ容易な手段で測定でき、しかも測定に用いられ
る本ウェハを無駄にすることがない。また、本ウェハと
は別の測定用試料片を製作する必要がなくなるので、試
料片製作に係わる工数の削減や作業性の向上が図れると
共に、半導体装置製造における処理能力の低下をも防止
することができる。従って、膜厚測定に係わる信頼性、
作業効率及び歩留りが著しく高められるという効果があ
る。
Therefore, the thickness of the deposited layer corresponding to an actual semiconductor device can be measured with high precision and with easy means, and the wafer used for the measurement is not wasted. Furthermore, since there is no need to manufacture a measurement sample piece separate from the wafer, it is possible to reduce the number of man-hours involved in sample piece manufacture and improve work efficiency, and also to prevent a decline in processing capacity in semiconductor device manufacturing. Can be done. Therefore, reliability related to film thickness measurement,
This has the effect of significantly increasing work efficiency and yield.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(f>は本発明の実施例における半導体
装置の膜厚測定方法を示す工程図、第2図(a)〜(e
)は従来の膜厚測定方法を示す工程図、及び第3図は第
1図(e)における膜厚測定方法を示す表面段差計の出
力データ図である。 21・・・・・・半導体基板、22・・・・・・誘電体
層、23・・・・・・測定用誘電体パターン、25・・
・・・・堆積層、27・・・・・・開口部。
FIGS. 1(a) to (f> are process diagrams showing a method for measuring film thickness of a semiconductor device in an embodiment of the present invention, and FIGS. 2(a) to (e)
) is a process diagram showing a conventional film thickness measuring method, and FIG. 3 is an output data diagram of a surface level difference meter showing the film thickness measuring method in FIG. 1(e). 21... Semiconductor substrate, 22... Dielectric layer, 23... Dielectric pattern for measurement, 25...
...Deposition layer, 27...Opening.

Claims (1)

【特許請求の範囲】 半導体基板の表面に測定用誘電体パターンを含む所定パ
ターンの誘電体層を形成する工程と、前記測定用誘電体
パターンを残し他の前記誘電体層を除去する工程と、 前記半導体基板及び前記測定用誘電体パターンの露出表
面に堆積層を成長させる工程と、 前記測定用誘電体パターン上の前記堆積層にエッチング
を施し、前記測定用誘電体パターンに達しかつその測定
用誘電体パターンの表面積より小さな開口面積を有する
開口部を形成する工程と、前記開口部内に露出した前記
測定用誘電体パターンにエッチングを施し、前記開口部
を前記半導体基板に到達させる工程と、 前記堆積層の表面に対する前記開口部の深さを表面段差
計により計測し、前記堆積層の膜厚を検出する工程とを
、 備えたことを特徴とする半導体装置の膜厚測定方法。
[Scope of Claims] A step of forming a dielectric layer of a predetermined pattern including a dielectric pattern for measurement on the surface of a semiconductor substrate, and a step of removing the other dielectric layer while leaving the dielectric pattern for measurement. growing a deposited layer on the exposed surfaces of the semiconductor substrate and the measurement dielectric pattern; etching the deposited layer on the measurement dielectric pattern to reach the measurement dielectric pattern and the measurement dielectric pattern; forming an opening having an opening area smaller than the surface area of the dielectric pattern; etching the measurement dielectric pattern exposed within the opening to cause the opening to reach the semiconductor substrate; A method for measuring film thickness of a semiconductor device, comprising: measuring the depth of the opening with respect to the surface of the deposited layer using a surface step meter, and detecting the thickness of the deposited layer.
JP2688389A 1989-02-06 1989-02-06 Measurement of film thickness of semiconductor device Pending JPH02206146A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2688389A JPH02206146A (en) 1989-02-06 1989-02-06 Measurement of film thickness of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2688389A JPH02206146A (en) 1989-02-06 1989-02-06 Measurement of film thickness of semiconductor device

Publications (1)

Publication Number Publication Date
JPH02206146A true JPH02206146A (en) 1990-08-15

Family

ID=12205677

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2688389A Pending JPH02206146A (en) 1989-02-06 1989-02-06 Measurement of film thickness of semiconductor device

Country Status (1)

Country Link
JP (1) JPH02206146A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6010914A (en) * 1996-10-28 2000-01-04 Nec Corporation Method for manufacturing a semiconductor device
US6521470B1 (en) * 2001-10-31 2003-02-18 United Microelectronics Corp. Method of measuring thickness of epitaxial layer
EP1739056A2 (en) * 2005-06-29 2007-01-03 Honeywell International, Inc. Systems and methods for direct silicon epitaxy thickness measuring

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6010914A (en) * 1996-10-28 2000-01-04 Nec Corporation Method for manufacturing a semiconductor device
US6521470B1 (en) * 2001-10-31 2003-02-18 United Microelectronics Corp. Method of measuring thickness of epitaxial layer
EP1739056A2 (en) * 2005-06-29 2007-01-03 Honeywell International, Inc. Systems and methods for direct silicon epitaxy thickness measuring
EP1739056A3 (en) * 2005-06-29 2008-01-23 Honeywell International, Inc. Systems and methods for direct silicon epitaxy thickness measuring

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