JPH0269925A - Manufacture of semiconductor element - Google Patents

Abstract

PURPOSE:To manufacture a semiconductor element in which its alignment can be automated by forming a sidewall made of silicon nitride at the end of a mask oxide formed with an oblique face of a first alignment mark, and the coating it with a thin Si film to form a step. CONSTITUTION:A wafer 11 in which its surface orientation is inclined at a predetermined angle from a plane (100) or (111) is thermally oxidized in a wet oxygen atmosphere, a mask oxide film 25 having, for example, 1mum of thickness is formed, the film 25 of a mark forming region 26 is removed by etching thereby to form an opening 27. Then, the surface of the exposed wafer 11 is covered with silicon oxide, and a thin pad oxide film 41 is formed of the film 25. Thereafter, the whole wafer 11 is covered with a silicon nitride layer 43, a sidewall 45 is formed, and the whole wafer 11 is coated with a thin silicon antimonide film 29. Subsequently, it is heat treated in a nonoxidative atmosphere like N2 to obtain a buried layer 47. A small amount of O2 is contained during heat treatment to form an oxide film 49 in a boundary between the film 29 and the wafer 11. Thus, the surface of the wafer 11 is formed with a step composed of oblique faces 51a, 51b.

Description

Detailed Description of the Invention (Industrial Field of Application) The present invention relates to a technology for manufacturing semiconductor devices, and in particular to the production of silicon wafers (photolithography after an epitaxial layer of a desired material has been grown). It relates to auto-alignment technology that facilitates photomask alignment during the process.

(Prior Art) Conventionally, in order to manufacture various semiconductor devices, the photolithography process has been widely used.As is well known, in the photolithography process, a predetermined amount of The process of forming resist patterns has become important.

Among the above processes, positioning when overlapping the wafer and photomask is the most important, and the so-called
Various proposals have been made as alignment techniques. This alignment technology optically reads the alignment marks between the alignment marks defined on the wafer side and the alignment marks defined on the photomask side.
Automation is progressing.

First, FIG. 3 is a schematic plan view showing a wafer on which alignment marks are formed. Usually, wafer 11 has 2
At least three alignment marks are formed in the area indicated by the symbol a (thereby, the accuracy of wafer positioning is improved).

Next, an example of the above-mentioned alignment mark will be explained with reference to FIGS. 4(A) and 4(B).

FIG. 4(A) is an explanatory diagram showing the above-mentioned region of the wafer 11 in an enlarged manner.

The illustrated alignment mark 13 is a chevron (Chevron).
It consists of a (vron) type pattern 13a and striped patterns +3b and 13c formed parallel to the straight line portions forming the pattern 13a. The alignment mark 13 formed on the wafer 11 side is usually
It is defined by forming a step with a height of about 0.2 (urn) on the surface of the wafer 11 (described in detail later).

To explain the dimensions of the alignment mark 13 by giving an example, the patterns 13a to 13c are all 5 to 5.
20 (L1171), and the Ni distance between the chevron pattern 13a and the stripe pattern +3b or 13c is about 50 to 150 (um). be.

On the other hand, FIG. 4(B) schematically shows an example of an alignment mark defined on a photomask in a plan view. The alignment mark 17 of the photomask 15 is composed of slit-like patterns 17a and +7b, and each pattern has two lines each having a width of about 2 to 3 (un). The distance between these two lines is generally set to match one width of the alignment mark/713 of the wafer.

Next, referring to FIGS. 5(A) and 5(B), the above-mentioned wafer +111! The alignment performed using the alignment mark 13 on the photomask 15 side and the alignment mark 17 on the photomask 15 side will be briefly explained.

FIG. 5(8) is a plan view perspectively showing the state in which the wafer 11 and the photomask 15 are overlapped, and FIG. This is an explanatory diagram showing a schematic cross-section of the portion indicated by .

First, the principle of alignment will be explained with reference to FIG. 5(A)V.

In conventional alignment, after the wafer 11 and the photomask 15 are overlapped, illumination is applied from the photomask 15 side. This illumination is scanned over the plane shown in FIG. 5(A), and the reflected light from the alignment marks 13 and 17 is detected, for example, along the dashed line. By this reflected light, the distance between the alignment marks shown as d or d2 is adjusted to the same value (the distance between the wafer 11 and the photomask 15 is adjusted).

Such positioning is performed using the chevron pattern 13a.
, using the striped pattern 13b and the slit pattern 17a, and then the chevron pattern 1
The process is repeated using the 3a2 stripe pattern 13c and the slit pattern +7bW. Therefore, by using the pair of alignment marks 13 and 17, the wafer 11 and the photomask 15 can be aligned two-dimensionally.

Next, with reference to FIG. 5(B), alignment actually performed during the manufacturing process of a semiconductor device will be explained. In the figure, hatching indicating a cross section is partially omitted. As is well known, alignment is performed by sequentially depositing a resist material on the surface of the wafer corresponding to the base (for example, a component to be patterned, such as an epitaxial layer), and then overlapping a photomask. Therefore, in addition to the wafer 11 and photomask 15 described in FIG. 5(A), the epitaxial layer 1 is also shown in FIG.
9 and resist material 21 are shown in the figure.

As described with reference to FIG. 5(A), alignment is performed by optically detecting the distance between alignment mark 13 and alignment mark 17. Therefore, in the actual manufacturing process, the epitaxial layer 19 and the resist material 2
When alignment is performed on the wafer 11 to which the wafer 1 is attached, instead of the alignment mark 13 formed on the surface of the wafer 11, an alignment mark 23 is formed by transferring the mark 13 onto the surface of the epitaxial layer 19.
This is done by detecting. Hereinafter, in order to facilitate understanding of the explanation, the alignment mark formed on the surface of the wafer 11 will be referred to as the first alignment mark 13, and the surface of the epitaxial layer 19 (this transferred mark will be referred to as the second alignment mark 23). .

Next, Fig. 6 (A) to (E) I? In the following, a technique for manufacturing semiconductor devices by forming the first alignment mark 13 on the surface of the wafer 11 will be described in detail. In the following description, a manufacturing process for manufacturing a bipolar transistor using a wafer made of p-type silicon will be exemplified.

FIGS. 6(A) to 6(F) are explanatory diagrams showing each manufacturing process through a schematic wafer cross section, with only the portion corresponding to the cross section of the alignment mark explained with reference to FIG. 5(B) enlarged. It is. In the figure, hatching indicating a cross section is partially omitted.

First of all, if the plane orientation of the surface is (100) or (III
) Wafer 1 tilted several degrees from one of the crystal planes
11F! ,prepare. The use of a wafer with such a crystal plane is, for example, as disclosed in Japanese Patent Application No. 4,517,084, when an oxide film is grown on a silicon surface, the surface that is generated at the interface with the oxide film is used. This is to reduce the distribution density of defects. In addition, for other purposes of utilizing such crystal planes, Document II: ``Silicon Crystals and Doping'' (p. 87, published by Maruhata, June 1986) describes the use of an epitaxial layer on the surface of a wafer. It has been disclosed that it is possible to reduce deviations and misalignments when grown.

Such a wafer 11 is thermally oxidized in a wet oxygen atmosphere at a temperature of +040 ('C) for about 3 hours to form a mask oxide film 2578 of about 1 (μm). Thereafter, the mask oxide film 25 deposited on the region 26 where the alignment mark is to be formed is etched away to form an opening 27 (FIG. 6A) using a conventionally well-known photolithography technique.

Next, by a spin code method, an antimony silica thin film 29 of about 0.2 to 0.0
．． A predetermined film thickness within the range of 3 (um) is applied and formed, and the sixth
The state shown in Figure (B) is obtained.

Here, the antimony silica thin film 29 described above is a silicon oxide coating solution containing antimony (Sb)I as an n-type impurity, and an example thereof is rSb-20.
220J (manufactured by Tokyo Ohka, trade name) was used.

After the antimony silica thin film 29 is coated and formed in this manner, heat treatment is performed for 4 hours at a temperature of about 1250 (° C.) in a non-oxidizing atmosphere such as nitrogen (N2) using a diffusion furnace. Through such heat treatment, antimony (Sb) is diffused into the wafer 11 through the aforementioned opening 27, and the depth is approximately 5 (un) and the layer resistance is approximately 20 (Ω).
A buried layer 31 is formed. In addition, in the atmosphere in which this heat treatment is performed (by containing a small amount of oxygen, the mask oxide film 25 described above grows again, and
An oxide film 33 is formed at the interface between the antimony silica thin film 29 and the wafer 11 (FIG. 6(C)).

Note that the above-described formation of the oxide film 33 may be performed as a separate process after the heat treatment for diffusion of antimony is performed.

Here, the growth of the above-mentioned mask oxide film 25 and oxide film 33 will be explained.

As is well known in the art, the growth rate of silicon oxide on the surface portion of the wafer where the buried layer 29 in which antimony is diffused is formed is faster than on the surface portion of the wafer where the mask oxide film 25 is deposited. is large. Because of this, the buried layer 2
A height of about 0.2
(um) level difference will occur. Further, oxidation of the wafer proceeds by isotropic diffusion through the aforementioned opening 27 (see FIG. 6(A)). Therefore, the slopes 35a and 35b forming the above-mentioned step are formed line-symmetrically with an inclination of about 3 to 10 degrees with respect to the original wafer surface (the above-mentioned crystal plane).

After forming such a step, the mask oxide film 25, oxide film 33, and antimony silica thin film 29 formed on the wafer surface are removed using, for example, a hydrofluoric acid-based etchant, as shown in FIG. 6(D). A first alignment mark 13 like this is obtained.

Subsequently, as shown in FIG. 6(E), the entire surface of the wafer 11 described above contains n-type impurities and has a specific resistance of about 2 (Ω-
The epitaxial layer 19 is grown to a thickness of about 10 mm (cm). As can be understood from this figure, the surface of the epitaxial layer 19 has a slope 37a and a slope 37 corresponding to the step of the first alignment mark 13 described above.
The step formed by b is transferred and formed, and the second alignment mask 23 is obtained.

Subsequently, after forming an isolation oxide film 39 for separating the elements according to the design of the semiconductor element, a resist material 2 is formed.
1 is coated to form a state as shown in FIG. 6(F). Here, the oxidation for forming the isolation oxide film 39 proceeds by isotropic diffusion as described above. Therefore, the shape of the second alignment mark 23 described with reference to FIG. 6(E) u is preserved even on the surface of the isolation oxide film 39.

After such a process, the alignment explained with reference to FIGS. 5(A) and 5(B) is performed using the second alignment mark 23 mentioned above, and various manufacturing processes according to the design of the device are carried out. After that, semiconductor devices are manufactured.

In addition, in the above-mentioned manufacturing technology, in order to manufacture a bipolar transistor, a silica thin film containing antimony is used for the purpose of forming a buried layer in an element region (not shown).
The case where the buried layer 31 is formed has been described. However, if it is not necessary to form such a buried layer 31, a silicon oxide coating solution may be used instead of the antimony silica thin film described with reference to FIG. 6(C), and a silica thin film may be formed. Even if the oxide film 33 is grown in
A first alignment mark 13 can be formed.

(Problem to be Solved by the Invention) As can be understood from the above explanation, in the conventional method for manufacturing semiconductor devices, the first alignment mark 13 is formed on a wafer. After that, when an epitaxial layer 19 is grown on the surface of this wafer, a second alignment mark 23 is transferred and formed on the surface of the layer.
Alignment is performed by detecting the

However, in order to reduce planar defects and sag/shift during epitaxial growth, the crystal plane of the underlying wafer is tilted, so the slope forming the second alignment mark and the first alignment mark are There was a problem in that the arrangement relationship with the constituent slopes did not match, making it difficult to perform alignment accurately.

Regarding this inconsistency in slope shape during epitaxial growth, see, for example, Document III: "5solid 5tate".
tech-nolo9y (Solid State Technology) (by S. P. Weeks, pp. 66-67, published January 1982 (
It is believed that facet growth occurs depending on the composition of the gas used for growth, temperature, or other conditions.

Briefly speaking, conventional alignment mark formation is performed using differences in the growth rate of oxide films. Therefore, the oxide film for forming the first alignment mark (the oxide film 33 shown in FIG. 6(C)) is formed by isotropic diffusion of oxygen to the underside of the mask oxide film.
For example, there was a problem in that only a gentle slope of about 3 to 106 degrees could be formed.

Therefore, since it is difficult to form a steep slope, the second alignment mark becomes unclear due to deviations and deviations accompanying epitaxial growth, and there are cases where alignment cannot be performed automatically.

In view of the above-mentioned conventional problems, an object of the present invention is to provide a technology that can clearly form a second alignment mark transferred to an epitaxial layer, thereby making it possible to automate alignment of semiconductors. The objective is to realize a method for manufacturing elements.

(Means for Solving the Problems) In order to achieve this object, the method for manufacturing a semiconductor device of the present invention includes a step of forming a first alignment mark on a base, and forming an epitaxial layer on the surface of the base. and a step of performing alignment using the first alignment mark described above or a second alignment mark transferred onto the surface of this epitaxial layer. Formation of the alignment mark is performed by forming a mask oxide film outside the area where the alignment mark is to be formed on the surface of the base mentioned above, and forming a pad oxide film which is thinner than the mask oxide film in this planned area, as described above. depositing a silicon nitride layer on top of the mask oxide film and the pad oxide film; forming a sidewall on the mask oxide film by anisotropically etching the silicon nitride layer; After etching and removing the pad oxide film described above using the sidewall as a mask, a step of applying and forming a silica thin film was performed, and a step of heat-treating the base on which the above-mentioned silica thin film was formed to form an oxide film. It is characterized by doing.

(Function) According to the method for manufacturing a semiconductor device of the present invention, a sidewall made of silicon nitride is formed at the end of the mask oxide film where the slope related to the first alignment mark is formed, and then a silica thin film is applied. The structure is such that the steps are formed by using the steps. For this reason, when forming the oxide film to form the first alignment mark mentioned above, the above-mentioned sidewall acts as an oxidation mask, and oxidation is performed in the wafer extending direction, compared to oxidation in the wafer thickness direction. Oxidation is suppressed.

Therefore, the slope constituting the first alignment mark can be formed steeply.

(Embodiments) Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. Note that in order to facilitate understanding of the following description, specific conditions will be illustrated and explained, but it should be understood that the present invention is not limited only to these illustrative conditions and illustrated examples.

FIGS. 1(A) to (I) are explanatory diagrams showing each manufacturing process by a schematic cross section of a substrate, similar to FIGS. 6(A) to (F), in order to explain the present invention in detail. . In the embodiments described below, the steps for manufacturing a bipolar transistor using a wafer made of p-type silicon will be exemplified and explained similarly to the prior art described above. Further, in these figures, components having the same functions as those already described are indicated by the same reference numerals, and hatching representing a cross section is partially omitted.

First of all, as in the conventional case, the surface orientation is (100
) or (Nl) is prepared. Thereafter, this wafer 11 is subjected to thermal oxidation treatment at a temperature of 1040 ('C) for about 3 hours in a wet oxygen atmosphere to form a mask oxide film 25 with a thickness of about 1 (um).
Form wo. Thereafter, the mask oxide film 25 in the region 26 where the alignment mark is to be formed is etched away in the same manner as in the conventional method using well-known photolithography technology to form an opening 27 (FIG. 1(A)).

Next, the surface of the wafer 110 exposed by forming the above-described opening 27 is coated with, for example, chemical vapor deposition (CVD).
Chemical Vapor Deposition
) or other techniques to deposit silicon oxide to a thickness smaller than that of the mask oxide film 25, e.g.
A pad oxide film 41 having a thickness of approximately 0.05 (urn) is formed (FIG. 1(B)).

From the formation of the mask oxide film 25 described above to the formation of the pad oxide film 4.
1, after removing the mask oxide film 25 and exposing a part of the wafer 11,
The figure shows a case in which a pad oxide film 41 is separately deposited. However, instead of such a process, in the etching process for forming the opening, the mask oxide film 2 is
The silicon oxide constituting 5.
It is also possible to stop etching and use it as a pad oxide film by leaving as much as 5 (um) thick.

Next, for example, C is applied to the entire surface of the wafer 11 in the above-described state.
A silicon nitride layer 43 having a film thickness of approximately 0.2 (un) is deposited using a deposition technique such as vD that provides excellent step coverage (FIG. 1(C)).

Subsequently, for example, carbon tetrafluoride (CF4)% etching gas or active ion etching (RIE: R
The silicon nitride layer 43 described above is etched by an anisotropic etching process such as an active inn etching method. As a result of this anisotropic etching process, the above-mentioned silicon nitride remains only on the upper side of the pad oxide film 41 and forms a sidewall 45 with two openings, resulting in the state shown in FIG. 1(D). can get.

Next, after the sidewall 45 is formed, the exposed pad oxide film 41 is removed by etching using the hydrofluoric acid etchant described above. After that, as before, a silicon oxide coating solution RSB-20220 J containing antimony (Sb) @ as an n-type impurity was applied.
(manufactured by Tokyo Ohka ■, trade name), apply an antimony silica thin film 29 to the entire surface of the wafer in the above-mentioned state with a predetermined film thickness within the range of approximately 0.2 to 0.3 (μm) by a spin code method. (Fig. 1(E)).

Subsequently, heat treatment is performed for 4 hours using a diffusion furnace in a non-oxidizing atmosphere such as nitrogen (N2) at a temperature of about 1250 CG) to form a layer with a resistivity of about 5 (un). A buried layer 47 of 20 (Ω/hole) is formed. Also,
As in the conventional method, the above-mentioned mask oxide film 25 is regrown by performing a heat treatment in which a small amount of oxygen is contained in the atmosphere for this heat treatment, or by separately performing a heat treatment in an oxidizing atmosphere. Antimony silica thin film 2
An oxide film 49 is formed at the interface between wafer 9 and wafer 11 .

By forming this oxide film 49, a step consisting of slopes 51a and 5To is created on the surface of the wafer 11 in contact with the antimony silica thin film 29 (FIG. 1(F)).

Here, with reference to FIG. 2, the formation of the above-mentioned oxide film 49 will be explained in detail.

Figure 2 shows the wafers in the state shown in Figure 1 (CF).
It is an explanatory view showing a portion shown as a slope 51a in an enlarged and schematic cross section. Note that, in order to facilitate understanding of the illustration, hatching indicating a cross section is omitted.

As can be understood from this figure, a feature of the method according to the present invention is that the sidewall 45 made of silicon nitride
An oxide film 49 is formed in the state in which the oxide film 49 is formed. Therefore, diffusion in the thickness direction of the wafer proceeds as in the conventional case, and in the extending direction of the wafer, the silicon nitride forming the sidewall 45 blocks oxygen diffusion.

In the process according to this embodiment, it is possible to form a step with a height of about 0.2 (um), and the slope 51 forming the step can be formed.
The angle e formed by a and 51b and the original wafer surface is within the range of approximately 20 to 30 degrees, and these two
The two slopes were formed line-symmetrically.

After the process described above with reference to FIG. 1 (CF) and FIG. The sidewall 45 and oxide film 49 are removed, and a first alignment mark 53 is formed on the surface of the wafer 11 corresponding to the base, as shown in FIG. 1CG).

Subsequently, as in the prior art, an epitaxial layer 19 containing n-type impurities and having a specific resistance of about 2 (Ω-cm) is grown to a thickness of about 10 (un) over the entire surface of the wafer 11 described above. In this epitaxial growth, a second alignment mark 57 formed by a slope 55a and a slope 55b corresponds to the step of the first alignment mark 53 described above.
is transferred (Fig. 1 (H)).

Here, the shape of the second alignment mark 57 mentioned above and the conditions for epitaxial growth will be explained.

As already explained, the crystal plane of the wafer 11 is (+00
) plane or the (111) plane, the slope shape constituting the second alignment mark and the slope shape constituting the first alignment mark are made invincible. . In this example,
In growing the epitaxial layer 19, 5IH2
This was carried out using an atmospheric pressure barrel type epitaxial apparatus at a temperature of about 1150 (°C) using C (12) as a reaction gas. In this way, under the general conditions conventionally used, the second alignment mark 57 After forming the slopes, the slopes of the slopes 55a and 55b were measured.As a result, one slope (
For example, the illustrated slope 55b) has approximately 2
(On the other hand, the other slope (the illustrated slope 55a) showed an inclination of about 15 to 256 degrees.As can be understood from this explanation, the method according to this example , we were able to improve the inclination of the slope compared to the conventional method.

Next, in the same way as explained with reference to FIG. 6(F)a,
After forming an isolation oxide film 39 for isolating the elements, a resist material 21 is applied and formed (FIG. 1(1)).

When the above-mentioned alignment was performed in this state, the slope 55a constituting the second alignment mark 57
Since the inclinations of and 55b have sufficient values as described above, it was possible to easily detect the alignment mark.

Furthermore, in the alignment using the second alignment mark 57 according to the method of the above-described embodiment, even if dirt adheres after the growth of the epitaxial layer 19, the detection signal related to the dirt and the alignment It was easy to distinguish it from detection signals related to marks.

Therefore, by applying the above-mentioned technique, it becomes easy to achieve automation of alignment.

The preferred embodiments of this invention have been described in detail above.
It is clear that the invention is not limited only to the preferred embodiments described above.

For example, in the above-described embodiments, the case where a wafer made of n-type silicon was used was described in detail, but similar effects can be obtained even when semiconductor elements are manufactured using n-type silicon.

Furthermore, in the above-described embodiments, the case where alignment was performed using the second alignment mark transferred to the surface of the epitaxial layer was explained. However, according to the method according to the present invention, it is possible to obtain a sufficient height of the first alignment mark using the sidewall, so that not only the second alignment mark obtained by transferring the mark but also , even alignment after the third alignment mark has been transferred and formed can be expected to be automated.

Generally, in the description of the embodiments, the planar shape of the alignment mark has been omitted, but it is clear that the method of the present invention is not effective only with alignment marks having a specific planar shape.

In addition, in the above embodiment, in order to form the buried layer of the bipolar transistor, a silicon oxide coating solution containing antimony as an impurity is applied, an antimony silica thin film is formed, and the oxide film 49 is grown. I explained the case.

However, as described above, depending on the design of the semiconductor element, if it is not necessary to form a buried layer, a silica thin film containing no impurities may be formed to form the first alignment mark.

It is clear that these materials, shapes, numerical conditions, arrangement relationships, and other conditions may be subjected to any suitable design changes and modifications within the scope of the purpose of the present invention.

(Effects of the Invention) As is clear from the above description, according to the method of manufacturing a semiconductor device of the present invention, silicon nitride is formed on the edge of the mask oxide film where the slope related to the first alignment mark is formed. After forming a side wall, a thin silica film is applied to form a step. Therefore, when forming the oxide film to form the first alignment mark mentioned above, the side wall mentioned above acts as an oxidation mask, and oxidation is performed in the direction of wafer extension rather than oxidation in the thickness direction of the wafer. It is possible to suppress the oxidation of

Therefore, the slope constituting the first alignment mark can be formed steeply, and even if misalignment or misalignment occurs during epitaxial growth, the second alignment mark can be clearly formed. Therefore, by providing a technique that can clearly form the second alignment mark transferred to the epitaxial layer, it is possible to realize a method of manufacturing a semiconductor device that can automate alignment.

[Brief explanation of the drawing]

FIGS. 1(C) to (I) are explanatory diagrams showing schematic cross sections for each manufacturing process in order to explain the present invention in detail. FIG. In order to explain the formation process of the alignment mark, an explanatory diagram showing a cross section of the main part. Fig. 3, Fig. 4 (△), and Fig. 4 (B) are schematic diagrams of the main part in order to explain the conventional alignment mark. FIGS. 5(A) and 5(B) are explanatory diagrams schematically shown using planes of main parts or cross-sections of main parts, respectively, in order to explain the alignment. F) is an explanatory diagram similar to FIGS. 1(A) to (I) for explaining the conventional manufacturing method. 11...Wafer (base) 53...First alignment mark 13a.
...Chevron pattern 13b, 13c...
・Stripe pattern 15...Photomask 17...Alignment mark (photomask side) 17
a17b... Slit pattern 19... Epitaxial layer, 21... Resist material υ, 57...
... Second alignment mark 25 ... Mask oxide film 26 ... Alignment mark formation area 27 ...
...Aperture, 29... (antimony) silica thin film 31
47...Buried layer, 33.49...Oxide film 3
5a, 35b, 51a, 51b...Slope (component forming the first alignment mark) 37a, 37b, 55a, 55b...Slope (component forming the second alignment mark) 39. ...Isolation oxide film, 41...Pad oxide film 43...Silicon nitride layer, 45...Side wall a...Area portions d+, d2 for forming alignment marks... ... Distance θ between alignment marks
...Angle between the slope and the wafer surface.

Claims (1)

[Claims] (1) A step of forming a first alignment mark on a base, a step of forming an epitaxial layer on the surface of the base, and a second alignment in which the first alignment mark is transferred to the surface of the epitaxial layer. In manufacturing a semiconductor device through a step of performing alignment using a mark, the first alignment mark is formed by forming a mask oxide film on the surface of the base outside the area where the alignment mark is planned to be formed, and applying the mask oxide film to the area where the alignment mark is planned to be formed on the surface of the base. forming a pad oxide film thinner than the mask oxide film; depositing a silicon nitride layer over the mask oxide film and the pad oxide film; anisotropically etching the silicon nitride layer; forming a sidewall on a mask oxide film; using the sidewall as a mask to remove the pad oxide film by etching, and then applying and forming a silica thin film; and heating the base on which the silica thin film is formed. . A method for manufacturing a semiconductor device, the method comprising: forming an oxide film.