JPS63300526A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS63300526A
JPS63300526A JP13682287A JP13682287A JPS63300526A JP S63300526 A JPS63300526 A JP S63300526A JP 13682287 A JP13682287 A JP 13682287A JP 13682287 A JP13682287 A JP 13682287A JP S63300526 A JPS63300526 A JP S63300526A
Authority
JP
Japan
Prior art keywords
film
semiconductor
oxide film
oxidation
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13682287A
Other languages
Japanese (ja)
Inventor
Shigeki Kayama
加山 茂樹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP13682287A priority Critical patent/JPS63300526A/en
Publication of JPS63300526A publication Critical patent/JPS63300526A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To eliminate the etching of a substrate and to prevent the characteristics of a semiconductor device from being deteriorated by relatively increasing the etching selection ratio of a second semiconductor oxide film to a first anti-oxide film to form a semiconductor layer between a first semiconductor oxide film and the first anti-oxide film on the substrate. CONSTITUTION:A thin first semiconductor oxide film 2, a semiconductor layer 3, a first anti-oxide film 4 and a second semiconductor oxide film 5 are sequentially formed on a silicon substrate 1. A resist 12 is selectively formed thereon, the films 5, 4 are selectively etched by RIE in such a manner that the film 4 is effectively removed slightly by overetching. With the film 5 as a mask P-type impurity is ion implanted through the layer 3 and the film 2 into the substrate 1. Then, an etching remainder 9 is formed on a sidewall 8 by anisotropically etching by RIE the film 6 formed on its whole surface, and with the film 4 and the remainder 9 as masks the substrate 1 is selectively thermally etched to form a field SiO2 film 10.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関する。本発明は、例
えばVLSIなどの素子骨Ma域を形成する際に好適に
用いることができる。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device. INDUSTRIAL APPLICATION This invention can be used suitably, for example when forming element bone Ma regions, such as VLSI.

〔発明の概要〕[Summary of the invention]

本発明は、半導体基板上に第1の半導体酸化膜、半導体
層、第1の耐酸化膜および第2の半導体酸化膜を順次形
成し、該第2の半導体酸化膜と上記耐酸化膜を選択的に
エツチング除去し、上記第2の半導体酸化膜をマスクに
して上記半導体基板に不純物を導入し、全面に第2の耐
酸化膜を形成し、該第2の耐酸化膜を異方性エツチング
して側壁部分にエツチング残りを形成し、上記第2の半
導体酸化膜を除去し、上記耐酸化膜をマスクにして上記
基板を選択的に酸化する方法により、半導体装置におい
て微細かつ良好な特性を備えた素子分離領域の形成を可
能ならしめたものである。
The present invention sequentially forms a first semiconductor oxide film, a semiconductor layer, a first oxidation-resistant film, and a second semiconductor oxide film on a semiconductor substrate, and selects the second semiconductor oxide film and the oxidation-resistant film. impurities are introduced into the semiconductor substrate using the second semiconductor oxide film as a mask, a second oxidation-resistant film is formed on the entire surface, and the second oxidation-resistant film is anisotropically etched. By forming an etching residue on the sidewall portion, removing the second semiconductor oxide film, and selectively oxidizing the substrate using the oxidation-resistant film as a mask, fine and good characteristics can be obtained in a semiconductor device. This makes it possible to form an element isolation region provided with the structure.

〔従来の技術〕[Conventional technology]

従来の半導体装置の製造方法、例えば半導体装置の素子
分離領域の形成方法には従来から行われているLOCO
3法などがあるが、バーズビークの発生により素子分離
領域の微細化が容易でない。
Conventional methods for manufacturing semiconductor devices, such as methods for forming element isolation regions in semiconductor devices, include LOCO, which has been conventionally performed.
Although there are three methods, miniaturization of the element isolation region is not easy due to the occurrence of bird's beaks.

第2図は従来の半導体装置の製造方法を示す半導体断面
図で、その(a)はシリコンナイトライド形成時の断面
図、(b)はサイドウオール形成時の断面図であるが、
同図(a)に示す如く、シリコン基板21上にSiO2
膜22+ Si3N4膜23(後述の場合にはさらにS
iO□膜24)を順次堆積させた後、素子分離を形成す
る領域のSi、N4膜23を(後述の場合はSiO□膜
24と共に)選択的に除去して行う通常のLOCOS法
の工程の間にシリコン・ナイトライド(SiJ4)を全
面にCVD して異方性エツチングする工程を入れるこ
とによって、第2図(b)の如く、凹部26の側壁27
部分にサイド・ウオール26′を形成し、バーズビーク
の発生を抑制して素子分離領域の微細化を図ることが行
われている。
FIG. 2 is a semiconductor cross-sectional view showing a conventional method for manufacturing a semiconductor device, in which (a) is a cross-sectional view when silicon nitride is formed, and (b) is a cross-sectional view when sidewalls are formed.
As shown in the same figure (a), SiO2 is placed on the silicon substrate 21
Film 22 + Si3N4 film 23 (in the case described later, S
After sequentially depositing the iO□ film 24), the Si and N4 films 23 in the region where element isolation is to be formed are selectively removed (along with the SiO□ film 24 in the case described later). By inserting a step in which silicon nitride (SiJ4) is deposited on the entire surface by CVD and anisotropically etched, the side wall 27 of the recess 26 is formed as shown in FIG. 2(b).
A side wall 26' is formed in the portion to suppress the occurrence of bird's beak and to miniaturize the element isolation region.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記のようにLOCOS法にシリコン・ナイトライド(
SiJ4)などでサイド・ウオール26′を形成して素
子分離領域を形成する従来の方法によると、第2図tb
)の如(、シリコン・ナイトライド(SiJa)をCV
D した後、RIBなどで全面エツチングする際にSi
ng膜22との間の選択比がとりにくいためシリコン基
板21までエツチングされて基板が露出する可能性があ
る。このようにRIHによって基板21を直接叩くと、
基板にダメージを与えて、デバイス特性が劣化するおそ
れがある。
As mentioned above, silicon nitride (
According to the conventional method of forming an element isolation region by forming a side wall 26' of SiJ4), etc.,
), CV of silicon nitride (SiJa)
After D, when etching the entire surface with RIB etc.
Since it is difficult to obtain a selectivity with respect to the NG film 22, there is a possibility that even the silicon substrate 21 is etched and the substrate is exposed. If you hit the board 21 directly with RIH like this,
There is a risk of damaging the substrate and deteriorating device characteristics.

また基板が露出すると、素子分離領域を形成する選択酸
化時にバーズビークが大きく入る可能性があり問題であ
る。
Furthermore, if the substrate is exposed, large bird's beaks may appear during selective oxidation to form element isolation regions, which is a problem.

また第2図山)に示す如(、シリコン・ナイトライド(
SisNa)のサイド・ウオール26′下の矢印Aで示
すSing膜22の膜厚が減少しているため、素子分離
領域を形成する選択酸化時にシリコン基板21とサイド
ウオール(st3N4) 26”とによってストレスが
かかり、結晶欠陥が生じることがあるという問題がある
Also, silicon nitride (
Since the film thickness of the Sing film 22 shown by arrow A below the side wall 26' of SisNa) is reduced, stress is caused by the silicon substrate 21 and the side wall (st3N4) 26'' during selective oxidation to form an element isolation region. There is a problem that crystal defects may occur.

さらに、素子分離領域を形成する場合、−aに素子分離
領域下の不純物濃度を増加させるためチャネル・ストッ
プ・イオンの注入が行われるが、イオン注入の加速電圧
が大きいとイオンが選択酸化マスク(例えば5i3N4
)を突き抜けて素子形成領域に達し、デバイス特性を変
動させるという問題がある。そこで第2図(a)に示す
如< 、5iJ4膜23上に5iOtrPA24などを
形成して素子形成領域上の膜厚を増加させることも考え
られる。しかし従来のLOCOS法にこれを適用しよう
とすると、5isNa膜23とSing膜24のRIH
によるエツチングの選択比が小さく、その下のSing
膜22と共にエツチングの選択比において同質であるた
めエツチングによる加工性が悪いという問題がある。
Furthermore, when forming an element isolation region, channel stop ions are implanted at -a to increase the impurity concentration under the element isolation region, but if the acceleration voltage of ion implantation is large, the ions will selectively oxidize ( For example 5i3N4
) and reach the element formation region, causing a problem of changing device characteristics. Therefore, as shown in FIG. 2(a), it is conceivable to form 5iOtrPA 24 on the 5iJ4 film 23 to increase the film thickness on the element formation region. However, when trying to apply this to the conventional LOCOS method, the RIH of the 5isNa film 23 and the Sing film 24
The selection ratio of etching is small, and the
Since the film 22 and the film 22 have the same etching selectivity, there is a problem that the etching processability is poor.

本発明は、上記問題点に鑑みて創作されたもので、本発
明の目的は、上記した従来の製造方法による素子骨NS
R域の形成から生ずる問題点を解決することが可能な半
導体装置の製造方法を提供することにある。
The present invention has been created in view of the above-mentioned problems, and an object of the present invention is to manufacture element bone NS by the above-described conventional manufacturing method.
It is an object of the present invention to provide a method for manufacturing a semiconductor device that can solve problems arising from the formation of the R region.

〔問題点を解決するための手段〕[Means for solving problems]

上記問題点を解決するため本発明は、半導体基板上に第
1の半導体酸化膜を形成する工程と、該半導体酸化膜上
に半導体層を形成する工程と、該半導体層上に第1の耐
酸化膜を形成する工程と、該耐酸化膜上に第2の半導体
酸化膜を形成する工程と、該第2の半導体酸化膜と上記
耐酸化膜を選択的にエツチング除去する工程と、上記第
2の半導体酸化膜をマスクにして上記半導体基板に不純
物を導入する工程と、全面に第2の耐酸化膜を形成する
工程と、該第2の耐酸化膜を異方性エツチングして側壁
部分にエツチング残りを形成する工程と、上記第2の半
導体酸化膜を除去する工程と、上記耐酸化膜をマスクに
して上記基板を選択的に酸化する工程とを備える方法を
とる。
In order to solve the above problems, the present invention includes a step of forming a first semiconductor oxide film on a semiconductor substrate, a step of forming a semiconductor layer on the semiconductor oxide film, and a step of forming a first acid-resistant film on the semiconductor layer. a step of forming a second semiconductor oxide film on the oxidation-resistant film; a step of selectively etching away the second semiconductor oxide film and the oxidation-resistant film; A step of introducing impurities into the semiconductor substrate using the second semiconductor oxide film as a mask, a step of forming a second oxidation resistant film on the entire surface, and anisotropic etching of the second oxidation resistant film to remove sidewall portions. A method is adopted which includes a step of forming an etching residue on the substrate, a step of removing the second semiconductor oxide film, and a step of selectively oxidizing the substrate using the oxidation-resistant film as a mask.

以下、本発明の半導体装置の製造方法を本発明を例示す
る第1図(a) (b) (c) (dl (e) (
f) (g)を参照して説明する。
Hereinafter, a method for manufacturing a semiconductor device according to the present invention will be described with reference to FIGS.
f) Explain with reference to (g).

本発明の半導体装置の製造方法は、素子分離領域の形成
にかかるLOCO3法を改良した本願と同一の出願人が
出願したPPL法(Poly Pad Locos法。
The method for manufacturing a semiconductor device of the present invention is the PPL method (Poly Pad Locos method), which is an improved version of the LOCO3 method for forming element isolation regions and was filed by the same applicant as the present application.

特願昭59− t9s3oitもとにさらに改良したも
のである。
This is a further improvement based on the patent application No. 59-T9S3OIT.

本発明の半導体装置の製造方法は、第1図(a)に示す
如く、例えばp型シリコンなどの半導体基板1上に第1
の半導体酸化膜(例えばSiO□)2を形成し、該半導
体酸化膜2上に半導体層(例えばポリシリコン)3を形
成し、該半導体層3上に第1の耐酸化膜(例えば5iJ
n)4を形成し、該耐酸化膜4上に第2の半導体酸化膜
(例えばSing) 5を形成し、その上にレジスト1
2を選択的に形成する。
As shown in FIG. 1(a), the method for manufacturing a semiconductor device according to the present invention includes a method for manufacturing a semiconductor device on a semiconductor substrate 1 made of, for example, p-type silicon.
A semiconductor oxide film (for example, SiO□) 2 is formed, a semiconductor layer (for example, polysilicon) 3 is formed on the semiconductor oxide film 2, and a first oxidation-resistant film (for example, 5iJ) is formed on the semiconductor layer 3.
n) 4 is formed, a second semiconductor oxide film (for example, Sing) 5 is formed on the oxidation-resistant film 4, and a resist 1 is formed on it.
2 is selectively formed.

第1図Ql+)に示す如く、該第2の半導体酸化膜5と
上記第1の耐酸化膜4を選択的にRIBなどでエツチン
グ除去し、上記第2の半導体酸化膜5をマスクにして上
記半導体基板1中に不純物(例えばホウ素B)7をイオ
ン・インプランチーシランなどを使ってイオン注入する
(図中の注入不純物を黒点・で表す)。
As shown in FIG. 1 (Ql+), the second semiconductor oxide film 5 and the first oxidation-resistant film 4 are selectively etched away using RIB or the like, and the second semiconductor oxide film 5 is used as a mask to remove the An impurity (for example, boron B) 7 is implanted into the semiconductor substrate 1 using ion implantation silane or the like (the implanted impurity is represented by a black dot in the figure).

次に第1図tc)に示す如(、全面に第2の耐酸化膜(
例えば5i3N4)6を形成し、第1図(d)に示す如
(、該第2の耐酸化膜6にRIBなどの異方性エツチン
グを行って側壁部分8にエツチング残り9を形成する。
Next, as shown in Fig. 1 (tc), a second oxidation-resistant film (
For example, 5i3N4) 6 is formed, and the second oxidation-resistant film 6 is subjected to anisotropic etching such as RIB to form etching residues 9 on the sidewall portions 8, as shown in FIG. 1(d).

これは第2の耐酸化膜6のエツチングがエツチング方向
から等速度で行われるため、膜厚が大である側壁部分に
エツチング残り(サイドウオールとも称される)が生じ
ることによる。
This is because the second oxidation-resistant film 6 is etched at a constant speed in the etching direction, so that etching remains (also called sidewalls) are left on the sidewall portions where the film is thick.

第1図(e)に示す如(、上記第2の半導体酸化膜6を
フン酸系の溶液などで除去する。
As shown in FIG. 1(e), the second semiconductor oxide film 6 is removed using a hydrochloric acid solution or the like.

第1図(f)に示す如く、上記第1の耐酸化膜4および
エツチング残り9をマスクにして上記基板lを選択的に
熱酸化を行うことによって半導体基板1にSin、膜1
0(フィールドSiO□膜とも称される)が形成される
As shown in FIG. 1(f), by selectively thermally oxidizing the substrate 1 using the first oxidation-resistant film 4 and the etching residue 9 as a mask, the semiconductor substrate 1 is coated with Sin and the film 1.
0 (also called field SiO□ film) is formed.

そして第1図(g)に示す如(、第1の半導体酸化膜、
半導体層3、第1の耐酸化膜4およびエツチング残り9
を適宜の手段で除去して(例えば酸化してエツチング除
去したり、フン酸溶液、リン酸溶液などを使う)素子分
m1911域を形成する。
As shown in FIG. 1(g), the first semiconductor oxide film,
Semiconductor layer 3, first oxidation resistant film 4 and etching residue 9
is removed by an appropriate means (for example, by oxidation and etching, or by using a hydrochloric acid solution, a phosphoric acid solution, etc.) to form an element region m1911.

なお半導体基板1中に注入された不純物7は、熱酸化の
際に電気的に活性化されると共に深さ方向にも拡散され
るので、5iOt膜10の下方にボロンイオンを使った
場合p′″型のチャネル・ストッパ11が形成される。
Note that the impurity 7 implanted into the semiconductor substrate 1 is electrically activated during thermal oxidation and is also diffused in the depth direction, so if boron ions are used below the 5iOt film 10, p''' type channel stopper 11 is formed.

第1の半導体酸化膜2の膜厚は、薄(形成することによ
ってバーズビークの発生を少なく抑えることができる。
The thickness of the first semiconductor oxide film 2 is thin (by forming the first semiconductor oxide film 2, the occurrence of bird's beak can be suppressed to a small level.

例えば50人程度の薄さに好ましく形成することができ
る。
For example, it can be preferably formed to be as thin as about 50 people.

第2の半導体酸化膜5の材質は、選択酸化前に第1の耐
酸化膜4との関係でエツチングの選択比がとれるもので
、かつイオン注入の際のマスクとなるものが望ましい。
The material of the second semiconductor oxide film 5 is desirably one that can maintain an etching selectivity in relation to the first oxidation-resistant film 4 before selective oxidation, and that can serve as a mask during ion implantation.

半導体層3は、第2の半導体酸化膜5と第1の耐酸化膜
4を選択的にエツチング除去する際に選択比がとれるス
トッパーの役割をはたすものが望ましい。例えばポリシ
リコンなどを好ましく用いることができる。
It is desirable that the semiconductor layer 3 serves as a stopper that can maintain a selectivity when selectively etching away the second semiconductor oxide film 5 and the first oxidation-resistant film 4. For example, polysilicon or the like can be preferably used.

〔作用〕[Effect]

上記したように、本発明は、半導体基板上の第1の半導
体酸化膜と、第1の耐酸化膜との間に半導体層を形成す
るため、第2の半導体酸化膜と第1の耐酸化膜を選択的
にエツチング除去する工程においてエツチングの選択比
を比較的大きくとることができ、このため、半導体基板
までエツチングして、基板を叩くことがな(なりデバイ
スの特性が劣化することを防止することができる。
As described above, in the present invention, in order to form a semiconductor layer between the first semiconductor oxide film and the first oxidation-resistant film on the semiconductor substrate, the second semiconductor oxide film and the first oxidation-resistant film In the process of selectively removing the film by etching, a relatively high etching selectivity can be achieved, which prevents the semiconductor substrate from being etched and hitting the substrate (which prevents deterioration of device characteristics. can do.

また第2の半導体酸化膜をマスクとして上記半導体基板
に不純物を選択的に導入することができるため、所望の
位置に確実に不純物が導入でき、所望のデバイス特性を
得ることができる。
Furthermore, since impurities can be selectively introduced into the semiconductor substrate using the second semiconductor oxide film as a mask, impurities can be reliably introduced into desired positions and desired device characteristics can be obtained.

また全面に第2の耐酸化膜を形成し、該第2の耐酸化膜
を異方性エツチングして側壁部分にエツチング残りを形
成することにより、例えば第1図(b)に示す素子分離
領域の幅Wがフォトリソグラフィの波長による限界の幅
であっても、第1図(dlに示す如く、エツチング残り
9(1つの幅をW゛とする)を形成することによってさ
らに内側に形成する素子分離領域の幅をW ′x 2の
幅だけ狭めることができるため、半導体装置の集積化を
高めることができる。
In addition, by forming a second oxidation-resistant film on the entire surface and anisotropically etching the second oxidation-resistant film to form etching residues on the sidewalls, for example, the element isolation region shown in FIG. 1(b) can be formed. Even if the width W is the limit width due to the wavelength of photolithography, as shown in FIG. Since the width of the isolation region can be reduced by the width W'x2, the integration of the semiconductor device can be increased.

〔実施例〕〔Example〕

以下、本発明の半導体装置の製造方法の一実施例を第1
図を参照しながら詳細に説明する。なお当然のことであ
るが、以下の実施例は本発明の一例を示すもので、本発
明はこの例にのみ限定されない。
Hereinafter, a first embodiment of the method for manufacturing a semiconductor device of the present invention will be described.
This will be explained in detail with reference to the drawings. It should be noted that, as a matter of course, the following example shows an example of the present invention, and the present invention is not limited only to this example.

第1図(a)〜(g)は本実施例の半導体装置の製造工
程を示す断面図である。
FIGS. 1(a) to 1(g) are cross-sectional views showing the manufacturing process of the semiconductor device of this embodiment.

本実施例では、第1図(alに示す如(、半導体基板l
にp型のシリコン基板を用い、基板表面を熱酸化して膜
厚50人の極めて薄い第1の半導体酸化膜(ここではS
iO□膜)2を形成し、さらに第1の半導体酸化膜2上
にそれぞれCVDによって膜厚500人の半導体層(こ
こではポリシリコン)3および膜厚1000人の第1の
耐酸化膜(ここでは5isNn) 4を形成し、該耐酸
化膜4上に第2の半導体酸化膜(ここではSing) 
5を例えば500人を形成する。
In this embodiment, as shown in FIG.
A p-type silicon substrate is used, and the substrate surface is thermally oxidized to form an extremely thin first semiconductor oxide film (here, S
A semiconductor layer (polysilicon in this case) 3 with a thickness of 500 and a first oxidation-resistant film (in this case with a thickness of 1000) are formed on the first semiconductor oxide film 2 by CVD. 5isNn) 4 is formed, and a second semiconductor oxide film (here Sing) is formed on the oxidation-resistant film 4.
5 to form, for example, 500 people.

そして半導体酸化膜5上にレジスト12を選択的に形成
する。
Then, a resist 12 is selectively formed on the semiconductor oxide film 5.

第1図(b)に示す如く、該第2の半導体酸化膜5と上
記第1の耐酸化膜4を選択的にRIBによりエツチング
除去する。この場合第゛1の耐酸化膜4はオーバーエツ
チング気味に確実に除去する。そして、上記第2の半導
体酸化膜5をマスクにして上記半導体基板l中にp型の
不純物として、例えばホウ素(B)7をイオン注入法を
用いて、半導体層3および第1の半導体酸化膜2を介し
て半導体基板1中にイオン注入する(図中の注入不純物
を黒点・で表す)。
As shown in FIG. 1(b), the second semiconductor oxide film 5 and the first oxidation-resistant film 4 are selectively etched away by RIB. In this case, the first oxidation-resistant film 4 is surely removed with a slight overetching. Then, using the second semiconductor oxide film 5 as a mask, a p-type impurity, such as boron (B) 7, is implanted into the semiconductor substrate l using an ion implantation method to form the semiconductor layer 3 and the first semiconductor oxide film. Ions are implanted into the semiconductor substrate 1 through 2 (injected impurities are represented by black dots in the figure).

次に第1図(01に示す如く、全面に第2の耐酸化膜(
ここでは5iaNe) 6を形成し、第1図(d)に示
す如く、該第2の耐酸化膜6にRIEの異方性エツチン
グを行い、側壁部分8にエツチング残り9を形成する。
Next, as shown in Figure 1 (01), a second oxidation-resistant film (
Here, 5iaNe) 6 is formed, and as shown in FIG. 1(d), the second oxidation-resistant film 6 is anisotropically etched by RIE to form etching residues 9 on the sidewall portions 8.

次に第1図(e)に示す如く、上記第2の半導体酸化膜
6をフッ酸溶液で除去する。
Next, as shown in FIG. 1(e), the second semiconductor oxide film 6 is removed using a hydrofluoric acid solution.

第1図(f)に示す如く、上記第1の耐酸化膜4および
エツチング残り9をマスクにして上記基板1を選択的に
熱酸化を行うことによって半導体基板1にSiO□膜1
0(フィールド5ift膜とも称される)が形成される
As shown in FIG. 1(f), by selectively thermally oxidizing the substrate 1 using the first oxidation-resistant film 4 and the etching residue 9 as a mask, a SiO□ film 1 is formed on the semiconductor substrate 1.
0 (also called field 5ift film) is formed.

そして第1図(g)に示す如(、第1の半導体酸化膜は
フッ酸溶液でウェットエツチングし、第1の耐酸化膜4
およびエツチング残り9はリン酸溶液でウェットエツチ
ングし、半導体層3は酸化してエツチングすることによ
って除去して素子分離領域を形成する。
Then, as shown in FIG. 1(g), the first semiconductor oxide film is wet-etched with a hydrofluoric acid solution, and the first oxidation-resistant film 4 is etched.
The etched residue 9 is wet-etched with a phosphoric acid solution, and the semiconductor layer 3 is oxidized and removed by etching to form an element isolation region.

本実施例の方法によって得られる素子分N領域は、エツ
チングの選択比の採れる層構成とすることによって、基
板をエツチングで叩くことがなくなり、安定したデバイ
スの特性が得られ、半導体基板に不純物を確実に所望の
位置に4入することができるため、所望のデバイス特性
を得ることができ、さらに素子分離領域の幅の微細化に
よって半導体装置の集積化を高めることができる。
The N regions obtained by the method of this example have a layer structure that allows for etching selectivity, so that the substrate is not hit by etching, stable device characteristics are obtained, and impurities are not introduced into the semiconductor substrate. Since it is possible to reliably insert the semiconductor device into a desired position, desired device characteristics can be obtained, and furthermore, by reducing the width of the element isolation region, it is possible to increase the integration of the semiconductor device.

〔発明の効果〕〔Effect of the invention〕

上記したように、本発明の半導体装置の製造方法を用い
ることによって、安定かつ所望のデバイス特性が得られ
、素子分離領域の幅を微細化することによって、半導体
装置の集積化を高めることが可能となった。
As described above, by using the semiconductor device manufacturing method of the present invention, stable and desired device characteristics can be obtained, and by miniaturizing the width of the element isolation region, it is possible to increase the integration of the semiconductor device. It became.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(餠は本実施例の半導体装置の製造工程
を示す断面図である。第2図は従来の半導体装置の製造
方法を示す半導体断面図、その(a)はシリコンナイト
ライド形成時の断面図、(b)はサイドウオール形成時
の断面図である。 1・・・・・・・・半導体基板、2・・・・・・第1の
半導体酸化膜、3・・・・・・半導体層、4・・・・・
・第1の耐酸化膜、5・・・・・・第2の半導体酸化膜
、6・・・・第2の耐酸化膜、7・・・・・・・・不純
物、8・・・・・・側壁、9・・・・エツチング残り。
FIGS. 1(a) to 1(a) are cross-sectional views showing the manufacturing process of the semiconductor device of this embodiment. FIG. A cross-sectional view when forming a ride, and (b) a cross-sectional view when forming a sidewall. 1... Semiconductor substrate, 2... First semiconductor oxide film, 3... ...semiconductor layer, 4...
・First oxidation-resistant film, 5... Second semiconductor oxide film, 6... Second oxidation-resistant film, 7... Impurity, 8... ...Side wall, 9...Etching remaining.

Claims (1)

【特許請求の範囲】 半導体基板上に第1の半導体酸化膜を形成する工程と、 該半導体酸化膜上に半導体層を形成する工程と、該半導
体層上に第1の耐酸化膜を形成する工程と、 該耐酸化膜上に第2の半導体酸化膜を形成する工程と、 該第2の半導体酸化膜と上記耐酸化膜を選択的にエッチ
ング除去する工程と、 上記第2の半導体酸化膜をマスクにして上記半導体基板
に不純物を導入する工程と、 全面に第2の耐酸化膜を形成する工程と、 該第2の耐酸化膜を異方性エッチングして側壁部分にエ
ッチング残りを形成する工程と、上記第2の半導体酸化
膜を除去する工程と、上記耐酸化膜をマスクにして上記
基板を選択的に酸化する工程を備えた半導体装置の製造
方法。
[Claims] A step of forming a first semiconductor oxide film on a semiconductor substrate, a step of forming a semiconductor layer on the semiconductor oxide film, and a step of forming a first oxidation-resistant film on the semiconductor layer. a step of forming a second semiconductor oxide film on the oxidation-resistant film; a step of selectively etching away the second semiconductor oxide film and the oxidation-resistant film; and the second semiconductor oxide film. a step of introducing impurities into the semiconductor substrate using a mask as a mask, a step of forming a second oxidation-resistant film on the entire surface, and anisotropic etching of the second oxidation-resistant film to form an etching residue on the sidewall portion. a step of removing the second semiconductor oxide film; and a step of selectively oxidizing the substrate using the oxidation-resistant film as a mask.
JP13682287A 1987-05-29 1987-05-29 Manufacture of semiconductor device Pending JPS63300526A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13682287A JPS63300526A (en) 1987-05-29 1987-05-29 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13682287A JPS63300526A (en) 1987-05-29 1987-05-29 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS63300526A true JPS63300526A (en) 1988-12-07

Family

ID=15184318

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13682287A Pending JPS63300526A (en) 1987-05-29 1987-05-29 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS63300526A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5137843A (en) * 1990-12-22 1992-08-11 Samsung Electronics Co., Ltd. Isolation method for semiconductor device
DE4413815A1 (en) * 1993-04-28 1994-11-03 Mitsubishi Electric Corp Production method for a semiconductor device
US5789305A (en) * 1997-01-27 1998-08-04 Chartered Semiconductor Manufacturing Ltd. Locos with bird's beak suppression by a nitrogen implantation
US5834360A (en) * 1996-07-31 1998-11-10 Stmicroelectronics, Inc. Method of forming an improved planar isolation structure in an integrated circuit
US5874347A (en) * 1994-11-23 1999-02-23 Electronics And Telecommunications Research Institute Method for fabricating field oxide isolation region for semiconductor devices
US5933745A (en) * 1996-04-26 1999-08-03 Mitsubishi Denki Kabushiki Kaisha Method of making total dielectric semiconductor device isolation region
US5972773A (en) * 1995-03-23 1999-10-26 Advanced Micro Devices, Inc. High quality isolation for high density and high performance integrated circuits
US5972776A (en) * 1995-12-22 1999-10-26 Stmicroelectronics, Inc. Method of forming a planar isolation structure in an integrated circuit
US5977607A (en) * 1994-09-12 1999-11-02 Stmicroelectronics, Inc. Method of forming isolated regions of oxide

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5137843A (en) * 1990-12-22 1992-08-11 Samsung Electronics Co., Ltd. Isolation method for semiconductor device
DE4413815A1 (en) * 1993-04-28 1994-11-03 Mitsubishi Electric Corp Production method for a semiconductor device
US5538916A (en) * 1993-04-28 1996-07-23 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semiconductor device isolation region
US5977607A (en) * 1994-09-12 1999-11-02 Stmicroelectronics, Inc. Method of forming isolated regions of oxide
US5874347A (en) * 1994-11-23 1999-02-23 Electronics And Telecommunications Research Institute Method for fabricating field oxide isolation region for semiconductor devices
US5972773A (en) * 1995-03-23 1999-10-26 Advanced Micro Devices, Inc. High quality isolation for high density and high performance integrated circuits
US5972776A (en) * 1995-12-22 1999-10-26 Stmicroelectronics, Inc. Method of forming a planar isolation structure in an integrated circuit
US5933745A (en) * 1996-04-26 1999-08-03 Mitsubishi Denki Kabushiki Kaisha Method of making total dielectric semiconductor device isolation region
US6410973B2 (en) 1996-04-26 2002-06-25 Mitsubishi Denki Kabushiki Kaisha Thin film SOI MOSFET
US5834360A (en) * 1996-07-31 1998-11-10 Stmicroelectronics, Inc. Method of forming an improved planar isolation structure in an integrated circuit
US6046483A (en) * 1996-07-31 2000-04-04 Stmicroelectronics, Inc. Planar isolation structure in an integrated circuit
US5789305A (en) * 1997-01-27 1998-08-04 Chartered Semiconductor Manufacturing Ltd. Locos with bird's beak suppression by a nitrogen implantation

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