JP2683318B2 - Method for forming field oxide film of semiconductor device - Google Patents

Method for forming field oxide film of semiconductor device

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Publication number
JP2683318B2
JP2683318B2 JP6061512A JP6151294A JP2683318B2 JP 2683318 B2 JP2683318 B2 JP 2683318B2 JP 6061512 A JP6061512 A JP 6061512A JP 6151294 A JP6151294 A JP 6151294A JP 2683318 B2 JP2683318 B2 JP 2683318B2
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JP
Japan
Prior art keywords
film
forming
oxide film
field oxide
trench
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP6061512A
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Japanese (ja)
Other versions
JPH06302685A (en
Inventor
オグ ジャン セ
Original Assignee
ヒュンダイ エレクトロニクス インダストリイズ カンパニー リミテッド
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Publication of JPH06302685A publication Critical patent/JPH06302685A/en
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Publication of JP2683318B2 publication Critical patent/JP2683318B2/en
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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/05Etch and refill

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は半導体素子の製造工程の
素子分離膜形成に関し、特に活性領域を広く確保し、フ
ィールド酸化膜表面を滑らかに形成できる半導体素子の
フィールド酸化膜形成方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device isolation film formation in a semiconductor device manufacturing process, and more particularly to a method for forming a field oxide film of a semiconductor device which can secure a wide active region and form a smooth field oxide film surface.

【0002】[0002]

【従来の技術】従来のフィールド酸化膜形成方法は、図
17に示したように、シリコン基板1にパッド酸化膜
2、窒化膜4を順次蒸着した後に上記窒化膜4を選択的
に蝕刻してフィールド酸化膜を形成しようとする部分を
開放させた後、さらに窒化膜を蒸着し、エッチバック(e
tch back)してスペーサ窒化膜6を形成した後、上記窒
化膜4とスペーサ窒化膜を蝕刻マスクとしてシリコン基
板1にトレンチ7を形成する。
2. Description of the Related Art In a conventional field oxide film forming method, as shown in FIG. 17, a pad oxide film 2 and a nitride film 4 are sequentially deposited on a silicon substrate 1 and then the nitride film 4 is selectively etched. After opening the part where the field oxide film is to be formed, a nitride film is further deposited and an etchback (e
After tch back) to form the spacer nitride film 6, a trench 7 is formed in the silicon substrate 1 using the nitride film 4 and the spacer nitride film as an etching mask.

【0003】図18には図17の構造で酸化工程を行っ
たときに形成されるフィールド酸化膜10が示されてお
り、また、パッド酸化膜2を通じて酸素が拡散され、シ
リコン基板1の一部分も同時に酸化されてフィールド酸
化膜の耳Cが生じ、さらに活性領域に嘴状部分(bird's
beak)Dが厚く形成されるのを示している。
FIG. 18 shows a field oxide film 10 formed when the oxidation process is performed in the structure of FIG. 17, oxygen is diffused through the pad oxide film 2, and a part of the silicon substrate 1 is also shown. At the same time, the ear C of the field oxide film is generated by being oxidized, and the beak-shaped portion (bird's
It is shown that the beak) D is formed thick.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、上述の
ようにすると、フィールド酸化膜に形成される耳と嘴状
部分は活性領域の面積を減少させるのみならず、フィー
ルド酸化膜表面が荒くなって後続工程に困難を生じると
いう問題点があった。上記した問題点を解決するため、
本発明は嘴状部分の発生要因を減少させ、活性領域をよ
り広いものにし、フィールド酸化膜の表面を滑らかに成
形して後続工程を円滑に行えるようにして、優れた素子
分離特性を有する高度集積半導体素子のフィールド酸化
膜形成方法を提供することを目的とする。
However, in the above-described manner, the ears and beaks formed in the field oxide film not only reduce the area of the active region, but also the surface of the field oxide film becomes rough and the subsequent surface is roughened. There is a problem that the process is difficult. In order to solve the above problems,
The present invention reduces the cause of the beak-like portion, widens the active region, and smoothly molds the surface of the field oxide film so that the subsequent process can be performed smoothly. An object is to provide a method for forming a field oxide film of an integrated semiconductor device.

【0005】[0005]

【課題を解決するための手段】上記した目的を達成する
ため、本発明にかかる第1の半導体素子のフィールド酸
化膜形成方法は、半導体基板にパッド酸化膜を形成する
工程;前記パッド酸化膜を熱処理(annealing)して第1
の酸化窒化膜を形成する工程;前記第1の酸化窒化膜上
にポリシリコン膜、第1の窒化膜を順次形成する工程;
前記第1の窒化膜、ポリシリコン膜の所定の部位を順次
蝕刻した後、第2の窒化膜を蒸着する工程;前記第2の
窒化膜をエッチバックしてスペーサ窒化膜を形成し、露
出した第1の酸化窒化膜、半導体基板を順次蝕刻してト
レンチを形成する工程;トレンチ底部とトレンチ側壁を
熱処理(annealing)して第2の酸化窒化膜を形成する工
程;及び、前記トレンチ底部に形成された第2の酸化窒
化膜を蝕刻して除去し、フィールド酸化膜を形成する工
程からなることを特徴とする。
In order to achieve the above-mentioned object, a first method for forming a field oxide film of a semiconductor device according to the present invention comprises a step of forming a pad oxide film on a semiconductor substrate; 1st after annealing
A step of forming an oxynitride film of the above; a step of sequentially forming a polysilicon film and a first nitride film on the first oxynitride film;
A step of sequentially etching a predetermined portion of the first nitride film and the polysilicon film and then depositing a second nitride film; etching back the second nitride film to form a spacer nitride film and exposing the spacer nitride film. Forming a trench by sequentially etching the first oxynitride film and the semiconductor substrate; forming a second oxynitride film by annealing the trench bottom and trench sidewalls; and forming the trench bottom It is characterized by comprising the step of etching and removing the formed second oxynitride film to form a field oxide film.

【0006】 また、本発明に係る第2の半導体素子の
フィールド酸化膜形成方法は、半導体基板上にパッド酸
化膜、ポリシリコン膜、第1の窒化膜を順次形成する工
程;前記第1の窒化膜、ポリシリコン膜の所定の部位を
順次蝕刻した後、第2の窒化膜を蒸着する工程;前記第
2の窒化膜をエッチバックしてスペーサ窒化膜を形成
るとともに、このエッチバックにより露出したパッド酸
化膜、半導体基板を順次蝕刻してトレンチを形成する工
程;前記トレンチ底部と同トレンチ側壁を熱処理(an
nealing)して酸化窒化膜を形成する工程;およ
び、前記トレンチ底部に形成した酸化窒化膜を蝕刻して
除去、フィールド酸化膜を形成する工程からなること
を特徴とする。
A second method for forming a field oxide film of a semiconductor device according to the present invention includes a step of sequentially forming a pad oxide film, a polysilicon film, and a first nitride film on a semiconductor substrate; the first nitride film. film, after sequentially etching the predetermined portion of the polysilicon film, a step of depositing a second nitride layer; said second nitride film is etched back to form a spacer nitride film
And the pad acid exposed by this etch back
Forming a trench by sequentially etching the oxide film and the semiconductor substrate; heat-treating the trench bottom and the trench sidewall (an
and a step of forming a field oxide film by etching and removing the oxynitride film formed on the bottom of the trench.

【0007】[0007]

【発明の作用・効果】上記のように構成された本発明の
方法によるフィールド酸化膜は非等方性酸化を誘発して
側壁ポリシリコンの酸化を大幅に減少させることができ
る。したがって、嘴状部分の長さが減少し、活性領域を
より広く確保し、フィールド酸化膜の表面を滑らかに形
成することができる。また、電気的にフィールドの臨界
電圧(threshold voltage)が高められたフィールド酸
化膜を形成することができるので、パンチスルー特性が
優れた高度集積素子を製造することができる。
The field oxide film according to the method of the present invention constructed as described above can induce anisotropic oxidation to significantly reduce the oxidation of the sidewall polysilicon. Therefore, the length of the beak-shaped portion is reduced, the active region can be secured wider, and the surface of the field oxide film can be formed smoothly. In addition, since a field oxide film having an electrically increased threshold voltage can be formed, a highly integrated device having excellent punch-through characteristics can be manufactured.

【0008】[0008]

【実施例】【Example】

実施例1 以下、図1〜図9を参照して本発明の第1実施例を詳述
する。
First Embodiment Hereinafter, a first embodiment of the present invention will be described in detail with reference to FIGS.

【0009】図1に示したように、シリコン基板1にパ
ッド酸化膜2を50〜200オングストロームの厚さに
形成した後、図2に示したようにパッド酸化膜2をアン
モニア(NH2)またはN2Oガス雰囲気下で所定の温度
にて熱処理して酸化窒化膜5(請求項1記載の第1の酸
化窒化膜)を50〜100オングストロームの厚さに成
長させる。
As shown in FIG. 1, after the pad oxide film 2 is formed on the silicon substrate 1 to a thickness of 50 to 200 angstroms, the pad oxide film 2 is replaced with ammonia (NH 2 ) or as shown in FIG. Heat treatment is performed at a predetermined temperature in an N 2 O gas atmosphere to grow the oxynitride film 5 (the first oxynitride film according to claim 1) to a thickness of 50 to 100 Å.

【0010】次いで、図3に示したように、ポリシリコ
ン膜3を200〜500オングストローム、窒化膜4
(請求項1記載の第1の窒化膜)を1500〜3000
オングストロームの厚さで酸化窒化膜5上に順次形成し
た後、図4に示したように、所定の大きさで上記窒化膜
4、ポリシリコン膜3を順次乾式蝕刻してフィールド酸
化膜を形成しようとする領域を開放させた後、さらに窒
化膜4’(請求項1記載の第2の窒化膜)を1500〜
2000オングストロームの厚さに形成する。
Next, as shown in FIG. 3, the polysilicon film 3 is formed to a thickness of 200 to 500 angstroms and a nitride film 4 is formed.
(First nitride film according to claim 1) is set to 1500-3000.
After sequentially forming an angstrom thickness on the oxynitride film 5, as shown in FIG. 4, the nitride film 4 and the polysilicon film 3 are sequentially dry-etched to form a field oxide film. After the region to be defined as is opened, the nitride film 4 ′ (second nitride film according to claim 1) is further added to 1500 to
It is formed to a thickness of 2000 angstrom.

【0011】次いで、図5に示したように、上記窒化膜
4をエッチバックしてスペーサ窒化膜6を形成し、酸化
窒化膜5、シリコン基板1を順次乾式蝕刻して500〜
1000オングストロームの深さのトレンチ7を形成し
た後、図6に示したように、トレンチ底部8とトレンチ
側壁8’をN2Oガス雰囲気下で熱処理して酸化窒化膜
9(請求項1記載の第2の酸化窒化膜)を50〜100
オングストロームの厚さに成長させ、図7に示したよう
に、上記トレンチ底部8の酸化窒化膜9を乾式蝕刻して
除去する。
Next, as shown in FIG. 5, the nitride film 4 is etched back to form a spacer nitride film 6, and the oxynitride film 5 and the silicon substrate 1 are sequentially dry-etched to 500 to 500 nm.
After forming the trench 7 having a depth of 1000 angstrom, as shown in FIG. 6, the trench bottom portion 8 and the trench side wall 8 ′ are heat-treated in an N 2 O gas atmosphere to form the oxynitride film 9 (claim 1). Second oxynitride film) 50-100
After growing to a thickness of angstrom, as shown in FIG. 7, the oxynitride film 9 on the trench bottom 8 is removed by dry etching.

【0012】最後に、図8に示したように、フィールド
酸化膜10を形成した後、図9に示したように、残留し
ている上記窒化膜4、スペーサ窒化膜6、ポリシリコン
膜3、酸化窒化膜5を除去し、フィールド酸化膜10上
部の所定の部位を除去して平坦化させる。
Finally, as shown in FIG. 8, after forming the field oxide film 10, as shown in FIG. 9, the remaining nitride film 4, spacer nitride film 6, polysilicon film 3, The oxynitride film 5 is removed, and a predetermined portion above the field oxide film 10 is removed to be planarized.

【0013】実施例2 以下、図10〜図16を参照して本発明に係る第2実施
例を詳述する。
Second Embodiment Hereinafter, a second embodiment according to the present invention will be described in detail with reference to FIGS.

【0014】図10に示したように、シリコン基板1に
パッド酸化膜2を50〜200オングストロームの厚さ
に形成した後、ポリシリコン膜3を200〜500オン
グストロームの厚さに、窒化膜4(請求項5の第1の窒
化膜)を1500〜3000オングストロームの厚さに
それぞれ形成した後、図11に示したように、所定の大
きさで窒化膜4、ポリシリコン膜3を順次乾式蝕刻して
フィールド酸化膜を形成しようとする領域を開放させた
後、全体構造の上部に窒化膜4’請求項5の第2の窒
化膜)を1500〜2000オングストロームの厚さに
形成する。
As shown in FIG. 10, after the pad oxide film 2 is formed on the silicon substrate 1 to a thickness of 50 to 200 angstroms, the polysilicon film 3 is formed to a thickness of 200 to 500 angstroms and the nitride film 4 ( The first step of claim 5
Then , as shown in FIG. 11, the nitride film 4 and the polysilicon film 3 are sequentially dry-etched in order to form a field oxide film. After the region to be defined as is opened, the nitride film 4 ′ is formed on the upper portion of the entire structure ( the second nitride film of claim 5).
Film ) to a thickness of 1500-2000 angstroms.

【0015】次いで、図12に示したように、窒化膜
をエッチバックしてスペーサ窒化膜6を形成した
後、窒化膜4’とスペーサ窒化膜6を蝕刻マスクとして
パッド酸化膜2とシリコン基板1を順次乾式蝕刻して5
00〜1000オングストロームの深さのトレンチ7を
形成する。
[0015] Then, as shown in FIG. 12, 'after forming the spacer nitride film 6 is etched back, the nitride film 4' nitride film 4 pad oxide film 2 and silicon and a spacer nitride film 6 as an etching mask Substrate 1 is sequentially dry etched 5
A trench 7 having a depth of 00 to 1000 angstrom is formed.

【0016】次いで、図13に示したように、トレンチ
底部8とトレンチ側壁8’をNOガス雰囲気下で熱処
理して酸化窒化膜9(請求項5の酸化窒化膜)を50〜
100オングストロームの厚さに成長させた後、図14
に示したように、トレンチ底部8の酸化窒化膜9を蝕刻
して除去し、図15に示したようにフィールド酸化膜1
0を形成する。
Then, as shown in FIG. 13, the trench bottom portion 8 and the trench side wall 8'are heat-treated in an N 2 O gas atmosphere to form an oxynitride film 9 (oxynitride film of claim 5 ) in an amount of 50 to 50.
After growing to a thickness of 100 Å, FIG.
As shown in FIG. 15, the oxynitride film 9 on the bottom 8 of the trench is etched and removed, and the field oxide film 1 is removed as shown in FIG.
Form 0.

【0017】最後に、図16に示したように、窒化膜
4、スペーサ窒化膜6、ポリシリコン膜3、パッド酸化
膜2を除去し、フィールド酸化膜10上部の所定部位を
除去して平坦化させる。
Finally, as shown in FIG. 16, the nitride film 4, the spacer nitride film 6, the polysilicon film 3 and the pad oxide film 2 are removed, and a predetermined portion above the field oxide film 10 is removed to be planarized. Let

【0018】上記のように構成された本発明の方法によ
るフィールド酸化膜は非等方性酸化を誘発して側壁ポリ
シリコンの酸化を大幅に減少させることができる。した
がって、嘴状部分の長さが減少し、活性領域をより広く
確保し、フィールド酸化膜の表面を滑らかに形成するこ
とができる。また、電気的にフィールドの臨界電圧(th
reshold voltage)を高められたフィールド酸化膜を形
成することができるので、パンチスルー特性が優れた高
度集積素子を製造することができる。
The field oxide according to the method of the present invention constructed as described above can induce anisotropic oxidation to significantly reduce the oxidation of the sidewall polysilicon. Therefore, the length of the beak-shaped portion is reduced, the active region can be secured wider, and the surface of the field oxide film can be formed smoothly. Also, the electrical field critical voltage (th
Since it is possible to form a field oxide film having an increased reshold voltage, it is possible to manufacture a highly integrated device having excellent punch-through characteristics.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1実施例によるフィールド酸化膜形
成の第1工程を示す断面図。
FIG. 1 is a sectional view showing a first step of forming a field oxide film according to a first embodiment of the present invention.

【図2】本発明の第1実施例によるフィールド酸化膜形
成の第2工程を示す断面図。
FIG. 2 is a sectional view showing a second step of forming a field oxide film according to the first embodiment of the present invention.

【図3】本発明の第1実施例によるフィールド酸化膜形
成の第3工程を示す断面図。
FIG. 3 is a sectional view showing a third step of forming a field oxide film according to the first embodiment of the present invention.

【図4】本発明の第1実施例によるフィールド酸化膜形
成の第4工程を示す断面図。
FIG. 4 is a sectional view showing a fourth step of forming a field oxide film according to the first embodiment of the present invention.

【図5】本発明の第1実施例によるフィールド酸化膜形
成の第5工程を示す断面図。
FIG. 5 is a sectional view showing a fifth step of forming a field oxide film according to the first embodiment of the present invention.

【図6】本発明の第1実施例によるフィールド酸化膜形
成の第6工程を示す断面図。
FIG. 6 is a sectional view showing a sixth step of forming a field oxide film according to the first embodiment of the present invention.

【図7】本発明の第1実施例によるフィールド酸化膜形
成の第7工程を示す断面図。
FIG. 7 is a sectional view showing a seventh step of forming a field oxide film according to the first embodiment of the present invention.

【図8】本発明の第1実施例によるフィールド酸化膜形
成の第8工程を示す断面図。
FIG. 8 is a sectional view showing an eighth step of forming a field oxide film according to the first embodiment of the present invention.

【図9】本発明の第1実施例によるフィールド酸化膜形
成の第9工程を示す断面図。
FIG. 9 is a sectional view showing a ninth step of forming a field oxide film according to the first embodiment of the present invention.

【図10】本発明の第2実施例によるフィールド酸化膜
形成の第1工程を示す断面図。
FIG. 10 is a sectional view showing a first step of forming a field oxide film according to the second embodiment of the present invention.

【図11】本発明の第2実施例によるフィールド酸化膜
形成の第2工程を示す断面図。
FIG. 11 is a sectional view showing a second step of forming a field oxide film according to the second embodiment of the present invention.

【図12】本発明の第2実施例によるフィールド酸化膜
形成の第3工程を示す断面図。
FIG. 12 is a sectional view showing a third step of forming a field oxide film according to the second embodiment of the present invention.

【図13】本発明の第2実施例によるフィールド酸化膜
形成の第4工程を示す断面図。
FIG. 13 is a sectional view showing a fourth step of forming a field oxide film according to the second embodiment of the present invention.

【図14】本発明の第2実施例によるフィールド酸化膜
形成の第5工程を示す断面図。
FIG. 14 is a sectional view showing a fifth step of forming a field oxide film according to the second embodiment of the present invention.

【図15】本発明の第2実施例によるフィールド酸化膜
形成の第6工程を示す断面図。
FIG. 15 is a sectional view showing a sixth step of forming a field oxide film according to the second embodiment of the present invention.

【図16】本発明の第2実施例によるフィールド酸化膜
形成の第7工程を示す断面図。
FIG. 16 is a sectional view showing a seventh step of forming a field oxide film according to the second embodiment of the present invention.

【図17】従来のフィールド酸化膜形成工程を示す断面
図。
FIG. 17 is a sectional view showing a conventional field oxide film forming step.

【図18】図17の工程を用いて形成したフィールド酸
化膜の形態を示す断面図。
FIG. 18 is a cross-sectional view showing the form of a field oxide film formed by using the process of FIG.

【符号の説明】[Explanation of symbols]

1…シリコン基板、2…パッド酸化膜、3…ポリシリコ
ン膜、4…窒化膜、4’…窒化膜、5…酸化窒化膜、6
…スペーサ窒化膜、7…トレンチ、8…トレンチ底部、
8’…トレンチ側壁、9…酸化窒化膜、10…フィール
ド酸化膜。
1 ... Silicon substrate, 2 ... Pad oxide film, 3 ... Polysilicon film, 4 ... Nitride film, 4 '... Nitride film, 5 ... Oxynitride film, 6
... spacer nitride film, 7 ... trench, 8 ... trench bottom,
8 '... trench side wall, 9 ... oxynitride film, 10 ... field oxide film.

Claims (8)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 半導体素子のフィールド酸化膜形成方法
において、 半導体基板にパッド酸化膜を形成する工程、 前記パッド酸化膜を熱処理して第1の酸化窒化膜を形成
する工程、 前記第1の酸化窒化膜上にポリシリコン膜、第1の窒化
膜を順次形成する工程、 前記第1の窒化膜、ポリシリコン膜の所定部位を順次蝕
刻した後、第2の窒化膜を蒸着する工程、 前記第2の窒化膜をエッチバックしてスペーサ窒化膜を
形成し、露出した第1の酸化窒化膜、半導体基板を順次
蝕刻してトレンチを形成する工程、 前記トレンチ底部と同トレンチ側壁を熱処理して第2の
酸化窒化膜を形成する工程及び、 前記トレンチ底部に形成した第2の酸化窒化膜を蝕刻し
て除去し、フィールド酸化膜を形成する工程からなるこ
とを特徴とする半導体素子のフィールド酸化膜形成方
法。
1. A field oxide film formation method of a semiconductor device, the step of forming a pad oxide film on a semiconductor substrate, forming a first oxynitride layer by heat-treating the pad oxide layer, the first oxide A step of sequentially forming a polysilicon film and a first nitride film on the nitride film, a step of sequentially etching a predetermined portion of the first nitride film and the polysilicon film, and a step of depositing a second nitride film, A step of etching back the second nitride film to form a spacer nitride film and sequentially etching the exposed first oxynitride film and the semiconductor substrate to form a trench; and heat treating the trench bottom and the trench sidewall to form a trench. And a step of forming a field oxide film by etching and removing the second oxynitride film formed on the bottom of the trench. Field oxide film forming method.
【請求項2】 前記半導体基板に形成されるパッド酸
化膜の厚さが、50〜200オングストロームであるこ
とを特徴とする請求項1に記載の半導体素子のフィール
ド酸化膜形成方法。
2. The method for forming a field oxide film of a semiconductor device according to claim 1, wherein the pad oxide film formed on the semiconductor substrate has a thickness of 50 to 200 angstroms.
【請求項3】 前記第1の酸化窒化膜及び第2の酸化窒
化膜を50〜100オングストロームの厚さに、アンモ
ニア(NH)またはNOガス雰囲気下で、形成する
ことを特徴とする請求項1に記載の半導体素子のフィー
ルド酸化膜形成方法。
3. The first oxynitride film and the second oxynitride film are formed to a thickness of 50 to 100 angstroms in an atmosphere of ammonia (NH 3 ) or N 2 O gas. The method for forming a field oxide film of a semiconductor device according to claim 1.
【請求項4】 前記トレンチの深さを500〜1000
オングストロームに形成することを特徴とする請求項1
に記載の半導体素子のフィールド酸化膜形成方法。
4. The depth of the trench is 500 to 1000.
2. Forming in Angstrom.
A method for forming a field oxide film of a semiconductor device as described in 1.
【請求項5】 半導体素子のフィールド酸化膜形成方法
において、 半導体基板上にパッド酸化膜、ポリシリコン膜、第1の
窒化膜を順次形成する工程、 前記第1の窒化膜、ポリシリコン膜の所定の部位を順次
蝕刻した後、第2の窒化膜を蒸着する工程前記第2の窒
化膜をエッチバックしてスペーサ窒化膜を形成するとと
もに、このエッチバックにより露出したパッド酸化膜
半導体基板を順次蝕刻してトレンチを形成する工程、 前記トレンチ底部と同トレンチ側壁を熱処理して酸化窒
化膜を形成する工程、 および、前記トレンチ底部に形成した酸化窒化膜を蝕刻
して除去し、フィールド酸化膜を形成する工程からなる
ことを特徴とする半導体素子のフィールド酸化膜形成方
法。
5. A method of forming a field oxide film of a semiconductor device, comprising the steps of sequentially forming a pad oxide film, a polysilicon film, and a first nitride film on a semiconductor substrate, and a predetermined process of forming the first nitride film and the polysilicon film. After sequentially etching the above-mentioned region, a step of depositing a second nitride film is performed. The second nitride film is etched back to form a spacer nitride film.
In fact, the pad oxide film exposed by this etch back ,
A step of sequentially etching the semiconductor substrate to form a trench, a step of heat-treating the trench bottom and the same trench sidewall to form an oxynitride film, and an etching removal of the oxynitride film formed on the trench bottom, A method for forming a field oxide film of a semiconductor device, comprising the step of forming a field oxide film.
【請求項6】 前記半導体基板上に形成したパッド酸化
膜が、50〜200オングストロームの厚さであること
を特徴とする請求項5に記載の半導体素子のフィールド
酸化膜形成方法。
6. The method for forming a field oxide film of a semiconductor device according to claim 5, wherein the pad oxide film formed on the semiconductor substrate has a thickness of 50 to 200 angstroms.
【請求項7】 前記半導体基板に形成されるトレンチの
深さが、500〜1000オングストロームであること
を特徴とする請求項5に記載の半導体素子のフィールド
酸化膜形成方法。
7. The method for forming a field oxide film of a semiconductor device according to claim 5, wherein the depth of the trench formed in the semiconductor substrate is 500 to 1000 angstrom.
【請求項8】 前記酸化窒化膜を50〜100オングス
トロームの厚さに、アンモニア(NH)またはN
ガス雰囲気下で、形成することを特徴とする請求項5に
記載の半導体素子のフィールド酸化膜形成方法。
8. The oxynitride film is formed to a thickness of 50 to 100 angstroms with ammonia (NH 3 ) or N 2 O.
The method for forming a field oxide film of a semiconductor device according to claim 5, wherein the method is performed in a gas atmosphere.
JP6061512A 1993-03-31 1994-03-30 Method for forming field oxide film of semiconductor device Expired - Fee Related JP2683318B2 (en)

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KR1993-5468 1993-03-31
KR1019930005468A KR960005553B1 (en) 1993-03-31 1993-03-31 Manufacturing method of field oxide

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Families Citing this family (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970003731B1 (en) * 1993-10-14 1997-03-21 엘지반도체 주식회사 Method of forming the isolation elements on the semiconductor device
US5470770A (en) * 1994-03-31 1995-11-28 Nippondenso Co., Ltd. Manufacturing method of semiconductor device
KR0136518B1 (en) * 1994-04-01 1998-04-24 Hyundai Electroncis Ind Co Ltd Method for forming a field oxide layer
US5564180A (en) * 1994-11-14 1996-10-15 United Microelectronics Corp. Method of fabricating DRAM cell capacitor
KR0143713B1 (en) * 1994-12-26 1998-07-01 김주용 Transistors and manufacturing methods thereof
US5972773A (en) * 1995-03-23 1999-10-26 Advanced Micro Devices, Inc. High quality isolation for high density and high performance integrated circuits
KR0151051B1 (en) * 1995-05-30 1998-12-01 김광호 Method of forming insulation film for semiconductor device
KR100190363B1 (en) * 1995-06-28 1999-06-01 김영환 Forming element isolation region in semiconductor device
JP3394859B2 (en) * 1995-10-18 2003-04-07 シャープ株式会社 Method for manufacturing semiconductor memory device
KR100197651B1 (en) * 1995-11-03 1999-06-15 김영환 Method of forming an element isolation film of semiconductor device
KR19980030859U (en) * 1996-11-29 1998-08-17 진호선 Men's shorts
US5780353A (en) * 1996-03-28 1998-07-14 Advanced Micro Devices, Inc. Method of doping trench sidewalls before trench etching
US5811347A (en) * 1996-04-29 1998-09-22 Advanced Micro Devices, Inc. Nitrogenated trench liner for improved shallow trench isolation
US5643824A (en) * 1996-07-29 1997-07-01 Vanguard International Semiconductor Corporation Method of forming nitride sidewalls having spacer feet in a locos process
US5895257A (en) * 1996-08-01 1999-04-20 Taiwan Semiconductor Manfacturing Company, Ltd. LOCOS field oxide and field oxide process using silicon nitride spacers
US5728614A (en) * 1996-09-25 1998-03-17 Vanguard International Semiconductor Corporation Method to improve the topography of a field oxide region
KR100231484B1 (en) * 1996-11-19 1999-11-15 문정환 Method of forming field oxide film
US5789305A (en) * 1997-01-27 1998-08-04 Chartered Semiconductor Manufacturing Ltd. Locos with bird's beak suppression by a nitrogen implantation
US5721174A (en) * 1997-02-03 1998-02-24 Chartered Semiconductor Manufacturing Pte Ltd Narrow deep trench isolation process with trench filling by oxidation
KR100232899B1 (en) 1997-06-02 1999-12-01 김영환 Semiconductor element isolation film manufacturing method
KR100235950B1 (en) * 1997-06-26 1999-12-15 김영환 Method of forming a device field oxide film of semiconductor device
KR100419877B1 (en) * 1997-06-30 2004-06-30 주식회사 하이닉스반도체 Isolation method of semiconductor device
US5891787A (en) * 1997-09-04 1999-04-06 Advanced Micro Devices, Inc. Semiconductor fabrication employing implantation of excess atoms at the edges of a trench isolation structure
US6087241A (en) * 1997-09-05 2000-07-11 Microchip Technology Incorporated Method of forming side dielectrically isolated semiconductor devices and MOS semiconductor devices fabricated by this method
KR100439107B1 (en) * 1997-12-29 2004-07-16 주식회사 하이닉스반도체 Method for forming isolation layer of semiconductor device to prevent leakage current
KR100439109B1 (en) * 1997-12-29 2004-07-16 주식회사 하이닉스반도체 Method for forming isolation layer of semiconductor device to avoid decrease in quality of gate insulation layer and defect of gate electrode
US6727569B1 (en) 1998-04-21 2004-04-27 Advanced Micro Devices, Inc. Method of making enhanced trench oxide with low temperature nitrogen integration
US6096612A (en) * 1998-04-30 2000-08-01 Texas Instruments Incorporated Increased effective transistor width using double sidewall spacers
US6074927A (en) * 1998-06-01 2000-06-13 Advanced Micro Devices, Inc. Shallow trench isolation formation with trench wall spacer
US6097069A (en) * 1998-06-22 2000-08-01 International Business Machines Corporation Method and structure for increasing the threshold voltage of a corner device
US6372601B1 (en) * 1998-09-03 2002-04-16 Micron Technology, Inc. Isolation region forming methods
US6274498B1 (en) * 1998-09-03 2001-08-14 Micron Technology, Inc. Methods of forming materials within openings, and method of forming isolation regions
TW393724B (en) * 1998-09-19 2000-06-11 United Microelectronics Corp A manufacturing method of shallow trench isolation
US6218720B1 (en) 1998-10-21 2001-04-17 Advanced Micro Devices, Inc. Semiconductor topography employing a nitrogenated shallow trench isolation structure
US6876145B1 (en) 1999-09-30 2005-04-05 Semiconductor Energy Laboratory Co., Ltd. Organic electroluminescent display device
US6613651B1 (en) * 2000-09-05 2003-09-02 Lsi Logic Corporation Integrated circuit isolation system
US6417093B1 (en) 2000-10-31 2002-07-09 Lsi Logic Corporation Process for planarization of metal-filled trenches of integrated circuit structures by forming a layer of planarizable material over the metal layer prior to planarizing
US6586814B1 (en) 2000-12-11 2003-07-01 Lsi Logic Corporation Etch resistant shallow trench isolation in a semiconductor wafer
US6617251B1 (en) 2001-06-19 2003-09-09 Lsi Logic Corporation Method of shallow trench isolation formation and planarization
TWI234228B (en) * 2004-05-12 2005-06-11 Powerchip Semiconductor Corp Method of fabricating a shallow trench isolation
DE102004044222A1 (en) * 2004-09-14 2006-03-16 Robert Bosch Gmbh Micromechanical component and corresponding manufacturing method

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5693344A (en) * 1979-12-26 1981-07-28 Fujitsu Ltd Manufacture of semiconductor device
JPS5821842A (en) * 1981-07-30 1983-02-08 インタ−ナシヨナル・ビジネス・マシ−ンズ・コ−ポレ−シヨン Method of forming isolating region
EP0075875A3 (en) * 1981-09-28 1986-07-02 General Electric Company Method of making integrated circuits comprising dielectric isolation regions
US4398992A (en) * 1982-05-20 1983-08-16 Hewlett-Packard Company Defect free zero oxide encroachment process for semiconductor fabrication
JPS60236245A (en) * 1984-05-10 1985-11-25 Fujitsu Ltd Manufacture of semiconductor device
US4561172A (en) * 1984-06-15 1985-12-31 Texas Instruments Incorporated Integrated circuit fabrication method utilizing selective etching and oxidation to form isolation regions
JPS61100945A (en) * 1984-10-22 1986-05-19 Seiko Epson Corp Mos type semiconductor integrated circuit device
JPS61247051A (en) * 1985-04-24 1986-11-04 Hitachi Ltd Manufacture of semiconductor device
JPS62211938A (en) * 1986-03-12 1987-09-17 Fujitsu Ltd Manufacture of semiconductor device
JP2757358B2 (en) * 1987-05-29 1998-05-25 ソニー株式会社 Method for manufacturing semiconductor device
US4923563A (en) * 1987-06-15 1990-05-08 Ncr Corporation Semiconductor field oxide formation process using a sealing sidewall of consumable nitride
JPH04127433A (en) * 1990-09-18 1992-04-28 Sharp Corp Formation of semiconductor element isolation region
US5248350A (en) * 1990-11-30 1993-09-28 Ncr Corporation Structure for improving gate oxide integrity for a semiconductor formed by a recessed sealed sidewall field oxidation process
JPH04234145A (en) * 1990-12-28 1992-08-21 Nec Corp Element isolation forming method
FR2672731A1 (en) * 1991-02-07 1992-08-14 France Telecom PROCESS FOR BURIED LOCALIZED OXIDATION OF A SILICON SUBSTRATE AND CORRESPONDING INTEGRATED CIRCUIT
US5298451A (en) * 1991-04-30 1994-03-29 Texas Instruments Incorporated Recessed and sidewall-sealed poly-buffered LOCOS isolation methods
JPH05206263A (en) * 1992-01-29 1993-08-13 Sharp Corp Manufacture of semiconductor device

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US5399520A (en) 1995-03-21

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