WO2014020403A1

WO2014020403A1 - Improved fluctuation resistant fdsoi transistors with charged subchannel and reduced access resistance

Info

Publication number: WO2014020403A1
Application number: PCT/IB2013/001637
Authority: WO
Inventors: Asen ASENOV
Original assignee: Gold Standard Simulations Ltd.
Priority date: 2012-07-28
Filing date: 2013-07-26
Publication date: 2014-02-06

Abstract

The structures, and fabrication methods thereof, implement fully depleted silicon- on-insulator (SOI) transistors using "Channel Last" procedures in which the active channel is a low-temperature epitaxial layer in an etched recess in the SOI silicon film. In one form, an optional δ-layer of extremely high doping allows its threshold voltage to be set to a desired value. The utilization of active silicon layer that is two or more times thicker than those used in conventional fully depleted SOI devices, reduces the access resistance and improves the on-current of the SOI transistor. In another form, a highly localized ion implantation may be used to set the threshold voltage of the transistor and to improve the short channel behavior of the final device. Based on high-K metal gate technology, these transistors have reduced threshold uncertainty and superior source and drain conductance.

Description

IMPROVED FLUCTUATION RESISTANT FDSOI TRANSISTORS WITH CHARGED SUBCHANNEL AND REDUCED ACCESS RESISTANCE

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Patent Application No. 61/676,932 filed July 28, 2012 and U.S. Provisional Patent Application No. 61/676,935 filed July 28, 2012.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to the manufacturing of metal-oxide- semiconductor field effect transistors (MOSFETs), and more particularly to transistors fabricated in thin films over an insulating layer. Even more specifically, this invention deals with those instances where random variations of the threshold voltages of such transistors adversely affect integrated circuit performance.

2. Prior Art

MOS transistors have long been troubled by the adverse effects of their underlying substrates, like parasitic capacitance and area-consuming isolation. In the earliest days of integrated circuit technology, the use of a thin film of silicon on a sapphire substrate was proposed as a solution to these problems. RCA Laboratories was an early proponent of this technology, as in Meyer, J.E.; Boleky, E.J.; "High performance, low power CMOS memories using silicon-on-sapphire technology," Electron Devices Meeting, 1971

International, vol. 17, p. 44, 1971. The basic ideas of this technology have evolved over the years driven by improvements in materials technology, and as less exotic substrates became practical, this technology became known as silicon-on-insulator (SOI). In the earliest implementations, the silicon was simply a very thin, i. e., less than 1 micron thick, substrate with a conventional level of doping and a depletion layer beneath the transistor's gate. This depletion layer is thinner than the silicon thickness, resulting in 'partially depleted' SOI (PD SOI). The un-depleted doped region beneath the gate of a PD SOI transistor proved to have its own disadvantages, largely caused by its tendency to charge and discharge, resulting in step changes in the drain current. These problems became known as a "kink" effect, and it was closely tied to the behavior of hot electrons from the transistor's channel.

The next stage in silicon-on-insulator evolution was the fully-depleted film

(FDSOI). This was achieved by making the silicon beneath the gate so thin that there would be no region where there would be mobile carriers. Some of the early work was done at HP Laboratories and reported as Colinge, J.-P.; "Hot-electron effects in Silicon-on-insulator n- channel MOSFET's," Electron Devices, IEEE Transactions on , vol. 34, no. 10, pp. 2173- 2177, Oct 1987. In this work, the silicon film is thinner by a factor of 10, i.e., only 100 nm thick.

The next step in fully depleted silicon-on-insulator technology has been prompted by the emergence of threshold voltage variations that are associated with the uncertainty of the number of discrete doping ions immediately beneath the gate. This uncertainty is similar to shot noise, because it is an irreducible, statistical uncertainty. For large devices, the counting uncertainty, roughly proportional to the square root of the total number of ions, was never a problem. However, in a world where devices have dimensions of the order of 30 nm, the total number of doping ions drops below 1000, and the counting uncertainty is about 3%, rising to 10% for smaller devices. These deviations are devastating when billions of transistors are integrated into a single integrated circuit chip. The immediate solution required eliminating all doping from the silicon layer, placing all the responsibility for threshold control on the relative work functions of the gate material, now a metal, and the silicon film. This has been done with both planar and FinFET transistor structures. A good review of this work may be found in Kuhn, K.J.; Giles, M.D.; Becher, D.; Kolar, P.;

Kornfeld, A.; Kotlyar, R.; Ma, S.T.; Maheshwari, A.; Mudanai, S.; "Process Technology Variation," Electron Devices, IEEE Transactions on, vol. 58, no. 8, pp. 2197-2208, Aug. 2011.

Planar transistors at 32/28 nm CMOS technology generation manufactured to have good electrostatic integrity and resistance to doping fluctuations must employ extremely thin silicon layers, of the order of 7 nm, and they are fabricated over thin buried oxide layers, roughly 10 nm thick. This is discussed in detail in Maleville, C; "Extending planar device roadmap beyond node 20nm through ultra thin body technology," VLSI Technology, Systems and Applications (VLSI-TSA), 2011 International Symposium on, pp. 1-4, 25-27 April 2011. Layers in the sub- 10 nm thickness range present manufacturing challenges, and the very thin layers have an adverse effect on performance because the parasitic series resistance in sources and drains cuts down on the transistors' gain figures. The limited number of dopants, particularly in the access regions below the spacer also introduce variability to access resistance and on-current, as published by S. Markov, S; Cheng, B.; Asenov, A.; "Statistical variability in fully depleted SOI MOSFETs due to random dopant fluctuations in the source and drain extensions," IEEE Electron Dev. Let. Vol. 33, pp. 315 - 317 (March, 2012).

There have been a variety of publications that address the use of an undoped or lightly doped epitaxial channel region to mitigate the fluctuations associated with random doping variations. The publications include Takeuchi, K.; Tatsumi, T.; Furukawa, A.; "Channel engineering for the reduction of random-dopant-placement-induced threshold voltage fluctuation," Electron Devices Meeting, 1997. IEDM '97. Technical Digest., International, pp. 841-844, 7-10 Dec 1997; Asenov, A.; Saini, S.; "Suppression of random dopant-induced threshold voltage fluctuations in sub-O. l-μπι MOSFETs with epitaxial and δ-doped channels," Electron Devices, IEEE Transactions on, vol. 46, no. 8, pp. 1718- 1724, Aug 1999; and Thompson; Scott E.; Thummalapally; Damodar R.; "Electronic Devices and Systems, and Methods for Making and Using the Same," U. S. Patent Application

2011/0074498, March 31, 2011. All these publications address the use of epitaxy in the channels of bulk transistors.

Figure 1 shows a schematic representation of conventional, fully-depleted silicon on insulator transistor. This figure is prior art. The transistor in Figure 1 is fabricated on a substrate 10, with a buried oxide 11 separating all components of the transistor from the underlying substrate 10. The active region 13 is doped at a level that permits the active region to be totally free of carriers when there is no applied voltage difference between the gate 15 and 16 and the source, one of either region marked 19. This is made possible because a metal gate 15 has been chosen to have a work function which establishes the appropriate electrostatic potentials within the silicon channel region 13. The gate region 16 comprises a robust material like polycrystalline silicon. It permits fabrication of spacers, contact holes and inter-layer dielectric. Normally in the fabrication of such a transistor, there is a protective oxide 17 which is removed and replaced by a thin, high dielectric constant stack identified as 14. On each side of the gate structure comprising elements 14, 15 and 16, there is a spacer 18. Typically, this spacer is a robust dielectric like silicon - nitride that has been etched anisotropically to leave walls of finite thickness on each side of the gate structure. Because of the limitations in FDSOI transistors, the total thickness of region 13 and that part of region 19 that lies beneath the spacer is the same, 4 nm to 8 nm in advanced technologies. The transistor described in Figure 1 suffers from the limitations described hereinabove.

While the use of prior art FDSOI structures eliminates threshold voltage variations associated with random doping fluctuations, that advantage vanishes when doping is used to adjust threshold voltages. Further, the prior art transistors are subject to variations associated with the randomness of the drain-channel interface, and their source and drain conductances are limited by the very thin film thickness.

BRIEF DESCRIPTION OF THE DRAWINGS

The subject matter that is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the invention will be apparent from the following detailed description taken in conjunction with the accompanying drawings.

Figure 1 is a schematic cross section of a prior art fully depleted SOI transistor (prior art).

Figure 2 is a schematic cross section of a transistor reflecting the structural improvements in an embodiment of the present invention.

Figures 3A through 3H schematically illustrate an exemplary initial processing sequence by which the "Channel Last" structures can be built to realize the structural and performance improvements to fully depleted SOI transistors as described herein.

Figures 31 through 3L schematically illustrate an exemplary remaining processing sequence by which one embodiment of the "Channel Last" structures may be manufactured using channel ion implantation.

Figure 4 is a schematic cross section of a transistor reflecting the structural improvements in another embodiment of the present invention. Figures 5A thorough 5D illustrate an exemplary final processing sequence by which, when combined with the initial processing sequence of Figures 3A through 3H, a "Channel Last" structure of the embodiment of Figure 4 can be built to realize the structural and performance improvements to fully depleted SOI transistors as described herein.

Figures 6A through 6D show an alternative method of realizing the "Channel Last" structures that achieve the structural and performance improvements of fully depleted SOI transistors.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The structures, and fabrication methods thereof, implement fully depleted silicon- on-insulator (SOI) transistors using a "Channel Last" procedure in which the active channel is a low-temperature epitaxial layer in an etched recess in the SOI silicon film. In one embodiment, an optional δ-layer of extremely high doping allows its threshold voltage to be set to a desired value. The utilization of active silicon layer that is two or more times thicker than those used in conventional fully depleted SOI devices, reduces the access resistance and improves the on-current of the SOI transistor. In other embodiments, highly localized ion implantation is used to set the threshold voltage of the transistor and to improve the short channel behavior of the final device. Based on high-K metal gate technology, this transistor has reduced threshold uncertainty and superior source and drain conductance.

Embodiments of the invention achieve extremely low random variability in fully depleted SOI transistors by modifying the transistors structure to substantially reduce the variations associated with random doping fluctuations and allow the use of thicker films. The use of thicker films also results in reduction of the access resistance and an increase in the drive current. Further, this invention addresses a second source of fluctuations, variability associated with the uncertainty of the location of the PN junctions that separate sources and drains from the bodies of their respective transistors. This is achieved creating fully-depleted SOI transistors using a "channel last" process. This process and its resulting structure present several advantages, including reduced threshold variations, use of thicker silicon films, improved access resistance, and process means for defining a variety of threshold voltages. The new structures differ from the prior art, described for example in Figure 1 in the physical and electrical structure of the channel region of the thin-film, SOI transistor. This is illustrated for one embodiment in the exemplary and non-limiting Figure 2. As in the prior art, the transistor is supported by a substrate 20 and a buried oxide 21. Instead of a single channel region, this transistor has a compound channel region made up of an epitaxial region 231, which is very lightly doped, i. e., less than 10¹⁷ doping ions/cm³ and preferably less than 10¹⁶ doping ions/cm³. At the top of the lightly doped epitaxial region, there is a high-K gate stack 24. Beneath the epitaxial region there is a δ-layer 22, extremely thin, which is doped with acceptors for NMOS and donors for PMOS. The lateral extent of the channel region 231 and the δ-layer 22 along an axis passing between the source/drain electrodes 29 is essentially identical to the span between the spacers 28. According to an embodiment the thickness of layer 231 should be half or less of the thickness of layer 29. The transistor is completed by a metallic gate with controlled work function 25 and a robust gate handle 26, typically amorphous or polycrystalline silicon. Regions 27 are residual patches of protective oxide from early stages of the process.

The role of the δ-layer 22 is to screen the lateral penetration of the drain field in the channel, reducing the short channel effects despite the increased thickness of the channel region. The δ-layer 22 also provides electrostatic control of the threshold voltage. The δ- layer 22 has a thickness of 1-3 nm, representing a few atomic layers. A typical doping density for the δ-layer 22 is 1 x 10 ions per cm . That means that for every 500 silicon atoms in that δ-layer there is one active doping atom. For an NMOS transistor the dopants are acceptor ions, like boron or indium. For a PMOS transistor the dopants in δ-layer 22 are donors like phosphorus, arsenic or antimony. Further, because δ-layer 22 is so thin, in normal operation conditions those dopants are always fully ionized, and there are no mobile charges in the δ-layer 22. By adjusting the doping density in δ-layer 22, it is possible to tune the threshold voltage to a higher or lower value, so the doping density cited above can vary from essentially zero to around 5 x 10¹³ ions/cm². Expressed as volume doping densities, the range would go up to 5 x 10²⁰ ions/cm³, with 1 x 10²⁰ being a more typical number. In order to realize the full benefits of this structure, it is important to build the device so the boundary between δ-layer 22 with its high doping is steep enough to retain the sharply localized character of that thin layer. A typical thickness for the undoped epi region 231 is in the range from 5 nm to 15 nm. Adjacent to region 231 is the gate dielectric 24, and for this class of transistor, that dielectric is expected to be a high-K dielectric stack. While silicon dioxide has a dielectric constant K of 3.9, a high-K dielectric stack has an effective dielectric constant of 6 or more. Oxides or oxynitrides of hafnium are typical constituents of the high-K stack, along with thin transition layers to minimize surface states. On top of the gate dielectric, there is a metallic gate 25, and its composition is chosen for both its manufacturability and its work function. While TiN is a frequent choice, many other metals, alloys and metallic compounds can be used.

The gate structure is completed by a gate "handle" 26, which provides both electric contact and physical protection for the underlying metal gate 25. The gate handle 26 is typically formed from amorphous or polycrystalline silicon. The transistor structure is completed with sources and drains 29, which are heavily doped regions providing current paths to the active channel that can be induced in region 23 near the gate dielectric 24. There are a variety of approaches to forming the source and drain regions, like simple heavy doping with arsenic or phosphorus for NMOS, boron or indium for PMOS. Other approaches include adding epitaxial silicon or silicon-germanium to enhance the conductivity of the sources and drains 29 by making them thicker. The epitaxial germanium also inserts compressive strain and increases the performance of the p-channel transistors. Also, the sources and drains 29 may have their conductance enhanced by the addition of a layer of metal silicide, nickel silicide being frequently used. ¾

One way to realize the structure in Figure 2 is by a "Channel Last" process sequence. This is illustrated in the exemplary and non-limiting sequence of Figures 3A through 3L, which are a sequence of schematic cross sections having the same orientation as that of Figure 2. The series of steps shown in Figures 3A through 3L are intended to realize the improved transistor structure described hereinabove.

Figure 3A shows a substrate 30, and above that there is a buried oxide 31. Region 33 is single crystal silicon, typically between 10 nm and 30 nm thick, and in an embodiment of the invention is at least twice as thick as layer 331. For the purposes of the ongoing illustration, it will be assumed, without limiting the scope of the invention, to be 15 nm thick. (It should be noted that in conventional FDSOI this layer would be much thinner; for example for a 22 nm technology, the thickness would be 5 to 6 nm.) Ultimately, the extra thickness can be used to enhance the source and drain conductance. The silicon region 33 is defined in its extents by isolation 311. The boundaries between silicon 33 and isolation 311, as shown in Figure 3A, define the overall length of silicon required for the transistor, which comprises a source region, a channel region and a drain region, which are described in the succeeding illustrations herein below. Perpendicular to the plane of Figures 3A-3L, the silicon region 33 has a width of the channel width of the transistor. The silicon region 33 may be undoped, or it might be doped p-type for NMOS transistors or doped n-type for PMOS transistors. Typical maximum doping levels for the silicon 33 are 5 x 10¹⁸ ions/cm³ or even slightly higher. Above the silicon region 33, there is a layer of silicon dioxide 371. In a full process flow involving a variety of transistors, this oxide plays various roles. For the purposes of this explanation, it is referred to as a screen oxide. The thickness of this oxide is not critical for the present explanation, but it is assumed to be 3 nm thick, without limiting the scope of the invention. Overlying everything else there is a layer 351 of amorphous (preferably) or polycrystalline silicon. This layer is not to scale in the drawings, because it can range from 50 nm to 150 nm in thickness. Its thickness is not critical to the explanations that follow. These procedures are well known to practitioners of SOI semiconductor fabrication.

In Figure 3B the amorphous silicon layer 361 is selectively etched, using standard photo, electron beam or X-ray masking techniques to leave a sacrificial gate structure 352. As viewed in Figure 3B, the width of element 352 defines the eventual channel length of the thin film transistor. This procedure is well known to practitioners of SOI semiconductor fabrication.

Figure 3C shows the addition of an ion implantation 391. This implantation is typically known as a drain extension, and it is a very shallow implantation of donors, e.g., phosphorus, arsenic or antimony, for NMOS transistors or acceptors, e.g., boron BF₂ ⁺ or indium, for PMOS transistors. The dose in this implantation is in an intermediate range, preferably around 1 x 10¹⁴ ions/cm², and its energy is such that it is confined to a layer depth of 5 to 10 nm in the silicon. It should be noted that the implant is localized and excluded from the channel region by the masking effect of the sacrificial gate 352.

According to other details of the transistor design, this implant may be accompanied by other implants which are designed to mitigate short channel effects in conventional transistors. Besides the local definition by the sacrificial gate, drain extension implants are dedicated to specific classes of transistors by photoresist masking. These procedures are well known to practitioners of SOI semiconductor fabrication.

Figure 3D shows the deposition of dielectric layer 381. This layer is typically silicon nitride, and it may be deposited by either chemical vapor deposition (CVD) or plasma enhanced CVD. The latter process is preferred in order to preclude crystal growth in the sacrificial gate 352. This is the material that provides the spacers 18 and 28 shown in Figure 1 and Figure 2 respectively. This thickness of layer 381 will determine in large part the eventual width of the spacers. Typical thicknesses might range from 10 nm to 200 nm. This procedure is well known to practitioners in SOI semiconductor fabrication.

Figure 3E shows the effect of anisotropic etching of layer 381. Where the surface of layer 381 was flat, the material 381 is cleared, but where it covers a vertical surface, there is a wedge 38 of material left. This is commonly known as a gate spacer. This procedure is well known to practitioners in SOI semiconductor fabrication.

Figure 3F shows the addition of heavy source and drain implants 392. These implants are typically the heaviest implants in the process flow, and are of the order of 1 x 10¹⁵ ions/cm² or higher. The implants use phosphorus or arsenic for NMOS transistors and boron (sometimes as BF₂ ⁺) for PMOS transistors. Within each specific transistor, this implant is localized by the masking effect of the spacers 38 and the sacrificial gate 352. The dose and energy of this implant are typically tailored to assure that it reaches through the silicon 33 after activation. After this implant and other related implants are done, they are all activated by one of various rapid thermal annealing processes, e.g., tungsten halogen, xenon flash or laser heating. This procedure is well known to practitioners in SOI semiconductor fabrication.

Figure 3G shows the consequence of several steps. First, the screen oxide 371 is removed by either wet or dry etching except where it is protected by the spacers 38 and the sacrificial gate 352, leaving the remaining piece 372 of the screen oxide. After that a reactive metal, typically nickel is deposited, then heated to form a highly conductive metal- silicide layer 393. This is one typical method of enhancing the conductivity of the sources and drains 39 of the transistors. An alternative procedure, not otherwise illustrated here, involves using epitaxial growth on the surface characterized by label 393 to significantly increase the thickness and conductivity of the thin sources and drains. After the source and drain 39 conductivity enhancement is complete, a dielectric layer 385 is deposited, typically by plasma enhanced CVD. Layer 385 is the first interlayer dielectric. After deposition, layer 385 is planarized by chemical-mechanical polishing (CMP). This exposes the top of the sacrificial gate 352. These procedures are well known to practitioners in SOI semiconductor fabrication.

At this stage, as shown by Figure 3H, the sacrificial gate is selectively etched away, leaving a cavity identified as region 353. This step is commonly used in the class of processes known as "Gate Last' processes.

Figure 31 shows the creation of a recess in accordance with one embodiment. Using the first interlayer dielectric 385 and the spacers 38 as hard masks, the screen oxide 372 is etched through the cavity 353, leaving the residual sections 37 under the spacers 38. This clears the surface of the underlying silicon 33, which is subsequently etched in a controlled fashion to create the recess 332. Both of these etching steps are preferably done with anisotropic processes in order to carry the profile of the spacers 38 into the recess 332. The depth of the recess is part of the overall transistor design, but it can range from 5 nm to 15 nm. This discussion and the drawings assume a depth of 10 nm without limiting the scope of the invention.

In Figure 3J, by using a process like molecular beam epitaxy or atomic layer deposition, a very highly doped δ-layer 32 is deposited on the floor of the recess 332. This δ-layer 32 is intended to be extremely thin, for example in the order of 1-3 nm, and it will contain acceptors like boron or indium for NMOS transistor or donors like phosphorus, arsenic or antimony for PMOS transistors. In operation, this layer is fully depleted, meaning that the doping ions act electrically as a layer of charge. The exact amount of charge in the δ-layer 32 is a part of the transistor design because that charge is an important factor in controlling the short channel effects and setting the threshold voltage of the transistor. While a typical value of charge in the δ-layer 32 are 1 x 10¹³ e/cm² (where e is the magnitude of an electron's charge, about 1.6 x 10^"19 coulomb), that charge may range from 1 x 10¹² e/cm² to 3 x 10¹³ e/cm². For a 1 nm thick δ-layer 32, those values imply peak doping densities of 1 x 10 ions/cm to 3 x 10 ions/cm . For thicker layers, the peak doping densities are correspondingly less as the important factor in threshold determination is the amount of charge per square centimeter.

The next step in creating a Channel Last process is shown in Figure 3K. The recess 332 is refilled by epitaxially growing region 331, which is the channel region. Besides its crystalline integration with the surrounding silicon, there are two other critical factors about this epi region: 1) it must be grown at a very low temperature, preferably not exceeding 650°C; and, 2) it should have essentially zero doping, certainly not to exceed 1 x 10¹⁷ ions/cm³. The low temperature epi is important because the efficacy of this structure in reducing threshold voltage fluctuations is greatest when the boundary between high doping and zero doping is perfectly abrupt; high temperature processing softens that interface through thermal diffusion. The low doping in the epi layer is important because each time there is an ionized dopant in that region it causes a deviation of the threshold voltage from its nominal value.

While silicon is the most obvious material from which to epitaxially form region 331, other materials may be used. Silicon: germanium combinations are commonly used in advanced semiconductor devices, and even pure germanium is a possibility. Certain III-V compounds may grow satisfactorily in this small volume. Choice of material should not limit the scope of the invention disclosed herein.

The transistor is completed like any other "Gate Last" transistor as shown in Figure 3L. A High-K dielectric stack 34 is first deposited over the channel epitaxial layer 331. This stack may have one or more layers, and its effective dielectric constant is typically 6 or more. Its effective oxide thickness, a frequently used measure of electrical thickness, is typically 1 nm or less. Various compounds are employed in the High-K dielectric stack, but most include compounds of hafnium, as Hf0₂, HfON, HfLaO and others. The next layer in Figure 3L is a metal gate 35, which is formulated to achieve specific work functions in order to set the threshold voltage of the transistor. This layer is typically between 50 nm and 150 nm thick, and it may consist of one or more layers of metallic materials. One commonly used metallic material is TiN, but hafnium, ruthenium, TaN, MoN and WN also arise as candidates. The final material is a gate handle 36, which is typically amorphous silicon or poly-crystalline silicon. This material protects the underlying metal from chemical or mechanical damage. It also provides electrical connection to the metal gate 35. Once all of layers 34, 35 and 36 are deposited, it is normal to use CMP to restore the planar surface of the first interlayer dielectric 385. All of the steps associated with Figure 3L are well known to those of ordinary skill in the art.

It is well known that, subsequent to forming the structure shown in Figure 3L, other steps are necessary to complete the integrated circuit. These include adding a second interlayer dielectric, creating contacts, and adding multiple layers of metal interconnect. Such additional processing steps should not be viewed as departing from the scope of the invention.

Referring back to Figure 2, it should be recognized that the essential properties of this structure do not depend upon the specific materials used to fabricate the gate dielectric 24 or the gate electrode 25. While the description was written in the context of High-K Metal Gate technology because that is the prevalent materials strategy used in combination with Gate Last processing, other techniques may be used without departing from the scope of the invention. As long as the processing temperatures are kept low, for example but not by way of limitation, below 650°C and the processing times are kept short, minutes in aggregate, the gate dielectric 24 could be silicon dioxide or silicon oxynitride, and the gate electrode could be amorphous silicon.

Further, still considering Figure 2, the description hereinabove addresses an ideal case where layer 22 approximates a Dirac δ function in its doping profile, the underlying reason for calling it a δ-layer. However, the principles in this description can be applied by designing the transistor with greater thickness for layer 22, compensating the doping density to realize an appropriate level of charge per unit area and compensating the recess depth and low-doped epi thickness to maintain a charge-free region of several nanometers beneath the gate stack 24. Further, sufficient silicon 23 must be retained to seed good epitaxial growth.

At the other end of the process spectrum, eliminating the δ-layer 22 does not eliminate many of the advantages of this structure, but the threshold voltage is then determined by the charge associated with the underlying silicon film 23, particularly that amount of charge that resides between the bottom of the low doped epi layer 231 and the buried oxide 21. That number typically has a value in the low range, for example a few times 1 x 10¹² e/cm². Alternate embodiments are illustrated in Figure 4, and in Figures 5A thorough 5D and Figures 6A through 6D. In both instances, these alternate embodiments built on the initial processing illustrated in Figures 3A through 3H or its equivalent.

Figure 5A shows the cross-section after ion implantation that is used to create region 322. This implantation is masked from other parts of the transistor by the combination of the spacers 38 and the first interlayer dielectric 385. It goes through the screen oxide 372. This implant is typically designed to have its peak doping density at or near the boundary between the silicon 322 and buried oxide 31. For NMOS transistors the implanted ions will be acceptors like boron or indium. For PMOS transistors the implanted ions will be donors like phosphorus or arsenic. The dose of this implant is selected to realize a doping density between 5 x 10¹⁸ ions/cm³ and 1 x 10²⁰ ions/cm³ at the boundary with the buried oxide 31. This implant makes it possible to customize the threshold voltage of the transistors, so one class of transistor might receive a lighter implant, while another class, intended to have a threshold voltage of greater magnitude, receives a heavier implant. After all implants of this type are completed, they need to be activated. At this stage, with the silicide layer 393 in place, the activation has to be done with the least possible heating of the substrate. That typically means that fast laser activation is indicated, although other rapid thermal processes may be used without departing from the scope of the invention.

Figure 5B depicts a cross-section after etching into the implanted layer 322. After etching away the screen oxide 372, leaving just those portions 37 beneath the spacers 38, a recess 332 is etched to controlled depth between 5 nm and 15 nm. For the discussion here a depth of 10 nm will be assumed. Creating this recess is the first part of making this a "Channel Last" process. The sidewalls 38 act as hard masks to define the lateral extent of the etches illustrated in Figure 5B. Note that this etch eliminates any irregularities in the diffusion boundary between the drain extensions 39 and the eventual channel. The remaining silicon region 32 represents part of the seed region for the epitaxial growth in the next step, and it holds the charge that helps define the transistor's threshold voltage. In this example, it is 5 nm thick, so its effective charge is in a range from 2.5 x 10¹²/cm² to 5 x 10¹³/cm² for the peak doping density ranges cited above.

The next step in creating a Channel Last process is shown in Figure 5C. The recess 332 is refilled by epitaxially growing region 331, which is the channel region. Besides its crystalline integration with the surrounding silicon, there are two other critical factors about this epi region: 1) It must be grown at a very low temperature, preferably not exceeding 650°C, and 2) it should have essentially zero doping, certainly not to exceed 1 x 10¹⁷ ions/cm³. The low temperature epi is important because the efficacy of this structure in reducing threshold voltage fluctuations is greatest when the boundary between high doping and zero doping is perfectly abrupt; high temperature processing softens that interface through thermal diffusion. The low doping in the epi layer is important because each time there is an ionized dopant in that region it causes a deviation of the threshold voltage from its nominal value.

While silicon is the preferred constituent material of epitaxially formed region 331, other materials may be used. Silicon:germanium alloys are commonly used in advanced semiconductor devices, and even pure germanium is a possibility. Certain III-V compounds may also be grown satisfactorily in this small volume.

The transistor is completed like any other "Gate Last" transistor as shown in Figure 5D. A High-K dielectric stack 34 is first deposited over the channel epitaxial layer 331. This stack may have one or more layers, and its effective dielectric constant will be 6 or more. Its effective oxide thickness, a frequently used measure of electrical thickness, will be 1 nm or less. Various compounds are employed in the High-K dielectric stack, but most include compounds of hafnium, as Hf0₂, HfON, HfLaO and others. The next layer in Figure 5D is a metal gate 35, which is formulated to achieve specific work functions in order to set the threshold voltage. This layer is typically from 50 nm to 150 nm thick, and it may consist of one or more layers of metallic materials. One commonly used metallic material is TiN, but hafnium, ruthenium, TaN, MoN and WN also arise as candidates. The final material is a gate handle 36, which is typically amorphous or poly-crystalline silicon. This material protects the underlying metal from chemical or mechanical damage. After all of layers 34, 35 and 36 have been deposited, it is normal to use CMP to restore the planar surface of the first interlayer dielectric 385. All of the steps associated with Figure 5D are well known to practitioners of High-K, metal gate semiconductor science and engineering.

It is well known that, subsequent to forming the structure shown in Figure 5D, other steps are necessary to complete the integrated circuit. These include adding a second interlayer dielectric, creating contacts, and adding multiple layers of metal interconnect. The exemplary and non-limiting sequence of Figures 6A through 6D give an abbreviated explanation of an alternative method of creating the structure shown in Figures 4 and 5D. This approach delays the implant until after the recess is etched in the silicon layer.

Figure 6A shows the schematic cross section of the transistor after the sources and drains have been completely formed, the first interlayer dielectric has been deposited and planarized, and the sacrificial gate has been etched away. The components of Fig. 6A include the substrate 40, the buried oxide 41, isolation oxide regions 411, silicon film 421 in which the transistor is being formed, the cavity 453 from which the sacrificial gate has been removed, the screen oxide 472, sidewall spacers 48, first interlayer dielectric 485, source/drain regions 49 and source drain silicide 493.

Figure 6B shows the sacrificial oxide 472 etched to leave segments 47 under the spacers 48. Then the recess 432 is etched into the underlying silicon 421 to a controlled depth between 5 nm and 15 nm. It should be noted that this etch eliminates any irregularities in the diffusion boundary between the drain extensions 49 and the eventual channel.

Figure 6C shows the region beneath the recess 432 implanted with acceptors for NMOS transistors or donors for PMOS transistors. The fact that region 42 is so thin implies that the energy of this implant should be very low, so that the peak of the distribution lies within the that layer. As before the expected doping density is in the range of 5 x 10¹⁸ ions/cm³ to 1 x 10²⁰ ions/cm³. This implant makes it possible to customize the threshold voltage of the transistors. At this stage, the implant must be activated using the least possible wafer heating. Among the rapid thermal processing treatments available, laser activation is the most likely candidate.

In Figure 6D, the channel is formed by epitaxially growing zero-doped, certainly

17 3

less than 1 x 10 ions/cm , silicon, silicon.-germanium or other appropriate semiconductor to fill the recess forming region 431. It is important that this epitaxial layer is grown at a low temperature in order to preserve a very steep gradient between the heavily doped region 42 and the zero-doped region 43. Subsequent to completing the growth of the zero-doped region 431, the transistor is completed using the well-known "Gate Last" process sequence. This includes deposition of a high-K gate stack, deposition of a work-function controlled metallic layer, and deposition of a robust gate handle material. After CMP, a second interlayer dielectric, contacts and the interconnect structures complete the integrated circuit.

It will be appreciated that there are a variety of approaches to realizing a structure possessing the essential properties of the "Channel Last" SOI transistors described hereinabove. The resulting structure has a superior opportunity for threshold definition. For a given threshold voltage, it has a lower magnitude of threshold fluctuation due to random doping variations. Because most of the structure beneath the gate has no doping, it is possible to make the transistor film thicker than a uniformly doped, fully depleted structure. A thicker film means that the mechanical tolerances are somewhat relaxed and that the source and drain structures can have lower resistances. Because the drain edge is defined by the etch that creates a recess in the silicon, wide variations of effective channel length are avoided.

A person of ordinary skill-in-the-art would readily understand that the invention can be adapted for use in a plurality of ways, including integrated circuits where all transistors or a portion thereof are manufactured using the techniques disclosed hereinabove.

Furthermore, although the invention is described herein with reference to the preferred embodiments, one skilled-in-the-art will readily appreciate that other applications may be substituted for those set forth herein without departing from the spirit and scope of the present invention. Accordingly, the invention should only be limited by the claims included below.

Claims

CLAIMS What is claimed is:

1. A metal-oxide-semiconductor field effect transistor (MOSFET) comprising: a semiconductor on insulator (SOI) substrate having a semiconductor layer on an insulator layer, which insulator layer is on an underlying substrate;

a source region and a drain region formed in the semiconductor layer;

a semiconductor channel region separating the source and the drain regions, the semiconductor channel region having a doping ranging from undoped to less than 10¹⁷ doping ions/cm³;

the semiconductor channel region having substantially vertical sides, with the source and drain regions each having an edge region truncated by the vertical sides of the semiconductor channel region;

the semiconductor channel region having a thickness of between 5 nm to 15 nm; a gate dielectric over the semiconductor channel region; and,

a conductive gate region over the gate dielectric.

2. The MOSFET of claim 1 wherein the semiconductor channel region does not extend through the semiconductor layer to the insulator layer.

3. The MOSFET of claim 1 further comprising a δ-layer under the

semiconductor channel region having a doping that is greater than the doping of the semiconductor channel region.

4. The MOSFET of claim 3 wherein the δ-layer also does not extend through the semiconductor layer to the insulator layer.

5. The MOSFET of claim 3 wherein the doping in the δ-layer is one of:

acceptors for an N-type MOSFET and donors for a P-type MOSFET.

6. The MOSFET of claim 3, wherein the δ-layer is fully depleted at operational voltages of the MOSFET.

7. The MOSFET of claim 1 wherein the source and drain regions extend through the semiconductor layer to the insulator layer.

8. The MOSFET of claim 1, further comprising

a pair of passive spacers above the semiconductor layer, each having substantially vertical faces spaced apart and defining a length of the conductive gate region.

9. The MOSFET of claim 8, wherein the semiconductor channel region fills an etched recess in the semiconductor layer between the spacers.

10. The MOSFET of claim 9 wherein the semiconductor channel region is an epitaxially grown semiconductor region in the etched recess.

11. The MOSFET of claim 1 wherein the gate dielectric is one or more dielectric layers having an effective dielectric constant greater than 6.

12. The MOSFET of claim 11 wherein the conductive gate region is a metal gate region.

13. The MOSFET of claim 1 further comprising a doped layer under the semiconductor channel region having a doping that is greater than the doping of the semiconductor channel region and extending through the semiconductor layer to the insulator layer.

14. The MOSFET of claim 13 wherein the doping in the doped layer under the semiconductor channel region is one of: acceptors for an N-type MOSFET and donors for a P-type MOSFET.

15. The MOSFET of claim 13, wherein the doped layer under the semiconductor channel region is fully depleted at operational voltages of the MOSFET.

16. The MOSFET of claim 13 wherein the conductive gate region is a metal gate region.

17. A metal-oxide-semiconductor field effect transistor (MOSFET) comprising: a semiconductor on insulator (SOI) substrate having a silicon layer on an oxide layer, which oxide layer is on an underlying substrate;

a source region and a drain region extending through the semiconductor layer to the oxide layer;

an epitaxially grown semiconductor channel region truncating an edge of the source and the drain regions, the semiconductor channel region having a doping ranging from undoped to less than 10¹⁷ doping ions/cm³;

a δ-layer under the semiconductor channel region;

the semiconductor channel region having a thickness of between 5 nm to 15 nm and not extending through the semiconductor layer to the insulator layer;

a gate oxide over the semiconductor channel region; and,

a metal gate region over the gate dielectric.

18. The MOSFET of claim 17 wherein the δ-layer also does not extend through the semiconductor layer to the insulator layer.

19. The MOSFET of claim 17 wherein the doping in the δ-layer is one of:

acceptors for an N-type MOSFET and donors for a P-type MOSFET.

20. The MOSFET of claim 17, wherein the δ-layer is fully depleted at operational voltages of the MOSFET.

21. The MOSFET of claim 17, further comprising a pair of passive spacers above the semiconductor layer, each having substantially vertical faces spaced apart and defining a length of the conductive gate region.

22. The MOSFET of claim 21, wherein the semiconductor channel region fills an etched recess in the semiconductor layer between the spacers.

23. The MOSFET of claim 21 wherein the semiconductor channel region and the δ-layer fill an etched recess in the semiconductor layer between the spacers.

24. A metal-oxide-semiconductor field effect transistor (MOSFET) comprising: a semiconductor on insulator (SOI) substrate having a silicon layer on an oxide layer, which oxide layer is on an underlying substrate;

an epitaxially grown semiconductor channel region truncating an edge of the source and the drain regions, the semiconductor channel region having a doping ranging from undoped to not to exceed 10¹⁷ doping ions/cm³;

a doped layer under the semiconductor channel region having a doping that is greater than the doping of the semiconductor channel region and extending through the semiconductor layer to the insulator layer;

a gate oxide over the semiconductor channel region; and,

a metal gate region over the gate dielectric.

25. The MOSFET of claim 24 wherein the doping in the doped layer under the semiconductor channel is one of: acceptors for an N-type MOSFET and donors for a P-type MOSFET.

26. The MOSFET of claim 24, wherein the doped layer under the semiconductor channel is fully depleted at operational voltages of the MOSFET.

27. The MOSFET of claim 24, further comprising a pair of passive spacers above the semiconductor layer, each having substantially vertical faces spaced apart and defining a length of the conductive gate region.

28. The MOSFET of claim 24, wherein the semiconductor channel region fills an etched recess in the semiconductor layer between the spacers.

29. A method of forming a MOSFET comprising:

providing an underlying substrate with a buried oxide layer thereon and a first semiconductor layer on the buried oxide layer;

forming a sacrificial gate structure above a region designated to be the transistor channel;

creating source and drain structures comprising source and drain extensions, highly conductive source and drain regions contacting the source and drain extensions, respectively, and sidewall spacers adjacent the sacrificial gate;

etching away the sacrificial gate structure and any other materials to selectively expose the first semiconductor layer in the region between the sidewall spacers;

creating a recess in the first semiconductor layer between the sidewall spacers in anisotropic processes using the gate spacers as a mask, the recess truncating the source and drain extensions and not extending to the buried oxide layer;

epitaxially growing a semiconductor channel region in the recess;

depositing a dielectric stack over the epitaxially grown semiconductor channel region; and,

depositing a conductive gate over the dielectric stack;

wherein epitaxially growing a semiconductor channel region in the recess and all subsequent processes are low temperature processes not subjecting the MOSFET to temperatures exceeding 650°C.

30. The method of claim 29 further comprising depositing a second

semiconductor layer at the bottom of the recess before epitaxially growing the

semiconductor channel region in the recess, the second semiconductor layer being a δ-layer having a doping level higher than the doping level of the semiconductor channel region.

31. The method of claim 30 wherein the δ-layer also does not extend through the semiconductor layer to the insulator layer.

32. The method of claim 29 wherein the source and drain regions extend through the first semiconductor layer to the buried oxide layer.

33. The method of claim 29 further comprising depositing a conductive gate handle over the metal gate.

34. The method of claim 29 wherein the dielectric stack has an effective dielectric constant of at least 6.

35. The method of claim 29 wherein the metal gate is formulated for specific work functions to set the threshold voltage of the MOSFET.

36. The method of claim 35 wherein the semiconducting channel region is germanium or silicon-germanium.

37. The method of claim 29 wherein the doping in the δ-layer is one of:

acceptors for an N-type MOSFET and donors for a P-type MOSFET.

38. The method of claim 29 wherein the doping in the semiconductor channel region is in the range of undoped to less than 10¹⁷ doping ions/cm³.

39. The method of claim 29 wherein the semiconductor channel region is undoped.

40. The method of claim 29 wherein the first and second semiconductor layers and the semiconductor channel region are silicon.

41. A method of forming a MOSFET comprising:

providing a second oxide layer over the first semiconductor layer;

forming a sacrificial gate structure on the second oxide layer; implanting through the second oxide layer a source extension on one side of the sacrificial gate structure and a drain extension on a second side of the sacrificial gate structure opposite the first side of the sacrificial gate structure;

depositing a first dielectric layer over the top of the second oxide layer and the sacrificial gate structure;

anisotropically etching the first dielectric layer to form gate sidewall spacers;

implanting, through the second oxide layer, source and drain regions which connect to the source and drain extensions;

removing the exposed regions of the second oxide layer;

depositing a second dielectric layer over the second oxide layer, the gate spacers and the sacrificial gate structure;

etching away the sacrificial gate structure;

removing the second oxide layer between the gate spacers and creating a recess in the first semiconductor layer between the gate spacers by anisotropic processes using the gate spacers as a mask, the recess truncating the source and drain extensions and not extending to the buried oxide layer;

depositing a second semiconductor layer having a first doping level at the bottom of the recess, the second semiconductor layer being a δ-layer;

epitaxially growing a semiconductor channel region in the recess over the second semiconductor layer, the epitaxial channel region having a second doping level lower than the first doping level;

depositing a metal gate over the dielectric stack;

the epitaxially growing a semiconductor channel region in the recess over the second semiconductor layer and all succeeding steps being low temperature processes not subjecting the MOSFET to temperatures exceeding 650°C.

42. A method of forming a MOSFET comprising:

forming a sacrificial gate structure above a region designated to be the transistor channel; creating source and drain structures in the first semiconductor layer comprising source and drain extensions, sidewall spacers adjacent the sacrificial gate, and highly conductive source and drain regions contacting the source and drain extensions, respectively;

etching away the sacrificial gate structure;

implanting in the first semiconductor layer aligned with and below the sidewall spacers, a doped region adjacent and extending to the buried oxide layer;

epitaxially growing a semiconductor channel region in a recess in the first semiconductor layer over the doped region of a first doping level that extends to the buried oxide layer, the recess being formed by anisotropic processes using the gate spacers as a mask;

depositing a conductive gate over the dielectric stack;

43. The method of claim 42 wherein forming in the first semiconductor layer aligned with and below the sidewall spacers, a doped region adjacent and extending to the buried oxide layer comprises forming the doped region by ion implantation using the sidewall spacers as a mask, and etching away part of the first semiconductor layer by an anisotropic process using the gate spacers as a mask.

44. The method of claim 43 wherein implanting of the doped region in the first semiconductor layer aligned with and below the sidewall spacers precedes the etching away part of the first semiconductor layer by an anisotropic process using the gate spacers as a mask.

45. The method of claim 43 wherein the implanting of the doped region by ion implantation using the sidewall spacers as a mask follows the etching away part of the first semiconductor layer by an anisotropic process using the gate spacers as a mask.

46. The method of claim 42 wherein etching away the sacrificial gate structure includes etching a recess in the first semiconductor layer using the sidewall spacers as a mask, the recess not extending to the buried oxide layer, and wherein the doped region adjacent and extending to the buried oxide layer is formed by implantation after the recess is formed.

47. The method of claim 42 wherein the source and drain regions extend through the first semiconductor layer to the buried oxide layer.

48. The method of claim 47 wherein the dielectric stack has an effective dielectric constant of at least 6.

49. The method of claim 42 further comprising depositing a conductive gate handle over the metal gate.

50. The method of claim 42 wherein the metal gate is formulated for specific work functions to set the threshold voltage of the MOSFET.

51. The method of claim 50 wherein the semiconductor channel region is germanium or silicon-germanium.

52. The method of claim 42 wherein the doping in the doped region adjacent and extending to the buried oxide layer is one of: acceptors for an N-type MOSFET and donors for a P-type MOSFET.

53. The method of claim 42 wherein the doping in the semiconductor channel region is in the range of undoped to not exceeding 10¹⁷ doping ions/cm³.

54. The method of claim 42 wherein the semiconductor channel region is undoped.

55. The method of claim 42 wherein the first semiconductor layer and the semiconductor channel region are silicon.

56. A method of forming a MOSFET comprising:

providing a second oxide layer over the first semiconductor layer;

forming a sacrificial gate structure on the second oxide layer;

implanting through the second oxide layer a source extension on one side of the sacrificial gate structure and a drain extension on a second side of the sacrificial gate structure opposite the first side of the sacrificial gate structure;

removing the exposed regions of the second oxide layer;

etching away the sacrificial gate structure;

epitaxially growing a semiconductor channel region in a recess in the first semiconductor layer over the doped region adjacent that extends to the buried oxide layer, the recess being formed by anisotropic processes using the gate spacers as a mask, the epitaxial channel region having a second doping level lower than the first doping level; depositing a dielectric stack over the epitaxially grown semiconductor channel region; and,

depositing a metal gate over the dielectric stack;

57. The method of claim 56 wherein implanting of the doped region in the first semiconductor layer aligned with and below the sidewall spacers precedes the etching away part of the first semiconductor layer by an anisotropic process using the gate spacers as a mask.

58. The method of claim 56 wherein the implanting of the doped region by ion implantation using the sidewall spacers as a mask follows the etching away part of the first semiconductor layer by an anisotropic process using the gate spacers as a mask.