CN105900241B - 包括超晶格耗尽层堆叠的半导体装置和相关方法 - Google Patents

包括超晶格耗尽层堆叠的半导体装置和相关方法 Download PDF

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CN105900241B
CN105900241B CN201480071521.4A CN201480071521A CN105900241B CN 105900241 B CN105900241 B CN 105900241B CN 201480071521 A CN201480071521 A CN 201480071521A CN 105900241 B CN105900241 B CN 105900241B
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CN105900241A (zh
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R·J·梅尔斯
武内秀木
E·特洛特曼
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Atomera Inc
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Abstract

一种半导体装置，所述半导体装置可以包括：衬底上交替的超晶格层和体半导体层的堆叠，每个超晶格层包括多个堆叠的层组，所述超晶格层的每个层组包括限定基础半导体部分的多个堆叠的基础半导体单层和约束在相邻的基础半导体部分的晶格内的至少一个非半导体单层。所述半导体装置可以进一步包括在所述交替的超晶格层和体半导体层的堆叠的上部体半导体层中的间隔开的源极区和漏极区，以及在间隔开的源极区和漏极区之间，在所述上部体半导体层上的栅极，和延伸穿过体层和超晶格层并进入衬底的STI区，并且可以用交替的掺杂剂导电类型对体层进行掺杂。

Description

包括超晶格耗尽层堆叠的半导体装置和相关方法
技术领域
本申请涉及半导体领域，并且更具体地，涉及包含超晶格的半导体装置和相关方法。
背景技术
已经提出了结构和技术来增强半导体装置的性能，比如通过增强电荷载流子的迁移率来增强半导体装置的性能。例如，Currie等人的美国专利申请No.2003/0057416公开了硅的应变材料层、硅-锗以及松弛硅并且还包括无杂质区域(否则将会引起性能退化)。上部硅层中产生的双轴应变改变载流子迁移率，从而允许较高速和/或较低功耗装置。Fitzgerald等人的已公布的美国专利申请No.2003/0034529公开了同样基于类似应变硅技术的CMOS反相器。
Takagi的美国专利No.6,472,685B2公开了一种半导体装置，该半导体装置包括夹于硅层间的硅碳层，以使得第二硅层的导带和价带受到拉伸应变。具有较小的有效质量并且已被施加到栅极电极的电场感应的电子被限制在第二硅层中，因此，可以肯定n沟道MOSFET具有更高的迁移率。
Ishibashi等人的美国专利No.4,937,204公开了一种超晶格，其中多层(少于8个单层，且包含部分或双金属半导体层或二元化合物半导体层)交替地并且外延地生长。主电流流动方向垂直于超晶格层。
Wang等人的美国专利No.5,357,119公开了具有通过减少超晶格中的合金散射获得的较高迁移率的硅-锗短周期超晶格。按照这些原则，Candelaria的美国专利No.5,683,934公开了包括沟道层的增强迁移率MOSFET，该沟道层包含硅和在硅晶格中以一定比例替代性出现的第二材料的合金，这将沟道层置于拉伸应力下。
Tsu的美国专利No.5,216,262公开了包括两个势垒区和夹于势垒之间的薄外延生长的半导体层的量子阱结构。每个势垒区包括厚度通常在2到6个单层范围内的交替的SiO2/Si层。硅的更厚部分夹于势垒之间。
同样Tsu于2000年9月6日在Appllied Physics and Materials Science &Processing的第391-402页在线发表的题目为“Phenomena in silicon nanostructuredevices”的文章公开了硅和氧的半导体-原子超晶格(SAS)。Si/O超晶格被公开为在硅量子以及发光装置中是有用的。具体地，构建和测试了绿色电致发光二极管结构。二极管结构中电流流动是垂直的，即垂直于SAS层。公开的SAS可以包括由吸附物(诸如氧原子、以及CO分子)分开的半导体层。在吸收的氧单层上硅的生长被描述为具有相当低缺陷密度的外延。一个SAS结构包括1.1nm厚的硅部分(即，大约8个硅原子层)以及具有两倍于此硅厚度的另一个结构。Luo等人在Physics Review Letters，Vol.89，No.7(2002年8月12日)发表的题目为“Chemical Design of Direct-Gap Light-Emitting Silicon”的文章进一步讨论了Tsu的发光SAS结构。
Wang、Tsu和Lofgren的已公开的国际申请WO 02/103,767A1公开了薄硅和氧、碳、氮、磷、锑、砷或者氢的势垒构成块，从而使垂直地流过晶格的电流降低了超过四个量级。绝缘层/势垒层允许低缺陷外延硅接着沉积到绝缘层。
Mears等人的已公开的英国专利申请2,347,520公开了非周期性光子带隙(APBG)结构的原理可能适合于电子带隙工程。具体地，该申请公开了可以设定材料参数(例如，能带极小值的位置、有效质量等等)来产生具有期望的能带结构特性的新非周期性材料。还公开了可以对材料进行设计的其它参数(诸如电导率、热导率和介电常数或者磁导率)。
尽管由这些结构提供了优势，但是用于在各种半导体装置中集成先进半导体材料的进一步的发展可能是希望的。
发明内容
一种用于制备半导体装置的方法，所述方法可以包括：在衬底上形成交替的超晶格层和体半导体层的堆叠，每个超晶格层包括多个堆叠的层组，并且超晶格层的每个层组包括限定基础半导体部分的多个堆叠的基础半导体单层和约束在相邻的基础半导体部分的晶格内的至少一个非半导体单层。所述方法还可以包括在交替的超晶格层和体半导体层的堆叠的上部体半导体层中形成间隔开的源极区和漏极区，并且在间隔开的源极区和漏极区之间，在上部体半导体层上形成栅极。
更具体地，所述方法可以进一步包括形成延伸穿过所述交替的超晶格层和体半导体层的堆叠并进入所述衬底的至少一个浅沟槽隔离(STI)区。此外，所述方法还可以包括以交替的掺杂剂导电类型对相应的超晶格之间的体层进行掺杂。
通过示例，每个基础半导体部分可以包含硅、锗等。同样通过示例，所述至少一个非半导体单层包含选自包括氧、氮、氟和碳-氧的组的非半导体。形成所述栅极可以包括在所述间隔开的源极区和漏极区之间，在所述上部体半导体层上形成氧化物层，以及形成覆在所述氧化物层上的栅极电极。此外，来自相对的基础半导体部分的至少一些半导体原子通过其间的所述非半导体层可以被化学地束缚在一起。
相关的半导体装置可以包括：衬底上交替的超晶格层和体半导体层的堆叠，每个超晶格层包括多个堆叠的层组，并且所述超晶格层的每个层组包括限定基础半导体部分的多个堆叠的基础半导体单层和约束在相邻的基础半导体部分的晶格内的至少一个非半导体单层。所述半导体装置可以进一步包括在交替的超晶格层和体半导体层的堆叠的上部体半导体层中的间隔开的源极区和漏极区，以及在间隔开的源极区和漏极区之间，在所述上部体半导体层上的栅极。
附图说明
图1是根据本发明的用于在半导体装置中使用的超晶格的高倍放大的示意性截面图。
图2是图1中示出的超晶格的一部分的透视示意性原子图。
图3是根据本发明的超晶格的另一个实施例的高倍放大的示意性截面图。
图4A是对现有技术中的体硅和图1-2中示出的4/1 Si/O超晶格两者从伽马点(G)计算的能带结构的图表。
图4B是对现有技术中的体硅和图1-2中示出的4/1 Si/O超晶格两者从Z点计算的能带结构的图表。
图4C是对现有技术中的体硅和图3中示出的5/1/3/1 Si/O超晶格两者从伽马点和Z点计算的能带结构的图表。
图5是根据示例实施例的包括超晶格耗尽层堆叠的平面CMOS装置的截面图。
图6-8是例示制备图5的平面CMOS装置的方法的一系列截面图。
图9是对应于图5-8中例示的工艺步骤的流程图。
具体实施方式
现在将参考附图在下文中更完整地描述本发明，附图中示出了本发明的优选实施例。然而，本发明可以以多种不同形式来体现并且不应该解释为局限于本文阐述的实施例。相反，提供这些实施例以使得本公开将是透彻且完整的，并且将向本领域技术人员完整地传达本发明的范围。同样的附图标记始终指代同样的要素，并且主要符号被用来指示不同实施例中的类似要素。
本发明涉及在原子或分子层面控制半导体材料的性质。进一步地，本发明涉及用于在半导体装置中使用的改进材料的确定、创造以及使用。
申请人从理论上阐明(但不希望束缚于此)本文描述的特定超晶格降低了电荷载流子的有效质量，并且这从而导致更高的电荷载流子迁移率。在文献中，用各种定义来描述有效质量。作为有效质量的改进的测量，申请人分别针对电子和空穴使用“电导率倒数有效质量张量(conductivity reciprocal effective mass tensor)”Me -1和Mh -1，对于电子定义为：
Figure GDA0001982264130000051
以及对于空穴定义为：
Figure GDA0001982264130000052
其中f是费米狄拉克分布，EF是费米能级，T是温度，E(k，n)是电子在与波矢k和第n个能带对应的态中的能量，下标i和j指的是笛卡尔坐标系x、y、z，在布里渊区(B.Z.)进行积分，并且分别对于电子和空穴的能量在费米能级以上或以下的能带进行求和。
申请人对电导率倒数有效质量张量的定义使得材料的电导率的张量分量比电导率倒数有效质量张量的相应分量的较大值更大。再次，申请人从理论上阐明(但不希望束缚于此)本文描述的超晶格设置电导率倒数有效质量张量的值以便增强材料的导电性质(诸如一般针对电荷载流子输运的优选方向)。适当张量参数元(appropriate tensorelement)的逆也被称为电导率有效质量。换句话说，为了表征半导体材料结构，使用如上描述并在预期的载流子输运方向上计算的电子/空穴的电导率有效质量来区分改进的材料。
申请人已经确认了用于在半导体装置中使用的改进的材料或结构。更具体地，申请人已经确认了具有电子和/或空穴的适当的电导率有效质量比硅的相应值小得多的能带结构的材料或结构。除这些结构的增强的迁移率特性之外，如将会在下面进一步讨论的，还可以以它们提供压电、热电、和/或铁电的性质这样的方式来形成或使用它们，这些性质对于用在很多不同类型的装置中是有益的。
现在参照图1和2，材料或结构以超晶格25的形式，超晶格25的结构被在原子或分子层面控制并且可以使用已知的原子或分子层沉积的技术来形成。超晶格25包括以堆叠关系布置的多个层组45a-45n，也许具体参考图1的示意性截面图能最好理解。
超晶格25的每个层组45a-45n例示性地包括限定相应的基础半导体部分46a-46n的多个堆叠的基础半导体单层46和其上的能带修改层50。为了清晰地例示，通过图1中的点画指示能带修改层50。
能带修改层50例示性地包括约束在相邻的基础半导体部分的晶格内的一个非半导体单层。“约束在相邻的基础半导体部分的晶格内”意味着：来自相对的基础半导体部分46a-46n的至少一些半导体原子通过其间的非半导体单层50被化学地束缚在一起，如图2所示。如下面将进一步讨论的，一般来说，通过原子层沉积技术来控制沉积在半导体部分46a-46n上的非半导体材料的量以使得不是所有可用的半导体键合位点(即，小于全部或100％覆盖)被到非半导体原子的键占据，可以实现这种配置。因此，随着半导体材料的另外单层46沉积在非半导体单层50上或之上，新沉积的半导体原子将会占据在非半导体单层之下的半导体原子的其余空位键合位点。
在其它实施例中，可以是多于一个这样的非半导体单层。应该注意，在此对非半导体或半导体单层的引述意味着：用于该单层的材料以体形成则会是非半导体或半导体。也就是说，本领域技术人员将意识到，诸如硅的材料的单个单层可能并不必然展现出与它形成为体或相对厚的层的情况下的相同的性质。
申请人从理论上阐明(但不希望束缚于此)：能带修改层50和相邻的基础半导体部分46a-46n使得超晶格25在平行层的方向上对于电荷载流子具有比以其它方式出现的低的适当电导率有效质量。以另一种方式考虑，该平行方向与堆叠方向是正交的。能带修改层50还可以使得超晶格25具有常见能带结构，同时还有益地起在垂直地位于超晶格之上和之下的层或区之间的绝缘体的作用。
此外，该超晶格结构还可以有益地作为对在垂直地位于超晶格25之上和之下的层之间的掺杂剂和/或材料扩散的阻挡物。本领域技术人员将意识到，这些性质可以因此有益地允许超晶格25提供针对高K电介质的界面，该界面不仅减少高K材料扩散进入沟道区，而且还可以有益地降低不期望的散射效应并且改进装置迁移率。
还可以从理论上阐明，包括超晶格25的半导体装置基于比以其它方式存在的更低的电导率有效质量，可以享有更高的电荷载流子迁移率。在一些实施例中，作为由本发明获得的能带工程的结果，超晶格25可以进一步具有基本上直接带隙，这例如对光电装置尤其有益。
超晶格25还例示性地包括在上部层组45n上的帽层52。该帽层52可以包含多个基础半导体单层46。帽层52可以具有2到100个基础半导体的单层，并且，更优选地具有10到50个单层。
每个基础半导体部分46a-46n可以包含选自包括IV族半导体、III-V族半导体以及II-VI族半导体的组的基础半导体。当然，本领域技术人员将意识到，术语“IV族半导体”还包括IV-IV族半导体。更具体地，例如，基础半导体可以包括硅和锗中的至少一种。
例如，每个能带修改层50可以包含选自包括氧、氮、氟、碳和碳-氧的组的非半导体。该非半导体通过下一层的沉积是合乎期望地热稳定的，从而促进制造。在其它实施例中，非半导体可以是与给定半导体工艺相兼容的另外的无机或有机的元素或化合物，如本领域技术人员将意识到的。更具体地，例如，基础半导体可以包含硅和锗中的至少一种。
应该注意的是，术语“单层”意在包括单原子层以及单分子层。还需注意的是，由单个单层提供的能带修改层50也意在包括其中不是所有可能的位点都被占据(即，少于全部或100％覆盖)的单层。例如，特别参考图2的原子图示，例示了用于硅作为基础半导体材料和氧作为能带修改材料的4/1重复结构。在例示的示例中，用于氧的可能位点只有一半被占据。
在其它实施例和/或以不同的材料，这种一半占据将不一定会是本领域技术人员将会意识到的情况。事实上，甚至在这个示意图中也可以看到，给定单层中的个体氧原子并没有如原子沉积的领域的普通技术人员将意识到的那样精确地沿着平面对齐。举例来说，优选的占据范围是从可能的氧位点被占满的大约八分之一到一半，尽管在其它特定实施例中可以使用其它数字。
当前在传统半导体工艺中广泛使用硅和氧，并且因此，制造商们很容易能够使用本文描述的这些材料。原子或单层沉积现在同样被广泛使用。因此，本领域技术人员将意识到，根据本发明的包含超晶格25的半导体装置可以非常容易被采纳和实施。
申请人从理论上阐明(但不希望被束缚于此)，对于超晶格(诸如Si/O超晶格)，例如，硅单层的数量理想地应该是7或者更小以便超晶格的能带始终是一致或者相对均匀的，以获得期望的优点。图1和2中示出的Si/O的4/1重复结构已经被模型化来指示电子和空穴在X方向的增强的迁移率。例如，电子的计算的电导率有效质量(对于体硅，各向同性)是0.26，且对于4/1Si/O超晶格它在X方向上是0.12，得到了0.46的比率。类似地，对于空穴的计算，对体硅产生了0.36的值以及对4/1Si/O超晶格产生0.16的值，得到了0.44的比率。
尽管这种方向性优选特征在某些半导体装置中可能是期望的，但是其它装置可能得益于在任何平行于层组的方向上的迁移率更加均匀地增加。本领域技术人员将意识到，具有对于电子和空穴两者或者仅仅这些类型的电荷载流子的一种的迁移率的增大也可以是有益的。
对于超晶格25的4/1 Si/O实施例的较低电导率有效质量可以比以其它方式发生的电导率有效质量的2/3小，并且这适用于电子和空穴两者。当然，本领域技术人员将意识到，超晶格25可以进一步包含至少一种类型的导电性掺杂剂。
事实上，现在附加地参考图3，现在描述根据本发明的具有不同性质的超晶格25’的另一个实施例。在这个实施例中，例示了3/1/5/1的重复模式。更具体地，最低的基础半导体部分46a’具有三个单层，并且第二低的基础半导体部分46b’具有5个单层。在超晶格25’中始终以这个模式重复。能带修改层50’各自可以包括单个单层。对于这样的包括Si/O的超晶格25’，电荷载流子迁移率的增强独立于在层平面的取向。图3中未特别提到的那些其它项与以上参照图1讨论的项类似，并且不需要在此进一步的讨论。
在一些装置实施例中，超晶格的所有基础半导体部分可以是相同数量的单层那样厚。在其它实施例中，至少一些基础半导体部分可以是不同数量的单层那样厚。在另外的其它实施例中，所有的基础半导体部分可以是不同数量的单层那样厚。
在图4A-4C中，呈现了使用密度泛函理论(DFT)计算的能带结构。在本领域众所周知，DFT低估了带隙的绝对值。因此带隙之上的所有能带可以被移动适当的“剪刀修正(scissors correction)”。然而，已知能带的形状是可靠得多的。应该考虑此来解释垂直能量轴。
图4A示出了对体硅(由连续线表示)和图1示出的4/1Si/O超晶格25(由虚线表示)从伽马点(G)计算的能带结构。各方向涉及4/1Si/O结构的单元晶胞而不是传统的硅晶胞，尽管图中的(001)方向确实对应于传统硅单元晶胞的(001)方向，并因此，示出了硅导带最小值的期望位置。图中的(100)和(010)方向对应于传统硅单元晶胞的(110)和(-110)方向。本领域技术人员将会意识到，图中硅的能带被折叠以将它们表示在4/1Si/O结构的适当倒格子方向上。
可以看到，4/1 Si/O结构的导带最小值位于的伽马点处，与体硅(Si)形成对照，而价带最小值发生在(001)方向上布里渊区的边缘(我们称之为Z点)处。还应该注意到，相比于硅导带最小值的曲率，4/1 Si/O结构的导带最小值的曲率更大，这是因为由附加的氧层引入的扰动导致的能带分裂。
图4B示出了对体硅(连续线)和4/1 Si/O超晶格25(虚线)两者从Z点计算的能带结构。这个图例示了(100)方向上价带的增强的曲率。
图4C示出了对体硅(连续线)和图3的超晶格25’的5/1/3/1 Si/O结构(虚线)两者从伽马点和Z点计算的能带结构。由于5/1/3/1 Si/O结构的对称性，在(100)和(010)方向计算的能带结构是等价的。因此，预期电导率有效质量和迁移率在平行于层的平面(即，垂直于(001)堆叠方向)中是各向同性的。注意，在5/1/3/1 Si/O示例中，导带最小值和价带最大值两者都在Z点处或者靠近Z点。
尽管增大的曲率是降低的有效质量的指示，但是也可以通过电导率倒数有效质量张量的计算来取得合适的对比和区别。这使得申请人进一步从理论上阐明：5/1/3/1超晶格25’应该大体上是直接带隙的。本领域技术人员将会理解，光跃迁的合适的矩阵元是直接和非直接带隙行为之间差别的另一个指示。
使用上述手段，可以为特定的目的选择具有改进的能带结构的材料。更具体地参照图5，多个超晶格材料层125可以用在半导体装置100中，半导体装置100在示出的示例中是CMOS装置(具有在左侧的PMOS晶体管和在右侧的NMOS晶体管)，从而在PMOS晶体管的源极106、漏极107和沟道区108下面以及在NMOS晶体管的源极109、漏极110和沟道区111下面的硅衬底105上形成相应的“准-BOX”结构。更具体地，每个准-BOX包含一系列垂直间隔开的超晶格层125，体半导体材料(例如，硅)的区或层112-115堆叠在超晶格层125之间并具有交替的掺杂类型。在例示性示例中，NMOS堆叠包括衬底105上的底部超晶格层125、底部超晶格层上的N型硅层114、N型硅层上的中间超晶格层、中间超晶格层上的P型硅层115以及P型硅层上的上部超晶格层。如图所示，对于PMOS堆叠，P型硅层112在底部上且N型硅层113在顶部上。
如上所述，其中限定了沟道区108、111和源极区106、109以及漏极区107、110的上部半导体层116(图6)可以有利地在上部超晶格125上外延生长。然而，如果需要的话，在一些实施例中，沟道可以部分或全部地驻留在上部超晶格层中。本领域技术人员将意识到，这种准-BOX堆叠可以概念性地被考虑来执行与埋氧(BOX)层类似的功能，但是在此，准-BOX堆叠提供了嵌入的PN结来为沟道区108、111的进一步电隔离提供耗尽层的额外利益。准-BOX耗尽层堆叠可以因此被用在各种应用中，例如，在部分耗尽(PD)或全耗尽(FD)SOI实现中作为对SOI或BOX层的替换。
用于制备半导体装置100的示例方法将参照图6-9来描述。开始于块201，在块201，可以在硅衬底105上形成多个毯状超晶格层125，超晶格层125之间形成有层间外延硅层117。在块202，然后可以执行STI模块以形成NMOS和PMOS晶体管之间的STI区120。本领域技术人员将会意识到，STI工艺可以包括，例如，在期望位置刻蚀穿过三个超晶格层125的沟槽、衬垫氧化、衬里氧化、致密化退火以及牺牲氧化。在块203，然后可以执行阱注入模块来在超晶格层125之间的半导体层112-115中注入相应的P或N型掺杂剂，接着在合适时进行退火(例如，快速热退火(RTA))。在块204-205，该方法可以进一步包括栅极的形成和源极106、109以及漏极107、110的注入，如本领域技术人员将会意识到的。每个栅极例示性地包括覆在相应的沟道区108、111中每一个上、在源极区和漏极区106、107和109、110之间的氧化物层121以及在每个氧化物层上的栅极电极层122。
应该注意的是，虽然在本文阐述的示例中提供了特定参数(例如，尺寸等)和材料，但本领域技术人员将意识到，可以在不同实施例中使用其它合适的参数和材料。例如，耗尽层堆叠或准-BOX不需要在NMOS和PMOS装置中都使用(例如它可以在一个或另一个中使用)。此外，堆叠中可以包括多于一个的PN结。即，若需要的话，附加的超晶格125和掺杂的半导体层可以被包括在堆叠中。
得益于前面描述和相关附图呈现的教导，本领域技术人员会想到多种修改和其它实施例。因此，应该理解，本发明不限制于所公开的具体实施例，并且那些修改和实施例意在包括在所附权利要求的范围内。

Claims (18)

1.一种用于制备半导体装置的方法，所述方法包括：
在衬底上形成交替的超晶格和体半导体层的堆叠，每个超晶格层包括多个堆叠的层组，超晶格层的每个层组包括限定基础半导体部分的多个堆叠的基础半导体单层和约束在相邻的基础半导体部分的晶格内的至少一个非半导体单层；
以交替的掺杂剂导电类型对相应的超晶格之间的体半导体层进行掺杂而限定p-n结，其中相邻的经掺杂的体半导体层具有不同的导电类型，并且每个体半导体层与在该体半导体层上方和下方的超晶格直接接触；
在所述交替的超晶格和体半导体层的堆叠的上部体半导体层中形成间隔开的源极区和漏极区；以及
在所述间隔开的源极区和漏极区之间的所述上部体半导体层上形成栅极，并且在所述源极区和漏极区之间且在所述p-n结上方限定耗尽沟道；
其中交替的超晶格和经掺杂的体半导体层的堆叠被配置为在所述沟道和所述衬底之间提供电隔离。
2.根据权利要求1所述的方法，进一步包括形成延伸穿过所述交替的超晶格和体半导体层的堆叠并进入所述衬底的至少一个浅沟槽隔离STI区。
3.根据权利要求1所述的方法，其中每个基础半导体部分包含硅。
4.根据权利要求1所述的方法，其中每个基础半导体部分包含锗。
5.根据权利要求1所述的方法，其中所述至少一个非半导体单层包含氧。
6.根据权利要求1所述的方法，其中所述至少一个非半导体单层包含选自包括氧、氮、氟和碳-氧的组的非半导体。
7.根据权利要求1所述的方法，其中形成所述栅极包括在所述间隔开的源极区和漏极区之间的所述上部体半导体层上形成氧化物层，以及形成覆在所述氧化物层上的栅极电极。
8.根据权利要求1所述的方法，其中来自每个超晶格层的相对的基础半导体部分的至少一些半导体原子通过其间的非半导体层被化学地束缚在一起。
9.一种半导体装置，包括：
衬底上交替的超晶格和体半导体层的堆叠，每个超晶格层包括多个堆叠的层组，超晶格层的每个层组包括限定基础半导体部分的多个堆叠的基础半导体单层和约束在相邻的基础半导体部分的晶格内的至少一个非半导体单层，相应的超晶格之间的体半导体层被用交替的掺杂剂导电类型进行掺杂而限定p-n结，其中相邻的经掺杂的体半导体层具有不同的导电类型，并且每个体半导体层与在该体半导体层上方和下方的超晶格直接接触；
在所述交替的超晶格和体半导体层的堆叠的上部体半导体层中的间隔开的源极区和漏极区；以及
栅极，在所述间隔开的源极区和漏极区之间的所述上部体半导体层上，并且在所述源极区和漏极区之间且在所述p-n结上方限定耗尽沟道；
其中交替的超晶格和经掺杂的体半导体层的堆叠被配置为在所述沟道和所述衬底之间提供电隔离。
10.根据权利要求9所述的半导体装置，进一步包括延伸穿过所述交替的超晶格和体半导体层的堆叠并进入所述衬底的至少一个浅沟槽隔离STI区。
11.根据权利要求9所述的半导体装置，其中每个基础半导体部分包含硅。
12.根据权利要求9所述的半导体装置，其中每个基础半导体部分包含锗。
13.根据权利要求9所述的半导体装置，其中所述至少一个非半导体单层包含氧。
14.根据权利要求9所述的半导体装置，其中所述至少一个非半导体单层包含选自包括氧、氮、氟和碳-氧的组的非半导体。
15.根据权利要求9所述的半导体装置，其中所述栅极包括：在所述间隔开的源极区和漏极区之间的所述上部体半导体层上的氧化物层，以及覆在所述氧化物层上的栅极电极。
16.根据权利要求9所述的半导体装置，其中来自相对的基础半导体部分的至少一些半导体原子通过其间的非半导体单层被化学地束缚在一起。
17.一种半导体装置，包括：
衬底上交替的超晶格和体半导体层的堆叠，每个超晶格层包括多个堆叠的层组，超晶格层的每个层组包括限定基础硅部分的多个堆叠的基础硅单层和约束在相邻的基础硅部分的晶格内的至少一个氧单层，相应的超晶格之间的体半导体层被用交替的掺杂剂导电类型进行掺杂而限定p-n结，其中相邻的经掺杂的体半导体层具有不同的导电类型，并且每个体半导体层与在该体半导体层上方和下方的超晶格直接接触；
在交替的超晶格和体硅层的堆叠的上部体硅层中的间隔开的源极区和漏极区；以及
栅极，在所述间隔开的源极区和漏极区之间的所述上部体硅层上，并且在所述源极区和漏极区之间且在所述p-n结上方限定耗尽沟道；
其中交替的超晶格和经掺杂的体半导体层的堆叠被配置为在所述沟道和所述衬底之间提供电隔离。
18.根据权利要求17所述的半导体装置，进一步包括延伸穿过所述交替的超晶格和体硅层的堆叠并进入所述衬底的至少一个浅沟槽隔离STI区。
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