CN112074959A - 用于制造包括超晶格的倒t形沟道场效应晶体管(itfet)的器件和方法 - Google Patents

用于制造包括超晶格的倒t形沟道场效应晶体管(itfet)的器件和方法 Download PDF

Info

Publication number
CN112074959A
CN112074959A CN201980029269.3A CN201980029269A CN112074959A CN 112074959 A CN112074959 A CN 112074959A CN 201980029269 A CN201980029269 A CN 201980029269A CN 112074959 A CN112074959 A CN 112074959A
Authority
CN
China
Prior art keywords
semiconductor
superlattice
group
inverted
base semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201980029269.3A
Other languages
English (en)
Inventor
R·J·史蒂芬森
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Atomera Inc
Original Assignee
Atomera Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atomera Inc filed Critical Atomera Inc
Publication of CN112074959A publication Critical patent/CN112074959A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
    • H01L29/78687—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys with a multilayer structure or superlattice structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/15—Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
    • H01L29/151—Compositional structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/15—Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
    • H01L29/151—Compositional structures
    • H01L29/152—Compositional structures with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H01L21/02507—Alternating layers, e.g. superlattice
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13066—Inverted-T field effect transistor [ITFET]

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

半导体器件可以包括基板和在基板上并且包括超晶格的倒T形沟道。超晶格可以包括堆叠的层组，其中每个层组包括限定基础半导体部分的堆叠的基础半导体单层，以及被限制在相邻基础半导体部分的晶格内的至少一个非半导体单层。半导体器件还可以包括在倒T形沟道的相对端上的源极区域和漏极区域，以及在源极区域和漏极区域之间覆盖倒T形沟道的栅极。

Description

用于制造包括超晶格的倒T形沟道场效应晶体管(ITFET)的器 件和方法
技术领域
本发明涉及半导体领域，并且更具体地，涉及包括超晶格的半导体器件和相关联的方法。
背景技术
已经提出了增强半导体器件的性能的结构和技术，诸如通过增强电荷载流子的移动性。例如，授予Currie等人的美国专利申请No.2003/0057416公开了硅、硅锗和松弛硅的应变材料层，并且还包括无杂质的区(否则杂质会造成性能降级)。在上部硅层中产生的双轴应变更改了载流子移动性，从而实现了更高速度和/或更低功率的器件。授予Fitzgerald等人的已公开美国专利申请No.2003/0034529公开了也基于类似的应变硅技术的CMOS反相器。
授予Takagi的美国专利No.6,472,685B2公开了一种半导体器件，其包括硅和夹在硅层之间的碳层，使得第二硅层的导带和价带接受拉伸应变。有效质量较小并且已经由施加到栅电极的电场感应出的电子被限制在第二硅层中，因此，断言n沟道MOSFET具有更高的移动性。
授予Ishibashi等人的美国专利No.4,937,204公开了一种超晶格，其中交替地且外延生长其中少于八个单层并且包含分数或二元或二元化合物半导体层的多个层。主电流流动的方向垂直于超晶格的层。
授予Wang等人的美国专利No.5,357,119公开了通过减少超晶格中的合金散射而获得的具有更高移动性的Si-Ge短周期超晶格。沿着这些思路，授予Candelaria的美国专利No.5,683,934公开了一种增强移动性的MOSFET，该MOSFET包括沟道层，该沟道层包括以将沟道层置于拉伸应变下的百分比交替存在于硅晶格中的硅合金和第二材料。
授予Tsu的美国专利No.5,216,262公开了一种量子阱结构，其包括两个势垒区域和夹在势垒之间的外延生长的薄半导体层。每个势垒区域由交替的SiO2/Si层组成，其厚度一般在二到六个单层的范围内。在势垒层之间夹有厚得多的硅部分。
Tsu于2000年9月6日在Applied Physics and Materials Science&Processing第391-402页在线发表的标题为“Phenomena in silicon nanostructure devices”的文章公开了硅和氧的半导体原子超晶格(SAS)。公开了在硅量子和发光器件中有用的Si/O超晶格。特别地，构造并测试了绿色电致发光二极管结构。二极管结构中的电流流动是垂直的，即，垂直于SAS的层。所公开的SAS可以包括被诸如氧原子和CO分子之类的吸附物质隔开的半导体层。超出被吸附的氧单层的硅生长被描述为具有相当低缺陷密度的外延生长。一种SAS结构包括1.1nm厚的硅部分，该部分大约为八个原子硅层，而另一种结构的硅厚度是该硅厚度的两倍。发表在Physical Review Letters第89卷第7期(2002年8月12日)上的Luo等人的标题为“Chemical Design of Direct-Gap Light-Emitting Silicon”的文章进一步讨论了Tsu的发光SAS结构。
授予Wang等人的美国专利No.6,376,337公开了由薄硅和氧、碳、氮、磷、锑、砷或氢形成的势垒层构造块，由此超过四个数量级进一步减少了垂直流过晶格的电流。绝缘层/势垒层允许在绝缘层旁边沉积低缺陷外延硅。
授予Mears等人的公开的英国专利申请2,347,520公开了非周期性光子带隙(APBG)结构的原理可以适用于电子带隙工程。特别地，该申请公开了可以调整材料参数(例如，能带最小值的位置、有效质量等)，以产生具有期望带结构特点的新型非周期性材料。还公开了其它参数(诸如电导率、热导率和介电常数或磁导率)也可能被设计进该材料中。
此外，授予Wang等人的美国专利No.6,376,337公开了用于生产半导体器件的绝缘或势垒层的方法，该方法包括在硅基板上沉积一层硅和至少一种附加元素，由此沉积层基本上没有缺陷，使得可以在沉积层上沉积基本上没有缺陷的外延硅。可替代地，一种或多种元素(优选地包括氧)的单层被吸收在硅基板上。夹在外延硅之间的多个绝缘层形成势垒复合物。
尽管存在此类方法，但是在某些应用中，可能期望进一步的增强以使用先进的半导体处理技术。
发明内容
半导体器件可以包括基板和在基板上并且包括超晶格的倒T形沟道。超晶格可以包括多个堆叠的层组，其中每个层组包括限定基础半导体部分的多个堆叠的基础半导体单层，以及被限制在相邻基础半导体部分的晶格内的至少一个非半导体单层。半导体器件还可以包括在倒T形沟道的相对端上的源极区域和漏极区域，以及在源极区域和漏极区域之间覆盖倒T形沟道的栅极。
在示例实施例中，基板可以包括绝缘体上半导体(SOI)基板。栅极可以包括覆盖超晶格沟道层的栅极绝缘体和覆盖栅极绝缘体的栅电极。举例来说，每个基础半导体部分可以包括选自由IV族半导体、III-V族半导体和II-VI族半导体组成的组中的基础半导体。此外，至少一个非半导体单层可以包括选自由氧、氮、氟和碳-氧组成的组中的非半导体。例如，基础半导体单层可以包括硅，并且至少一个非半导体单层可以包括氧。
在一些示例实施例中，所有的基础半导体部分可以是相同数量的单层厚度。在其它示例实施例中，至少一些基础半导体部分可以是不同数量的单层厚度。
用于制造半导体器件的方法可以包括在基板上形成倒T形沟道，其中该倒T形沟道包括超晶格。超晶格可以包括多个堆叠的层组，其中每个层组包括限定基础半导体部分的多个堆叠的基础半导体单层，以及被限制在相邻基础半导体部分的晶格内的至少一个非半导体单层。该方法还可以包括在倒T形沟道的相对端上形成源极和漏极区域，以及在源极区域和漏极区域之间形成覆盖倒T形沟道的栅极。
更特别地，形成倒T形沟道还可以包括在基板上形成超晶格、蚀刻超晶格以在其中限定翼片(fin)、在翼片的相对侧上形成侧壁间隔物、蚀刻超晶格的横向地位于侧壁间隔物外侧的部分，以限定倒T形沟道，以及去除侧壁间隔物。
附图说明
图1是用在根据本发明的半导体器件中的超晶格的非常放大的示意性横截面图。
图2是图1中所示的超晶格的一部分的透视原子示意图。
图3是根据本发明的超晶格的另一个实施例的非常放大的示意性横截面图。
图4A是对于现有技术中的块状硅以及对于如图1-2中所示的4/1Si/O超晶格，都从伽玛点(G)计算得到的能带结构的曲线图。
图4B是对于现有技术中的块状硅以及对于如图1-2中所示的4/1Si/O超晶格，都从Z点计算得到的能带结构的曲线图。
图4C是对于现有技术中的块状硅以及对于如图3中所示的5/1/3/1Si/O超晶格，都从伽玛和Z点计算得到的能带结构的曲线图。
图5是根据本发明的包括超晶格的ITFET的示意性横截面图。
图6A-6G是图示制造图5的ITFET的方法的一系列示意性横截面图。
具体实施方式
现在将在下文中参考附图更全面地描述本发明，在附图中示出了本发明的优选实施例。但是，本发明可以以许多不同的形式来实施，并且不应当被解释为限于本文阐述的实施例。更确切地说，提供这些实施例以使得本公开将是透彻和完整的，并将向本领域技术人员充分传达本发明的范围。贯穿全文，相似的数字指相似的元件。
本实施例涉及在原子或分子水平上控制半导体材料的特性。另外，本实施例涉及用在半导体器件中的改进材料的识别、创建和使用。
希望不限于此，申请人在理论上认为本文所述的某些超晶格降低了电荷载流子的有效质量，并且这导致更高的电荷载流子移动性。有效质量在文献中有各种定义。作为改善有效质量的措施，申请人使用“电导率倒数有效质量张量”，并且针对电子和空穴的
Figure BDA0002751379170000053
和
Figure BDA0002751379170000054
分别对于电子定义为：
Figure BDA0002751379170000051
并且对于空穴定义为：
Figure BDA0002751379170000052
其中f是费米-狄拉克(Fermi-Dirac)分布，EF是费米能量，T是温度，E(k,n)是处于在与波向量k和第n个能带对应的状态的电子的能量，索引i和j是指笛卡尔坐标x、y和z，积分在Brillouin区(B.Z.)上获取，并且总和在能量分别高于和低于费米能量的电子和空穴的能带上获取。
申请人对电导率倒数有效质量张量的定义使得，对于电导率倒数有效质量张量的对应分量的越大值，材料的电导率的张量分量越大。希望不限于此，申请人再次在理论上认为本文所述的超晶格设置电导率倒数有效质量张量的值，以增强材料的导电特性，诸如典型地对于电荷载流子运输的优选方向。适当张量元素的倒数被称为电导率有效质量。换句话说，为了表征半导体材料结构，如上所述并在预期的载流子运输方向上计算的电子/空穴的电导率有效质量被用于区分改进的材料。
申请人已经识别出用在半导体器件中的改进的材料或结构。更具体而言，申请人已经识别出具有能带结构的材料或结构，对于这些材料或结构，用于电子和/或空穴的适当电导率有效质量基本上小于针对硅的相应值。除了这些结构的增强的移动性特点外，它们还可以以提供有利于在各种不同类型的器件中使用的压电、热电和/或铁电特性的方式被形成或使用，如将在下面进一步讨论的。
现在参考图1和2，材料或结构为超晶格25的形式，其结构被控制在原子或分子水平，并且可以使用原子或分子层沉积的已知技术来形成。超晶格25包括以堆叠关系布置的多个层组45a-45n，如通过具体参考图1的示意性横截面图可能最好地理解的。
超晶格25的每个层组45a-45n说明性地包括多个堆叠的基础半导体单层46，其限定相应的基础半导体部分46a-46n和其上的能带改性层50。为了说明清楚，在图1中用点划线指示能带改性层50。
能带改性层50说明性地包括一个非半导体单层，该非半导体单层被约束在相邻基础半导体部分的晶格内。“约束在相邻基础半导体部分的晶格内”是指来自相对的基础半导体部分46a-46n的至少一些半导体原子通过其间的非半导体单层50化学键合在一起，如图2中所看到的。一般而言，通过控制通过原子层沉积技术沉积在半导体部分46a-46n上的非半导体材料的数量，使得并非所有(即，小于全部或100％覆盖率)可用半导体键合位点上都填充有与非半导体原子的键，使得这种构造成为可能，如下面将进一步讨论的。因此，当半导体材料的另外的单层46沉积在非半导体单层50上或上方时，新沉积的半导体原子将填充在非半导体单层下方的半导体原子的剩余的空键合位点。
在其它实施例中，有可能可以多于一个这样的非半导体单层。应当注意的是，本文中对非半导体或半导体单层的引用是指，如果用于该单层的材料以块状形成，那么它将是非半导体或半导体。即，如本领域技术人员将认识到的，材料(诸如硅)的单个单层不一定表现出与如果以块状或以相对厚的层形成时相同的特性。
希望不限于此，申请人在理论上认为能带改性层50和相邻的基础半导体部分46a-46n使得超晶格25对于在平行层方向上的电荷载流子具有比其它方式将存在的更低的适当电导率有效质量。以另一种方式考虑，这个平行方向与堆叠方向正交。能带改性层50还可以使得超晶格25具有共同的能带结构，同时还有利地用作在超晶格的垂直上方和下方的层或区域之间的绝缘体。
而且，这种超晶格结构还可以有利地充当在超晶格25的垂直上方和下方的层之间的掺杂剂和/或材料扩散的屏障。这些特性因此可以有利地允许超晶格25提供用于高K电介质的界面，该界面不仅减少高K材料向沟道区域中的扩散，而且还可以有利地减少不想要的散射效应并改善器件移动性，如本领域技术人员将认识到的。
理论上还认为包括超晶格25的半导体器件可以基于比其它情况下将存在的更低的电导率有效质量而享有更高的电荷载流子移动性。
在一些实施例中，并且作为由本发明实现的能带设计的结果，超晶格25还可以具有基本上直接的能带隙，这对于例如光电子器件可以是特别有利的。
超晶格25还说明性地包括在上层组45n上的盖层52。盖层52可以包括多个基础半导体单层46。盖层52可以具有基础半导体的2至100个单层，并且更优选地10至50个单层。
每个基础半导体部分46a-46n可以包括选自IV族半导体、III-V族半导体和II-VI族半导体的基础半导体。当然，如本领域技术人员将认识到的，术语“IV族半导体”还包括IV-IV族半导体。更特别地，例如，基础半导体可以包括硅和锗中的至少一种。
每个能带改性层50可以包括例如选自氧、氮、氟和碳-氧的非半导体。还期望通过沉积下一层来使非半导体热稳定，由此促进制造。在其它实施例中，非半导体可以是与给定的半导体处理兼容的另一种无机或有机元素或化合物，如本领域技术人员将认识到的。更特别地，例如，基础半导体可以包括硅和锗中的至少一种。
应当注意的是，术语“单层”意味着包括单个原子层以及单个分子层。还应该注意的是，由单个单层提供的能带改性层50还意味着包括其中并非所有可能的位点都被占据的单层(即，小于全部或100％的覆盖率)。例如，特别参考图2的原子图，图示了4/1重复结构，其中硅作为基础半导体材料，而氧作为能带改性材料。在所示的示例中，仅一半用于氧的可能位点被占用。
在其它实施例中和/或对于不同的材料，如本领域技术人员将认识到的那样，这种一半的占用将不一定是这种情况。实际上，即使在这个示意图中也可以看出给定单层中氧的各个原子没有沿着平坦的平面精确对准，这也是原子沉积领域的技术人员将认识到的。举例来说，优选的占用范围是可能的氧位点充满的大约八分之一至二分之一，但是在某些实施例中可以使用其它数量。
硅和氧目前广泛用在常规半导体处理中，因此，制造商将能够容易地使用本文中所述的这些材料。原子或单层沉积现在也被广泛使用。因而，如本领域技术人员将认识到的，结合有根据本发明的超晶格25的半导体器件可以容易地被采用和实现。
希望不限于此，申请人在理论上认为，例如，对于超晶格(诸如Si/O超晶格)，硅单层的数量应当期望地为七个或更少，以便超晶格的能带在整个超晶格是共同的或相对均匀的，以实现期望的优点。对于Si/O，图1和2中所示的4/1重复结构已被建模为指示电子和空穴在X方向上增强的移动性。例如，计算得出的电导率有效质量针对于电子(针对块状硅的各向同性)为0.26，并且对于X方向上的4/1SiO超晶格为0.12，导致比率为0.46。类似地，对于块状硅，对于空穴的计算得出的值为0.36，对于4/1Si/O超晶格的得出的值为0.16，导致比率为0.44。
虽然在某些半导体器件中可能期望这种方向上优先的特征，但是其它器件可以从平行于层组的任何方向上的移动性的更均匀增加中受益。如本领域技术人员将认识到的，对于电子或空穴两者或仅这些类型的电荷载流子之一具有增加的移动性也可以是有益的。
超晶格25的4/1Si/O实施例的较低电导率有效质量可以小于以其它方式将发生的电导率有效质量的三分之二，并且这适用于电子和空穴两者。当然，也如本领域技术人员将认识到的，超晶格25还可以在其中包括至少一种类型的电导率掺杂剂。
实际上，现在附加地参考图3，现在描述具有不同特性的根据本发明的超晶格25'的另一个实施例。在这个实施例中，示出了3/1/5/1的重复图案。更特别地，最低的基础半导体部分46a'具有三个单层，并且第二最低的基础半导体部分46b'具有五个单层。这种图案在整个超晶格25'上重复。能带改性层50'可以各自包括单个单层。对于包括Si/O的这种超晶格25'，电荷载流子移动性的增强与层在平面中的取向无关。图3中未具体提及的那些其它元件与以上参考图1讨论的那些元件相似，并且在此无需进一步讨论。
在一些器件实施例中，超晶格的所有基础半导体部分都可以是相同数量的单层那么厚。在其它实施例中，基础半导体部分中的至少一些可以是不同数量的单层那么厚。在其它实施例中，所有的基础半导体部分可以是不同数量的单层那么厚。
在图4A-4C中，呈现了使用密度泛函理论(DFT)计算的能带结构。在本领域中众所周知，DFT低估了带隙的绝对值。因此，可以通过适当的“剪刀校正”来移位间隙上方的所有能带。但是，已经知道能带的形状可靠得多。垂直能量轴应当以这个角度来解释。
图4A示出了对于块状硅(由连续线表示)和对于图1中所示的4/1Si/O超晶格25(由点线表示)两者从伽玛点(G)计算出的能带结构。方向涉及4/1Si/O结构的单元晶胞，而不是Si的常规单元晶胞，但是图中的(001)方向确实与Si的常规单元晶胞的(001)方向对应，因此示出了Si导带最小值的预期位置。图中的(100)和(010)方向与常规Si单元晶胞的(110)和(-110)方向对应。本领域技术人员将认识到的是，图上Si的能带被折叠，以针对4/1Si/O结构在适当的倒易晶格方向上表示它们。
可以看出，与块状硅(Si)相比，用于4/1Si/O结构的导带最小值位于伽玛点处，而价带最小值出现在(001)方向上Brillouin区的边缘处，我们称之为Z点。还可以注意到的是，由于由附加氧层引入的扰动引起的能带分裂，与用于Si的导带最小值的曲率相比，用于4/1Si/O结构的导带最小值具有更大的曲率。
图4B示出了对于块状硅(连续线)和4/1Si/O超晶格25(点线)两者从Z点计算出的能带结构。这个图图示了价带在(100)方向上的增强曲率。
图4C示出了对于块状硅(连续线)以及对于图3的超晶格25'的5/1/3/1Si/O结构(点线)，都从伽玛和Z点两者计算得到的能带结构。由于5/1/3/1Si/O结构的对称性，在(100)和(010)方向上计算出的能带结构是等效的。因此，预期电导率有效质量和移动性在平行于层(即，垂直于(001)堆叠方向)的平面上是各向同性的。注意的是，在5/1/3/1Si/O示例中，导带最小值和价带最大值均在Z点处或其附近。
虽然曲率增加指示有效质量减小，但是可以经由电导率倒数有效质量张量计算来进行适当的比较和判别。这导致申请人进一步在理论上认为5/1/3/1超晶格25'应当基本上是直接带隙。如本领域技术人员将理解的，用于光学跃迁的适当矩阵元素是直接带隙行为与间接带隙行为之间的区别的另一个指标。
使用上述教导，可以针对特定目的选择具有改善的带结构的材料。现在转到图5-6G，所示的示例是倒T形沟道场效应晶体管(ITFET)20中的超晶格25材料。作为背景技术，随着器件尺寸的不断缩小和栅极氧化物厚度的比例化缩小，平面CMOS器件可能继续经受栅极控制问题。特别地，这是由于超薄栅极增加了栅极泄漏问题。解决此问题的一种方法是使用FINFET结构，由于其几何形状，该结构可提供对器件的沟道区域更好的控制。
可以帮助减少栅极泄漏的另一种结构是ITFET。作为背景技术，发表在Semiconductor Manufacturing(2006年6月)上的Mathew等人的标题为“SiliconNanocrystal Non-Volatile Memory for Embedded Memory Scaling”的文章的第35-39页进一步一般地描述了ITFET，该文章通过引用其全部内容被并入本文。ITFET可能会同时享受FINFET和平面薄体SOI器件的优势。这是因为ITFET具有针对相同晶体管的水平和垂直主体，这可以减轻与FINFET相关联的稳定性问题，同时增加器件的总有效面积。但是，在一些应用中可能期望用先进的半导体材料的ITFET结构和制造ITFET的技术。
在示例实现方式中，ITFET 20可以形成有如上所述的超晶格25(例如，Si/O超晶格，但是在不同的实施例中可以使用其它材料)作为绝缘体上半导体(SOI)晶片或基板21上的起始材料。如图6A和6B所示，SOI基板21说明性地包括下部半导体层22(例如，硅)、掩埋氧化物(BOX)层23(例如，SiO2)和相对薄的上部半导体(例如，硅)层24。在一些实施例中，可以在其上形成超晶格层25的BOX层23上方的半导体层24(图6A)可以适当地变薄(例如，超薄体(UTB)SOI通常具有8-10nm的硅)以增强最终将提供沟道区域的超晶格层的量，如本领域技术人员将认识到的。
然后，如图6C所示，对超晶格层25进行构图和蚀刻以限定一个或多个翼片26。然后形成间隔物27(例如，SiN)以“掩蔽”倒T形28的基部(图6D)，然后通过随后的蚀刻和/或剥离步骤形成倒T形28的基部，如图6E所示。然后可以在倒T形上形成栅极氧化物29和栅电极30(图6F-6G)。此后，执行常规的ITFET处理步骤，包括形成间隔物、源/漏区域32、33、触点等，以生产图5所示的最终ITFET 20，如本领域技术人员将认识到的。
超晶格层25的上述高迁移率特征可以有利地为ITFET提供改善的驱动电流和整体器件速度特性。ITFET将进一步有利地保留FINFET的上述优点，同时还潜在地避免了与之相关联的一些缺点，诸如例如机械稳定性。
受益于前述描述和相关附图中呈现的教导，本领域技术人员将想到许多修改和其它实施例。因此，应该理解的是，本公开不限于以示例的方式在本文中阐述的具体实施例，并且修改和实施例旨在被包括在权利要求的范围内。

Claims (26)

1.一种半导体器件，包括：
基板；
在基板上并且包括超晶格的倒T形沟道，所述超晶格包括多个堆叠的层组，每个层组包括：限定基础半导体部分的多个堆叠的基础半导体单层，以及被限制在相邻基础半导体部分的晶格内的至少一个非半导体单层；
在倒T形沟道的相对端上的源极区域和漏极区域；以及
在源极区域和漏极区域之间覆盖倒T形沟道的栅极。
2.如权利要求1所述的半导体器件，其中所述基板包括绝缘体上半导体(SOI)基板。
3.如权利要求1所述的半导体器件，其中栅极包括覆盖超晶格沟道层的栅极绝缘体和覆盖栅极绝缘体的栅电极。
4.如权利要求1所述的半导体器件，其中基础半导体单层包括硅。
5.如权利要求1所述的半导体器件，其中每个基础半导体部分包括选自由IV族半导体、III-V族半导体和II-VI族半导体组成的组中的基础半导体。
6.如权利要求1所述的半导体器件，其中所述至少一个非半导体单层包括氧。
7.如权利要求1所述的半导体器件，其中所述至少一个非半导体单层包括选自由氧、氮、氟和碳-氧组成的组中的非半导体。
8.如权利要求1所述的半导体器件，其中所有基础半导体部分是相同数量的单层厚度。
9.如权利要求1所述的半导体器件，其中基础半导体部分中的至少一些是不同数量的单层厚度。
10.一种半导体器件，包括：
绝缘体上半导体(SOI)基板；
在绝缘体上半导体基板上并且包括超晶格的倒T形沟道，所述超晶格包括多个堆叠的层组，每个层组包括限定基础半导体部分的多个堆叠的基础半导体单层，以及被限制在相邻基础半导体部分的晶格内的至少一个非半导体单层；
在倒T形沟道的相对端上的源极区域和漏极区域；以及
在源极区域和漏极区域之间覆盖倒T形沟道的栅极，并且所述栅极包括覆盖超晶格沟道层的栅极绝缘体和覆盖栅极绝缘体的栅电极。
11.如权利要求10所述的半导体器件，其中基础半导体单层包括硅。
12.如权利要求10所述的半导体器件，其中每个基础半导体部分包括选自由IV族半导体、III-V族半导体和II-VI族半导体组成的组中的基础半导体。
13.如权利要求10所述的半导体器件，其中所述至少一个非半导体单层包括氧。
14.如权利要求10所述的半导体器件，其中所述至少一个非半导体单层包括选自由氧、氮、氟和碳-氧组成的组中的非半导体。
15.如权利要求10所述的半导体器件，其中所有基础半导体部分是相同数量的单层厚度。
16.如权利要求10所述的半导体器件，其中基础半导体部分中的至少一些是不同数量的单层厚度。
17.一种制造半导体器件的方法，包括：
在基板上形成倒T形沟道，所述倒T形沟道包括超晶格，所述超晶格包括多个堆叠的层组，每个层组包括：限定基础半导体部分的多个堆叠的基础半导体单层，以及被限制在相邻基础半导体部分的晶格内的至少一个非半导体单层；
在倒T形沟道的相对端上形成源极区域和漏极区域；以及
在源极区域和漏极区域之间形成覆盖倒T形沟道的栅极。
18.如权利要求17所述的方法，其中形成倒T形沟道还包括：
在基板上形成超晶格；
蚀刻超晶格以在其中限定翼片；
在翼片的相对侧上形成侧壁间隔物；
蚀刻超晶格的在侧壁间隔物的横向外侧的部分以限定倒T形沟道；以及
去除侧壁间隔物。
19.如权利要求17所述的方法，其中所述基板包括绝缘体上半导体(SOI)基板。
20.如权利要求17所述的方法，其中形成栅极包括形成覆盖超晶格沟道层的栅极绝缘体，以及形成覆盖栅极绝缘体的栅电极。
21.如权利要求17所述的方法，其中基础半导体单层包括硅。
22.如权利要求17所述的方法，其中每个基础半导体部分包括选自由IV族半导体、III-V族半导体和II-VI族半导体组成的组中的基础半导体。
23.如权利要求17所述的方法，其中所述至少一个非半导体单层包括氧。
24.如权利要求17所述的方法，其中所述至少一个非半导体单层包括选自由氧、氮、氟和碳-氧组成的组中的非半导体。
25.如权利要求17所述的方法，其中所有基础半导体部分是相同数量的单层厚度。
26.如权利要求17所述的方法，其中基础半导体部分中的至少一些是不同数量的单层厚度。
CN201980029269.3A 2018-04-12 2019-04-10 用于制造包括超晶格的倒t形沟道场效应晶体管(itfet)的器件和方法 Pending CN112074959A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201862656460P 2018-04-12 2018-04-12
US62/656,460 2018-04-12
PCT/US2019/026728 WO2019199926A1 (en) 2018-04-12 2019-04-10 Device and method for making an inverted t channel field effect transistor (itfet) including a superlattice

Publications (1)

Publication Number Publication Date
CN112074959A true CN112074959A (zh) 2020-12-11

Family

ID=66251866

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201980029269.3A Pending CN112074959A (zh) 2018-04-12 2019-04-10 用于制造包括超晶格的倒t形沟道场效应晶体管(itfet)的器件和方法

Country Status (5)

Country Link
US (2) US11664459B2 (zh)
EP (1) EP3776663A1 (zh)
CN (1) CN112074959A (zh)
TW (1) TWI734093B (zh)
WO (1) WO2019199926A1 (zh)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019199926A1 (en) * 2018-04-12 2019-10-17 Atomera Incorporated Device and method for making an inverted t channel field effect transistor (itfet) including a superlattice
US11329154B2 (en) 2019-04-23 2022-05-10 Atomera Incorporated Semiconductor device including a superlattice and an asymmetric channel and related methods
US11437486B2 (en) 2020-01-14 2022-09-06 Atomera Incorporated Methods for making bipolar junction transistors including emitter-base and base-collector superlattices
US11302823B2 (en) 2020-02-26 2022-04-12 Atomera Incorporated Method for making semiconductor device including a superlattice with different non-semiconductor material monolayers
US11177351B2 (en) 2020-02-26 2021-11-16 Atomera Incorporated Semiconductor device including a superlattice with different non-semiconductor material monolayers
US11075078B1 (en) 2020-03-06 2021-07-27 Atomera Incorporated Method for making a semiconductor device including a superlattice within a recessed etch
US11569368B2 (en) 2020-06-11 2023-01-31 Atomera Incorporated Method for making semiconductor device including a superlattice and providing reduced gate leakage
US11469302B2 (en) 2020-06-11 2022-10-11 Atomera Incorporated Semiconductor device including a superlattice and providing reduced gate leakage
US11837634B2 (en) 2020-07-02 2023-12-05 Atomera Incorporated Semiconductor device including superlattice with oxygen and carbon monolayers
EP4295409A1 (en) 2021-03-03 2023-12-27 Atomera Incorporated Radio frequency (rf) semiconductor devices including a ground plane layer having a superlattice and associated methods
US11923418B2 (en) 2021-04-21 2024-03-05 Atomera Incorporated Semiconductor device including a superlattice and enriched silicon 28 epitaxial layer
US11810784B2 (en) 2021-04-21 2023-11-07 Atomera Incorporated Method for making semiconductor device including a superlattice and enriched silicon 28 epitaxial layer
US11728385B2 (en) 2021-05-26 2023-08-15 Atomera Incorporated Semiconductor device including superlattice with O18 enriched monolayers
US11682712B2 (en) 2021-05-26 2023-06-20 Atomera Incorporated Method for making semiconductor device including superlattice with O18 enriched monolayers
US11721546B2 (en) 2021-10-28 2023-08-08 Atomera Incorporated Method for making semiconductor device with selective etching of superlattice to accumulate non-semiconductor atoms
US11631584B1 (en) 2021-10-28 2023-04-18 Atomera Incorporated Method for making semiconductor device with selective etching of superlattice to define etch stop layer

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6475890B1 (en) * 2001-02-12 2002-11-05 Advanced Micro Devices, Inc. Fabrication of a field effect transistor with an upside down T-shaped semiconductor pillar in SOI technology
US20040262699A1 (en) * 2003-06-30 2004-12-30 Rafael Rios N-gate transistor
US20060292889A1 (en) * 2003-06-26 2006-12-28 Rj Mears, Llc FINFET Including a Superlattice
CN107112354A (zh) * 2014-11-25 2017-08-29 阿托梅拉公司 包括超晶格和替换金属栅极结构的半导体装置和相关方法

Family Cites Families (70)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61210679A (ja) 1985-03-15 1986-09-18 Sony Corp 半導体装置
US4907048A (en) 1987-11-23 1990-03-06 Xerox Corporation Double implanted LDD transistor self-aligned with gate
US4994873A (en) * 1988-10-17 1991-02-19 Motorola, Inc. Local interconnect for stacked polysilicon device
JPH05152293A (ja) * 1991-04-30 1993-06-18 Sgs Thomson Microelectron Inc 段差付き壁相互接続体及びゲートの製造方法
US5216262A (en) 1992-03-02 1993-06-01 Raphael Tsu Quantum well structures useful for semiconductor devices
US5357119A (en) 1993-02-19 1994-10-18 Board Of Regents Of The University Of California Field effect devices having short period superlattice structures using Si and Ge
US5796119A (en) 1993-10-29 1998-08-18 Texas Instruments Incorporated Silicon resonant tunneling
US5561302A (en) 1994-09-26 1996-10-01 Motorola, Inc. Enhanced mobility MOSFET device and method
GB9419757D0 (en) 1994-09-30 1994-11-16 Lynxvale Ltd Wavelength selective filter and laser including it
US6376337B1 (en) 1997-11-10 2002-04-23 Nanodynamics, Inc. Epitaxial SiOx barrier/insulation layer
JP3443343B2 (ja) 1997-12-03 2003-09-02 松下電器産業株式会社 半導体装置
GB2385981B (en) 1999-03-05 2003-11-05 Nanovis Llc Laser with aperiodic grating
US6993222B2 (en) 1999-03-05 2006-01-31 Rj Mears, Llc Optical filter device with aperiodically arranged grating elements
GB9905196D0 (en) 1999-03-05 1999-04-28 Fujitsu Telecommunications Eur Aperiodic gratings
US20020100942A1 (en) 2000-12-04 2002-08-01 Fitzgerald Eugene A. CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
WO2003025984A2 (en) 2001-09-21 2003-03-27 Amberwave Systems Corporation Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
US7531850B2 (en) 2003-06-26 2009-05-12 Mears Technologies, Inc. Semiconductor device including a memory cell with a negative differential resistance (NDR) device
US7227174B2 (en) 2003-06-26 2007-06-05 Rj Mears, Llc Semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction
WO2005018005A1 (en) 2003-06-26 2005-02-24 Rj Mears, Llc Semiconductor device including mosfet having band-engineered superlattice
US20060267130A1 (en) 2003-06-26 2006-11-30 Rj Mears, Llc Semiconductor Device Including Shallow Trench Isolation (STI) Regions with a Superlattice Therebetween
US7586165B2 (en) 2003-06-26 2009-09-08 Mears Technologies, Inc. Microelectromechanical systems (MEMS) device including a superlattice
US7153763B2 (en) 2003-06-26 2006-12-26 Rj Mears, Llc Method for making a semiconductor device including band-engineered superlattice using intermediate annealing
US7514328B2 (en) 2003-06-26 2009-04-07 Mears Technologies, Inc. Method for making a semiconductor device including shallow trench isolation (STI) regions with a superlattice therebetween
US7491587B2 (en) 2003-06-26 2009-02-17 Mears Technologies, Inc. Method for making a semiconductor device having a semiconductor-on-insulator (SOI) configuration and including a superlattice on a thin semiconductor layer
US7659539B2 (en) 2003-06-26 2010-02-09 Mears Technologies, Inc. Semiconductor device including a floating gate memory cell with a superlattice channel
US20070020833A1 (en) * 2003-06-26 2007-01-25 Rj Mears, Llc Method for Making a Semiconductor Device Including a Channel with a Non-Semiconductor Layer Monolayer
US20060011905A1 (en) * 2003-06-26 2006-01-19 Rj Mears, Llc Semiconductor device comprising a superlattice dielectric interface layer
US7612366B2 (en) 2003-06-26 2009-11-03 Mears Technologies, Inc. Semiconductor device including a strained superlattice layer above a stress layer
US7531829B2 (en) 2003-06-26 2009-05-12 Mears Technologies, Inc. Semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance
US7531828B2 (en) 2003-06-26 2009-05-12 Mears Technologies, Inc. Semiconductor device including a strained superlattice between at least one pair of spaced apart stress regions
US20060220118A1 (en) 2003-06-26 2006-10-05 Rj Mears, Llc Semiconductor device including a dopant blocking superlattice
US7586116B2 (en) 2003-06-26 2009-09-08 Mears Technologies, Inc. Semiconductor device having a semiconductor-on-insulator configuration and a superlattice
US7045813B2 (en) 2003-06-26 2006-05-16 Rj Mears, Llc Semiconductor device including a superlattice with regions defining a semiconductor junction
US20070012910A1 (en) 2003-06-26 2007-01-18 Rj Mears, Llc Semiconductor Device Including a Channel with a Non-Semiconductor Layer Monolayer
US7045377B2 (en) 2003-06-26 2006-05-16 Rj Mears, Llc Method for making a semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction
US7446002B2 (en) 2003-06-26 2008-11-04 Mears Technologies, Inc. Method for making a semiconductor device comprising a superlattice dielectric interface layer
US6878576B1 (en) 2003-06-26 2005-04-12 Rj Mears, Llc Method for making semiconductor device including band-engineered superlattice
US7229902B2 (en) 2003-06-26 2007-06-12 Rj Mears, Llc Method for making a semiconductor device including a superlattice with regions defining a semiconductor junction
US6830964B1 (en) 2003-06-26 2004-12-14 Rj Mears, Llc Method for making semiconductor device including band-engineered superlattice
US7598515B2 (en) 2003-06-26 2009-10-06 Mears Technologies, Inc. Semiconductor device including a strained superlattice and overlying stress layer and related methods
US20050279991A1 (en) * 2003-06-26 2005-12-22 Rj Mears, Llc Semiconductor device including a superlattice having at least one group of substantially undoped layers
US7456476B2 (en) 2003-06-27 2008-11-25 Intel Corporation Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
US7148712B1 (en) 2005-06-24 2006-12-12 Oxford Instruments Measurement Systems Llc Probe for use in determining an attribute of a coating on a substrate
US7517702B2 (en) 2005-12-22 2009-04-14 Mears Technologies, Inc. Method for making an electronic device including a poled superlattice having a net electrical dipole moment
US7718996B2 (en) 2006-02-21 2010-05-18 Mears Technologies, Inc. Semiconductor device comprising a lattice matching layer
US7625767B2 (en) 2006-03-17 2009-12-01 Mears Technologies, Inc. Methods of making spintronic devices with constrained spintronic dopant
US20080012004A1 (en) 2006-03-17 2008-01-17 Mears Technologies, Inc. Spintronic devices with constrained spintronic dopant
US7781827B2 (en) 2007-01-24 2010-08-24 Mears Technologies, Inc. Semiconductor device with a vertical MOSFET including a superlattice and related methods
US7928425B2 (en) 2007-01-25 2011-04-19 Mears Technologies, Inc. Semiconductor device including a metal-to-semiconductor superlattice interface layer and related methods
US7880161B2 (en) 2007-02-16 2011-02-01 Mears Technologies, Inc. Multiple-wavelength opto-electronic device including a superlattice
US7863066B2 (en) 2007-02-16 2011-01-04 Mears Technologies, Inc. Method for making a multiple-wavelength opto-electronic device including a superlattice
US7812339B2 (en) 2007-04-23 2010-10-12 Mears Technologies, Inc. Method for making a semiconductor device including shallow trench isolation (STI) regions with maskless superlattice deposition following STI formation and related structures
US8158484B2 (en) 2007-10-03 2012-04-17 Freescale Semiconductor, Inc. Method of forming an inverted T shaped channel structure for an inverted T channel field effect transistor device
WO2011112574A1 (en) 2010-03-08 2011-09-15 Mears Technologies, Inc Semiconductor device including a superlattice and dopant diffusion retarding implants and related methods
WO2015077595A1 (en) 2013-11-22 2015-05-28 Mears Technologies, Inc. Vertical semiconductor devices including superlattice punch through stop layer and related methods
US9406753B2 (en) 2013-11-22 2016-08-02 Atomera Incorporated Semiconductor devices including superlattice depletion layer stack and related methods
US9716147B2 (en) 2014-06-09 2017-07-25 Atomera Incorporated Semiconductor devices with enhanced deterministic doping and related methods
US9941359B2 (en) 2015-05-15 2018-04-10 Atomera Incorporated Semiconductor devices with superlattice and punch-through stop (PTS) layers at different depths and related methods
WO2016196600A1 (en) 2015-06-02 2016-12-08 Atomera Incorporated Method for making enhanced semiconductor structures in single wafer processing chamber with desired uniformity control
US9558939B1 (en) 2016-01-15 2017-01-31 Atomera Incorporated Methods for making a semiconductor device including atomic layer structures using N2O as an oxygen source
WO2017197108A1 (en) 2016-05-11 2017-11-16 Atomera Incorporated Dram architecture to reduce row activation circuitry power and peripheral leakage and related methods
US10249745B2 (en) 2016-08-08 2019-04-02 Atomera Incorporated Method for making a semiconductor device including a resonant tunneling diode structure having a superlattice
US10191105B2 (en) 2016-08-17 2019-01-29 Atomera Incorporated Method for making a semiconductor device including threshold voltage measurement circuitry
US10410880B2 (en) 2017-05-16 2019-09-10 Atomera Incorporated Semiconductor device including a superlattice as a gettering layer
EP3639299A1 (en) 2017-06-13 2020-04-22 Atomera Incorporated Semiconductor device with recessed channel array transistor (rcat) including a superlattice and associated methods
US10109479B1 (en) 2017-07-31 2018-10-23 Atomera Incorporated Method of making a semiconductor device with a buried insulating layer formed by annealing a superlattice
EP3669401B1 (en) 2017-08-18 2023-08-02 Atomera Incorporated Manufacturing method for a semiconductor device including the removal of non-monocrystalline stringer adjacent a superlattice-sti interface
WO2019199926A1 (en) * 2018-04-12 2019-10-17 Atomera Incorporated Device and method for making an inverted t channel field effect transistor (itfet) including a superlattice
US11355667B2 (en) * 2018-04-12 2022-06-07 Atomera Incorporated Method for making semiconductor device including vertically integrated optical and electronic devices and comprising a superlattice
US10566191B1 (en) 2018-08-30 2020-02-18 Atomera Incorporated Semiconductor device including superlattice structures with reduced defect densities

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6475890B1 (en) * 2001-02-12 2002-11-05 Advanced Micro Devices, Inc. Fabrication of a field effect transistor with an upside down T-shaped semiconductor pillar in SOI technology
US20060292889A1 (en) * 2003-06-26 2006-12-28 Rj Mears, Llc FINFET Including a Superlattice
US20040262699A1 (en) * 2003-06-30 2004-12-30 Rafael Rios N-gate transistor
CN107112354A (zh) * 2014-11-25 2017-08-29 阿托梅拉公司 包括超晶格和替换金属栅极结构的半导体装置和相关方法

Also Published As

Publication number Publication date
US20190319136A1 (en) 2019-10-17
US20190319135A1 (en) 2019-10-17
US10763370B2 (en) 2020-09-01
WO2019199926A1 (en) 2019-10-17
EP3776663A1 (en) 2021-02-17
TWI734093B (zh) 2021-07-21
TW202004892A (zh) 2020-01-16
US11664459B2 (en) 2023-05-30

Similar Documents

Publication Publication Date Title
US10763370B2 (en) Inverted T channel field effect transistor (ITFET) including a superlattice
US11355667B2 (en) Method for making semiconductor device including vertically integrated optical and electronic devices and comprising a superlattice
CN111133582B (zh) 具有通过对超晶格退火形成的包埋绝缘层的半导体器件的制造方法
US9972685B2 (en) Vertical semiconductor devices including superlattice punch through stop layer and related methods
US9406753B2 (en) Semiconductor devices including superlattice depletion layer stack and related methods
US7491587B2 (en) Method for making a semiconductor device having a semiconductor-on-insulator (SOI) configuration and including a superlattice on a thin semiconductor layer
US7781827B2 (en) Semiconductor device with a vertical MOSFET including a superlattice and related methods
US20060289049A1 (en) Semiconductor Device Having a Semiconductor-on-Insulator (SOI) Configuration and Including a Superlattice on a Thin Semiconductor Layer
CN117413341A (zh) 包括超晶格和富集硅28外延层的半导体器件及相关方法
US11569368B2 (en) Method for making semiconductor device including a superlattice and providing reduced gate leakage
US11469302B2 (en) Semiconductor device including a superlattice and providing reduced gate leakage
WO2007005862A1 (en) Semiconductor device having a semiconductor-on-insulator (soi) configuration and including a superlattice on a thin semiconductor layer and associated methods
CN114258594A (zh) 具有包括超晶格的超突变结区域的半导体器件及相关方法
CN114258593A (zh) 具有含隔开的超晶格的超突变结区域的半导体器件及相关方法
CN114270535A (zh) 具有包括超晶格的超突变结区域的变容二极管及相关方法
CN114270534A (zh) 具有含隔开的超晶格的超突变结区域的变容二极管及相关方法
CN115917754A (zh) 包括超晶格并提供减少的栅泄漏的半导体器件及相关方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination