US9484205B2 - Semiconductor device having self-aligned gate contacts - Google Patents

Semiconductor device having self-aligned gate contacts Download PDF

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US9484205B2
US9484205B2 US14/585,381 US201414585381A US9484205B2 US 9484205 B2 US9484205 B2 US 9484205B2 US 201414585381 A US201414585381 A US 201414585381A US 9484205 B2 US9484205 B2 US 9484205B2
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trenches
contact
dielectric layer
gate
gate contact
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US20150287603A1 (en
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Josephine B. Chang
Paul Chang
Michael A. Guillorn
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Elpis Technologies Inc
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International Business Machines Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide

Definitions

  • the present invention relates to semiconductor devices. More specifically, the present invention relates to a semiconductor device having self-aligned gate contacts over an active area and a method for manufacturing the device.
  • FETs Field-effect transistors
  • a FET includes a source region and a drain region connected by a channel, and a gate that regulates electron flow through the channel between the source and drain regions.
  • MOSFETs metal oxide semiconductor field-effect transistors
  • a method for manufacturing a semiconductor device includes: depositing a first dielectric layer on a semiconductor device having a plurality of gate structures formed on a plurality of active regions, and a plurality of diffusion regions formed alongside the plurality active regions, wherein the plurality of gate structures have a top, a bottom, and two sides, and are encapsulated by an insulating layer on the top and two sides; forming a plurality of first trenches through the first dielectric layer, wherein the plurality of first trenches are formed at a plurality of first locations and expose a first portion of the plurality of diffusion regions; forming silicide on the first portion of the plurality of diffusion regions exposed by the plurality of the first trenches; depositing an insulating material in the plurality of first trenches; planarizing the plurality of first trenches; forming at least one first gate contact through the first dielectric layer and the insulating layer on the top of at least one of the plurality of
  • a semiconductor device includes: a first dielectric layer formed over a semiconductor device having a plurality of gate structures formed on a plurality of active regions, and a plurality of diffusion regions formed along side the plurality of active regions, wherein the plurality of gate structures have a top, a bottom, and two sides, and are encapsulated by an insulating layer on the top and two sides; a plurality of first trenches formed at a plurality of first locations through the first dielectric layer to a first portion of the plurality of diffusion regions, wherein silicide is formed on the first portion of the plurality of diffusion regions and the plurality of first trenches are filled with an insulating material; at least one first gate contact formed through the first dielectric layer and the insulating layer on the top at least one of the plurality of gate structures, wherein the at least one first gate contact is filled a first contact fill and formed between the plurality of first trenches; a second dielectric layer deposited on the first dielectric
  • FIG. 1 is a diagram of a generic MOSFET device, according to an embodiment of the present invention.
  • FIG. 2 depicts the device from FIG. 1 following the deposition of a first dielectric layer covering device, according to an embodiment of the present invention.
  • FIG. 3 depicts the device from FIG. 2 after a first set of trenches are formed through the first dielectric layer, according to an embodiment of the present invention.
  • FIG. 4 depicts the device from FIG. 3 after the first set of trenches are filled with an insulating material and planarized, according to an embodiment of the present invention.
  • FIG. 5 depicts the device from FIG. 4 following the formation of a first gate contact between the first set of trenches, according to an embodiment of the present invention.
  • FIG. 6 depicts the device from FIG. 5 after the first gate contact is filled with a metal and planarized, according to an embodiment of the present invention.
  • FIG. 7 depicts the device from FIG. 6 following the deposition of a second dielectric layer covering the device, according to an embodiment of the present invention.
  • FIG. 8 depicts the device from FIG. 7 after a second set of trenches are formed through the first and second dielectric layers, according to an embodiment of the present invention.
  • FIG. 9 depicts the device from FIG. 8 after the second set of trenches are filled with a conductive material and planarized, according to an embodiment of the present invention.
  • FIG. 10 depicts the device from FIG. 9 following the formation of a second gate contact, according to an embodiment of the present invention.
  • FIG. 11 depicts the device from FIG. 10 after the second gate contact is filled with a metal and planarized, according to an embodiment of the present invention.
  • FIG. 12 is a flow chart depicting the operations of the method for fabricating the semiconductor device, according to an embodiment of the present invention.
  • Embodiments of the present invention allow gate structures to be contacted over an active region while ensuring that such contacts do not short to the diffusion region or neighboring gate structures.
  • Processor 100 is a generic MOSFET processor that has gate structures 102 a, 102 b, and 102 c, which are formed on active regions.
  • the active regions can be planar, as shown, or they can be fins, nanowires, etc.
  • Diffusion regions 104 are alongside the active regions and between gate structures 102 a, 102 b, and 102 c.
  • Gate structures 102 a, 102 b, and 102 c are, as pictured in FIG. 1 , encapsulated by an insulating layer, shown as dark gray, on the top and two sides of the gate structures.
  • gate structures 102 a, 102 b, and 102 c can be at a pitch of 50 nm-100 nm. However, even smaller pitches can be contemplated.
  • processor 100 is depicted after the completion of operation S 10 .
  • a first dielectric layer 202 is deposited on processor 100 .
  • diffusion regions 104 and gate structures 102 a, 102 b, and 102 c are covered by first dielectric layer 202 .
  • First dielectric layer 202 can include a middle of the line (MOL) dielectric, such as SiO 2 or SiCOH.
  • first trenches 302 a and 302 b are formed through first dielectric layer 202 to expose a portion of diffusion regions 104 between gate structures 102 a, 102 b, and 102 c.
  • first trench 302 a exposes a portion of diffusion region 104 that is between gate structures 102 a and 102 b.
  • First trench 302 b exposes a portion of diffusion region 104 that is between gate structures 102 b and 102 c.
  • FIG. 3 depicts first trench 302 a between gate structures 102 a and 102 b, and first trench 302 b between gate structures 102 b and 102 c.
  • First trenches 302 a and 302 b are depicted as being formed at the midpoint of gate structures 102 a, 102 b, and 102 c.
  • the trenches can be formed at any position along the width (z direction) of the gate structures. Further, multiple trenches can be formed between a given pair of gate structures, as opposed to what is shown in FIG. 3 , where one trench is formed between the given pair of gate structures.
  • first trenches 302 a and 302 b are filled with an insulating material.
  • the insulating material used to fill the trenches can be a dielectric, such as silicon nitride (Si 3 N 4 ).
  • the material used in this operation to fill first trenches 302 a and 302 b is different than the material used in first dielectric layer 202 .
  • the process performed in operations S 20 and S 30 is a standard trench contact module, know by those skilled in the art, but with one difference.
  • an insulating material is used as a fill instead of a metal that would be used in the standard trench contact module.
  • an etch back or polish of the trenches is performed. Following the etch back or polish of first trenches 302 a and 302 b, processor 100 is planarized.
  • first gate contact 502 is formed above gate structure 102 b and between first trenches 302 a and 302 b. As shown in FIG. 5 , first gate contact 502 is formed through first dielectric layer 202 and through the insulating layer that is on the top side of gate structure 102 b. According to an embodiment of the present invention, one or more gate contacts can be formed above a gate structure when there are one or more pairs trenches formed along the gate structure. First gate contact 502 can be formed so that it is shorter (in the y direction) than first trenches 302 a and 302 b.
  • First trenches 302 a and 302 b can also be wider (in the z direction) than first gate contact 502 . This is ideal in preventing first gate contact 502 from shorting to the diffusion region. First gate contact 502 is protected from shorting to the diffusion regions below and neighboring gates by the insulating material that fills first trenches 302 a and 302 b. Also, to further prevent shorting to the diffusion or neighboring gate structures, first trenches 302 a and 302 b are longer (y direction) and wider (z direction) than first gate contact 502 .
  • first gate contact 502 is filled with a first contact fill.
  • the first contact fill can include a conductive material such as a metal, for example, titanium, titanium nitride, tungsten, aluminum, copper, platinum, tantalum, tantalum nitride, or any combination thereof. Standard contact processing can be used in order to deposit the first contact fill in first gate contact 502 .
  • first gate contact 502 is planarized in the same manner as first trenches 302 a and 302 b, described above.
  • processor 100 is shown after operation S 60 has been performed.
  • second dielectric layer 702 is deposited on processor 100 .
  • second dielectric layer 702 covers first trenches 302 a and 302 b, first gate contact 502 , and first dielectric layer 202 .
  • Second dielectric layer 702 can be a middle of the line (MOL) dielectric.
  • second trenches 802 a and 802 b are formed through both first dielectric layer 202 and second dielectric layer 702 .
  • second trenches 802 a and 802 b are formed between gate structures 102 a, 102 b, and 102 c.
  • Second trench 802 a exposes a portion of diffusion region 104 between gate structures 102 a and 102 b
  • second trench 802 b exposes a portion of diffusion region 104 between gate structures 102 b and 102 c.
  • Second trenches 802 a and 802 b are formed at different locations along the width (z-direction) of gate structure 102 b than first trenches 302 a and 302 b. Following the formation of the trenches, silicide is formed on the exposed portions of diffusion region 104 at the bottom of the trenches. Second trenches 802 a and 802 b can be contiguous with first trenches 302 a and 302 b, and second trenches 802 a and 802 b must not contact first gate contact 502 .
  • FIG. 8 depicts second trench 802 a between gate structures 102 a and 102 b, and second trench 802 b between gate structures 102 b and 102 c.
  • Second trenches 802 a and 802 b are depicted as being formed at the endpoint of gate structures 102 a, 102 b, and 102 c. However, the present invention is not limited to this design. Second trenches 802 a and 802 b can be formed at multiple positions along the width (z-direction) of the gate structures. For example, a pair of first trenches can be formed at the midpoint of the gate structure and two pair of second trenches can be formed at the ends of the gate structure. As another example, two pairs of first trenches can be formed at the ends of the gate structure and a pair of second trenches can be formed at the midpoint of the gate structure. The designer has the freedom to choose the arrangement of the processor and the arrangement of the first and second trenches.
  • processor 100 is shown following the completion of operation S 80 .
  • second trenches 802 a and 802 b are filled with a conductive material.
  • the conductive material used to fill the trenches can be metal, such as titanium, titanium nitride, tungsten, aluminum, copper, platinum, tantalum, tantalum nitride, or any combination thereof.
  • an etch back or polish of the trenches is performed in order to planarize processor 100 .
  • the process performed in operations S 70 and S 80 is a standard trench contact module and is know by those skilled in the art.
  • the prior trench contact module from operations S 20 and S 30 is similar to the trench contact module performed here, except an insulating material was used as a fill instead of the conductive material used in here.
  • processor 100 is depicted after operation S 90 has been performed.
  • second gate contact 1002 is formed above first gate contact 502 .
  • second gate contact 1002 is a contact via formed through second dielectric layer 702 to contact first gate contact 502 .
  • second gate contact 1002 does not contact second trenches 802 a and 802 b.
  • First trenches 302 a and 302 b help to prevent second gate contact 1002 from shorting to the diffusion region, and they give the designer tolerance when forming second gate contact 1002 .
  • First trenches 302 a and 302 b prevent shorting to the diffusion region and neighboring gate structures, and thus allows the designer more overlay tolerance.
  • second gate contact 1002 is filled with a second contact fill.
  • the second contact fill is a metal and can include, for example, titanium, titanium nitride, tungsten, aluminum, copper, platinum, tantalum, tantalum nitride, or any combination thereof. Standard contact processing can be used in order to deposit the second contact fill in second gate contact 1002 .
  • second gate contact 1002 is planarized.
  • the resulting structure after the completion of operations in FIG. 12 includes a semiconductor device with self-aligned gate contacts over an active area.
  • First trenches 302 a and 302 b are formed through first dielectric layer 202 and between gate structures 102 a, 102 b, and 102 c.
  • First gate contact 502 contacts gate structure 102 b and is formed between first trenches 302 a and 302 b.
  • Second trenches 802 a and 802 b are formed through first dielectric layer 202 and second dielectric layer 702 .
  • Second gate contact 1002 is formed so that it contacts first gate contact 502 but does not contact second trenches 802 a and 802 b.
  • the design of the device prevents the gate contacts from shorting to diffusion region 104 and neighboring gate structures 102 a and 102 c due to an insulating material that fills first trenches 302 a and 302 b.
  • the overall design of the device allows for greater flexibility and gives the designer of the FET extra overlay tolerance.

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Abstract

A semiconductor device and a method for manufacturing the device. The method includes: depositing a first dielectric layer on a semiconductor device; forming a plurality of first trenches through the first dielectric layer; depositing an insulating fill in the plurality of first trenches; planarizing the plurality of first trenches; forming a first gate contact between the plurality of first trenches; depositing a first contact fill in the first gate contact; planarizing the first gate contact; depositing a second dielectric layer on the device; forming a plurality of second trenches through the first and second dielectric layers; depositing a conductive fill in the plurality of second trenches; planarizing the plurality of second trenches; forming a second gate contact where the second gate contact is in contact with the first gate contact; depositing a second contact fill in the second gate contact; and planarizing the second gate contact.

Description

DOMESTIC PRIORITY
This application claims priority to U.S. Provisional Application No. 61/976,073, entitled “SEMICONDUCTOR DEVICE HAVING SELF-ALIGNED GATE CONTACTS,” filed Apr. 7, 2014, which is incorporated herein by reference in its entirety.
BACKGROUND
The present invention relates to semiconductor devices. More specifically, the present invention relates to a semiconductor device having self-aligned gate contacts over an active area and a method for manufacturing the device.
Field-effect transistors (FETs) are used in many integrated circuit designs, as switches to open and close the circuits. In general, a FET includes a source region and a drain region connected by a channel, and a gate that regulates electron flow through the channel between the source and drain regions.
For years, the continued minimization of metal oxide semiconductor field-effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Access to and operation of semiconductor devices is provided by contacts to the devices. During manufacture or forming of semiconductor devices, it is important to ensure that gate contacts do not short to the source/drain region. To avoid shorting, a gate must be contacted in a field region. This ground rule limits wiring flexibility at the first metal level and increases the footprint of cells which require multiple gate contacts, especially when adjacent gates must be contacted.
SUMMARY
According to a first aspect of the present invention, a method for manufacturing a semiconductor device is provided. The method includes: depositing a first dielectric layer on a semiconductor device having a plurality of gate structures formed on a plurality of active regions, and a plurality of diffusion regions formed alongside the plurality active regions, wherein the plurality of gate structures have a top, a bottom, and two sides, and are encapsulated by an insulating layer on the top and two sides; forming a plurality of first trenches through the first dielectric layer, wherein the plurality of first trenches are formed at a plurality of first locations and expose a first portion of the plurality of diffusion regions; forming silicide on the first portion of the plurality of diffusion regions exposed by the plurality of the first trenches; depositing an insulating material in the plurality of first trenches; planarizing the plurality of first trenches; forming at least one first gate contact through the first dielectric layer and the insulating layer on the top of at least one of the plurality of gate structures, wherein the at least one first gate contact is formed between the plurality of first trenches; depositing a first contact fill in the at least one first gate contact; planarizing the at least one first gate contact; depositing a second dielectric layer on the first dielectric layer, the plurality of filled first trenches, and the at least one filled gate contact; forming a plurality of second trenches through the first and second dielectric layers, wherein the plurality of second trenches are formed at a plurality of second locations and expose a second portion of the plurality of diffusion regions; forming silicide on the second portion of the plurality of diffusion regions exposed by the plurality of second trenches; depositing a conductive material in the plurality of second trenches; planarizing the plurality of second trenches; forming at least one second gate contact through the second dielectric layer, wherein the at least one second gate contact is in contact with the at least one first gate contact; depositing a second contact fill in the at least one second gate contact; and planarizing the at least one second gate contact.
According to another aspect of the present invention, a semiconductor device is provided. The device includes: a first dielectric layer formed over a semiconductor device having a plurality of gate structures formed on a plurality of active regions, and a plurality of diffusion regions formed along side the plurality of active regions, wherein the plurality of gate structures have a top, a bottom, and two sides, and are encapsulated by an insulating layer on the top and two sides; a plurality of first trenches formed at a plurality of first locations through the first dielectric layer to a first portion of the plurality of diffusion regions, wherein silicide is formed on the first portion of the plurality of diffusion regions and the plurality of first trenches are filled with an insulating material; at least one first gate contact formed through the first dielectric layer and the insulating layer on the top at least one of the plurality of gate structures, wherein the at least one first gate contact is filled a first contact fill and formed between the plurality of first trenches; a second dielectric layer deposited on the first dielectric layer, the plurality of first filled trenches, and the at least one filled gate contact; a plurality of second trenches formed at a plurality of second locations through the first and second dielectric layers to a second portion of the plurality of diffusion regions, wherein silicide is formed on the second portion of the plurality of diffusion regions and the plurality of second trenches are filled with a conductive material; and at least one second gate contact through the second dielectric layer, wherein the at least one second gate contact is filled with a second contact fill and is in contact with the at least one first gate contact.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
FIG. 1 is a diagram of a generic MOSFET device, according to an embodiment of the present invention.
FIG. 2 depicts the device from FIG. 1 following the deposition of a first dielectric layer covering device, according to an embodiment of the present invention.
FIG. 3 depicts the device from FIG. 2 after a first set of trenches are formed through the first dielectric layer, according to an embodiment of the present invention.
FIG. 4 depicts the device from FIG. 3 after the first set of trenches are filled with an insulating material and planarized, according to an embodiment of the present invention.
FIG. 5 depicts the device from FIG. 4 following the formation of a first gate contact between the first set of trenches, according to an embodiment of the present invention.
FIG. 6 depicts the device from FIG. 5 after the first gate contact is filled with a metal and planarized, according to an embodiment of the present invention.
FIG. 7 depicts the device from FIG. 6 following the deposition of a second dielectric layer covering the device, according to an embodiment of the present invention.
FIG. 8 depicts the device from FIG. 7 after a second set of trenches are formed through the first and second dielectric layers, according to an embodiment of the present invention.
FIG. 9 depicts the device from FIG. 8 after the second set of trenches are filled with a conductive material and planarized, according to an embodiment of the present invention.
FIG. 10 depicts the device from FIG. 9 following the formation of a second gate contact, according to an embodiment of the present invention.
FIG. 11 depicts the device from FIG. 10 after the second gate contact is filled with a metal and planarized, according to an embodiment of the present invention.
FIG. 12 is a flow chart depicting the operations of the method for fabricating the semiconductor device, according to an embodiment of the present invention.
 DETAILED DESCRIPTION
Embodiments of the present invention allow gate structures to be contacted over an active region while ensuring that such contacts do not short to the diffusion region or neighboring gate structures.
Referring to FIG. 1, a diagram of a processor 100 is shown. Processor 100 is a generic MOSFET processor that has gate structures 102 a, 102 b, and 102 c, which are formed on active regions. The active regions can be planar, as shown, or they can be fins, nanowires, etc. Diffusion regions 104 are alongside the active regions and between gate structures 102 a, 102 b, and 102 c. Gate structures 102 a, 102 b, and 102 c are, as pictured in FIG. 1, encapsulated by an insulating layer, shown as dark gray, on the top and two sides of the gate structures. According to an embodiment of the present invention, gate structures 102 a, 102 b, and 102 c can be at a pitch of 50 nm-100 nm. However, even smaller pitches can be contemplated.
Referring to FIGS. 2 & 12, processor 100 is depicted after the completion of operation S10. In operation S10, a first dielectric layer 202 is deposited on processor 100. As shown in FIG. 2, diffusion regions 104 and gate structures 102 a, 102 b, and 102 c are covered by first dielectric layer 202. First dielectric layer 202 can include a middle of the line (MOL) dielectric, such as SiO2 or SiCOH.
Referring to FIGS. 3 & 12, processor 100 is shown after operation S20 has been performed. In operation S20, first trenches 302 a and 302 b are formed through first dielectric layer 202 to expose a portion of diffusion regions 104 between gate structures 102 a, 102 b, and 102 c. As depicted in FIG. 3, first trench 302 a exposes a portion of diffusion region 104 that is between gate structures 102 a and 102 b. First trench 302 b exposes a portion of diffusion region 104 that is between gate structures 102 b and 102 c.
Following the formation of first trenches 302 a and 302 b, silicide is formed on the exposed portions of diffusion region 104 at the bottom of the trenches. The process of forming silicide in such a manner is well known in the art. FIG. 3 depicts first trench 302 a between gate structures 102 a and 102 b, and first trench 302 b between gate structures 102 b and 102 c. First trenches 302 a and 302 b are depicted as being formed at the midpoint of gate structures 102 a, 102 b, and 102 c. However, the present invention is not limited to this design. The trenches can be formed at any position along the width (z direction) of the gate structures. Further, multiple trenches can be formed between a given pair of gate structures, as opposed to what is shown in FIG. 3, where one trench is formed between the given pair of gate structures.
Referring to FIGS. 4 & 12, processor 100 is depicted following the completion of operation S30. In operation S30, first trenches 302 a and 302 b are filled with an insulating material. The insulating material used to fill the trenches can be a dielectric, such as silicon nitride (Si3N4). The material used in this operation to fill first trenches 302 a and 302 b is different than the material used in first dielectric layer 202. The process performed in operations S20 and S30 is a standard trench contact module, know by those skilled in the art, but with one difference. The only difference is that in operation S30, an insulating material is used as a fill instead of a metal that would be used in the standard trench contact module. After the trenches are filled with the insulating material, an etch back or polish of the trenches is performed. Following the etch back or polish of first trenches 302 a and 302 b, processor 100 is planarized.
Referring to FIGS. 5 & 12, processor 100 is shown after operation S40 has been performed. In operation S40, first gate contact 502 is formed above gate structure 102 b and between first trenches 302 a and 302 b. As shown in FIG. 5, first gate contact 502 is formed through first dielectric layer 202 and through the insulating layer that is on the top side of gate structure 102 b. According to an embodiment of the present invention, one or more gate contacts can be formed above a gate structure when there are one or more pairs trenches formed along the gate structure. First gate contact 502 can be formed so that it is shorter (in the y direction) than first trenches 302 a and 302 b. First trenches 302 a and 302 b can also be wider (in the z direction) than first gate contact 502. This is ideal in preventing first gate contact 502 from shorting to the diffusion region. First gate contact 502 is protected from shorting to the diffusion regions below and neighboring gates by the insulating material that fills first trenches 302 a and 302 b. Also, to further prevent shorting to the diffusion or neighboring gate structures, first trenches 302 a and 302 b are longer (y direction) and wider (z direction) than first gate contact 502.
Referring to FIGS. 6 & 12, processor 100 is depicted after the completion of operation S50. In operation S50, first gate contact 502 is filled with a first contact fill. The first contact fill can include a conductive material such as a metal, for example, titanium, titanium nitride, tungsten, aluminum, copper, platinum, tantalum, tantalum nitride, or any combination thereof. Standard contact processing can be used in order to deposit the first contact fill in first gate contact 502. After first gate contact 502 is filled with the first contact fill, first gate contact 502 is planarized in the same manner as first trenches 302 a and 302 b, described above.
Referring to FIGS. 7 & 12, processor 100 is shown after operation S60 has been performed. In operation S60, second dielectric layer 702 is deposited on processor 100. As illustrated in FIG. 7, second dielectric layer 702 covers first trenches 302 a and 302 b, first gate contact 502, and first dielectric layer 202. Second dielectric layer 702, just like first dielectric layer 202, can be a middle of the line (MOL) dielectric.
Referring to FIGS. 8 & 12, processor 100 is shown following the completion of operation S70. In operation S70, second trenches 802 a and 802 b are formed through both first dielectric layer 202 and second dielectric layer 702. As depicted in FIG. 8, second trenches 802 a and 802 b are formed between gate structures 102 a, 102 b, and 102 c. Second trench 802 a exposes a portion of diffusion region 104 between gate structures 102 a and 102 b and second trench 802 b exposes a portion of diffusion region 104 between gate structures 102 b and 102 c. Second trenches 802 a and 802 b are formed at different locations along the width (z-direction) of gate structure 102 b than first trenches 302 a and 302 b. Following the formation of the trenches, silicide is formed on the exposed portions of diffusion region 104 at the bottom of the trenches. Second trenches 802 a and 802 b can be contiguous with first trenches 302 a and 302 b, and second trenches 802 a and 802 b must not contact first gate contact 502. FIG. 8 depicts second trench 802 a between gate structures 102 a and 102 b, and second trench 802 b between gate structures 102 b and 102 c. Second trenches 802 a and 802 b are depicted as being formed at the endpoint of gate structures 102 a, 102 b, and 102 c. However, the present invention is not limited to this design. Second trenches 802 a and 802 b can be formed at multiple positions along the width (z-direction) of the gate structures. For example, a pair of first trenches can be formed at the midpoint of the gate structure and two pair of second trenches can be formed at the ends of the gate structure. As another example, two pairs of first trenches can be formed at the ends of the gate structure and a pair of second trenches can be formed at the midpoint of the gate structure. The designer has the freedom to choose the arrangement of the processor and the arrangement of the first and second trenches.
Referring to FIGS. 9 & 12, processor 100 is shown following the completion of operation S80. In operation S80, second trenches 802 a and 802 b are filled with a conductive material. The conductive material used to fill the trenches can be metal, such as titanium, titanium nitride, tungsten, aluminum, copper, platinum, tantalum, tantalum nitride, or any combination thereof. After the trenches are filled, an etch back or polish of the trenches is performed in order to planarize processor 100. The process performed in operations S70 and S80 is a standard trench contact module and is know by those skilled in the art. The prior trench contact module from operations S20 and S30 is similar to the trench contact module performed here, except an insulating material was used as a fill instead of the conductive material used in here.
Referring to FIGS. 10 & 12, processor 100 is depicted after operation S90 has been performed. In operation S90, second gate contact 1002 is formed above first gate contact 502. As illustrated in FIG. 10, second gate contact 1002 is a contact via formed through second dielectric layer 702 to contact first gate contact 502. However, second gate contact 1002 does not contact second trenches 802 a and 802 b. First trenches 302 a and 302 b help to prevent second gate contact 1002 from shorting to the diffusion region, and they give the designer tolerance when forming second gate contact 1002. First trenches 302 a and 302 b prevent shorting to the diffusion region and neighboring gate structures, and thus allows the designer more overlay tolerance.
Referring to FIGS. 11 & 12, processor 100 is shown following the completion of operation S100. In operation S100, second gate contact 1002 is filled with a second contact fill. The second contact fill is a metal and can include, for example, titanium, titanium nitride, tungsten, aluminum, copper, platinum, tantalum, tantalum nitride, or any combination thereof. Standard contact processing can be used in order to deposit the second contact fill in second gate contact 1002. After second gate contact 1002 is filled with the second contact fill, second gate contact 1002 is planarized.
The resulting structure after the completion of operations in FIG. 12 includes a semiconductor device with self-aligned gate contacts over an active area. First trenches 302 a and 302 b are formed through first dielectric layer 202 and between gate structures 102 a, 102 b, and 102 c. First gate contact 502 contacts gate structure 102 b and is formed between first trenches 302 a and 302 b. Second trenches 802 a and 802 b are formed through first dielectric layer 202 and second dielectric layer 702. Second gate contact 1002 is formed so that it contacts first gate contact 502 but does not contact second trenches 802 a and 802 b. The design of the device prevents the gate contacts from shorting to diffusion region 104 and neighboring gate structures 102 a and 102 c due to an insulating material that fills first trenches 302 a and 302 b. The overall design of the device allows for greater flexibility and gives the designer of the FET extra overlay tolerance.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims (9)

What is claimed is:
1. A method of manufacturing a semiconductor device, the method comprising:
depositing a first dielectric layer on a semiconductor device having a plurality of gate structures formed on a plurality of active regions and a plurality of diffusion regions formed alongside the plurality active regions, wherein the plurality of gate structures have a top, a bottom, and two sides, and are encapsulated by an insulating layer on the top and two sides;
forming a plurality of first trenches through the first dielectric layer, wherein the plurality of first trenches are formed at a plurality of first locations thereby exposing a first portion of the plurality of diffusion regions;
forming silicide on the first portion of the plurality of diffusion regions;
depositing an insulating material in the plurality of first trenches;
planarizing the plurality of first trenches;
forming at least one first gate contact through the first dielectric layer and the insulating layer on the top of at least one of the plurality of gate structures, wherein the at least one first gate contact is formed between the plurality of first trenches;
depositing a first contact fill in the at least one first gate contact;
planarizing the at least one first gate contact;
depositing a second dielectric layer on the first dielectric layer, the plurality of filled first trenches, and the at least one filled gate contact;
forming a plurality of second trenches through the first and second dielectric layers, wherein the plurality of second trenches are formed at a plurality of second locations thereby exposing a second portion of the plurality of diffusion regions;
forming silicide on the second portion of the plurality of diffusion regions exposed by the plurality of second trenches;
depositing a conductive material in the plurality of second trenches;
planarizing the plurality of second trenches;
forming at least one second gate contact through the second dielectric layer, wherein the at least one second gate contact is in contact with the at least one first gate contact;
depositing a second contact fill in the at least one second gate contact; and
planarizing the at least one second gate contact.
2. The method according to claim 1, wherein the first and second dielectric layer comprises a first middle of the line dielectric.
3. The method according to claim 1, wherein the plurality of second locations are contiguous with the plurality of first locations.
4. The method according to claim 1, wherein the insulating material comprises a second middle of the line dielectric.
5. The method according to claim 4, wherein the second middle of the line dielectric comprises silicon nitride.
6. The method according to claim 1, wherein the plurality of first trenches extend a distance through the first dielectric layer and the at least one first gate contact extends a distance through the first dielectric layer, the distance the at least one first gate contact extends through the first dielectric layer is less than the distance the plurality of first trenches extend through the first dielectric layer.
7. The method according to claim 1, wherein the conductive material, the first contact fill, and the second contact fill comprise a metal.
8. The method according to claim 7, wherein the metal is selected from a group consisting of: titanium, titanium nitride, tungsten, aluminum, copper, platinum, tantalum, tantalum nitride, and combinations thereof.
9. The method according to claim 1, wherein planarizing comprises performing an etch-back or polish.
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Publication number Priority date Publication date Assignee Title
US9484205B2 (en) 2014-04-07 2016-11-01 International Business Machines Corporation Semiconductor device having self-aligned gate contacts
US10339250B2 (en) 2016-11-29 2019-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of generating engineering change order (ECO) layout of base cell and computer-readable medium comprising executable instructions for carrying out said method
WO2018125109A1 (en) * 2016-12-29 2018-07-05 Intel Corporation Subtractive plug etching
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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6885055B2 (en) 2003-02-04 2005-04-26 Lee Jong-Ho Double-gate FinFET device and fabricating method thereof
US6936508B2 (en) 2003-09-12 2005-08-30 Texas Instruments Incorporated Metal gate MOS transistors and methods for making the same
US7241649B2 (en) 2004-10-29 2007-07-10 International Business Machines Corporation FinFET body contact structure
US7332779B2 (en) 2004-03-31 2008-02-19 Intel Corporation Memory with split gate devices and method of fabrication
US7452758B2 (en) 2007-03-14 2008-11-18 International Business Machines Corporation Process for making FinFET device with body contact and buried oxide junction isolation
US20090134469A1 (en) 2007-11-28 2009-05-28 Interuniversitair Microelektronica Centrum (Imec) Vzw Method of manufacturing a semiconductor device with dual fully silicided gate
US20120175712A1 (en) 2009-04-21 2012-07-12 International Business Machines Corporation Multiple Vt Field-Effect Transistor Devices
US20130020639A1 (en) 2009-09-30 2013-01-24 Suvolta, Inc Electronic devices and systems, and methods for making and using the same

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7208398B2 (en) * 2004-03-17 2007-04-24 Texas Instruments Incorporated Metal-halogen physical vapor deposition for semiconductor device defect reduction
US7193325B2 (en) * 2004-04-30 2007-03-20 Taiwan Semiconductor Manufacturing Company, Ltd. Reliability improvement of SiOC etch with trimethylsilane gas passivation in Cu damascene interconnects
DE102006040764B4 (en) * 2006-08-31 2010-11-11 Advanced Micro Devices, Inc., Sunnyvale Semiconductor device having a locally provided Metallsilizidgebiet in contact areas and production thereof
US8436404B2 (en) * 2009-12-30 2013-05-07 Intel Corporation Self-aligned contacts
US9484205B2 (en) 2014-04-07 2016-11-01 International Business Machines Corporation Semiconductor device having self-aligned gate contacts

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6885055B2 (en) 2003-02-04 2005-04-26 Lee Jong-Ho Double-gate FinFET device and fabricating method thereof
US6936508B2 (en) 2003-09-12 2005-08-30 Texas Instruments Incorporated Metal gate MOS transistors and methods for making the same
US7332779B2 (en) 2004-03-31 2008-02-19 Intel Corporation Memory with split gate devices and method of fabrication
US7241649B2 (en) 2004-10-29 2007-07-10 International Business Machines Corporation FinFET body contact structure
US7452758B2 (en) 2007-03-14 2008-11-18 International Business Machines Corporation Process for making FinFET device with body contact and buried oxide junction isolation
US20090134469A1 (en) 2007-11-28 2009-05-28 Interuniversitair Microelektronica Centrum (Imec) Vzw Method of manufacturing a semiconductor device with dual fully silicided gate
US20120175712A1 (en) 2009-04-21 2012-07-12 International Business Machines Corporation Multiple Vt Field-Effect Transistor Devices
US20130020639A1 (en) 2009-09-30 2013-01-24 Suvolta, Inc Electronic devices and systems, and methods for making and using the same

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
I. Saad et al., "Design and simulation of 50 nm vertical double-gate MOSFET (VDGM)," IEEE International Conference on Semiconductor Electronics, 2006, ICSE'06, pp. 549-553.
Z. Guo et al., "FinFET-based SRAM design,". Proceedings of the 2005 International Symposium on Low Power Electronics and Design, Aug. 2005, pp. 2-7.

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