JP5851595B2 - 半導体記憶装置を提供するための技法 - Google Patents
半導体記憶装置を提供するための技法 Download PDFInfo
- Publication number
- JP5851595B2 JP5851595B2 JP2014514550A JP2014514550A JP5851595B2 JP 5851595 B2 JP5851595 B2 JP 5851595B2 JP 2014514550 A JP2014514550 A JP 2014514550A JP 2014514550 A JP2014514550 A JP 2014514550A JP 5851595 B2 JP5851595 B2 JP 5851595B2
- Authority
- JP
- Japan
- Prior art keywords
- memory cell
- region
- word line
- data state
- floating gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims description 46
- 238000000034 method Methods 0.000 title description 17
- 230000005641 tunneling Effects 0.000 claims description 52
- 239000000758 substrate Substances 0.000 claims description 44
- 239000012535 impurity Substances 0.000 claims description 26
- 150000004767 nitrides Chemical class 0.000 claims description 10
- 230000000903 blocking effect Effects 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 claims 13
- 230000008878 coupling Effects 0.000 claims 1
- 238000010168 coupling process Methods 0.000 claims 1
- 238000005859 coupling reaction Methods 0.000 claims 1
- 238000009413 insulation Methods 0.000 claims 1
- 210000000746 body region Anatomy 0.000 description 65
- 239000002800 charge carrier Substances 0.000 description 40
- 239000000463 material Substances 0.000 description 24
- 239000002210 silicon-based material Substances 0.000 description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 18
- 229910052710 silicon Inorganic materials 0.000 description 18
- 239000010703 silicon Substances 0.000 description 18
- 239000007769 metal material Substances 0.000 description 16
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 8
- 229910052785 arsenic Inorganic materials 0.000 description 8
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 8
- 229910052698 phosphorus Inorganic materials 0.000 description 8
- 239000011574 phosphorus Substances 0.000 description 8
- 230000000694 effects Effects 0.000 description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 6
- 229910052796 boron Inorganic materials 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000001514 detection method Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000000779 depleting effect Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
- Dram (AREA)
Description
Claims (12)
- それぞれが第1拡散領域、第2拡散領域、並びにこれら第1及び第2拡散領域に挟まれた領域部分を有する第1及び第2のメモリセルであって、前記第1拡散領域、前記領域部分及び前記第2拡散領域が半導体基板平面に対して垂直方向に且つ前記第2拡散領域が前記半導体基板側となるように配置されている第1及び第2のメモリセルと、
前記第1及び第2のメモリセルのための共通のワード線であって、前記第1のメモリセルの前記領域部分に第1のトンネリング絶縁層を介して容量結合すると共に前記第2のメモリセルの前記領域部分に第2のトンネリング絶縁層を介して容量結合するワード線と、
前記第1及び第2のメモリセルの前記第1拡散領域に共通接続されて前記ワード線と交差する方向に延びるビット線と、
前記第1のメモリセルの前記第2拡散領域の下部に前記第2拡散領域と接続されて前記ワード線と並行して延びる第1ソース線と、
前記第2のメモリセルの前記第2拡散領域の下部に前記第2拡散領域と接続されて前記ワード線と並行し且つ前記第1ソース線から独立して延びる第2ソース線と、
を備える半導体装置。 - 前記第1拡散領域および前記第2拡散領域がドナー不純物を添加される、請求項1に記載の半導体装置。
- 前記領域部分がアクセプタ不純物を添加される、請求項1に記載の半導体装置。
- 前記第1及び第2のトンネリング絶縁層は、前記ワード線を介して対向している、請求項1に記載の半導体装置。
- 前記ワード線は第1のワード線であり、
前記第1のワード線と前記第1のメモリセルを介して対向し、前記第1のワード線と並行して伸びる第2のワード線と、
前記第1のトンネリング絶縁層と前記第1のメモリセルを介して対向する第3のトンネリング絶縁層と、
を更に備える請求項1に記載の半導体装置。 - 前記第1のメモリセルの前記領域部分は、第1の領域部分と前記第1の領域部分とは異なる第2の領域部分とで構成され、前記第2の領域部分は前記第3のトンネリング絶縁層を介して前記第2のワード線と容量結合することを特徴とする、請求項5に記載の半導体装置。
- 前記第1の領域部分と前記第2の領域部分は、同じデータ状態または異なったデータ状態が同時にまたは連続して書き込まれることを特徴とする、請求項6に記載の半導体装置。
- 前記第1の領域部分と前記第2の領域部分に書き込まれた同じデータ状態または異なったデータ状態が同時にまたは連続して読み取られることを特徴とする、請求項6に記載の半導体装置。
- 前記第1、第2及び第3のトンネリング絶縁層が、複数の絶縁層または複数の誘電層を備える、請求項5に記載の半導体装置。
- 前記複数の絶縁層または前記複数の誘電層が、熱酸化物層、窒化物層、酸化物層、電荷トラップ窒化物層、および遮断酸化物層の内の少なくとも1つを備える、請求項9に記載の半導体装置。
- 前記複数の絶縁層または前記複数の誘電層が多様な厚さから構成される、請求項9に記載の半導体装置。
- 前記第1及び第2のワード線が複数の層を備える、請求項5に記載の半導体装置。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/153,707 | 2011-06-06 | ||
US13/153,707 US9559216B2 (en) | 2011-06-06 | 2011-06-06 | Semiconductor memory device and method for biasing same |
PCT/US2012/040891 WO2012170409A2 (en) | 2011-06-06 | 2012-06-05 | Techniques for providing a semiconductor memory device |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2014517535A JP2014517535A (ja) | 2014-07-17 |
JP5851595B2 true JP5851595B2 (ja) | 2016-02-03 |
Family
ID=47261584
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2014514550A Active JP5851595B2 (ja) | 2011-06-06 | 2012-06-05 | 半導体記憶装置を提供するための技法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US9559216B2 (ja) |
EP (1) | EP2718973A4 (ja) |
JP (1) | JP5851595B2 (ja) |
CN (1) | CN103688357A (ja) |
WO (1) | WO2012170409A2 (ja) |
Families Citing this family (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5283960B2 (ja) * | 2008-04-23 | 2013-09-04 | 株式会社東芝 | 三次元積層不揮発性半導体メモリ |
US9385240B1 (en) * | 2015-03-03 | 2016-07-05 | Macronix International Co., Ltd. | Memory device and method for fabricating the same |
US9842853B2 (en) * | 2015-09-14 | 2017-12-12 | Toshiba Memory Corporation | Memory cell array with improved substrate current pathway |
US9892800B2 (en) | 2015-09-30 | 2018-02-13 | Sunrise Memory Corporation | Multi-gate NOR flash thin-film transistor strings arranged in stacked horizontal active strips with vertical control gates |
US11120884B2 (en) | 2015-09-30 | 2021-09-14 | Sunrise Memory Corporation | Implementing logic function and generating analog signals using NOR memory strings |
US10121553B2 (en) | 2015-09-30 | 2018-11-06 | Sunrise Memory Corporation | Capacitive-coupled non-volatile thin-film transistor NOR strings in three-dimensional arrays |
US9842651B2 (en) | 2015-11-25 | 2017-12-12 | Sunrise Memory Corporation | Three-dimensional vertical NOR flash thin film transistor strings |
US20180102161A1 (en) * | 2016-10-07 | 2018-04-12 | Kilopass Technology, Inc. | Vertical Thyristor Memory Array and Memory Array Tile Therefor |
US10692874B2 (en) | 2017-06-20 | 2020-06-23 | Sunrise Memory Corporation | 3-dimensional NOR string arrays in segmented stacks |
US10608011B2 (en) | 2017-06-20 | 2020-03-31 | Sunrise Memory Corporation | 3-dimensional NOR memory array architecture and methods for fabrication thereof |
US10608008B2 (en) | 2017-06-20 | 2020-03-31 | Sunrise Memory Corporation | 3-dimensional nor strings with segmented shared source regions |
KR102440227B1 (ko) * | 2017-10-11 | 2022-09-05 | 삼성전자주식회사 | 수직형 메모리 장치 및 수직형 메모리 장치의 제조 방법 |
US10622377B2 (en) | 2017-12-28 | 2020-04-14 | Sunrise Memory Corporation | 3-dimensional NOR memory array with very fine pitch: device and method |
US10475812B2 (en) | 2018-02-02 | 2019-11-12 | Sunrise Memory Corporation | Three-dimensional vertical NOR flash thin-film transistor strings |
US11069696B2 (en) * | 2018-07-12 | 2021-07-20 | Sunrise Memory Corporation | Device structure for a 3-dimensional NOR memory array and methods for improved erase operations applied thereto |
US11751391B2 (en) | 2018-07-12 | 2023-09-05 | Sunrise Memory Corporation | Methods for fabricating a 3-dimensional memory structure of nor memory strings |
US10741581B2 (en) | 2018-07-12 | 2020-08-11 | Sunrise Memory Corporation | Fabrication method for a 3-dimensional NOR memory array |
TWI713195B (zh) | 2018-09-24 | 2020-12-11 | 美商森恩萊斯記憶體公司 | 三維nor記憶電路製程中之晶圓接合及其形成之積體電路 |
CN113169041B (zh) | 2018-12-07 | 2024-04-09 | 日升存储公司 | 形成多层垂直nor型存储器串阵列的方法 |
JP7425069B2 (ja) | 2019-01-30 | 2024-01-30 | サンライズ メモリー コーポレイション | 基板接合を用いた高帯域幅・大容量メモリ組み込み型電子デバイス |
US11398492B2 (en) | 2019-02-11 | 2022-07-26 | Sunrise Memory Corporation | Vertical thing-film transistor and application as bit-line connector for 3-dimensional memory arrays |
WO2021041547A1 (en) * | 2019-08-28 | 2021-03-04 | Micron Technology, Inc. | Memory device having 2-transistor vertical memory cell and a common plate |
WO2021127218A1 (en) | 2019-12-19 | 2021-06-24 | Sunrise Memory Corporation | Process for preparing a channel region of a thin-film transistor |
WO2021159028A1 (en) | 2020-02-07 | 2021-08-12 | Sunrise Memory Corporation | High capacity memory circuit with low effective latency |
US11507301B2 (en) | 2020-02-24 | 2022-11-22 | Sunrise Memory Corporation | Memory module implementing memory centric architecture |
US11561911B2 (en) | 2020-02-24 | 2023-01-24 | Sunrise Memory Corporation | Channel controller for shared memory access |
WO2021207050A1 (en) | 2020-04-08 | 2021-10-14 | Sunrise Memory Corporation | Charge-trapping layer with optimized number of charge-trapping sites for fast program and erase of a memory cell in a 3-dimensional nor memory string array |
WO2022047067A1 (en) | 2020-08-31 | 2022-03-03 | Sunrise Memory Corporation | Thin-film storage transistors in a 3-dimensional array or nor memory strings and process for fabricating the same |
US11646372B2 (en) | 2020-09-19 | 2023-05-09 | International Business Machines Corporation | Vertical transistor floating body one transistor DRAM memory cell |
KR20220060381A (ko) | 2020-11-04 | 2022-05-11 | 삼성전자주식회사 | 집적회로 장치 |
US11842777B2 (en) | 2020-11-17 | 2023-12-12 | Sunrise Memory Corporation | Methods for reducing disturb errors by refreshing data alongside programming or erase operations |
US11848056B2 (en) | 2020-12-08 | 2023-12-19 | Sunrise Memory Corporation | Quasi-volatile memory with enhanced sense amplifier operation |
WO2022239192A1 (ja) * | 2021-05-13 | 2022-11-17 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体素子を用いたメモリ装置 |
TW202310429A (zh) | 2021-07-16 | 2023-03-01 | 美商日升存儲公司 | 薄膜鐵電電晶體的三維記憶體串陣列 |
Family Cites Families (341)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CA272437A (en) | 1925-10-22 | 1927-07-19 | Edgar Lilienfeld Julius | Electric current control mechanism |
US3439214A (en) | 1968-03-04 | 1969-04-15 | Fairchild Camera Instr Co | Beam-junction scan converter |
US4032947A (en) | 1971-10-20 | 1977-06-28 | Siemens Aktiengesellschaft | Controllable charge-coupled semiconductor device |
IT979035B (it) | 1972-04-25 | 1974-09-30 | Ibm | Dispositivo a circuito integrato per la memorizzazione di informa zioni binarie ad emissione elettro luminescente |
FR2197494A5 (ja) | 1972-08-25 | 1974-03-22 | Radiotechnique Compelec | |
US3997799A (en) | 1975-09-15 | 1976-12-14 | Baker Roger T | Semiconductor-device for the storage of binary data |
JPS5567993A (en) | 1978-11-14 | 1980-05-22 | Fujitsu Ltd | Semiconductor memory unit |
US4250569A (en) | 1978-11-15 | 1981-02-10 | Fujitsu Limited | Semiconductor memory device |
EP0014388B1 (en) | 1979-01-25 | 1983-12-21 | Nec Corporation | Semiconductor memory device |
JPS55113359A (en) | 1979-02-22 | 1980-09-01 | Fujitsu Ltd | Semiconductor integrated circuit device |
US4253106A (en) * | 1979-10-19 | 1981-02-24 | Rca Corporation | Gate injected floating gate memory device |
EP0030856B1 (en) | 1979-12-13 | 1984-03-21 | Fujitsu Limited | Charge-pumping semiconductor memory cell comprising a charge-storage region and memory device using such a cell |
JPS5742161A (en) | 1980-08-28 | 1982-03-09 | Fujitsu Ltd | Semiconductor and production thereof |
JPS5982761A (ja) | 1982-11-04 | 1984-05-12 | Hitachi Ltd | 半導体メモリ |
JPS6070760A (ja) | 1983-09-27 | 1985-04-22 | Fujitsu Ltd | 半導体記憶装置 |
US4658377A (en) | 1984-07-26 | 1987-04-14 | Texas Instruments Incorporated | Dynamic memory array with segmented bit lines |
JPS6177359A (ja) | 1984-09-21 | 1986-04-19 | Fujitsu Ltd | 半導体記憶装置 |
JPS61280651A (ja) | 1985-05-24 | 1986-12-11 | Fujitsu Ltd | 半導体記憶装置 |
JPS627149A (ja) | 1985-07-03 | 1987-01-14 | Agency Of Ind Science & Technol | 半導体装置における書込み、読出し方法 |
JPH0671067B2 (ja) | 1985-11-20 | 1994-09-07 | 株式会社日立製作所 | 半導体装置 |
JPH0715954B2 (ja) * | 1985-11-30 | 1995-02-22 | 株式会社東芝 | 不揮発性半導体記憶装置の製造方法 |
JPS62128567U (ja) | 1986-02-07 | 1987-08-14 | ||
JPS62272561A (ja) | 1986-05-20 | 1987-11-26 | Seiko Epson Corp | 1トランジスタ型メモリセル |
JPS6319847A (ja) | 1986-07-14 | 1988-01-27 | Oki Electric Ind Co Ltd | 半導体記憶装置 |
US4807195A (en) | 1987-05-18 | 1989-02-21 | International Business Machines Corporation | Apparatus and method for providing a dual sense amplifier with divided bit line isolation |
US4816884A (en) | 1987-07-20 | 1989-03-28 | International Business Machines Corporation | High density vertical trench transistor and capacitor memory cell structure and fabrication method therefor |
JP2582794B2 (ja) | 1987-08-10 | 1997-02-19 | 株式会社東芝 | 半導体装置及びその製造方法 |
US5677867A (en) | 1991-06-12 | 1997-10-14 | Hazani; Emanuel | Memory with isolatable expandable bit lines |
DE68926793T2 (de) | 1988-03-15 | 1997-01-09 | Toshiba Kawasaki Kk | Dynamischer RAM |
FR2629941B1 (fr) | 1988-04-12 | 1991-01-18 | Commissariat Energie Atomique | Memoire et cellule memoire statiques du type mis, procede de memorisation |
JPH0666443B2 (ja) | 1988-07-07 | 1994-08-24 | 株式会社東芝 | 半導体メモリセルおよび半導体メモリ |
US4910709A (en) | 1988-08-10 | 1990-03-20 | International Business Machines Corporation | Complementary metal-oxide-semiconductor transistor and one-capacitor dynamic-random-access memory cell |
US5164805A (en) | 1988-08-22 | 1992-11-17 | Massachusetts Institute Of Technology | Near-intrinsic thin-film SOI FETS |
US5144390A (en) | 1988-09-02 | 1992-09-01 | Texas Instruments Incorporated | Silicon-on insulator transistor with internal body node to source node connection |
US5258635A (en) | 1988-09-06 | 1993-11-02 | Kabushiki Kaisha Toshiba | MOS-type semiconductor integrated circuit device |
JPH02168496A (ja) | 1988-09-14 | 1990-06-28 | Kawasaki Steel Corp | 半導体メモリ回路 |
NL8802423A (nl) | 1988-10-03 | 1990-05-01 | Imec Inter Uni Micro Electr | Werkwijze voor het bedrijven van een mos-structuur en daarvoor geschikte mos-structuur. |
US4894697A (en) | 1988-10-31 | 1990-01-16 | International Business Machines Corporation | Ultra dense dram cell and its method of fabrication |
US5010524A (en) | 1989-04-20 | 1991-04-23 | International Business Machines Corporation | Crosstalk-shielded-bit-line dram |
JPH02294076A (ja) | 1989-05-08 | 1990-12-05 | Hitachi Ltd | 半導体集積回路装置 |
JPH03171768A (ja) | 1989-11-30 | 1991-07-25 | Toshiba Corp | 半導体記憶装置 |
US5366917A (en) | 1990-03-20 | 1994-11-22 | Nec Corporation | Method for fabricating polycrystalline silicon having micro roughness on the surface |
US5024993A (en) | 1990-05-02 | 1991-06-18 | Microelectronics & Computer Technology Corporation | Superconducting-semiconducting circuits, devices and systems |
US5313432A (en) | 1990-05-23 | 1994-05-17 | Texas Instruments Incorporated | Segmented, multiple-decoder memory array and method for programming a memory array |
JPH07123145B2 (ja) | 1990-06-27 | 1995-12-25 | 株式会社東芝 | 半導体集積回路 |
EP0465961B1 (en) | 1990-07-09 | 1995-08-09 | Sony Corporation | Semiconductor device on a dielectric isolated substrate |
JP2907970B2 (ja) * | 1990-08-08 | 1999-06-21 | 川崎製鉄株式会社 | 半導体装置及びその製造方法 |
JPH04176163A (ja) | 1990-11-08 | 1992-06-23 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JPH0493086U (ja) | 1990-12-26 | 1992-08-13 | ||
JP2700955B2 (ja) | 1991-01-11 | 1998-01-21 | 三菱電機株式会社 | 電界効果型トランジスタを備えた半導体装置 |
JP3046376B2 (ja) | 1991-03-29 | 2000-05-29 | 株式会社東芝 | 不揮発性半導体メモリ装置 |
US5331197A (en) | 1991-04-23 | 1994-07-19 | Canon Kabushiki Kaisha | Semiconductor memory device including gate electrode sandwiching a channel region |
US5424567A (en) | 1991-05-15 | 1995-06-13 | North American Philips Corporation | Protected programmable transistor with reduced parasitic capacitances and method of fabrication |
US5515383A (en) | 1991-05-28 | 1996-05-07 | The Boeing Company | Built-in self-test system and method for self test of an integrated circuit |
US5355330A (en) | 1991-08-29 | 1994-10-11 | Hitachi, Ltd. | Capacitive memory having a PN junction writing and tunneling through an insulator of a charge holding electrode |
JPH05347419A (ja) | 1991-08-29 | 1993-12-27 | Hitachi Ltd | 半導体記憶装置 |
DE69226687T2 (de) | 1991-10-16 | 1999-04-15 | Sony Corp., Tokio/Tokyo | Verfahren zur Herstellung einer SOI-Struktur mit einem DRAM |
US5526307A (en) | 1992-01-22 | 1996-06-11 | Macronix International Co., Ltd. | Flash EPROM integrated circuit architecture |
US5397726A (en) | 1992-02-04 | 1995-03-14 | National Semiconductor Corporation | Segment-erasable flash EPROM |
EP0836194B1 (en) | 1992-03-30 | 2000-05-24 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
US5528062A (en) | 1992-06-17 | 1996-06-18 | International Business Machines Corporation | High-density DRAM structure on soi |
US5315541A (en) | 1992-07-24 | 1994-05-24 | Sundisk Corporation | Segmented column memory array |
EP0599388B1 (en) | 1992-11-20 | 2000-08-02 | Koninklijke Philips Electronics N.V. | Semiconductor device provided with a programmable element |
JPH06216338A (ja) | 1992-11-27 | 1994-08-05 | Internatl Business Mach Corp <Ibm> | 半導体メモリセル及びその製造方法 |
JPH0799251A (ja) | 1992-12-10 | 1995-04-11 | Sony Corp | 半導体メモリセル |
DE69329376T2 (de) | 1992-12-30 | 2001-01-04 | Samsung Electronics Co., Ltd. | Verfahren zur Herstellung einer SOI-Transistor-DRAM |
US5986914A (en) | 1993-03-31 | 1999-11-16 | Stmicroelectronics, Inc. | Active hierarchical bitline memory architecture |
JP3613594B2 (ja) | 1993-08-19 | 2005-01-26 | 株式会社ルネサステクノロジ | 半導体素子およびこれを用いた半導体記憶装置 |
EP0655788B1 (en) | 1993-11-29 | 1998-01-21 | STMicroelectronics S.A. | A volatile memory cell |
US5448513A (en) | 1993-12-02 | 1995-09-05 | Regents Of The University Of California | Capacitorless DRAM device on silicon-on-insulator substrate |
US5432730A (en) | 1993-12-20 | 1995-07-11 | Waferscale Integration, Inc. | Electrically programmable read only memory array |
US5489792A (en) | 1994-04-07 | 1996-02-06 | Regents Of The University Of California | Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility |
US5446299A (en) | 1994-04-29 | 1995-08-29 | International Business Machines Corporation | Semiconductor random access memory cell on silicon-on-insulator with dual control gates |
JP3273582B2 (ja) | 1994-05-13 | 2002-04-08 | キヤノン株式会社 | 記憶装置 |
JPH0832040A (ja) | 1994-07-14 | 1996-02-02 | Nec Corp | 半導体装置 |
US5583808A (en) | 1994-09-16 | 1996-12-10 | National Semiconductor Corporation | EPROM array segmented for high performance and method for controlling same |
US5627092A (en) | 1994-09-26 | 1997-05-06 | Siemens Aktiengesellschaft | Deep trench dram process on SOI for low leakage DRAM cell |
JP3304635B2 (ja) | 1994-09-26 | 2002-07-22 | 三菱電機株式会社 | 半導体記憶装置 |
US5593912A (en) | 1994-10-06 | 1997-01-14 | International Business Machines Corporation | SOI trench DRAM cell for 256 MB DRAM and beyond |
FR2726935B1 (fr) | 1994-11-10 | 1996-12-13 | Commissariat Energie Atomique | Dispositif a memoire non-volatile electriquement effacable et procede de realisation d'un tel dispositif |
JP3392547B2 (ja) | 1994-11-21 | 2003-03-31 | 株式会社東芝 | 不揮発性半導体記憶装置 |
JP3315293B2 (ja) | 1995-01-05 | 2002-08-19 | 株式会社東芝 | 半導体記憶装置 |
JP3274306B2 (ja) | 1995-01-20 | 2002-04-15 | 株式会社東芝 | 半導体集積回路装置 |
US6292424B1 (en) | 1995-01-20 | 2001-09-18 | Kabushiki Kaisha Toshiba | DRAM having a power supply voltage lowering circuit |
JP2806286B2 (ja) | 1995-02-07 | 1998-09-30 | 日本電気株式会社 | 半導体装置 |
JP3407232B2 (ja) | 1995-02-08 | 2003-05-19 | 富士通株式会社 | 半導体記憶装置及びその動作方法 |
JPH08222648A (ja) | 1995-02-14 | 1996-08-30 | Canon Inc | 記憶装置 |
EP1209747A3 (en) | 1995-02-17 | 2002-07-24 | Hitachi, Ltd. | Semiconductor memory element |
JP3600335B2 (ja) | 1995-03-27 | 2004-12-15 | 株式会社東芝 | 半導体装置 |
JPH08274277A (ja) | 1995-03-31 | 1996-10-18 | Toyota Central Res & Dev Lab Inc | 半導体記憶装置およびその製造方法 |
US5568356A (en) | 1995-04-18 | 1996-10-22 | Hughes Aircraft Company | Stacked module assembly including electrically interconnected switching module and plural electronic modules |
DE69632098T2 (de) | 1995-04-21 | 2005-03-24 | Nippon Telegraph And Telephone Corp. | MOSFET Schaltung und ihre Anwendung in einer CMOS Logikschaltung |
US5606188A (en) | 1995-04-26 | 1997-02-25 | International Business Machines Corporation | Fabrication process and structure for a contacted-body silicon-on-insulator dynamic random access memory |
JP2848272B2 (ja) | 1995-05-12 | 1999-01-20 | 日本電気株式会社 | 半導体記憶装置 |
DE19519159C2 (de) | 1995-05-24 | 1998-07-09 | Siemens Ag | DRAM-Zellenanordnung und Verfahren zu deren Herstellung |
US5629546A (en) | 1995-06-21 | 1997-05-13 | Micron Technology, Inc. | Static memory cell and method of manufacturing a static memory cell |
JPH0946688A (ja) | 1995-07-26 | 1997-02-14 | Fujitsu Ltd | ビデオ情報提供/受信システム |
US6480407B1 (en) | 1995-08-25 | 2002-11-12 | Micron Technology, Inc. | Reduced area sense amplifier isolation layout in a dynamic RAM architecture |
JPH0982912A (ja) | 1995-09-13 | 1997-03-28 | Toshiba Corp | 半導体記憶装置及びその製造方法 |
JP3853406B2 (ja) | 1995-10-27 | 2006-12-06 | エルピーダメモリ株式会社 | 半導体集積回路装置及び当該装置の製造方法 |
US5585285A (en) | 1995-12-06 | 1996-12-17 | Micron Technology, Inc. | Method of forming dynamic random access memory circuitry using SOI and isolation trenches |
JP2910647B2 (ja) * | 1995-12-18 | 1999-06-23 | 日本電気株式会社 | 不揮発性半導体記憶装置の製造方法 |
DE19603810C1 (de) | 1996-02-02 | 1997-08-28 | Siemens Ag | Speicherzellenanordnung und Verfahren zu deren Herstellung |
JP3759648B2 (ja) | 1996-03-04 | 2006-03-29 | 株式会社ルネサステクノロジ | 半導体記憶装置 |
US5936265A (en) | 1996-03-25 | 1999-08-10 | Kabushiki Kaisha Toshiba | Semiconductor device including a tunnel effect element |
TW382164B (en) | 1996-04-08 | 2000-02-11 | Hitachi Ltd | Semiconductor IC device with tunnel current free MOS transistors for power supply intercept of main logic |
EP0801427A3 (en) | 1996-04-11 | 1999-05-06 | Matsushita Electric Industrial Co., Ltd. | Field effect transistor, semiconductor storage device, method of manufacturing the same and method of driving semiconductor storage device |
US5715193A (en) | 1996-05-23 | 1998-02-03 | Micron Quantum Devices, Inc. | Flash memory system and method for monitoring the disturb effect on memory cell blocks due to high voltage conditions of other memory cell blocks |
US6424016B1 (en) | 1996-05-24 | 2002-07-23 | Texas Instruments Incorporated | SOI DRAM having P-doped polysilicon gate for a memory pass transistor |
US5754469A (en) | 1996-06-14 | 1998-05-19 | Macronix International Co., Ltd. | Page mode floating gate memory device storing multiple bits per cell |
US5886376A (en) | 1996-07-01 | 1999-03-23 | International Business Machines Corporation | EEPROM having coplanar on-insulator FET and control gate |
US5778243A (en) | 1996-07-03 | 1998-07-07 | International Business Machines Corporation | Multi-threaded cell for a memory |
US5811283A (en) | 1996-08-13 | 1998-09-22 | United Microelectronics Corporation | Silicon on insulator (SOI) dram cell structure and process |
JP3260660B2 (ja) | 1996-08-22 | 2002-02-25 | 株式会社東芝 | 半導体装置およびその製造方法 |
US5774411A (en) | 1996-09-12 | 1998-06-30 | International Business Machines Corporation | Methods to enhance SOI SRAM cell stability |
US5798968A (en) | 1996-09-24 | 1998-08-25 | Sandisk Corporation | Plane decode/virtual sector architecture |
JP2877103B2 (ja) | 1996-10-21 | 1999-03-31 | 日本電気株式会社 | 不揮発性半導体記憶装置およびその製造方法 |
US6097624A (en) | 1997-09-17 | 2000-08-01 | Samsung Electronics Co., Ltd. | Methods of operating ferroelectric memory devices having reconfigurable bit lines |
KR19980057003A (ko) | 1996-12-30 | 1998-09-25 | 김영환 | 반도체 메모리 디바이스 및 그 제조방법 |
US6034389A (en) | 1997-01-22 | 2000-03-07 | International Business Machines Corporation | Self-aligned diffused source vertical transistors with deep trench capacitors in a 4F-square memory cell array |
JP3161354B2 (ja) | 1997-02-07 | 2001-04-25 | 日本電気株式会社 | 半導体装置及びその製造方法 |
US5926730A (en) * | 1997-02-19 | 1999-07-20 | Micron Technology, Inc. | Conductor layer nitridation |
US5732014A (en) | 1997-02-20 | 1998-03-24 | Micron Technology, Inc. | Merged transistor structure for gain memory cell |
EP0860878A2 (en) | 1997-02-20 | 1998-08-26 | Texas Instruments Incorporated | An integrated circuit with programmable elements |
JP3441330B2 (ja) | 1997-02-28 | 2003-09-02 | 株式会社東芝 | 半導体装置及びその製造方法 |
JPH11191596A (ja) | 1997-04-02 | 1999-07-13 | Sony Corp | 半導体メモリセル及びその製造方法 |
US6424011B1 (en) | 1997-04-14 | 2002-07-23 | International Business Machines Corporation | Mixed memory integration with NVRAM, dram and sram cell structures on same substrate |
US5881010A (en) | 1997-05-15 | 1999-03-09 | Stmicroelectronics, Inc. | Multiple transistor dynamic random access memory array architecture with simultaneous refresh of multiple memory cells during a read operation |
KR100554112B1 (ko) | 1997-05-30 | 2006-02-20 | 미크론 테크놀로지,인코포레이티드 | 256 메가 다이내믹 랜덤 액세스 메모리 |
US5784311A (en) | 1997-06-13 | 1998-07-21 | International Business Machines Corporation | Two-device memory cell on SOI for merged logic and memory applications |
US6133597A (en) | 1997-07-25 | 2000-10-17 | Mosel Vitelic Corporation | Biasing an integrated circuit well with a transistor electrode |
KR100246602B1 (ko) | 1997-07-31 | 2000-03-15 | 정선종 | 모스트랜지스터및그제조방법 |
JPH1187649A (ja) | 1997-09-04 | 1999-03-30 | Hitachi Ltd | 半導体記憶装置 |
US5907170A (en) | 1997-10-06 | 1999-05-25 | Micron Technology, Inc. | Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor |
US5943581A (en) | 1997-11-05 | 1999-08-24 | Vanguard International Semiconductor Corporation | Method of fabricating a buried reservoir capacitor structure for high-density dynamic random access memory (DRAM) circuits |
US5976945A (en) | 1997-11-20 | 1999-11-02 | Vanguard International Semiconductor Corporation | Method for fabricating a DRAM cell structure on an SOI wafer incorporating a two dimensional trench capacitor |
JPH11163329A (ja) | 1997-11-27 | 1999-06-18 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
DE19752968C1 (de) | 1997-11-28 | 1999-06-24 | Siemens Ag | Speicherzellenanordnung und Verfahren zu deren Herstellung |
DE59814170D1 (de) | 1997-12-17 | 2008-04-03 | Qimonda Ag | Speicherzellenanordnung und Verfahren zu deren Herstellung |
US5943258A (en) | 1997-12-24 | 1999-08-24 | Texas Instruments Incorporated | Memory with storage cells having SOI drive and access transistors with tied floating body connections |
JP4199338B2 (ja) | 1998-10-02 | 2008-12-17 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
US6097056A (en) | 1998-04-28 | 2000-08-01 | International Business Machines Corporation | Field effect transistor having a floating gate |
US6225158B1 (en) | 1998-05-28 | 2001-05-01 | International Business Machines Corporation | Trench storage dynamic random access memory cell with vertical transfer device |
US6229161B1 (en) | 1998-06-05 | 2001-05-08 | Stanford University | Semiconductor capacitively-coupled NDR device and its applications in high-density high-speed memories and in power switches |
TW432545B (en) | 1998-08-07 | 2001-05-01 | Ibm | Method and improved SOI body contact structure for transistors |
JP4030198B2 (ja) | 1998-08-11 | 2008-01-09 | 株式会社ルネサステクノロジ | 半導体集積回路装置の製造方法 |
KR100268419B1 (ko) | 1998-08-14 | 2000-10-16 | 윤종용 | 고집적 반도체 메모리 장치 및 그의 제조 방법 |
US6333866B1 (en) | 1998-09-28 | 2001-12-25 | Texas Instruments Incorporated | Semiconductor device array having dense memory cell array and heirarchical bit line scheme |
US6423596B1 (en) | 1998-09-29 | 2002-07-23 | Texas Instruments Incorporated | Method for two-sided fabrication of a memory array |
US6096598A (en) | 1998-10-29 | 2000-08-01 | International Business Machines Corporation | Method for forming pillar memory cells and device formed thereby |
US6214694B1 (en) | 1998-11-17 | 2001-04-10 | International Business Machines Corporation | Process of making densely patterned silicon-on-insulator (SOI) region on a wafer |
KR100290787B1 (ko) | 1998-12-26 | 2001-07-12 | 박종섭 | 반도체 메모리 소자의 제조방법 |
US6184091B1 (en) | 1999-02-01 | 2001-02-06 | Infineon Technologies North America Corp. | Formation of controlled trench top isolation layers for vertical transistors |
US6081456A (en) * | 1999-02-04 | 2000-06-27 | Tower Semiconductor Ltd. | Bit line control circuit for a memory array using 2-bit non-volatile memory cells |
US6157216A (en) | 1999-04-22 | 2000-12-05 | International Business Machines Corporation | Circuit driver on SOI for merged logic and memory circuits |
US6111778A (en) | 1999-05-10 | 2000-08-29 | International Business Machines Corporation | Body contacted dynamic memory |
US6333532B1 (en) | 1999-07-16 | 2001-12-25 | International Business Machines Corporation | Patterned SOI regions in semiconductor chips |
JP2001036092A (ja) | 1999-07-23 | 2001-02-09 | Mitsubishi Electric Corp | 半導体装置 |
JP2001044391A (ja) | 1999-07-29 | 2001-02-16 | Fujitsu Ltd | 半導体記憶装置とその製造方法 |
AU6918300A (en) | 1999-09-24 | 2001-04-30 | Intel Corporation | A nonvolatile memory device with a high work function floating-gate and method of fabrication |
US6566177B1 (en) | 1999-10-25 | 2003-05-20 | International Business Machines Corporation | Silicon-on-insulator vertical array device trench capacitor DRAM |
US6391658B1 (en) | 1999-10-26 | 2002-05-21 | International Business Machines Corporation | Formation of arrays of microelectronic elements |
US6633066B1 (en) | 2000-01-07 | 2003-10-14 | Samsung Electronics Co., Ltd. | CMOS integrated circuit devices and substrates having unstrained silicon active layers |
US6544837B1 (en) | 2000-03-17 | 2003-04-08 | International Business Machines Corporation | SOI stacked DRAM logic |
US6359802B1 (en) | 2000-03-28 | 2002-03-19 | Intel Corporation | One-transistor and one-capacitor DRAM cell for logic process technology |
US6524897B1 (en) | 2000-03-31 | 2003-02-25 | Intel Corporation | Semiconductor-on-insulator resistor-capacitor circuit |
US20020031909A1 (en) | 2000-05-11 | 2002-03-14 | Cyril Cabral | Self-aligned silicone process for low resistivity contacts to thin film silicon-on-insulator mosfets |
JP2002064150A (ja) | 2000-06-05 | 2002-02-28 | Mitsubishi Electric Corp | 半導体装置 |
DE10028424C2 (de) | 2000-06-06 | 2002-09-19 | Infineon Technologies Ag | Herstellungsverfahren für DRAM-Speicherzellen |
JP3526446B2 (ja) | 2000-06-09 | 2004-05-17 | 株式会社東芝 | フューズプログラム回路 |
US6262935B1 (en) | 2000-06-17 | 2001-07-17 | United Memories, Inc. | Shift redundancy scheme for wordlines in memory circuits |
US6479862B1 (en) | 2000-06-22 | 2002-11-12 | Progressant Technologies, Inc. | Charge trapping device and method for implementing a transistor having a negative differential resistance mode |
JP2002009081A (ja) | 2000-06-26 | 2002-01-11 | Toshiba Corp | 半導体装置及びその製造方法 |
JP4011833B2 (ja) | 2000-06-30 | 2007-11-21 | 株式会社東芝 | 半導体メモリ |
KR100339425B1 (ko) | 2000-07-21 | 2002-06-03 | 박종섭 | 리세스된 소이 구조를 갖는 반도체 소자 및 그의 제조 방법 |
JP4226205B2 (ja) | 2000-08-11 | 2009-02-18 | 富士雄 舛岡 | 半導体記憶装置の製造方法 |
JP4713783B2 (ja) | 2000-08-17 | 2011-06-29 | 株式会社東芝 | 半導体メモリ装置 |
US6621725B2 (en) | 2000-08-17 | 2003-09-16 | Kabushiki Kaisha Toshiba | Semiconductor memory device with floating storage bulk region and method of manufacturing the same |
US6492211B1 (en) | 2000-09-07 | 2002-12-10 | International Business Machines Corporation | Method for novel SOI DRAM BICMOS NPN |
JP4064607B2 (ja) | 2000-09-08 | 2008-03-19 | 株式会社東芝 | 半導体メモリ装置 |
US20020070411A1 (en) | 2000-09-08 | 2002-06-13 | Alcatel | Method of processing a high voltage p++/n-well junction and a device manufactured by the method |
JP2002094027A (ja) | 2000-09-11 | 2002-03-29 | Toshiba Corp | 半導体記憶装置とその製造方法 |
US6350653B1 (en) | 2000-10-12 | 2002-02-26 | International Business Machines Corporation | Embedded DRAM on silicon-on-insulator substrate |
US6421269B1 (en) | 2000-10-17 | 2002-07-16 | Intel Corporation | Low-leakage MOS planar capacitors for use within DRAM storage cells |
US6496402B1 (en) | 2000-10-17 | 2002-12-17 | Intel Corporation | Noise suppression for open bit line DRAM architectures |
US6849871B2 (en) | 2000-10-20 | 2005-02-01 | International Business Machines Corporation | Fully-depleted-collector silicon-on-insulator (SOI) bipolar transistor useful alone or in SOI BiCMOS |
US6429477B1 (en) | 2000-10-31 | 2002-08-06 | International Business Machines Corporation | Shared body and diffusion contact structure and method for fabricating same |
US6440872B1 (en) | 2000-11-03 | 2002-08-27 | International Business Machines Corporation | Method for hybrid DRAM cell utilizing confined strap isolation |
US6549450B1 (en) | 2000-11-08 | 2003-04-15 | Ibm Corporation | Method and system for improving the performance on SOI memory arrays in an SRAM architecture system |
US6441436B1 (en) | 2000-11-29 | 2002-08-27 | United Microelectronics Corp. | SOI device and method of fabrication |
JP3808700B2 (ja) | 2000-12-06 | 2006-08-16 | 株式会社東芝 | 半導体装置及びその製造方法 |
US20020072155A1 (en) | 2000-12-08 | 2002-06-13 | Chih-Cheng Liu | Method of fabricating a DRAM unit |
US7101772B2 (en) | 2000-12-30 | 2006-09-05 | Texas Instruments Incorporated | Means for forming SOI |
US6552398B2 (en) | 2001-01-16 | 2003-04-22 | Ibm Corporation | T-Ram array having a planar cell structure and method for fabricating the same |
US6441435B1 (en) | 2001-01-31 | 2002-08-27 | Advanced Micro Devices, Inc. | SOI device with wrap-around contact to underside of body, and method of making |
JP4216483B2 (ja) | 2001-02-15 | 2009-01-28 | 株式会社東芝 | 半導体メモリ装置 |
JP3884266B2 (ja) | 2001-02-19 | 2007-02-21 | 株式会社東芝 | 半導体メモリ装置及びその製造方法 |
US6620682B1 (en) | 2001-02-27 | 2003-09-16 | Aplus Flash Technology, Inc. | Set of three level concurrent word line bias conditions for a nor type flash memory array |
US6548848B2 (en) | 2001-03-15 | 2003-04-15 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
JP4354663B2 (ja) | 2001-03-15 | 2009-10-28 | 株式会社東芝 | 半導体メモリ装置 |
JP4071476B2 (ja) | 2001-03-21 | 2008-04-02 | 株式会社東芝 | 半導体ウェーハ及び半導体ウェーハの製造方法 |
US7456439B1 (en) | 2001-03-22 | 2008-11-25 | T-Ram Semiconductor, Inc. | Vertical thyristor-based memory with trench isolation and its method of fabrication |
US6462359B1 (en) | 2001-03-22 | 2002-10-08 | T-Ram, Inc. | Stability in thyristor-based memory device |
JP4053738B2 (ja) | 2001-04-26 | 2008-02-27 | 株式会社東芝 | 半導体メモリ装置 |
EP1253634A3 (en) | 2001-04-26 | 2005-08-31 | Kabushiki Kaisha Toshiba | Semiconductor device |
US6556477B2 (en) | 2001-05-21 | 2003-04-29 | Ibm Corporation | Integrated chip having SRAM, DRAM and flash memory and method for fabricating the same |
US6563733B2 (en) | 2001-05-24 | 2003-05-13 | Winbond Electronics Corporation | Memory array architectures based on a triple-polysilicon source-side injection non-volatile memory cell |
TWI230392B (en) | 2001-06-18 | 2005-04-01 | Innovative Silicon Sa | Semiconductor device |
JP3963664B2 (ja) | 2001-06-22 | 2007-08-22 | 富士雄 舛岡 | 半導体記憶装置及びその製造方法 |
US6573566B2 (en) | 2001-07-09 | 2003-06-03 | United Microelectronics Corp. | Low-voltage-triggered SOI-SCR device and associated ESD protection circuit |
JP2003031684A (ja) | 2001-07-11 | 2003-01-31 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
JP2003031693A (ja) | 2001-07-19 | 2003-01-31 | Toshiba Corp | 半導体メモリ装置 |
EP1288955A3 (en) | 2001-08-17 | 2004-09-22 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
JP2003132682A (ja) | 2001-08-17 | 2003-05-09 | Toshiba Corp | 半導体メモリ装置 |
US6664589B2 (en) | 2001-08-30 | 2003-12-16 | Micron Technology, Inc. | Technique to control tunneling currents in DRAM capacitors, cells, and devices |
US6552932B1 (en) | 2001-09-21 | 2003-04-22 | Sandisk Corporation | Segmented metal bitlines |
JP3984014B2 (ja) | 2001-09-26 | 2007-09-26 | 株式会社東芝 | 半導体装置用基板を製造する方法および半導体装置用基板 |
JP4322453B2 (ja) | 2001-09-27 | 2009-09-02 | 株式会社東芝 | 半導体装置およびその製造方法 |
US6870225B2 (en) | 2001-11-02 | 2005-03-22 | International Business Machines Corporation | Transistor structure with thick recessed source/drain structures and fabrication process of same |
US6657259B2 (en) | 2001-12-04 | 2003-12-02 | International Business Machines Corporation | Multiple-plane FinFET CMOS |
US6518105B1 (en) | 2001-12-10 | 2003-02-11 | Taiwan Semiconductor Manufacturing Company | High performance PD SOI tunneling-biased MOSFET |
JP3998467B2 (ja) | 2001-12-17 | 2007-10-24 | シャープ株式会社 | 不揮発性半導体メモリ装置及びその動作方法 |
JP2003203967A (ja) | 2001-12-28 | 2003-07-18 | Toshiba Corp | 部分soiウェーハの製造方法、半導体装置及びその製造方法 |
US20030123279A1 (en) | 2002-01-03 | 2003-07-03 | International Business Machines Corporation | Silicon-on-insulator SRAM cells with increased stability and yield |
US20030230778A1 (en) | 2002-01-30 | 2003-12-18 | Sumitomo Mitsubishi Silicon Corporation | SOI structure having a SiGe Layer interposed between the silicon and the insulator |
US6975536B2 (en) | 2002-01-31 | 2005-12-13 | Saifun Semiconductors Ltd. | Mass storage array and methods for operation thereof |
US6750515B2 (en) | 2002-02-05 | 2004-06-15 | Industrial Technology Research Institute | SCR devices in silicon-on-insulator CMOS process for on-chip ESD protection |
DE10204871A1 (de) | 2002-02-06 | 2003-08-21 | Infineon Technologies Ag | Kondensatorlose 1-Transistor-DRAM-Zelle und Herstellungsverfahren |
JP2003243528A (ja) | 2002-02-13 | 2003-08-29 | Toshiba Corp | 半導体装置 |
US6686624B2 (en) | 2002-03-11 | 2004-02-03 | Monolithic System Technology, Inc. | Vertical one-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region |
US6661042B2 (en) | 2002-03-11 | 2003-12-09 | Monolithic System Technology, Inc. | One-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region |
US6560142B1 (en) | 2002-03-22 | 2003-05-06 | Yoshiyuki Ando | Capacitorless DRAM gain cell |
US6677646B2 (en) | 2002-04-05 | 2004-01-13 | International Business Machines Corporation | Method and structure of a disposable reversed spacer process for high performance recessed channel CMOS |
JP4880867B2 (ja) | 2002-04-10 | 2012-02-22 | セイコーインスツル株式会社 | 薄膜メモリ、アレイとその動作方法および製造方法 |
EP1355316B1 (en) | 2002-04-18 | 2007-02-21 | Innovative Silicon SA | Data storage device and refreshing method for use with such device |
US6574135B1 (en) | 2002-04-19 | 2003-06-03 | Texas Instruments Incorporated | Shared sense amplifier for ferro-electric memory cell |
US6940748B2 (en) | 2002-05-16 | 2005-09-06 | Micron Technology, Inc. | Stacked 1T-nMTJ MRAM structure |
JP3962638B2 (ja) | 2002-06-18 | 2007-08-22 | 株式会社東芝 | 半導体記憶装置、及び、半導体装置 |
US6853587B2 (en) | 2002-06-21 | 2005-02-08 | Micron Technology, Inc. | Vertical NROM having a storage density of 1 bit per 1F2 |
KR100437856B1 (ko) | 2002-08-05 | 2004-06-30 | 삼성전자주식회사 | 모스 트랜지스터 및 이를 포함하는 반도체 장치의 형성방법. |
JP4044401B2 (ja) | 2002-09-11 | 2008-02-06 | 株式会社東芝 | 半導体記憶装置 |
US6861689B2 (en) | 2002-11-08 | 2005-03-01 | Freescale Semiconductor, Inc. | One transistor DRAM cell structure and method for forming |
US7030436B2 (en) | 2002-12-04 | 2006-04-18 | Micron Technology, Inc. | Embedded DRAM gain memory cell having MOS transistor body provided with a bi-polar transistor charge injecting means |
DE10362018B4 (de) | 2003-02-14 | 2007-03-08 | Infineon Technologies Ag | Anordnung und Verfahren zur Herstellung von vertikalen Transistorzellen und transistorgesteuerten Speicherzellen |
US6714436B1 (en) | 2003-03-20 | 2004-03-30 | Motorola, Inc. | Write operation for capacitorless RAM |
US7233024B2 (en) | 2003-03-31 | 2007-06-19 | Sandisk 3D Llc | Three-dimensional memory device incorporating segmented bit line memory array |
US6867433B2 (en) | 2003-04-30 | 2005-03-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors |
JP2004335553A (ja) | 2003-04-30 | 2004-11-25 | Toshiba Corp | 半導体装置およびその製造方法 |
JP3913709B2 (ja) | 2003-05-09 | 2007-05-09 | 株式会社東芝 | 半導体記憶装置 |
JP2004335031A (ja) | 2003-05-09 | 2004-11-25 | Toshiba Corp | 半導体記憶装置 |
US7085153B2 (en) | 2003-05-13 | 2006-08-01 | Innovative Silicon S.A. | Semiconductor memory cell, array, architecture and device, and method of operating same |
US20040228168A1 (en) | 2003-05-13 | 2004-11-18 | Richard Ferrant | Semiconductor memory device and method of operating same |
US6912150B2 (en) | 2003-05-13 | 2005-06-28 | Lionel Portman | Reference current generator, and method of programming, adjusting and/or operating same |
JP4108537B2 (ja) | 2003-05-28 | 2008-06-25 | 富士雄 舛岡 | 半導体装置 |
US6909151B2 (en) | 2003-06-27 | 2005-06-21 | Intel Corporation | Nonplanar device with stress incorporation layer and method of fabrication |
US7095075B2 (en) | 2003-07-01 | 2006-08-22 | Micron Technology, Inc. | Apparatus and method for split transistor memory having improved endurance |
US7335934B2 (en) | 2003-07-22 | 2008-02-26 | Innovative Silicon S.A. | Integrated circuit device, and method of fabricating same |
US6897098B2 (en) | 2003-07-28 | 2005-05-24 | Intel Corporation | Method of fabricating an ultra-narrow channel semiconductor device |
JP4077381B2 (ja) | 2003-08-29 | 2008-04-16 | 株式会社東芝 | 半導体集積回路装置 |
US6936508B2 (en) | 2003-09-12 | 2005-08-30 | Texas Instruments Incorporated | Metal gate MOS transistors and methods for making the same |
US20050062088A1 (en) | 2003-09-22 | 2005-03-24 | Texas Instruments Incorporated | Multi-gate one-transistor dynamic random access memory |
US7184298B2 (en) | 2003-09-24 | 2007-02-27 | Innovative Silicon S.A. | Low power programming technique for a floating body memory transistor, memory cell, and memory array |
US6982902B2 (en) | 2003-10-03 | 2006-01-03 | Infineon Technologies Ag | MRAM array having a segmented bit line |
US7072205B2 (en) | 2003-11-19 | 2006-07-04 | Intel Corporation | Floating-body DRAM with two-phase write |
US7002842B2 (en) | 2003-11-26 | 2006-02-21 | Intel Corporation | Floating-body dynamic random access memory with purge line |
JP2005175090A (ja) | 2003-12-09 | 2005-06-30 | Toshiba Corp | 半導体メモリ装置及びその製造方法 |
US6952376B2 (en) | 2003-12-22 | 2005-10-04 | Intel Corporation | Method and apparatus to generate a reference value in a memory array |
JP4559728B2 (ja) | 2003-12-26 | 2010-10-13 | 株式会社東芝 | 半導体記憶装置 |
US6903984B1 (en) | 2003-12-31 | 2005-06-07 | Intel Corporation | Floating-body DRAM using write word line for increased retention time |
US6992339B2 (en) | 2003-12-31 | 2006-01-31 | Intel Corporation | Asymmetric memory cell |
US7001811B2 (en) | 2003-12-31 | 2006-02-21 | Intel Corporation | Method for making memory cell without halo implant |
JP4342970B2 (ja) | 2004-02-02 | 2009-10-14 | 株式会社東芝 | 半導体メモリ装置及びその製造方法 |
JP4028499B2 (ja) | 2004-03-01 | 2007-12-26 | 株式会社東芝 | 半導体記憶装置 |
JP4032039B2 (ja) | 2004-04-06 | 2008-01-16 | 株式会社東芝 | 半導体記憶装置 |
JP4110115B2 (ja) | 2004-04-15 | 2008-07-02 | 株式会社東芝 | 半導体記憶装置 |
JP2005346755A (ja) | 2004-05-31 | 2005-12-15 | Sharp Corp | 半導体記憶装置 |
US7042765B2 (en) | 2004-08-06 | 2006-05-09 | Freescale Semiconductor, Inc. | Memory bit line segment isolation |
US7158410B2 (en) * | 2004-08-27 | 2007-01-02 | Micron Technology, Inc. | Integrated DRAM-NVRAM multi-level memory |
JP3898715B2 (ja) | 2004-09-09 | 2007-03-28 | 株式会社東芝 | 半導体装置およびその製造方法 |
US7422946B2 (en) | 2004-09-29 | 2008-09-09 | Intel Corporation | Independently accessed double-gate and tri-gate transistors in same process flow |
US7061806B2 (en) | 2004-09-30 | 2006-06-13 | Intel Corporation | Floating-body memory cell write |
US7611943B2 (en) | 2004-10-20 | 2009-11-03 | Texas Instruments Incorporated | Transistors, integrated circuits, systems, and processes of manufacture with improved work function modulation |
US7476939B2 (en) | 2004-11-04 | 2009-01-13 | Innovative Silicon Isi Sa | Memory cell having an electrically floating body transistor and programming technique therefor |
US7251164B2 (en) | 2004-11-10 | 2007-07-31 | Innovative Silicon S.A. | Circuitry for and method of improving statistical distribution of integrated circuits |
US7301838B2 (en) | 2004-12-13 | 2007-11-27 | Innovative Silicon S.A. | Sense amplifier circuitry and architecture to write data into and/or read from memory cells |
US7301803B2 (en) | 2004-12-22 | 2007-11-27 | Innovative Silicon S.A. | Bipolar reading technique for a memory cell having an electrically floating body transistor |
CN100562987C (zh) | 2005-02-18 | 2009-11-25 | 富士通微电子株式会社 | 存储单元阵列及其制造方法以及使用该存储单元阵列的半导体电路装置 |
US7563701B2 (en) | 2005-03-31 | 2009-07-21 | Intel Corporation | Self-aligned contacts for transistors |
US7319617B2 (en) | 2005-05-13 | 2008-01-15 | Winbond Electronics Corporation | Small sector floating gate flash memory |
US7612403B2 (en) * | 2005-05-17 | 2009-11-03 | Micron Technology, Inc. | Low power non-volatile memory and gate stack |
US7538389B2 (en) | 2005-06-08 | 2009-05-26 | Micron Technology, Inc. | Capacitorless DRAM on bulk silicon |
US7230846B2 (en) | 2005-06-14 | 2007-06-12 | Intel Corporation | Purge-based floating body memory |
US7317641B2 (en) | 2005-06-20 | 2008-01-08 | Sandisk Corporation | Volatile memory cell two-pass writing method |
US7460395B1 (en) | 2005-06-22 | 2008-12-02 | T-Ram Semiconductor, Inc. | Thyristor-based semiconductor memory and memory array with data refresh |
US20070023833A1 (en) | 2005-07-28 | 2007-02-01 | Serguei Okhonin | Method for reading a memory cell having an electrically floating body transistor, and memory cell and array implementing same |
US7476927B2 (en) * | 2005-08-24 | 2009-01-13 | Micron Technology, Inc. | Scalable multi-functional and multi-level nano-crystal non-volatile memory device |
US7511332B2 (en) | 2005-08-29 | 2009-03-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Vertical flash memory |
US7416943B2 (en) | 2005-09-01 | 2008-08-26 | Micron Technology, Inc. | Peripheral gate stacks and recessed array gates |
US7606066B2 (en) | 2005-09-07 | 2009-10-20 | Innovative Silicon Isi Sa | Memory cell and memory cell array having an electrically floating body transistor, and methods of operating same |
US7355916B2 (en) | 2005-09-19 | 2008-04-08 | Innovative Silicon S.A. | Method and circuitry to generate a reference current for reading a memory cell, and device implementing same |
US20070085140A1 (en) | 2005-10-19 | 2007-04-19 | Cedric Bassin | One transistor memory cell having strained electrically floating body region, and method of operating same |
US7436706B2 (en) | 2005-10-31 | 2008-10-14 | Gregory Allan Popoff | Method and apparatus for varying the programming duration and/or voltage of an electrically floating body transistor, and memory cell array implementing same |
KR100724560B1 (ko) | 2005-11-18 | 2007-06-04 | 삼성전자주식회사 | 결정질 반도체층을 갖는 반도체소자, 그의 제조방법 및그의 구동방법 |
US7687851B2 (en) | 2005-11-23 | 2010-03-30 | M-Mos Semiconductor Sdn. Bhd. | High density trench MOSFET with reduced on-resistance |
JP2007157296A (ja) | 2005-12-08 | 2007-06-21 | Toshiba Corp | 半導体記憶装置 |
KR100675297B1 (ko) * | 2005-12-19 | 2007-01-29 | 삼성전자주식회사 | 캐패시터가 없는 동적 메모리 셀을 구비한 반도체 메모리장치 및 이 장치의 배치 방법 |
US7683430B2 (en) | 2005-12-19 | 2010-03-23 | Innovative Silicon Isi Sa | Electrically floating body memory cell and array, and method of operating or controlling same |
US8022482B2 (en) | 2006-02-14 | 2011-09-20 | Alpha & Omega Semiconductor, Ltd | Device configuration of asymmetrical DMOSFET with schottky barrier source |
US7542345B2 (en) | 2006-02-16 | 2009-06-02 | Innovative Silicon Isi Sa | Multi-bit memory cell having electrically floating body transistor, and method of programming and reading same |
DE102006009225B4 (de) | 2006-02-28 | 2009-07-16 | Advanced Micro Devices, Inc., Sunnyvale | Herstellung von Silizidoberflächen für Silizium/Kohlenstoff-Source/Drain-Gebiete |
US7492632B2 (en) | 2006-04-07 | 2009-02-17 | Innovative Silicon Isi Sa | Memory array having a programmable word length, and method of operating same |
US7324387B1 (en) | 2006-04-18 | 2008-01-29 | Maxim Integrated Products, Inc. | Low power high density random access memory flash cells and arrays |
DE102006019935B4 (de) | 2006-04-28 | 2011-01-13 | Advanced Micro Devices, Inc., Sunnyvale | SOI-Transistor mit reduziertem Körperpotential und ein Verfahren zur Herstellung |
JP5068035B2 (ja) | 2006-05-11 | 2012-11-07 | ルネサスエレクトロニクス株式会社 | 半導体記憶装置 |
US7542340B2 (en) | 2006-07-11 | 2009-06-02 | Innovative Silicon Isi Sa | Integrated circuit including memory array having a segmented bit line architecture and method of controlling and/or operating same |
JP5051342B2 (ja) | 2006-07-12 | 2012-10-17 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 不揮発性半導体メモリ及びその駆動方法 |
US7545694B2 (en) | 2006-08-16 | 2009-06-09 | Cypress Semiconductor Corporation | Sense amplifier with leakage testing and read debug capability |
US7359226B2 (en) | 2006-08-28 | 2008-04-15 | Qimonda Ag | Transistor, memory cell array and method for forming and operating a memory device |
US7553709B2 (en) | 2006-10-04 | 2009-06-30 | International Business Machines Corporation | MOSFET with body contacts |
KR100819552B1 (ko) | 2006-10-30 | 2008-04-07 | 삼성전자주식회사 | 반도체 메모리 장치 및 이 장치의 동작 방법 |
US7608898B2 (en) | 2006-10-31 | 2009-10-27 | Freescale Semiconductor, Inc. | One transistor DRAM cell structure |
JP2008117489A (ja) | 2006-11-07 | 2008-05-22 | Toshiba Corp | 半導体記憶装置 |
US7675781B2 (en) | 2006-12-01 | 2010-03-09 | Infineon Technologies Ag | Memory device, method for operating a memory device, and apparatus for use with a memory device |
KR100790823B1 (ko) | 2006-12-14 | 2008-01-03 | 삼성전자주식회사 | 리드 디스터브를 개선한 불휘발성 반도체 메모리 장치 |
KR100861236B1 (ko) * | 2007-04-10 | 2008-10-02 | 경북대학교 산학협력단 | 낮은 누설전류를 갖는 기둥형 전계효과트랜지스터 |
US7688660B2 (en) | 2007-04-12 | 2010-03-30 | Qimonda Ag | Semiconductor device, an electronic device and a method for operating the same |
JP2008263133A (ja) | 2007-04-13 | 2008-10-30 | Toshiba Microelectronics Corp | 半導体記憶装置およびその駆動方法 |
US20080258206A1 (en) | 2007-04-17 | 2008-10-23 | Qimonda Ag | Self-Aligned Gate Structure, Memory Cell Array, and Methods of Making the Same |
KR100866966B1 (ko) | 2007-05-10 | 2008-11-06 | 삼성전자주식회사 | 비휘발성 메모리 소자, 그 제조 방법 및 반도체 패키지 |
EP2015362A1 (en) | 2007-06-04 | 2009-01-14 | STMicroelectronics (Crolles 2) SAS | Semiconductor array and manufacturing method thereof |
JP2009032384A (ja) | 2007-06-29 | 2009-02-12 | Toshiba Corp | 半導体記憶装置の駆動方法および半導体記憶装置 |
FR2919112A1 (fr) | 2007-07-16 | 2009-01-23 | St Microelectronics Crolles 2 | Circuit integre comprenant un transistor et un condensateur et procede de fabrication |
US7688648B2 (en) | 2008-09-02 | 2010-03-30 | Juhan Kim | High speed flash memory |
US7927938B2 (en) | 2007-11-19 | 2011-04-19 | Micron Technology, Inc. | Fin-JFET |
JP2009152498A (ja) | 2007-12-21 | 2009-07-09 | Toshiba Corp | 不揮発性半導体メモリ |
US8014195B2 (en) | 2008-02-06 | 2011-09-06 | Micron Technology, Inc. | Single transistor memory cell |
US7924630B2 (en) | 2008-10-15 | 2011-04-12 | Micron Technology, Inc. | Techniques for simultaneously driving a plurality of source lines |
US8223574B2 (en) | 2008-11-05 | 2012-07-17 | Micron Technology, Inc. | Techniques for block refreshing a semiconductor memory device |
US8139418B2 (en) | 2009-04-27 | 2012-03-20 | Micron Technology, Inc. | Techniques for controlling a direct injection semiconductor memory device |
US9076543B2 (en) | 2009-07-27 | 2015-07-07 | Micron Technology, Inc. | Techniques for providing a direct injection semiconductor memory device |
JP5586528B2 (ja) | 2011-05-31 | 2014-09-10 | 京セラドキュメントソリューションズ株式会社 | 画像形成装置 |
-
2011
- 2011-06-06 US US13/153,707 patent/US9559216B2/en active Active
-
2012
- 2012-06-05 WO PCT/US2012/040891 patent/WO2012170409A2/en unknown
- 2012-06-05 JP JP2014514550A patent/JP5851595B2/ja active Active
- 2012-06-05 EP EP12796567.1A patent/EP2718973A4/en not_active Ceased
- 2012-06-05 CN CN201280035279.6A patent/CN103688357A/zh active Pending
Also Published As
Publication number | Publication date |
---|---|
EP2718973A4 (en) | 2015-04-15 |
EP2718973A2 (en) | 2014-04-16 |
JP2014517535A (ja) | 2014-07-17 |
US20120307568A1 (en) | 2012-12-06 |
WO2012170409A2 (en) | 2012-12-13 |
WO2012170409A3 (en) | 2013-03-14 |
US9559216B2 (en) | 2017-01-31 |
CN103688357A (zh) | 2014-03-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5851595B2 (ja) | 半導体記憶装置を提供するための技法 | |
US10340276B2 (en) | Method of maintaining the state of semiconductor memory having electrically floating body transistor | |
US9524971B2 (en) | Techniques for providing a semiconductor memory device | |
US9030872B2 (en) | Method of maintaining the state of semiconductor memory having electrically floating body transistor | |
US8947965B2 (en) | Techniques for providing a direct injection semiconductor memory device | |
US8139418B2 (en) | Techniques for controlling a direct injection semiconductor memory device | |
US9263133B2 (en) | Techniques for providing a semiconductor memory device | |
US9093311B2 (en) | Techniques for providing a semiconductor memory device | |
TW200834886A (en) | One transistor DRAM cell structure and method for forming | |
KR20190113192A (ko) | 반도체 메모리 소자, 이의 구동 방법 및 이의 제조 방법 | |
US8982633B2 (en) | Techniques for providing a direct injection semiconductor memory device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20131204 Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20140127 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20140408 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20140408 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20150219 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20150303 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20150602 Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20150602 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20151110 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20151202 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5851595 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |