CN108431952A - 内嵌的引线接合线 - Google Patents

内嵌的引线接合线 Download PDF

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Publication number
CN108431952A
CN108431952A CN201680058261.6A CN201680058261A CN108431952A CN 108431952 A CN108431952 A CN 108431952A CN 201680058261 A CN201680058261 A CN 201680058261A CN 108431952 A CN108431952 A CN 108431952A
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China
Prior art keywords
microelectronic device
wire bonding
coupled
vertical integration
those
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CN201680058261.6A
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English (en)
Inventor
阿修克·S·普拉布
阿比欧拉·奥佐拉
惠尔·佐尼
威尔马·苏比杜
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Ying Fansasi Co
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Ying Fansasi Co
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Publication of CN108431952A publication Critical patent/CN108431952A/zh
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Abstract

大致相关于一种垂直整合的微电子封装的设备被揭示。在本揭示的设备中，基板具有上表面以及与该上表面相对的下表面。第一微电子装置耦接至该基板的该上表面。该第一微电子装置是被动微电子装置。第一引线接合线耦接至该基板的该上表面，并且从该基板的该上表面延伸离开。第二引线接合线耦接至该第一微电子装置的上表面，并且从该第一微电子装置的该上表面延伸离开。该些第二引线接合线是比该些第一引线接合线短。第二微电子装置耦接至该些第一引线接合线以及该些第二引线接合线的上末端。该第二微电子装置是位在该第一微电子装置上方，并且至少部分地重叠该第一微电子装置。

Description

内嵌的引线接合线
相关申请案的交互参照
此申请案兹主张2015年10月12日申请的美国临时专利申请案序号US62/240,443的优先权，该专利申请案的整体是为了所有的目的而藉此被纳入在此作为参考。
技术领域
以下的说明是大致有关于内嵌的引线接合线。更具体而言，以下的说明是有关于被互连接至封装的各种表面以用于多层的互连线的垂直的整合的内嵌的引线接合线。
背景技术
微电子组件一般包含一或多个IC，例如是一或多个经封装的晶粒("晶片")或是一或多个晶粒。此种IC中的一或多个可被安装在电路平台上方，例如像是晶圆层级封装("WLP")的晶圆、印刷板("PB")、印刷线路板("PWB")、印刷电路板("PCB")、印刷线路组件("PWA")、印刷电路组件("PCA")、封装基板、中介体、或是晶片载体。此外，IC可被安装在另一IC上方。中介体可以是被动式IC或是主动式IC，其中后者包含一或多个例如是电晶体的主动装置，而前者并不包含任何主动装置，但是可包含一或多个例如是电容器、电感器、及/或电阻器的被动装置。再者，中介体可被形成像是PWB，亦即不具有任何的电路元件，例如是不具有任何被动或主动装置。此外，中介体可包含至少穿过基板的贯孔(via)。
IC例如可包含导电的元件，例如是路径、线路、轨迹、贯孔、接点、像是接触垫及焊垫的垫、插塞、节点、或是端子，其可被使用于与电路平台电互连。这些配置可以使得被用来提供IC的功能的电连接变得容易。IC可以藉由接合来耦接至电路平台，例如是接合此种电路平台的线路或端子至IC的焊垫或是接脚或柱的露出的末端或类似者；或是IC可以藉由焊接来耦接至电路平台。此外，重分布层("RDL")可以是IC的部分，以例如使得覆晶的配置、晶粒堆叠、或是焊垫的更便利或可接达的位置变得容易。
某些被动或是主动微电子装置可被用在一种系统级封装("SiP")或是其它多晶粒/构件的封装中。然而，用于某些应用的某些SiP可能会占据过大的面积。再者，对于某些低轮廓的应用而言，某些SiP可被使用；然而，利用穿过半导体的贯孔来形成用于堆叠的SiP对于某些应用而言可能是过于昂贵的。
于是，提供用于SiP的垂直的整合将会是所期望且有用的。
发明内容
一设备大致有关于一种垂直整合的微电子封装。在此种设备中，基板具有上表面以及与该上表面相对的下表面。第一微电子装置耦接至该基板的该上表面。该第一微电子装置可以是主动或被动微电子装置。第一引线接合线耦接至该基板的该上表面，并且从该基板的该上表面延伸离开。第二引线接合线耦接至该第一微电子装置的上表面，并且从该第一微电子装置的该上表面延伸离开。该些第二引线接合线比该些第一引线接合线短。第二微电子装置耦接至该些第一引线接合线以及该些第二引线接合线的上末端。该第二微电子装置是位在该第一微电子装置上方，并且至少部分地重叠该第一微电子装置。
一设备是大致有关于另一种垂直整合的微电子封装。在此种设备中，基板具有上表面以及与该上表面相对的下表面。第一微电子装置耦接至该基板的该上表面。该第一微电子装置是主动或被动微电子装置。第一引线接合线耦接至该基板的该上表面，并且从该基板的该上表面延伸离开。第二引线接合线耦接至该第一微电子装置的上表面，并且从该第一微电子装置的该上表面延伸离开。该些第一引线接合线的第一部分是高于该些第二引线接合线。第二微电子装置耦接至该些第一引线接合线的该第一部分的第一上末端，并且耦接至该些第二引线接合线的上末端。该第二微电子装置是位在该第一微电子装置上方，并且至少部分地重叠该第一微电子装置。该些第一引线接合线的第二部分具有第二上末端，该些第二上末端耦接至该第一微电子装置的上表面。
一设备是大致有关于又一种垂直整合的微电子封装。在此设备中，第一电路平台具有上表面以及与该上表面相对的下表面。微电子装置耦接至该第一电路平台的上表面。第一引线接合线耦接至该第一电路平台的上表面，并且从该第一电路平台的该上表面延伸离开。第二引线接合线耦接至该微电子装置的上表面，并且从该微电子装置的该上表面延伸离开。该些第二引线接合线比该些第一引线接合线短。第二电路平台耦接至该些第一引线接合线以及该些第二引线接合线的上末端。该第二电路平台是位在该第一微电子装置上方，并且至少部分地重叠该第一微电子装置。
附图说明
所附的图式是展示根据范例的设备或方法的一或多个特点的范例实施例。然而，所附的图式不应该被视为限制申请专利范围的范畴，而只是用于解说及理解而已。
图1A是描绘范例性的习知的系统级封装("SiP")的侧视方块图。
图1B是描绘另一范例性的习知的SiP的侧视方块图。
图2是描绘习知的EMI屏蔽的范例的部分角落的俯视立体图。
图3A及3B是描绘个别的具有EMI屏蔽的范例的SiP的俯视方块图。
图4是描绘具有EMI屏蔽的范例的SiP的侧视横截面方块图。
图5是描绘范例性的SiP的侧视横截面方块图，其具有导电罩盖并且具有在该导电罩盖之下的EMI屏蔽区域中的信号引线接合线。
图6是描绘具有利用上方的基板的EMI屏蔽的范例的SiP的侧视横截面方块图。
图7是描绘在法拉第笼(Faraday cage)的上方的导电表面加入之前的SiP的范例的部分的俯视方块图。
图8是描绘在法拉第笼的上方的导电表面加入之前的另一SiP的范例的部分的俯视方块图。
图9A是描绘具有EMI屏蔽的堆叠式封装("PoP")装置的范例的部分的侧视横截面方块图。
图9B是描绘另一具有EMI屏蔽的PoP装置的范例的部分的侧视横截面方块图。
图10是描绘另一SiP的范例的部分的侧视横截面方块图。
图11A是描绘不具有引线接合线EMI屏蔽的SiP的范例的部分的侧视横截面方块图。
图11B是描绘另一不具有引线接合线EMI屏蔽的SiP的范例的部分的侧视横截面方块图。
图12A至12D是描绘个别的不具有引线接合线EMI屏蔽的SiP的范例的部分的个别的侧视横截面方块图。
图13A至13D是描绘个别的不具有引线接合线EMI屏蔽而具有垂直整合的微电子封装的SiP的范例的部分的个别的侧视横截面方块图。
图14A至14D是描绘用于垂直整合的微电子封装的范例的SiP的个别的侧视横截面方块图。
图15A至15D是描绘引线接合垫以及覆晶的垫在相同的基板上的渐进的形成的侧视方块图。
具体实施方式
在以下的说明中，许多特定的细节被阐述，以提供在此所述的特定例子的更彻底的说明。然而，对于熟习此项技术者应该明显的是，一或多个其它例子或是这些例子的变化可以在无所有以下给出的特定细节下加以实施。在其它实例中，众所周知的特点并未详细地叙述，以防模糊在此的例子的说明。为了便于说明，相同的元件符号在不同的图中被使用以参照到相同的项目；然而，在替代的例子中，该些项目可以是不同的。
范例的设备及/或方法在此加以描述。应了解的是，该字词"范例的"在此被使用以表示"当作为一个例子、实例、或是例证"。任何在此叙述为"范例"的例子或特点并不一定被解释为相对其它例子或特点为较佳或是有利的。
在微电子装置中的干扰可能是来自电磁干扰("EMI")及/或射频干扰("RFI")。干扰屏蔽的以下的说明可被使用于这些类型的干扰的任一种或是两者。然而，为了举例且非限制性的清楚的目的起见，大致只有针对EMI的屏蔽在以下用额外的细节来加以描述。
图1A是描绘不具有EMI屏蔽的范例的习知系统级封装("SiP")10的侧视方块图。在SiP 10中，可以有耦接至封装基板19的一或多个主动微电子装置11、被动微电子装置12、及/或IC晶粒13。在此例子中，可以是被动式或主动式的晶粒的IC晶粒13可能会遭受到EMI。IC晶粒13可以利用引线接合15而被引线接合至封装基板19，该些引线接合15是用于载有输入/输出信号及其它信号、电源电压以及接地参考电压。
封装基板19可以是由称为积层或积层基板的薄层所形成的。积层可以是有机或无机的。用于"刚性"封装基板的材料例子包含例如是FR4或FR5的环氧树脂基的积层、例如是双马来酰亚胺-三嗪("BT")树脂基的积层、陶瓷基板(例如，低温共烧陶瓷(LTCC))、玻璃基板、或是其它形式的刚性封装基板。再者，封装基板19在此可以是PCB或是其它电路板。为了清楚的目的起见，其它有关习知的SiP 10的已知的细节并未被叙述。
图1B是描绘另一不具有EMI屏蔽的范例的习知的SiP 10的侧视方块图。除了例如是微凸块的覆晶的("FC")互连17被使用，而不是引线接合15之外，图1B的SiP 10与图1A的SiP 10相同的。即使微凸块互连17是说明性地被描绘，但是其它类型的晶粒表面安装的互连亦可被使用。再者，尽管未说明性地描绘在图1B中，但是微凸块互连17可以在引线接合15之外另外被使用。
图2是描绘习知的EMI屏蔽20的范例的部分的角落的俯视立体图。在习知的EMI屏蔽20中，顶端导电板23可被设置在底部导电板24上方，其中此种底部导电板24具有大于此种顶端导电板23的表面积。
导电板23及24分别可以耦接至具有引线接合21及22的列的封装基板19。因此，顶端板23的两个侧边可以与对应的列的引线接合21来加以引线接合，并且底部板24的两个侧边同样地可以与对应的列的引线接合22来加以引线接合。非导电的间隙壁(未显示)可被用来隔离引线接合21与底部导电板24。待被EMI屏蔽的微电子装置(未显示)可被夹设在顶端及底部导电板23及24之间。此类型的具有引线接合的EMI屏蔽对于许多应用而言可能是过于庞大的。再者，在相关提供侧边EMI屏蔽的引线接合的相对的侧边上可能会有间隙。
干扰屏蔽
图3A及3B是描绘个别的具有EMI屏蔽的范例的SiP 100的俯视方块图。SiP 100的每一个都可包含封装基板19，其具有耦接至其的上表面132的一或多个主动微电子装置11、一或多个被动微电子装置12、以及引线接合线131，其中此种引线接合线131的上末端可以耦接至封装基板19的上表面132。上表面132可以是导电表面。引线接合线131可包含等于或小于约0.0508毫米(2密耳)的导线直径。
引线接合线131的一部分可被设置以界定屏蔽区域133。以此种方式，引线接合线131的BVA配置136的列与行可被用来包围或者是围绕屏蔽区域133。此种引线接合线131的至少一子集合的围绕屏蔽区域133的上末端可被用来支撑导电表面130，因而此种导电表面130可以是在此种屏蔽区域133上方，以用于覆盖此种屏蔽区域133。
导电表面130可以是导电的刚性或可挠性的表面。在一实施方式中，导电表面130可以是可挠性的，例如是在可挠性的片的表面上的可挠性的导电涂层。在另一实施方式中，刚性板可以提供导电表面。刚性板可以是由一种导电材料所做成的。然而，导电涂层可被喷涂或是擦涂在刚性板或是可挠性的片上。在图3B的例子中，如同在以下以额外的细节叙述的，导电表面130可以具有孔洞137，以用于容许界定屏蔽区域133的引线接合线131中的至少一些引线接合线131的上方部分能够延伸穿过导电表面130。
图4是描绘具有EMI屏蔽的范例的SiP 100的侧视横截面方块图。SiP 100可包含封装基板19，其具有耦接至封装基板19的上表面132的一或多个主动微电子装置11、一或多个被动微电子装置12、以及引线接合线131，其中此种引线接合线131的上末端可以耦接至导电表面130。即使SiP 100被描述，但是其它类型的具有免于EMI的保护的微电子封装亦可被使用。
封装基板19具有上表面132以及与该上表面相对的下表面149。封装基板19可以具有位在表面132及149之间的接地面140以及贯孔142，其中贯孔142可以互连接至此种接地面140以用于导电。
引线接合线131可以利用贯孔142来耦接至接地面140。某些引线接合线131可以利用用于导电的球体接合141来机械式地耦接至上表面132；然而，在其它实施方式中，其它类型的接合亦可被使用。再者，并非所有的引线接合线131都需要耦接至接地面140。某些引线接合线131可被使用于在SiP 100之内载有供应电压或信号。某些引线接合线131可被使用于耦接至在SiP 100之内的其它装置。
主动或被动的微电子装置145可以耦接至封装基板19的上表面132。微电子装置145可包含主动的集成电路晶粒及/或被动构件。被动构件例如可以是电容器、电感器、或是电阻器、或是其的任意组合。
微电子装置145可以利用如先前所述的球体或凸块互连及/或引线接合线来耦接至封装基板19。再者，微电子装置145可以利用粘着剂或是底胶填充层(未显示)来耦接至上表面132。
微电子装置145可被设置在介电保护材料中，该介电保护材料可被设置为围堰(dam)填充或是一模制层("模制层")143。此种模制层143可以是密封剂或是模制材料，以用于至少覆盖微电子装置145的上表面以及侧壁。引线接合线131可被设置在微电子装置145的侧壁的周围。
导电表面130可以是位在介电保护材料模制层143的顶端或上表面146上方、或是耦接至介电保护材料模制层143的顶端或上表面146。然而，在另一实施方式中，如同在以下以额外的细节叙述的，介电保护材料模制层143的顶表面可以是位在高于引线接合线131的尖端148的高度处。导电表面130可被设置在和法拉第笼153相关的引线接合线131上方。此种引线接合线131的上末端或尖端148可以机械式地耦接至导电表面130。此耦接可以是利用热压接合或是其它形式的机械式耦接。
法拉第笼153可以是接地面140的一部分例如利用贯孔142来互连接至支撑导电表面130的引线接合线131的一组合。在另一实施方式中，在导电表面130与引线接合线131的某些个的尖端148之间可以有间隙144。以此种方式，导电表面130的底部，例如是导电板的底部例如可以附接至、或是安置在介电保护材料模制层143的顶表面上方，因而介电保护材料模制层143的高度可以是大于引线接合线131的高度。
因此，导电表面130可被设置在引线接合线131的一部分上方，其中引线接合线131的上末端或尖端148是和导电表面130间隔开。然而，一种具有间隙144的配置可能会提供较不有效的法拉第笼153，因而为了例如且非限制性的清楚的目的起见，应假设是没有间隙的。
耦接至接地面140而从封装基板19的上表面132向上突出或延伸离开的引线接合线131可加以排列。以此种方式，即使引线接合线131的一种Bond Via ArrayTM或是配置136的单一列与行在一实施方式中可以存在，但是一种BVA配置136的多个列及/或多个行的引线接合线131可以沿着屏蔽区域133的一或多个侧边而存在。
为了重述要点，引线接合线131中的某些例如是在界定屏蔽区域133的BVA配置136中的引线接合线131可被设置，以提供此种避免EMI或相关EMI的屏蔽区域133给微电子装置145。引线接合线131的其它位在屏蔽区域133之外的部分可能并未被使用于EMI屏蔽。再者，一或多个其它主动或被动微电子装置11及/或12可以耦接至基板19，并且是位在屏蔽区域133之外，因而不是此种屏蔽区域的部分、或是被设置用于此种屏蔽区域的位置。
图5是描绘范例性的SiP 100的侧视横截面方块图，其具有导电罩盖150，并且在导电罩盖150之下的EMI屏蔽区域中具有信号引线接合线131s。图5的SiP 100是与图4的SiP100相同的，但是具有以下的差异。
在此例子中，引线接合线131的一部分具有高度大于引线接合线131的另一部分的高度。两组的引线接合线131都可以接近微电子装置145而且在微电子装置145的周围来加以设置。然而，引线接合线131的较高的部分可以是用于提供相关EMI的屏蔽区域133给微电子装置145。然而，引线接合线131的其它较矮的部分("引线接合线131s")可以是耦接微电子装置145至封装基板19的导体的信号线。此种较矮的引线接合线131s中的一些引线接合线131s可以是在法拉第笼153之内。较高的引线接合线131的高度可能会受限于低轮廓的封装应用。
导电罩盖150可以耦接至封装基板19的上表面132。导电罩盖150可以覆盖SiP 100的耦接至上表面132的构件，其包含微电子装置145、微电子装置11、12以及引线接合线131。并非BVA配置136的部分的引线接合线131可以将导电罩盖150以及接地面140互连。此耦接可被使用以降低内部的杂讯。然而，法拉第笼153可以是位在覆盖150之下，以用于内部的EMI屏蔽。选配的是，导电表面130可被省略，而有利于利用导电罩盖150作为法拉第笼153的上方的导电表面，而不论在尖端148与导电罩盖150的底面之间具有或是不具有间隙144。
某些在BVA配置136之内的引线接合线131可以是信号线，亦即引线接合线131s。引线接合线131s可以不耦接至接地面140，而是可以耦接至封装基板19的线路(未显示)。引线接合线131s的尖端可以在介电保护材料模制层143的使用之前，先被接合或是焊接至微电子装置145。在另一实施方式中，相关微电子装置145的介电保护材料模制层143可被省略。
引线接合线131s可被接合到被动微电子装置12或是主动微电子装置11中的一或多个的上表面。这些引线接合线131s可以是用于在SiP 100之内的互连。
图6是描绘范例性的SiP 100的侧视横截面方块图，其具有利用上方的基板169的EMI屏蔽。图6的SiP 100是与图5的SiP 100相同的，但是并不具有导电罩盖150，而且具有以下的差异。
上方的基板169可包含贯孔162以及接地面160。引线接合线131的尖端或是上末端148可以沿着上方的基板169的底表面，利用互连161(例如是利用微球体或微凸块)来互连接至贯孔162，例如以用于耦接至接地面160。互连161可被设置在介电保护材料模制层143的上表面168上。接地面160可以提供法拉第笼153的上方的导电表面130。
另一不论是主动或被动的微电子装置165可以耦接至上方的基板169的顶表面。微电子装置165可以利用引线接合线15来耦接至基板169的贯孔或线路；然而，微球体或是微凸块可以在另一实施方式中被使用。微电子装置165可以耦接在法拉第笼153之外。
图7是描绘在法拉第笼153的上方的导电表面130加入之前的SiP 100的一范例的部分的俯视方块图。焊垫170可以接近微电子装置145而且在微电子装置145的周围来加以设置，以用于将引线接合线131分别耦接至其，以用于提供法拉第笼153的屏蔽区域133。屏蔽区域133可被界定在BVA配置136之内。
焊垫170可以在介电保护材料模制层143的侧边周围和彼此间隔开。在介电保护材料模制层143中的微电子装置145可以是位在屏蔽区域133的中央部分中。焊垫170的垫至垫的间距171可以是等于或小于约250微米。焊垫170的间距171可以针对于和例如是EMI及/或RFI的干扰相关的频率来加以选择，以将微电子装置145与EMI及/或RFI屏蔽开。再者，微电子装置145可能是干扰的辐射体，并且因而此种屏蔽可以是用以保护SiP 100的其它构件免于由微电子装置145所产生的干扰。
即使单一列与行的焊垫170说明性地被描绘，但是在另一实施方式中可以有超过一或两个列及/或行。再者，焊垫170的列及/或行可以相关彼此来交错的，以提供较稠密的屏蔽。引线接合线131可以有效地被用来提供低通滤波器的法拉第笼，以用于降低相关微电子装置145的操作的EMI。以此种方式，尽管并非必要的，但焊垫170的设置以及因此的引线接合线131的设置可以是一致的。引线接合线131可以针对于被调适以屏蔽往微电子装置145、或是来自微电子装置145的特定范围的频率密度来加以置放及/或调整。
图8是描绘在法拉第笼153的上方的导电表面130加入之前的另一SiP 100的一范例的部分的俯视方块图。在此例子中，引线接合线131的BVA配置136的两个列以及两个行是被用来界定屏蔽区域133。在此例子中，在列与行之间的间隔是交错的，以提供较稠密的引线接合线131的样式。
在此例子中，BVA配置136的引线接合线131中的某些个是用于载有信号，亦即引线接合线131s。以此种方式，互连180可被形成以用于从微电子装置145延伸到介电保护材料模制层143之外，以用于与引线接合线131s的互连，该些引线接合线131s可包含一或多个信号线。
图9A是描绘具有EMI屏蔽的堆叠式封装的("PoP")装置190的一范例的部分的侧视横截面方块图。PoP装置190可包含上方的SiP 100U，其堆叠在下方的SiP 100L的顶端上。PoP装置190例如可包含一或多个在屏蔽区域之外的其它微电子装置以及其它的细节，例如是先前参考图3A至8所述者。于是，为了清楚且非限制性的目的起见，先前针对于SiP 100所叙述的细节并未在以下加以叙述。
下方的SiP 100L的下方的封装基板19L可包含下方的接地面140L，其使得下方的引线接合线131L从下方的封装基板19L的上表面向上地延伸。此种下方的引线接合线131L及接地面140L可以例如是利用如先前所述的贯孔及球体接合来互连接至彼此，以用于形成法拉第笼153的下方的部分。下方的引线接合线131L的尖端148可以沿着上方的封装基板19U的下方侧，利用互连191而被接合或耦接至针对该些互连191的垫及贯孔。
选配的是，上方的封装基板19U可包含上方的接地面140U，以用于形成法拉第笼153来作为两个法拉第笼的堆叠，亦即上方的法拉第笼192U以及下方的法拉第笼192L。法拉第笼192U及192L的每一个都可包含分别耦接至封装基板19U及19L的上表面的个别的封装的微电子装置145U及145L。
上方的基板19U的上方的接地面140U可以是位在下方的微电子装置145L上方，因而下方的引线接合线131L的尖端或上末端148可以沿着上方的封装基板19U的底表面，利用互连191来互连接至垫或接点以用于电耦接至上方的接地面140U。上方的引线接合线131U以及选配的接地面140U可以例如利用如先前所述的贯孔以及球体接合来互连接至彼此，以用于形成法拉第笼153的上方部分。上方的引线接合线131U的尖端148可被接合或是耦接至导电表面130，以用于完成此种上方的法拉第笼192U。
在另一实施方式中，上方的基板封装19U的贯孔可以在不连接至上方的接地面140U之下，互连下方的引线接合线131L以及上方的引线接合线131U，以形成用于两个微电子装置145U、145L的"两个楼层的"或是两层的法拉第笼153。即使只有两层是说明性地被描绘，但是超过两层亦可被使用在其它的实施方式中。
图9B是描绘另一具有EMI屏蔽的PoP装置190的范例的部分的侧视横截面方块图。PoP装置190例如可包含一或多个在屏蔽区域之外的其它的微电子装置以及其它细节，例如是先前参考图3A至9A所述者。于是，为了清楚且非限制性的目的起见，先前针对于SiP 100所叙述的细节并未在以下加以叙述。
除了以下的差异之外，图9B的PoP装置190可以是与图9A的PoP装置190相同的。图9B的PoP装置190可包含信号引线接合线131s。信号引线接合线131s可以是位在法拉第笼153之内，其包含在法拉第笼192U之内。
在此配置中的信号引线接合线131s可以从下方的微电子装置145L的上表面向上地延伸。从下方的微电子装置145L的上表面延伸的引线接合线131s的尖端或上末端148可以例如是利用互连191而互连接至上方的封装基板19U的下面侧。贯孔及/或线路(未显示)可以利用信号引线接合线131s来电耦接上方及下方的微电子装置145。再者，下方的基板封装19L可包含用于与下方的微电子装置145互连的贯孔及/或线路(未显示)。
图10是描绘另一具有EMI屏蔽的SiP 100的范例的部分的侧视横截面方块图。SiP100例如可包含一或多个在屏蔽区域之外的其它的微电子装置以及其它细节，例如是先前参考图3A至9B所述。于是，为了清楚且非限制性的目的起见，先前针对于SiP 100所叙述的细节并未在以下加以叙述。
在此例子中，引线接合线131以及例如是IC晶粒的微电子装置145被介电保护材料模制层143所保护。微电子装置145可以在沉积或是注入介电保护材料模制层143之前，利用微凸块互连17来互连至封装基板19的上表面。同样地，在沉积或是注入介电保护材料模制层143之前，引线接合线131可以被球体接合到封装基板19的上表面。
选配的是，信号引线接合线131s可以在沉积或是注入介电保护材料模制层143之前，被球体接合到微电子装置145的上表面201。信号引线接合线131s因此可以是在法拉第笼153的屏蔽区域133之内。
引线接合线131的尖端或上末端148以及选配的信号引线接合线131s可以延伸在介电保护材料模制层143的上表面202上方。焊料球体或是其它的互连共晶体204可加以沉积到尖端148上方，以用于例如是在此的别处所描述的后续的互连。
不具有干扰屏蔽的垂直的整合
图11A是描绘不具有引线接合线EMI屏蔽的SiP 100的一范例的部分的侧视横截面方块图。图11B是描绘另一不具有引线接合线EMI屏蔽的SiP 100的一范例的部分的侧视横截面方块图。同时参考图11A及11B，分别说明性地描绘在那些图中的SiP 100是进一步加以叙述。SiP 100的每一个都可以包含一或多个其它微电子装置以及其它细节，例如是先前所叙述者。于是，为了清楚且非限制性的目的起见，先前针对于SiP 100所叙述的细节并未在以下加以叙述。
SiP 100的每一个包含垂直整合的微电子封装200。微电子封装200的每一个包含基板19，其具有上表面132以及与该上表面相对的下表面149。封装基板19可以具有位在表面132及149之间的接地面140、以及互连接至此种接地面以用于导电的贯孔142。
微电子装置145可以耦接至基板19的上表面132，其中微电子装置是被动微电子装置。以此种方式，在SiP 100中，可以有被动或是主动微电子装置中的任一种或是两者的一或多个耦接至上表面132。此表示有此种微电子装置的上表面在过去对于垂直的整合而言可能已经变成是未使用的，现在则例如藉由如同在此所述的使得接合的引线接合线附接至此种微电子装置的此种上表面。
以此种方式，引线接合线131可以耦接至基板19的上表面132并且从该上表面132延伸离开，并且引线接合线231可以耦接至微电子装置145的上表面201并且从该上表面201延伸离开。引线接合线131及231分别可以利用用于导电的球体接合141来机械式地耦接至上表面132及201。然而，在其它实施方式中，其它类型的接合亦可被使用。引线接合线231在长度上比引线接合线131短的。
参考图11A，引线接合线131可以具有整体完成后的长度261，并且引线接合线231可以具有整体完成后的长度262。然而，引线接合线131及231的完成后的高度可以是大致相同的。引线接合线131以及231的尖端或是上末端148可以延伸在模制层143的上表面202上方。
上末端148可以为了大致是共面的而为毗连的。焊料球体或是其它的互连共晶体204可以在上表面202上，而分别加以沉积在上末端148上方，以用于与在主动或被动微电子装置165的正面的底面上的垫(未显示)形成互连。
一被动微电子装置145可以耦接至封装基板19的上表面132。微电子装置145可包含导电线路，并且可以只包含被动构件。被动构件可包含电容器、电感器、或是电阻器、或是其任意组合中的一或多个。
如同先前所述的，微电子装置145可以利用球体或凸块互连及/或引线接合线来耦接至封装基板19。再者，微电子装置145可以利用粘着剂或是底胶填充层(未显示)来耦接至上表面132。
在此实施方式中，微电子装置145以及微电子装置165可以具有面向下的朝向，亦即朝向基板19的上表面132之面朝下的朝向。然而，在另一实施方式中，微电子装置165可以具有从基板19的上表面132面向上的正面的侧面。
微电子装置165可以被耦接在模制层143的最上面的表面202上方。在一实施方式中，微电子装置165可以利用共晶体204或是其它的机械式互连来耦接至引线接合线131及231的上末端148。微电子装置165可以是位在微电子装置145上方，并且至少部分地重叠此种微电子装置145。
模制层143可以具有最上面的表面202以及与该最上面的表面相对的最下面的表面252。模制层143可被设置以用于围绕引线接合线131及231两者的长度261及262的部分。上末端148例如可以像是藉由用于注入模制的模制辅助膜的使用而不被模制层143所覆盖。在另一实施方式中，模制层143可以暂时完全覆盖长度261及262，接着是回蚀以露出上末端148。
在一垂直整合的微电子封装200的一实施方式中，微电子装置145可被设置在模制层143中。以此种方式，在一实施方式中，微电子装置145可以完全位在模制层143的最上面的表面202与最下面的表面252之间。引线接合线131可被设置在微电子装置145的侧壁203的周围，尽管在此范例实施方式中并非是用于干扰的屏蔽。
引线接合线131可以耦接至接地面140，以用于从封装基板19的上表面132向上地突出或延伸，并且可加以排列。以此种方式，尽管引线接合线131及/或231的一配置的单一列与行在一实施方式中可以存在，但是多个列及/或多个行的此种引线接合线亦可以是在配置中。
在垂直整合的微电子封装200的一实施方式中，本身是被动微电子装置的微电子装置165可被使用。然而，在垂直整合的微电子封装200的另一实施方式中，本身是主动微电子装置的微电子装置165可被使用。
参考图11B，内部的引线接合线131i可以具有整体完成后的长度263，并且引线接合线231可以具有整体完成后的长度264。如同先前参考图11A所述的，外部的引线接合线131o可以具有整体完成后的高度261。引线接合线131i及231在形成之后的完成后的高度可以是大致相同的。引线接合线131i及231的上末端148可以是大致与彼此为高低相同的。
引线接合线131i及231的上末端148可以是为了大致是共面的而为毗连的。焊料球体或是其它的互连共晶体274分别可以将主动或被动微电子装置271的下表面耦接至引线接合线131i及231的上末端148，以用于与在主动或被动微电子装置271的正面的底面上的垫(未显示)形成互连。在微电子装置271处于适当的地方下，模制材料可被注入以形成模制材料层143，并且因此微电子装置271的下表面可以接触到模制层143的模制材料。为了模制，模制辅助膜可被用来容许外部的引线接合线131o的尖端148、以及微电子装置271的垫或是其它互连(未显示)，能够延伸在模制层143的上表面202上方。在另一实施方式中，模制层143可以暂时完全地覆盖长度261，接着是回蚀以露出其的上末端148。
微电子装置271可以耦接至微电子装置145而且位在微电子装置145上方，并且可以至少部分地重叠微电子装置145。以此种方式，微电子装置271可以横向地延伸在微电子装置145的周边之外，以用于内部的引线接合线131i在基板19的上表面132与微电子装置271的面对此种上表面132的下表面之间的互连。引线接合线131i以及引线接合线131o可被设置在微电子装置145的侧壁203的周围，尽管在此范例实施方式中并非用于干扰的屏蔽。
同样地，一被动微电子装置145可以耦接至封装基板19的上表面132。微电子装置145可包含导电线路，并且可以只包含被动构件、只包含被动构件、或是其之组合。被动构件可包含电容器、电感器、或是电阻器、或是其的任意组合。如先前所述，微电子装置145可以利用球体或是凸块互连及/或引线接合线来耦接至封装基板19。再者，微电子装置145可以利用粘着剂或是底胶填充层(未显示)来耦接至上表面132。
模制层143可以具有最上面的表面202以及与该最上面的表面相对的最下面的表面252。模制层143可被设置以用于围绕引线接合线131o的长度261的部分，并且用于围绕引线接合线131i及231两者的长度263及264。
在垂直整合的微电子封装200的实施方式中，微电子装置145可被设置在模制层143中，并且完全位在模制层143的最上面的表面202与最下面的表面252之间。微电子装置271可被设置在模制层143中，并且至少部分地位在模制层143的最上面的表面202与最下面的表面252之间。微电子装置165可以被耦接在模制层143的最上面的表面202上方。
对于被动微电子装置271而言，微电子装置271可包含导电线路，并且可以只包含被动构件。微电子装置271可包含RDL。被动构件可以是电容器、电感器、或是电阻器、或是前述构件的任意组合。在此实施方式中，微电子装置145及271、以及微电子装置165具有面向下的朝向，亦即朝向基板19的上表面132的面朝下的朝向。然而，在另一实施方式中，微电子装置165及/或微电子装置271可以具有从基板19的上表面132面向上的正面的侧面。
在垂直整合的微电子封装200的一实施方式中，本身是被动微电子装置的微电子装置165可被使用。然而，在垂直整合的微电子封装200的另一实施方式中，本身是主动微电子装置的微电子装置165可被使用。微电子装置165可以耦接在模制层143的最上面的表面202上方，以用于与微电子装置271的互连。在一实施方式中，微电子装置165可以利用用于导电的共晶体204或是其它的机械式互连来耦接至微电子装置271的上表面。
微电子装置165可以是位在微电子装置271上方，并且至少部分地重叠此种微电子装置271。以此种方式，微电子装置165可以耦接在模制层143的最上面的表面202上方，以用于与外部的引线接合线131o的上末端148的互连、以及与微电子装置271的上表面的互连。
引线接合线131i及131o可以耦接至接地面140，以用于从封装基板19的上表面132向上地突出或延伸，并且可加以排列。以此种方式，即使引线接合线131i、131o及/或231的一配置的单一列与行在一实施方式中可以存在，但是多个列及/或多个行的此种引线接合线可以是在一配置中。
图12A是描绘另一不具有引线接合线EMI屏蔽的SiP 100的一范例的部分的侧视横截面方块图。除了以下的细节之外，图12A的SiP 100可以是与在图11A中的相同。在垂直整合的微电子封装200的此实施方式中，微电子装置165可以悬臂伸出，以用于横向地延伸超过引线接合线131并且在引线接合线131上方。以此种方式，引线接合线131的上末端148可以利用共晶体204来互连至微电子装置165的下表面。
图12B是描绘另一不具有引线接合线EMI屏蔽的SiP 100的一范例的部分的侧视横截面方块图。除了以下的细节之外，图12B的SiP 100可以是与在图11B中的相同。在垂直整合的微电子封装200的此实施方式中，微电子装置165并未悬臂伸出以用于横向地延伸超过引线接合线131o并且在引线接合线131o上方。以此种方式，微电子装置165以及微电子装置271对于其分别的下表面以及上表面可以具有大致相等的表面积。
图12C是描绘另一具有或是不具有整合的引线接合线EMI屏蔽的SiP 100的一范例的部分的侧视横截面方块图。除了以下的细节之外，图12C的SiP 100可以是与在图12A中的相同。在垂直整合的微电子封装200的此实施方式中，微电子装置165悬臂伸出以用于在微电子装置145在该图中的一右侧以及一左侧上横向地延伸超过引线接合线131并且在引线接合线131上方。以此种方式，引线接合线131的上末端148可以利用共晶体204来互连至微电子装置165的下表面。于是，应该体认到的是，被设置在微电子装置的周围并且互连接至微电子装置165的引线接合线131可被使用于扇出。
图12D是描绘另一具有或是不具有整合的引线接合线EMI屏蔽的SiP 100的一范例的部分的侧视横截面方块图。除了以下的细节之外，图12D的SiP 100可以是与在图12B中的相同。在垂直整合的微电子封装200的此实施方式中，微电子装置165并未悬臂伸出以用于横向地延伸超过引线接合线131o并且在引线接合线131o上方。以此种方式，微电子装置165以及微电子装置271对于其分别的下表面以及上表面可以具有大致相等的表面积。以此种方式，引线接合线131i的上末端148可以利用共晶体274来互连至微电子装置271的下表面。于是，应该体认到的是，被设置在一电子装置145的周围并且互连接至微电子装置271的引线接合线131i可被使用于扇出。
图13A是描绘具有垂直整合的微电子封装200的范例的SiP 100的侧视横截面方块图。在此实施方式中，垂直整合的微电子封装200可以是耦接至基板19的独立的封装，即如同在图12D中的SiP 100。由于SiP 100的构件先前已经例如是参考图4来加以叙述，因而此种说明并未予以重复。
在此实施方式中，例如是焊料球的共晶体274被形成在模制层143的上表面202上、在重分布层上、或是在该些引线接合线131i及231的尖端上。共晶体274将引线接合线131i及231的上末端148互连至微电子装置271的下表面。在另一实施方式中，共晶体274可被封入在模制层143中。在此例子中，微电子装置271的下表面并未接触模制层143的上表面202。
再者，在此范例实施方式中，信号引线接合线131s可被封入在模制层143的模制材料中，但不包括信号引线接合线131s的接触末端。信号引线接合线131s可以是短于内部的引线接合线131i，并且可以是如先前所述的用于与微电子装置145的互连。以此种方式，微电子装置271可以耦接至例如是引线接合线131i被耦接到上表面132的引线接合线131的较高的部分的上末端148。微电子装置271可以进一步耦接至引线接合线231的上末端148。例如是先前所叙述的，引线接合线131的另一耦接至上表面132的部分(例如是信号引线接合线131s)可以使得引线接合线131的上末端148耦接至微电子装置145的上表面。
选配的是，引线接合线331可以耦接至主动微电子装置11及/或被动微电子装置12的一或多个上表面，该微电子装置11及/或12直接被耦接到基板19的上表面132。
有关图13A的SiP 100的其它细节先前已经加以叙述，并且因此为了清楚且非限制性的目的起见而未予以重复。
图13B是描绘不具有EMI屏蔽而具有垂直整合的微电子封装200的范例的SiP 100的侧视横截面方块图。在此实施方式中，如同在图13A中的SiP 100，垂直整合的微电子封装200可以是耦接至基板19的独立的封装。由于SiP 100的构件先前已经例如参考图4来加以叙述，因而此种说明并不予以重复。
除了以下的差异之外，图13B的SiP 100是类似于图13A的SiP 100。在图13B的SiP100中，垂直整合的微电子封装200是省略微电子装置271。因此，例如是先前叙述的，微电子装置165可以利用共晶体204来直接耦接至模制层143的上表面202。
图13C是描绘具有垂直整合的微电子封装200的范例的SiP 100的侧视横截面方块图。在此实施方式中，如同在图13A中的SiP 100，垂直整合的微电子封装200可以是耦接至基板19的独立的封装。由于SiP 100的构件先前已经例如参考图4来加以叙述，因而此种说明并不予以重复。
除了以下的差异之外，图13C的SiP 100是类似于图13A的SiP 100。在图13C的SiP100中，垂直整合的微电子封装200具有某些如先前所述的被封入在模制层143的模制材料中的引线接合线131i，并且具有某些并未被封入在模制层143的模制材料中的引线接合线131i。
图13D是描绘具有垂直整合的微电子封装200的范例的SiP 100的侧视横截面方块图。在此实施方式中，如同在图13B中的SiP 100，垂直整合的微电子封装200可以是耦接至基板19的独立的封装。由于SiP 100的构件先前已经例如参考图4来加以叙述，因而此种说明并不予以重复。
除了以下的差异之外，图13D的SiP 100是类似于图13B的SiP 100。在图13D的SiP100中，垂直整合的微电子封装200并不具有被封入在模制层143的模制材料中的引线接合线131。
图14A是描绘具有垂直整合的微电子封装200的范例的SiP 100的侧视横截面方块图。由于图14A的SiP 100是类似于先前在此所述的SiP 100，因此为了清楚的目的起见，大致只有差异才在以下用额外的细节来加以描述。
在此范例实施方式中，电路平台400例如可以是像是封装基板19的封装基板、晶粒基板或中介体、导线架、或是例如RDL的绕线层。在此例子中，被动微电子装置271是大致被表示为电路平台401，其可以是绕线层、晶粒基板或中介体、或是封装基板。垂直的引线接合线131i可以互连电路平台400的上表面405至电路平台401的下表面403。在此例子中，微电子装置145是一个只有引线接合的装置，其利用环氧树脂或是其它的粘着层402，以使得微电子装置145的下表面406耦接至电路平台400的上表面405，该环氧树脂或其它的粘着层402是在此种面对的表面之间。
微电子装置145可以是处于一面朝上的朝向。引线接合线131s可以互连电路平台400的上表面405至微电子装置145的上表面407。较短的垂直的引线接合线231可以互连微电子装置145的上表面407以及电路平台401的下表面403。
介电保护材料模制层143可以是模制层或是一围堰填入的层，并且尽管展示只覆盖该SiP的一部分，但可以替代的是覆盖在该SiP 100中的构件的任一个或是全部。微电子装置145可以利用粘着层402来耦接至电路平台400，接着是将引线接合线131s及231引线接合。引线接合线231及131i可以在加入介电保护材料模制层143的模制或围堰填入的层之前，先耦接至电路平台401的下表面403。介电保护材料可以提供比仅使得引线接合线131i及231支撑电路平台401更加刚性的结构，因为下表面403以及侧壁表面404的至少部分可以被此种介电保护材料模制层143所覆盖。
图14B是描绘具有垂直整合的微电子封装200的范例的SiP 100的侧视横截面方块图。由于图14B的SiP 100是类似于图14A的SiP 100，因此大致只有差异才在以下用额外的细节来加以描述。
除了在微电子装置145的上表面407上的引线接合线231以外，另一微电子装置410可以利用另一环氧树脂或是其它的粘着层402以使得微电子装置410的下表面耦接至微电子装置145的上表面，该环氧树脂或是其它的粘着层402是在此种面对的表面之间。由垂直的引线接合线432所提供的另一组的互连可以耦接在微电子装置410的上表面与电路平台401的下表面403之间，以用于在微电子装置410与电路平台401之间的电性通讯。微电子装置145及410可以组合地形成晶粒堆叠，其中此种装置都处于一面朝上的朝向，以用于引线接合至其上方表面。
再者，除了具有引线接合线231以及微电子装置410在微电子装置145的上表面407上的一开始的设置以外，另一组的引线接合线431可以耦接至上表面407，以用于与微电子装置410的上表面408的互连。引线接合线431可以在向上弯弧以用于耦接至上表面408。这些引线接合线431因此可以将微电子装置145及410的上表面彼此互连。微电子装置145及410可以是主动装置、被动装置、或是主动及被动装置的组合。
同时参考到图14A及14B，耦接至电路平台401的可以是表面安装技术("SMT")的构件(其可以是主动或被动SMT微电子装置165)、以及引线接合安装的构件(例如是主动或被动引线接合的微电子装置411)的任一种或是两者。主动或被动SMT微电子装置165可以面向下地被安装至电路平台401的上表面441，并且主动或被动引线接合的微电子装置411可以面向上地被安装至电路平台401的上表面441。
图14C是描绘具有垂直整合的微电子封装200的范例的SiP 100的侧视横截面方块图。由于图14B的SiP 100是类似于图14A及14B的SiP 100，因此大致只有差异才在以下用额外的细节来加以描述。
在此范例实施方式中，中介体或是其它的电路平台414的下表面是利用微凸块或是其它的小形状因数的互连413来互连接至一面朝上的微电子装置145的上表面上的接点。中介体414的上表面是利用微凸块或是其它的小形状因数的互连415来互连接至一面朝下的微电子装置416的下表面上的接点。引线接合线131s的远端可以耦接至中介体414的上表面，以用于互连至电路平台400的上表面405。引线接合线231的近端或下方的末端可以耦接至中介体414的上表面，其中此种引线接合线的远端或上末端是耦接至电路平台401的下表面403。藉由利用中介体414以及覆晶或类似的微电子装置416，更多用于引线接合线231及/或131s的区域以及更多在微电子装置145及416之间的互连线可加以提供。
图14D是图14C的方块图，尽管是利用保护介电材料的模制层143覆盖电路平台400。此保护介电材料的模制层143是在电路平台400的上表面405上方提供互连表面418。引线接合线131及331可以使得引线接合线131及331的尖端或上末端延伸超出表面418，以用于一或多个被动或主动电路的互连。
这些是用于SiP 100的垂直整合的微电子封装200的各种实施方式中的一些实施方式。这些或其它的实施方式亦可以根据在此的说明来加以提供。
焊料上的引线接合
已经假设引线接合线是被引线接合到例如是铜的导电金属层上方。然而，如同在以下用额外的细节叙述的，引线接合线可被引线接合到焊料上方。以此种方式，无电电镀镍(Ni)无电电镀钯(Pd)浸金(Au)("ENEPIG")是一种用于基板制造(例如是用于IC)的表面处理。然而，由于IC制造商抛弃ENEPIG基板而不用于覆晶的应用，因此使得基板具有带有有机表面保护("OSP")层的铜以及ENEPIG处理的混合是有问题的。以此种方式，如同在以下以额外的细节叙述的，铜OSP是对于叠层的表面使用一种焊料加在垫上("SOP")的技术，其中例如是BVATM接脚的引线接合线是接合到此种焊料上方。
图15A至15D是描绘引线接合垫以及覆晶的垫在相同的基板600上的渐进的形成的侧视方块图。基板600可以是如上所述的封装基板或是其它基板，以用于SiP或是其它的微电子构件650。以此种方式，如同在以下用额外的细节叙述的，具有焊料的引线接合垫可被使用于上述的引线接合线，例如是被球体接合至此种垫。
参考图15A，基板600可以具有被沉积、电镀、或是以其它方式形成在其的上表面605上的导电层603，例如是铜的层或是其它的导电金属层。导电层603可被图案化，以用于在上表面605上提供引线接合垫601以及覆晶或类似的小形状因数的垫602两者。
焊料遮罩604可加以沉积及图案化。以此种方式，导电层603的上表面616可以是低于焊料遮罩604的上表面615，并且焊料遮罩604的部分可以是位在相邻的垫的垫601及602之间。以此种方式，焊料遮罩604可以具有用于接达引线接合垫601的间隙606、以及用于接达覆晶的垫602的较窄的间隙607。
参考图15B，焊料或其它的共晶层的焊料或其它的共晶垫608及609可以被印刷到垫601及602的上表面616上方。引线接合垫601的被露出的上表面616的表面积相对置放于引线接合垫601上的焊料垫608的下表面617的表面积之比例可以是实质小于引线接合垫602的被露出的上表面616的表面积相对置放于其上的焊料垫609的下表面617的表面积的比例。焊料垫608及609的每一个的一部分可以是高于焊料遮罩604的上表面615，并且焊料垫609的一部分可以重叠到上表面615上方。上表面615是在上表面616上方、或是高于上表面616。
参考图15C，在焊料垫608及609的回焊之后，焊料垫608及609的焊料可以散开，并且一助焊剂的量可被消除。以此种方式，焊料垫608可以散开在原先是对应至其的引线接合垫601的露出的表面区域上方。以此种方式，焊料垫608在回焊之后的上表面611可以是在焊料遮罩层604的上表面615之下、或是低于该上表面615。然而，焊料垫609在回焊之后的上表面613可以是在焊料遮罩层604的上表面615上方，并且可以重叠该上表面615。选配的是，在回焊之后，焊料垫609可以被压实以用于平坦化。
参考图15D，例如是引线接合线131的引线接合线可被例如是球体、针脚或是其它方式的接合至焊料垫608。以此种方式，沿着焊料垫608的上表面611的焊料可以附接至引线接合线131的铜、钯、或是其它材料。覆晶的IC晶粒649可以使得例如是微凸块的覆晶的接点648分别耦接至焊料垫609。
尽管前述内容描述根据本发明的一或多个特点的范例实施例，但是根据本发明的该一或多个特点的其它及进一步的实施例可以在不脱离本发明的范畴下而被设计出，该范畴是藉由本发明的权利要求书以及其等同物来加以决定。权利要求书所列的步骤并不意指该些步骤的任何顺序。商标则是其个别的拥有者的财产权。

Claims (28)

1.一种垂直整合的微电子封装，其包括：
基板，其具有上表面以及与该上表面相对的下表面；
第一微电子装置，其耦接至该基板的该上表面，该第一微电子装置是被动微电子装置；
第一引线接合线，其耦接至该基板的该上表面，并且从该基板的该上表面延伸离开；
第二引线接合线，其耦接至该第一微电子装置的上表面，并且从该第一微电子装置的该上表面延伸离开，该些第二引线接合线比该些第一引线接合线短；以及
第二微电子装置，其耦接至该些第一引线接合线以及该些第二引线接合线的上末端，该第二微电子装置是位在该第一微电子装置上方，并且至少部分地重叠该第一微电子装置。
2.根据权利要求1的垂直整合的微电子封装，其进一步包括模制层，其具有最上面的表面以及与该最上面的表面相对的最下面的表面，其被设置以用于围绕该些第一引线接合线以及该些第二引线接合线的长度的部分。
3.根据权利要求2的垂直整合的微电子封装，其中：
该第一微电子装置被设置在该模制层中，并且完全位在该模制层的该最上面的表面与该最下面的表面之间；以及
该第二微电子装置被耦接在该模制层的该最上面的表面上方。
4.根据权利要求权利要求3的的垂直整合的微电子封装，其中该第二微电子装置是一被动微电子装置。
5.根据权利要求3的垂直整合的微电子封装，其中该第二微电子装置是一主动微电子装置。
6.根据权利要求3的垂直整合的微电子封装，其中该第一微电子装置以及该第二微电子装置都处于一面朝下的朝向，以用于面对该基板的该上表面。
7.根据权利要求1的垂直整合的微电子封装，其进一步包括：
第三微电子装置，其耦接至该第二微电子装置而且位在该第二微电子装置上方，并且至少部分地重叠该第二微电子装置。
8.根据权利要求7的垂直整合的微电子封装，其进一步包括：
模制层，其具有最上面的表面以及与该最上面的表面相对的最下面的表面；
该第一微电子装置被设置在该模制层中并且完全地位在该模制层的该最上面的表面与该最下面的表面之间；
该第二微电子装置被设置在该模制层中并且至少部分地位在该模制层的该最上面的表面与该最下面的表面之间；以及
该第三微电子装置耦接在该模制层的该最上面的表面上方。
9.根据权利要求8的垂直整合的微电子封装，其中该第二微电子装置以及该第三微电子装置分别是被动微电子装置。
10.根据权利要求8的垂直整合的微电子封装，其中该第二微电子装置以及该第三微电子装置分别是另一被动微电子装置以及主动微电子装置。
11.根据权利要求8的垂直整合的微电子封装，其中：
该第一微电子装置以及该第三微电子装置都处于一面朝下的朝向，以用于面对该基板的该上表面；以及
该第二微电子装置包含重分布层。
12.一种系统级封装，其包括根据权利要求1的垂直整合的微电子封装，其中该系统级封装包括：
第三微电子装置，其耦接至该基板的该上表面；以及
第三引线接合线耦接至该第三微电子装置的上表面，并且从该第三微电子装置的该上表面延伸离开；以及
该第三微电子装置是主动微电子装置。
13.一种垂直整合的微电子封装，其包括：
基板，其具有上表面以及与该上表面相对的下表面；
第一微电子装置，其耦接至该基板的该上表面，该第一微电子装置是一被动微电子装置；
第一引线接合线，其耦接至该基板的该上表面，并且从该基板的该上表面延伸离开；
第二引线接合线，其耦接至该第一微电子装置的上表面，并且从该第一微电子装置的该上表面延伸离开；
该些第一引线接合线的第一部分是高于该些第二引线接合线；
第二微电子装置，其耦接至该些第一引线接合线的该第一部分的第一上末端，并且耦接至该些第二引线接合线的上末端，该第二微电子装置是位在该第一微电子装置上方并且至少部分地重叠该第一微电子装置；以及
该些第一引线接合线的第二部分具有第二上末端，该些第二上末端耦接至该第一微电子装置的上表面。
14.根据权利要求13的垂直整合的微电子封装，其进一步包括模制层，其具有最上面的表面以及与该最上面的表面相对的最下面的表面，其被设置以用于围绕该些第一引线接合线以及该些第二引线接合线两者的长度。
15.根据权利要求14的垂直整合的微电子封装，其进一步包括：
该第一微电子装置是被设置在该模制层中，并且完全地位在该模制层的该最上面的表面与该最下面的表面之间；以及
该第二微电子装置是耦接在该模制层的该最上面的表面上方。
16.根据权利要求13的垂直整合的微电子封装，其进一步包括第三微电子装置，其耦接至该第二微电子装置而且位在该第二微电子装置上方，并且至少部分地重叠该第二微电子装置。
17.根据权利要求16的垂直整合的微电子封装，其进一步包括：
模制层，其具有最上面的表面以及与该最上面的表面相对的最下面的表面；
该第一微电子装置被设置在该模制层中，并且完全地位在该模制层的该最上面的表面与该最下面的表面之间；
该第二微电子装置被设置在该模制层中，并且至少部分地位在该模制层的该最上面的表面与该最下面的表面之间；以及
该第三微电子装置耦接在该模制层的该最上面的表面上方。
18.根据权利要求17的垂直整合的微电子封装，其中该第二微电子装置以及该第三微电子装置分别是被动微电子装置。
19.根据权利要求17的垂直整合的微电子封装，其中该第二微电子装置以及该第三微电子装置分别是另一被动微电子装置以及主动微电子装置。
20.根据权利要求17的垂直整合的微电子封装，其中：
该第一微电子装置以及该第三微电子装置都处于一面朝下的朝向，以用于面对该基板的该上表面；以及
该第二微电子装置包含重分布层。
21.一种垂直整合的微电子封装，其包括：
第一电路平台，其具有上表面以及与该上表面相对的下表面；
微电子装置，其耦接至该第一电路平台的上表面；
第一引线接合线，其耦接至该第一电路平台的上表面，并且从该第一电路平台的该上表面延伸离开；
第二引线接合线，其耦接至该微电子装置的一上表面，并且从该微电子装置的该上表面延伸离开，该些第二引线接合线比该些第一引线接合线短；以及
第二电路平台，其耦接至该些第一引线接合线以及该些第二引线接合线的上末端，该第二电路平台是位在该第一微电子装置上方并且至少部分地重叠该第一微电子装置。
22.根据权利要求21的垂直整合的微电子封装，其中该微电子装置是处于一面朝上的朝向。
23.根据权利要求22的垂直整合的微电子封装，其进一步包括：至少处于一面朝下的朝向的被动或主动电路装置是耦接至该第二电路平台的上表面。
24.根据权利要求22的垂直整合的微电子封装，其进一步包括：至少处于一面朝上的朝向的被动或主动电路装置是耦接至该第二电路平台的上表面。
25.根据权利要求22的垂直整合的微电子封装，其进一步包括：
该微电子装置是第一微电子装置；
第二微电子装置是耦接至处于一面朝上的朝向的该第一微电子装置的上表面；
第三引线接合线是耦接至该第二微电子装置的上表面并且从该第二微电子装置的该上表面延伸离开，该些第三引线接合线比该些第二引线接合线短；以及
该第二电路平台是耦接至该第三引线接合的上末端。
26.根据权利要求22的垂直整合的微电子封装，其进一步包括模制或围堰填充层的介电材料，以用于覆盖该第一微电子装置以及该第二微电子装置，并且用于覆盖该些第一引线接合线、该些第二引线接合线、以及该些第三引线接合线的垂直的范围。
27.根据权利要求22的垂直整合的微电子封装，其进一步包括：
该微电子装置是一第一微电子装置；
第三电路平台，其在该些第一引线接合线与该第一微电子装置的上表面之间耦接至该第一微电子装置的上表面；
该些第一引线接合线被接合到该第三电路平台的上表面；以及
第二微电子装置，其处于一面朝下的朝向来耦接至该第三电路平台的上表面。
28.根据权利要求27的垂直整合的微电子封装，其进一步包括：
第三引线接合线，其接合至第一电路平台的上表面，并且耦接至该第三电路平台的上表面。
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US10490528B2 (en) 2019-11-26
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