TW201724428A - 內嵌的引線接合線 - Google Patents
內嵌的引線接合線 Download PDFInfo
- Publication number
- TW201724428A TW201724428A TW105132856A TW105132856A TW201724428A TW 201724428 A TW201724428 A TW 201724428A TW 105132856 A TW105132856 A TW 105132856A TW 105132856 A TW105132856 A TW 105132856A TW 201724428 A TW201724428 A TW 201724428A
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- microelectronic device
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- wire bonding
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Abstract
大致相關於一種垂直整合的微電子封裝的設備係被揭示。在其之一設備中,一基板係具有一上表面以及一與該上表面相對的下表面。一第一微電子裝置係耦接至該基板的該上表面。該第一微電子裝置是一被動微電子裝置。第一引線接合線係耦接至該基板的該上表面,並且從該基板的該上表面延伸離開。第二引線接合線係耦接至該第一微電子裝置的一上表面,並且從該第一微電子裝置的該上表面延伸離開。該些第二引線接合線係比該些第一引線接合線短。一第二微電子裝置係耦接至該些第一引線接合線以及該些第二引線接合線的上方的末端。該第二微電子裝置係位在該第一微電子裝置之上,並且至少部分地重疊該第一微電子裝置。
Description
以下的說明係大致有關於內嵌的引線接合線。更具體而言,以下的說明係有關於被互連接至一封裝的各種表面以用於多層的互連線的垂直的整合之內嵌的引線接合線。
此申請案茲主張2015年10月12日申請的美國臨時專利申請案序號US 62/240,443的優先權,該專利申請案的整體係為了所有的目的而藉此被納入在此作為參考。
微電子組件一般包含一或多個IC,例如是一或多個經封裝的晶粒("晶片")或是一或多個晶粒。此種IC中的一或多個可被安裝在一電路平台之上,例如一像是晶圓層級封裝("WLP")的晶圓、印刷板("PB")、一印刷線路板("PWB")、一印刷電路板("PCB")、一印刷線路組件("PWA")、一印刷電路組件("PCA")、一封裝基板、一中介體、或是一晶片載體。此外,一IC可被安裝在另一IC之上。一中介體可以是一被動式IC或是一主動式IC,其中後者係包含一或多個例如是電晶體的主動裝置,而前者並不包含任何主動裝置,但是可包含一或多個例如是電容器、電感器、及/或電阻器的被動裝置。再者,一中介體可被形成像是一PWB,亦即不具有任何的電路元
件,例如是不具有任何被動或主動裝置。此外,一中介體可包含至少一穿過基板的貫孔(via)。
一IC例如可包含導電的元件,例如是路徑、線路、軌跡、貫孔、接點、像是接觸墊及焊墊的墊、插塞、節點、或是端子,其可被使用於與一電路平台電互連。這些配置可以使得被用來提供IC的功能的電連接變得容易。一IC可以藉由接合來耦接至一電路平台,例如是接合此種電路平台的線路或端子至一IC的焊墊或是接腳或柱的露出的末端或類似者;或是一IC可以藉由焊接來耦接至一電路平台。此外,一重分佈層("RDL")可以是一IC的部分,以例如使得一覆晶的配置、晶粒堆疊、或是焊墊的更便利或可接達的位置變得容易。
某些被動或是主動微電子裝置可被用在一種系統級封裝("SiP")或是其它多晶粒/構件的封裝中。然而,用於某些應用的某些SiP可能會佔據過大的面積。再者,對於某些低輪廓的應用而言,某些SiP可被使用;然而,利用穿過半導體的貫孔來形成一用於堆疊的SiP對於某些應用而言可能是過於昂貴的。
於是,提供用於一SiP之垂直的整合將會是所期望且有用的。
一設備係大致有關於一種垂直整合的微電子封裝。在此種設備中,一基板係具有一上表面以及一與該上表面相對的下表面。一第一微電子裝置係耦接至該基板的該上表面。該第一微電子裝置可以是一主動或被動微電子裝置。第一引線接合線係耦接至該基板的該上表面,並且從該
基板的該上表面延伸離開。第二引線接合線係耦接至該第一微電子裝置的一上表面,並且從該第一微電子裝置的該上表面延伸離開。該些第二引線接合線係比該些第一引線接合線短。一第二微電子裝置係耦接至該些第一引線接合線以及該些第二引線接合線的上方的末端。該第二微電子裝置係位在該第一微電子裝置之上,並且至少部分地重疊該第一微電子裝置。
一設備係大致有關於另一種垂直整合的微電子封裝。在此種設備中,一基板係具有一上表面以及一與該上表面相對的下表面。一第一微電子裝置係耦接至該基板的該上表面。該第一微電子裝置是一主動或被動微電子裝置。第一引線接合線係耦接至該基板的該上表面,並且從該基板的該上表面延伸離開。第二引線接合線係耦接至該第一微電子裝置的一上表面,並且從該第一微電子裝置的該上表面延伸離開。該些第一引線接合線的一第一部分係高於該些第二引線接合線。一第二微電子裝置係耦接至該些第一引線接合線的該第一部分的第一上方的末端,並且耦接至該些第二引線接合線的上方的末端。該第二微電子裝置係位在該第一微電子裝置之上,並且至少部分地重疊該第一微電子裝置。該些第一引線接合線的一第二部分係使得其之第二上方的末端耦接至該第一微電子裝置的上表面。
一設備係大致有關於又一種垂直整合的微電子封裝。在此設備中,一第一電路平台係具有一上表面以及一與該上表面相對的下表面。一微電子裝置係耦接至該第一電路平台的上表面。第一引線接合線係耦接至該第一電路平台的上表面,並且從該第一電路平台的該上表面延伸離開。第二引線接合線係耦接至該微電子裝置的一上表面,並且從該微電子
裝置的該上表面延伸離開。該些第二引線接合線係比該些第一引線接合線短。一第二電路平台係耦接至該些第一引線接合線以及該些第二引線接合線的上方的末端。該第二電路平台係位在該第一微電子裝置之上,並且至少部分地重疊該第一微電子裝置。
10‧‧‧系統級封裝(SiP)
11‧‧‧主動微電子裝置
12‧‧‧被動微電子裝置
13‧‧‧IC晶粒
15‧‧‧引線接合
17‧‧‧覆晶的互連(微凸塊互連)
19‧‧‧封裝基板
19L‧‧‧下方的封裝基板
19U‧‧‧上方的封裝基板
20‧‧‧EMI屏蔽
21、22‧‧‧引線接合
23‧‧‧頂端導電板
24‧‧‧底部導電板
100‧‧‧系統級封裝(SiP)
100L‧‧‧下方的SiP
100U‧‧‧上方的SiP
130‧‧‧導電的表面
131‧‧‧引線接合線
131i‧‧‧內部的引線接合線
131L‧‧‧下方的引線接合線
131o‧‧‧外部的引線接合線
131s‧‧‧信號引線接合線
131U‧‧‧上方的引線接合線
132‧‧‧上表面
133‧‧‧屏蔽區域
136‧‧‧BVA配置
137‧‧‧孔洞
140‧‧‧接地面
140L‧‧‧下方的接地面
140U‧‧‧上方的接地面
141‧‧‧球體接合
142‧‧‧貫孔
143‧‧‧介電保護材料模製層
144‧‧‧間隙
145、145U‧‧‧微電子裝置
145L‧‧‧下方的微電子裝置
146‧‧‧上表面
148‧‧‧尖端
149‧‧‧下表面
150‧‧‧導電的覆蓋
153‧‧‧法拉第籠
160‧‧‧接地面
161‧‧‧互連
162‧‧‧貫孔
165‧‧‧微電子裝置
168‧‧‧上表面
169‧‧‧上方的基板
170‧‧‧焊墊
171‧‧‧墊至墊的間距
180‧‧‧互連
190‧‧‧堆疊式封裝的(PoP)裝置
191‧‧‧互連
192L‧‧‧下方的法拉第籠
192U‧‧‧上方的法拉第籠
200‧‧‧垂直整合的微電子封裝
201‧‧‧上表面
202‧‧‧上表面
203‧‧‧側壁
204‧‧‧互連共晶體
231‧‧‧引線接合線
252‧‧‧最下面的表面
261、262、263、264‧‧‧長度
271‧‧‧微電子裝置
274‧‧‧互連共晶體
331‧‧‧引線接合線
400‧‧‧電路平台
401‧‧‧電路平台
402‧‧‧黏著層
403‧‧‧下表面
404‧‧‧側壁表面
405‧‧‧上表面
406‧‧‧下表面
407‧‧‧上表面
408‧‧‧上表面
410‧‧‧微電子裝置
411‧‧‧微電子裝置
413‧‧‧互連
414‧‧‧電路平台(中介體)
415‧‧‧互連
416‧‧‧微電子裝置
418‧‧‧互連表面
431‧‧‧引線接合線
432‧‧‧引線接合線
441‧‧‧上表面
600‧‧‧基板
601‧‧‧引線接合墊
602‧‧‧覆晶的墊
603‧‧‧導電層
604‧‧‧焊料遮罩
605‧‧‧上表面
606‧‧‧間隙
607‧‧‧間隙
608‧‧‧焊料墊
609‧‧‧焊料墊
611‧‧‧上表面
613‧‧‧上表面
615‧‧‧上表面
616‧‧‧上表面
617‧‧‧下表面
648‧‧‧覆晶的接點
649‧‧‧覆晶的IC晶粒
650‧‧‧微電子構件
所附的圖式係展示根據範例的設備或方法的一或多個特點之範例實施例。然而,所附的圖式不應該被視為限制申請專利範圍的範疇,而只是用於解說及理解而已。
圖1A是描繪一範例的習知的系統級封裝("SiP")的側視方塊圖。
圖1B是描繪另一範例的習知的SiP的側視方塊圖。
圖2是描繪一習知的EMI屏蔽的一範例的部分之角落的俯視立體圖。
圖3A及3B是描繪個別的具有EMI屏蔽的範例的SiP的俯視方塊圖。
圖4是描繪一具有EMI屏蔽的範例的SiP的側視橫截面方塊圖。
圖5是描繪一範例的SiP的側視橫截面方塊圖,其係具有一導電的覆蓋並且具有在該導電的覆蓋之下的一EMI屏蔽區域中的信號引線接合線。
圖6是描繪一具有利用一上方的基板的EMI屏蔽的範例的SiP的側視橫截面方塊圖。
圖7是描繪在一法拉第籠(Faraday cage)的一上方的導電的表面的加入之前的一SiP的一範例的部分的俯視方塊圖。
圖8是描繪在一法拉第籠的一上方的導電的表面的加入之前的另一SiP的一範例的部分的俯視方塊圖。
圖9A是描繪一具有EMI屏蔽的堆疊式封裝("PoP")裝置的一範例的部分
的側視橫截面方塊圖。
圖9B是描繪另一具有EMI屏蔽的PoP裝置的一範例的部分的側視橫截面方塊圖。
圖10是描繪另一SiP的一範例的部分的側視橫截面方塊圖。
圖11A是描繪一不具有引線接合線EMI屏蔽的SiP的一範例的部分的側視橫截面方塊圖。
圖11B是描繪另一不具有引線接合線EMI屏蔽的SiP的一範例的部分的側視橫截面方塊圖。
圖12A至12D是描繪個別的不具有引線接合線EMI屏蔽的SiP的範例的部分之個別的側視橫截面方塊圖。
圖13A至13D是描繪個別的不具有引線接合線EMI屏蔽而具有垂直整合的微電子封裝的SiP的範例的部分之個別的側視橫截面方塊圖。
圖14A至14D是描繪用於一垂直整合的微電子封裝的範例的SiP的個別的側視橫截面方塊圖。
圖15A至15D是描繪引線接合墊以及覆晶的墊在一相同的基板上的漸進的形成的側視方塊圖。
在以下的說明中,許多特定的細節係被闡述,以提供在此所述的特定例子之更徹底的說明。然而,對於熟習此項技術者應該明顯的是,一或多個其它例子或是這些例子的變化可以在無所有以下給出的特定細節下加以實施。在其它實例中,眾所週知的特點並未詳細地敘述,以防模糊在此的例子的說明。為了便於說明,相同的元件符號係在不同的圖中被使
用以參照到相同的項目;然而,在替代的例子中,該些項目可以是不同的。
範例的設備及/或方法係在此加以描述。應瞭解的是,該字詞"範例的"係在此被使用以表示"當作為一個例子、實例、或是例證"。任何在此敘述為"範例"的例子或特點並不一定被解釋為相對其它例子或特點為較佳或是有利的。
在微電子裝置中的干擾可能是來自電磁干擾("EMI")及/或射頻干擾("RFI")。干擾屏蔽的以下的說明可被使用於這些類型的干擾的任一種或是兩者。然而,為了舉例且非限制性之清楚的目的起見,大致只有針對EMI的屏蔽係在以下用額外的細節來加以描述。
圖1A是描繪一不具有EMI屏蔽之範例的習知系統級封裝("SiP")10的側視方塊圖。在SiP 10中,可以有耦接至一封裝基板19的一或多個主動微電子裝置11、被動微電子裝置12、及/或IC晶粒13。在此例子中,可以是一被動式或主動式的晶粒的IC晶粒13可能會遭受到EMI。IC晶粒13可以利用引線接合15而被引線接合至封裝基板19,該些引線接合15是用於載有輸入/輸出信號及其它信號、一電源電壓以及接地參考電壓。
封裝基板19可以是由稱為積層或積層基板的薄層所形成的。積層可以是有機或無機的。用於"剛性"封裝基板的材料例子係包含一例如是FR4或FR5的環氧樹脂基的積層、一例如是雙馬來醯亞胺-三嗪("BT")樹脂基的積層、一陶瓷基板(例如,一低溫共燒陶瓷(LTCC))、一玻璃基板、或是其它形式的剛性封裝基板。再者,一封裝基板19在此可以是一PCB或是其它電路板。為了清楚的目的起見,其它有關習知的SiP 10的已知的細節並未被敘述。
圖1B是描繪另一不具有EMI屏蔽之範例的習知的SiP 10的側視方塊圖。除了例如是微凸塊的覆晶的("FC")互連17被使用,而不是引線接合15之外,圖1B的SiP 10係與圖1A的SiP 10相同的。即使微凸塊互連17係說明性地被描繪,但是其它類型的晶粒表面安裝的互連亦可被使用。再者,儘管未說明性地描繪在圖1B中,但是微凸塊互連17可以在引線接合15之外另外被使用。
圖2是描繪一習知的EMI屏蔽20的一範例的部分的角落的俯視立體圖。在習知的EMI屏蔽20中,一頂端導電板23可被設置在一底部導電板24之上,其中此種底部導電板24係具有一大於此種頂端導電板23的表面積。
導電板23及24分別可以耦接至一具有引線接合21及22的列之封裝基板19。因此,頂端板23的兩個側邊可以與對應的列的引線接合21來加以引線接合,並且底部板24的兩個側邊同樣地可以與對應的列的引線接合22來加以引線接合。非導電的間隙壁(未顯示)可被用來隔離引線接合21與底部導電板24。一待被EMI屏蔽的微電子裝置(未顯示)可被夾設在頂端及底部導電板23及24之間。此類型的具有引線接合的EMI屏蔽對於許多應用而言可能是過於龐大的。再者,在相關提供側邊EMI屏蔽的引線接合之相對的側邊上可能會有間隙。
干擾屏蔽
圖3A及3B是描繪個別的具有EMI屏蔽之範例的SiP 100的俯視方塊圖。SiP 100的每一個都可包含一封裝基板19,其係具有耦接至其之一上表面132的一或多個主動微電子裝置11、一或多個被動微電子裝
置12、以及引線接合線131,其中此種引線接合線131的上方的末端可以耦接至一封裝基板19的一上表面132。上表面132可以是一導電的表面。引線接合線131可包含等於或小於約0.0508毫米(2密耳)的導線直徑。
引線接合線131的一部分可被設置以界定一屏蔽區域133。以此種方式,引線接合線131的一BVA配置136的列與行可被用來包圍或者是圍繞一屏蔽區域133。此種引線接合線131的至少一子集合之圍繞一屏蔽區域133的上方的末端可被用來支撐導電的表面130,因而此種導電的表面130可以是在此種屏蔽區域133之上,以用於其之覆蓋。
導電的表面130可以是一導電的剛性或撓性的表面。在一實施方式中,導電的表面130可以是撓性的,例如是在一撓性的片的一表面上之一撓性的導電的塗層。在另一實施方式中,一剛性板可以提供一導電的表面。一剛性板可以是由一種導電材料所做成的。然而,一導電的塗層可被噴塗或是擦塗在一剛性板或是撓性的片上。在圖3B的例子中,如同在以下以額外的細節敘述的,導電的表面130可以具有孔洞137,以用於容許引線接合線131中的界定一屏蔽區域133的至少某些個的上方的部分能夠延伸穿過導電的表面130。
圖4是描繪一具有EMI屏蔽之範例的SiP 100的側視橫截面方塊圖。SiP 100可包含一封裝基板19,其係具有耦接至其之一上表面132的一或多個主動微電子裝置11、一或多個被動微電子裝置12、以及引線接合線131,其中此種引線接合線131的上方的末端可以耦接至一導電的表面130。即使一SiP 100係被描述,但是其它類型的具有免於EMI的保護的微電子封裝亦可被使用。
封裝基板19係具有一上表面132以及一與該上表面相對的下表面149。封裝基板19可以具有位在表面132及149之間的一接地面140以及貫孔142,其中貫孔142可以互連接至此種接地面140以用於導電。
引線接合線131可以利用貫孔142來耦接至接地面140。某些引線接合線131可以利用用於導電的球體接合141來機械式地耦接至上表面132;然而,在其它實施方式中,其它類型的接合亦可被使用。再者,並非所有的引線接合線131都需要耦接至接地面140。某些引線接合線131可被使用於在SiP 100之內載有供應電壓或信號。某些引線接合線131可被使用於耦接至在SiP 100之內的其它裝置。
一主動或被動的微電子裝置145可以耦接至封裝基板19的上表面132。微電子裝置145可包含一主動的積體電路晶粒及/或一被動構件。一被動構件例如可以是一電容器、一電感器、或是一電阻器、或是其之任意組合。
微電子裝置145可以利用如先前所述的球體或凸塊互連及/或引線接合線來耦接至封裝基板19。再者,微電子裝置145可以利用一黏著劑或是一底膠填充層(未顯示)來耦接至上表面132。
微電子裝置145可被設置在一介電保護材料中,該介電保護材料可被設置為圍堰(dam)填充或是一模製層("模製層")143。此種模製層143可以是一密封劑或是一模製材料,以用於至少覆蓋微電子裝置145的一上表面以及側壁。引線接合線131可被設置在微電子裝置145的側壁的周圍。
導電的表面130可以是位在介電保護材料模製層143的一頂端或上表面146之上、或是耦接至其。然而,在另一實施方式中,如同在
以下以額外的細節敘述的,介電保護材料模製層143的一頂表面可以是位在一高於引線接合線131的尖端148的高度處。導電的表面130可被設置在和法拉第籠153相關的引線接合線131之上。此種引線接合線131的上方的末端或尖端148可以機械式地耦接至導電的表面130。此耦接可以是利用一熱壓接合或是其它形式的機械式耦接。
法拉第籠153可以是接地面140的一部分例如利用貫孔142來互連接至支撐一導電的表面130的引線接合線131的一組合。在另一實施方式中,在導電的表面130與引線接合線131的某些個的尖端148之間可以有一間隙144。以此種方式,導電的表面130的一底部,例如是一導電板的一底部例如可以附接至、或是安置在介電保護材料模製層143的一頂表面之上,因而介電保護材料模製層143的高度可以是大於引線接合線131的高度。
因此,一導電的表面130可被設置在引線接合線131的一部分之上,其中其之上方的末端或尖端148係和導電的表面130間隔開。然而,一種具有一間隙144的配置可能會提供一較不有效的法拉第籠153,因而為了例如且非限制性的清楚的目的起見,應假設是沒有間隙的。
耦接至接地面140而從封裝基板19的上表面132向上突出或延伸離開的引線接合線131可加以排列。以此種方式,即使引線接合線131的一種Bond Via ArrayTM或是BVA®配置136的單一列與行在一實施方式中可以存在,但是一種BVA配置136的多個列及/或多個行的引線接合線131可以沿著一屏蔽區域133的一或多個側邊而存在。
為了重述要點,引線接合線131中的某些例如是在界定一屏
蔽區域133的BVA配置136中的引線接合線131可被設置,以提供此種避免EMI或相關EMI的屏蔽區域133給微電子裝置145。引線接合線131的其它位在屏蔽區域133之外的部分可能並未被使用於EMI屏蔽。再者,一或多個其它主動或被動微電子裝置11及/或12可以耦接至基板19,並且是位在屏蔽區域133之外,因而不是此種屏蔽區域的部分、或是被設置用於此種屏蔽區域的位置。
圖5是描繪一範例的SiP 100的側視橫截面方塊圖,其係具有一導電的覆蓋150,並且在導電的覆蓋150之下的一EMI屏蔽區域中具有信號引線接合線131s。圖5的SiP 100是與圖4的SiP 100相同的,但是具有以下的差異。
在此例子中,引線接合線131的一部分係具有一高度大於引線接合線131的另一部分的一高度。兩組的引線接合線131都可以接近微電子裝置145而且在微電子裝置145的周圍來加以設置。然而,引線接合線131的較高的部分可以是用於提供一相關EMI的屏蔽區域133給微電子裝置145。然而,引線接合線131的其它較矮的部分("引線接合線131s")可以是耦接微電子裝置145至封裝基板19的導體的信號線。此種較矮的引線接合線131s中的某些個可以是在一法拉第籠153之內。較高的引線接合線131的高度可能會受限於低輪廓的封裝應用。
導電的覆蓋150可以耦接至封裝基板19的上表面132。導電的覆蓋150可以覆蓋SiP 100的耦接至上表面132的構件,其係包含微電子裝置145、微電子裝置11、12以及引線接合線131。並非BVA配置136的部分之引線接合線131可以將導電的覆蓋150以及接地面140互連。此耦接
可被使用以降低內部的雜訊。然而,法拉第籠153可以是位在覆蓋150之下,以用於內部的EMI屏蔽。選配的是,導電的表面130可被省略,而有利於利用導電的覆蓋150作為法拉第籠153的一上方的導電的表面,而不論在尖端148與導電的覆蓋150的一底面之間具有或是不具有一間隙144。
某些在BVA配置136之內的引線接合線131可以是信號線,亦即引線接合線131s。引線接合線131s可以不耦接至接地面140,而是可以耦接至封裝基板19的線路(未顯示)。引線接合線131s的尖端可以在介電保護材料模製層143的使用之前,先被接合或是焊接至微電子裝置145。在另一實施方式中,相關微電子裝置145的介電保護材料模製層143可被省略。
引線接合線131s可被接合到被動微電子裝置12或是主動微電子裝置11中的一或多個的上表面。這些引線接合線131s可以是用於在SiP 100之內的互連。
圖6是描繪一範例的SiP 100的側視橫截面方塊圖,其係具有利用一上方的基板169的EMI屏蔽。圖6的SiP 100係與圖5的SiP 100相同的,但是並不具有導電的覆蓋150,而且具有以下的差異。
上方的基板169可包含貫孔162以及一接地面160。引線接合線131的尖端或是上方的末端148可以沿著上方的基板169的一底表面,利用互連161(例如是利用微球體或微凸塊)來互連接至貫孔162,例如以用於耦接至接地面160。互連161可被設置在介電保護材料模製層143的一上表面168上。接地面160可以提供法拉第籠153的一上方的導電的表面130。
另一不論是主動或被動的微電子裝置165可以耦接至上方
的基板169的一頂表面。微電子裝置165可以利用引線接合線15來耦接至基板169的貫孔或線路;然而,微球體或是微凸塊可以在另一實施方式中被使用。微電子裝置165可以耦接在法拉第籠153之外。
圖7是描繪在一法拉第籠153的一上方的導電的表面130的加入之前的一SiP 100的一範例的部分的俯視方塊圖。焊墊170可以接近微電子裝置145而且在微電子裝置145的周圍來加以設置,以用於將引線接合線131分別耦接至其,以用於提供法拉第籠153的屏蔽區域133。屏蔽區域133可被界定在一BVA配置136之內。
焊墊170可以在介電保護材料模製層143的側邊周圍和彼此間隔開。在介電保護材料模製層143中的微電子裝置145可以是位在屏蔽區域133的一中央部分中。焊墊170的一墊至墊的間距171可以是等於或小於約250微米。焊墊170的間距171可以針對於和例如是EMI及/或RFI的干擾相關的頻率來加以選擇,以將微電子裝置145與EMI及/或RFI屏蔽開。再者,微電子裝置145可能是一干擾的輻射體,並且因而此種屏蔽可以是用以保護SiP 100的其它構件免於由微電子裝置145所產生的干擾。
即使單一列與行的焊墊170係說明性地被描繪,但是在另一實施方式中可以有超過一或兩個列及/或行。再者,焊墊170的列及/或行可以相關彼此來交錯的,以提供較稠密的屏蔽。引線接合線131可以有效地被用來提供一低通濾波器的法拉第籠,以用於降低相關微電子裝置145的操作的EMI。以此種方式,儘管並非必要的,但焊墊170的設置以及因此的引線接合線131的設置可以是一致的。引線接合線131可以針對於被調適以屏蔽往微電子裝置145、或是來自微電子裝置145的一特定範圍的頻率之密
度來加以置放及/或調整。
圖8是描繪在一法拉第籠153的一上方的導電的表面130的加入之前的另一SiP 100的一範例的部分的俯視方塊圖。在此例子中,引線接合線131的一BVA配置136的兩個列以及兩個行係被用來界定一屏蔽區域133。在此例子中,在列與行之間的間隔是交錯的,以提供一較稠密的引線接合線131的樣式。
在此例子中,BVA配置136的引線接合線131中的某些個係用於載有信號,亦即引線接合線131s。以此種方式,互連180可被形成以用於從微電子裝置145延伸到介電保護材料模製層143之外,以用於與引線接合線131s的互連,該些引線接合線131s可包含一或多個信號線。
圖9A是描繪一具有EMI屏蔽的堆疊式封裝的("PoP")裝置190的一範例的部分的側視橫截面方塊圖。PoP裝置190可包含一上方的SiP 100U,其係堆疊在一下方的SiP 100L的頂端上。PoP裝置190例如可包含一或多個在一屏蔽區域之外的其它微電子裝置以及其它的細節,例如是先前參考圖3A至8所述者。於是,為了清楚且非限制性的目的起見,先前針對於SiP 100所敘述的細節並未在以下加以敘述。
一下方的SiP 100L的一下方的封裝基板19L可包含一下方的接地面140L,其係使得下方的引線接合線131L從下方的封裝基板19L的一上表面向上地延伸。此種下方的引線接合線131L及接地面140L可以例如是利用如先前所述的貫孔及球體接合來互連接至彼此,以用於形成一法拉第籠153的一下方的部分。下方的引線接合線131L的尖端148可以沿著上方的封裝基板19U的一下方側,利用互連191而被接合或耦接至針對其
之墊及貫孔。
選配的是,上方的封裝基板19U可包含一上方的接地面140U,以用於形成一法拉第籠153來作為兩個法拉第籠的一堆疊,亦即一上方的法拉第籠192U以及一下方的法拉第籠192L。法拉第籠192U及192L的每一個都可包含分別耦接至封裝基板19U及19L的上表面之個別的封裝的微電子裝置145U及145L。
上方的基板19U的上方的接地面140U可以是位在一下方的微電子裝置145L之上,因而下方的引線接合線131L的尖端或上方的末端148可以沿著上方的封裝基板19U的一底表面,利用互連191來互連接至墊或接點以用於電耦接至上方的接地面140U。上方的引線接合線131U以及選配的接地面140U可以例如利用如先前所述的貫孔以及球體接合來互連接至彼此,以用於形成一法拉第籠153的一上方部分。上方的引線接合線131U的尖端148可被接合或是耦接至導電的表面130,以用於完成此種上方的法拉第籠192U。
在另一實施方式中,上方的基板封裝19U的貫孔可以在不連接至一上方的接地面140U之下,互連下方的引線接合線131L以及上方的引線接合線131U,以形成一用於兩個微電子裝置145U、145L的"兩個樓層的"或是兩層的法拉第籠153。即使只有兩層係說明性地被描繪,但是超過兩層亦可被使用在其它的實施方式中。
圖9B是描繪另一具有EMI屏蔽的PoP裝置190的一範例的部分的側視橫截面方塊圖。PoP裝置190例如可包含一或多個在一屏蔽區域之外的其它的微電子裝置以及其它細節,例如是先前參考圖3A至9A所述
者。於是,為了清楚且非限制性的目的起見,先前針對於SiP 100所敘述的細節並未在以下加以敘述。
除了以下的差異之外,圖9B的PoP裝置190可以是與圖9A的PoP裝置190相同的。圖9B的PoP裝置190可包含信號引線接合線131s。信號引線接合線131s可以是位在法拉第籠153之內,其係包含在法拉第籠192U之內。
在此配置中的信號引線接合線131s可以從一下方的微電子裝置145L的一上表面向上地延伸。從下方的微電子裝置145L的一上表面延伸之引線接合線131s的尖端或上方的末端148可以例如是利用互連191而互連接至上方的封裝基板19U的一下面側。貫孔及/或線路(未顯示)可以利用信號引線接合線131s來電耦接上方及下方的微電子裝置145。再者,下方的基板封裝19L可包含用於與下方的微電子裝置145互連的貫孔及/或線路(未顯示)。
圖10是描繪另一具有EMI屏蔽的SiP 100的一範例的部分的側視橫截面方塊圖。SiP 100例如可包含一或多個在一屏蔽區域之外的其它的微電子裝置以及其它細節,例如是先前參考圖3A至9B所述者。於是,為了清楚且非限制性的目的起見,先前針對於SiP 100所敘述的細節並未在以下加以敘述。
在此例子中,引線接合線131以及一例如是IC晶粒的微電子裝置145係被一介電保護材料模製層143所保護。微電子裝置145可以在沉積或是注入介電保護材料模製層143之前,利用微凸塊互連17來互連至封裝基板19的一上表面。同樣地,在沉積或是注入介電保護材料模製層143
之前,引線接合線131可以被球體接合到封裝基板19的一上表面。
選配的是,信號引線接合線131s可以在沉積或是注入介電保護材料模製層143之前,被球體接合到微電子裝置145的一上表面201。信號引線接合線131s因此可以是在一法拉第籠153的一屏蔽區域133之內。
引線接合線131的尖端或上方的末端148以及選配的信號引線接合線131s可以延伸在介電保護材料模製層143的一上表面202之上。焊料球體或是其它的互連共晶體204可加以沉積到尖端148之上,以用於例如是在此的別處所描述的後續的互連。
不具有干擾屏蔽的垂直的整合
圖11A是描繪一不具有引線接合線EMI屏蔽的SiP 100的一範例的部分的側視橫截面方塊圖。圖11B是描繪另一不具有引線接合線EMI屏蔽的SiP 100的一範例的部分的側視橫截面方塊圖。同時參考圖11A及11B,分別說明性地描繪在那些圖中的SiP 100係進一步加以敘述。SiP 100的每一個都可以包含一或多個其它微電子裝置以及其它細節,例如是先前所敘述者。於是,為了清楚且非限制性的目的起見,先前針對於SiP 100所敘述的細節並未在以下加以敘述。
SiP 100的每一個係包含一垂直整合的微電子封裝200。微電子封裝200的每一個係包含一基板19,其係具有一上表面132以及一與該上表面相對的下表面149。封裝基板19可以具有位在表面132及149之間的一接地面140、以及互連接至此種接地面以用於導電的貫孔142。
一微電子裝置145可以耦接至基板19的上表面132,其中微電子裝置是一被動微電子裝置。以此種方式,在一SiP 100中,可以有被動
或是主動微電子裝置中的任一種或是兩者的一或多個耦接至上表面132。此表示有此種微電子裝置的上表面在過去對於垂直的整合而言可能已經變成是未使用的,現在則例如藉由如同在此所述的使得接合的引線接合線附接至此種微電子裝置的此種上表面。
以此種方式,引線接合線131可以耦接至基板19的上表面132並且從該上表面132延伸離開,並且引線接合線231可以耦接至微電子裝置145的一上表面201並且從該上表面201延伸離開。引線接合線131及231分別可以利用用於導電的球體接合141來機械式地耦接至上表面132及201。然而,在其它實施方式中,其它類型的接合亦可被使用。引線接合線231係在長度上比引線接合線131短的。
參考圖11A,引線接合線131可以具有一整體完成後的長度261,並且引線接合線231可以具有一整體完成後的長度262。然而,引線接合線131及231的完成後的高度可以是大致相同的。引線接合線131以及231的尖端或是上方的末端148可以延伸在模製層143的一上表面202之上。
上方的末端148可以為了大致是共面的而為毗連的。焊料球體或是其它的互連共晶體204可以在上表面202上,而分別加以沉積在上方的末端148之上,以用於與在一主動或被動微電子裝置165的一正面的底面上的墊(未顯示)形成互連。
一被動微電子裝置145可以耦接至封裝基板19的上表面132。微電子裝置145可包含導電線路,並且可以只包含被動構件。一被動構件可包含一電容器、一電感器、或是一電阻器、或是其之任意組合中的一或多個。
如同先前所述的,微電子裝置145可以利用球體或凸塊互連及/或引線接合線來耦接至封裝基板19。再者,微電子裝置145可以利用一黏著劑或是一底膠填充層(未顯示)來耦接至上表面132。
在此實施方式中,微電子裝置145以及微電子裝置165係可以具有面向下的朝向,亦即朝向基板19的上表面132之面朝下的朝向。然而,在另一實施方式中,微電子裝置165可以具有從基板19的一上表面132面向上的一正面的側面。
一微電子裝置165可以被耦接在模製層143的最上面的表面202之上。在一實施方式中,一微電子裝置165可以利用共晶體204或是其它的機械式互連來耦接至引線接合線131及231之上方的末端148。微電子裝置165可以是位在微電子裝置145之上,並且至少部分地重疊此種微電子裝置145。
模製層143可以具有一最上面的表面202以及一與該最上面的表面相對的最下面的表面252。模製層143可被設置以用於圍繞引線接合線131及231兩者的長度261及262的部分。上方的末端148例如可以像是藉由用於一注入模製的一模製輔助膜的使用而不被模製層143所覆蓋。在另一實施方式中,模製層143可以暫時完全覆蓋長度261及262,接著是一回蝕以露出上方的末端148。
在一垂直整合的微電子封裝200的一實施方式中,微電子裝置145可被設置在模製層143中。以此種方式,在一實施方式中,微電子裝置145可以完全位在模製層143的最上面的表面202與最下面的表面252之間。引線接合線131可被設置在微電子裝置145的側壁203的周圍,儘管在
此範例實施方式中並非是用於干擾的屏蔽。
引線接合線131可以耦接至接地面140,以用於從封裝基板19的上表面132向上地突出或延伸,並且可加以排列。以此種方式,儘管引線接合線131及/或231的一BVA®配置的單一列與行在一實施方式中可以存在,但是多個列及/或多個行的此種引線接合線亦可以是在一BVA®配置中。
在垂直整合的微電子封裝200的一實施方式中,本身是一被動微電子裝置的微電子裝置165可被使用。然而,在垂直整合的微電子封裝200的另一實施方式中,本身是一主動微電子裝置的微電子裝置165可被使用。
參考圖11B,內部的引線接合線131i可以具有一整體完成後的長度263,並且引線接合線231可以具有一整體完成後的長度264。如同先前參考圖11A所述的,外部的引線接合線131o可以具有一整體完成後的高度261。引線接合線131i及231在形成之後的完成後的高度可以是大致相同的。引線接合線131i及231的上方的末端148可以是大致與彼此為高低相同的。
引線接合線131i及231的上方的末端148可以是為了大致是共面的而為毗連的。焊料球體或是其它的互連共晶體274分別可以將一主動或被動微電子裝置271的一下表面耦接至引線接合線131i及231的上方的末端148,以用於與在一主動或被動微電子裝置271的一正面的底面上的墊(未顯示)形成互連。在微電子裝置271處於適當的地方下,一模製材料可被注入以形成模製材料層143,並且因此微電子裝置271的一下表面可以接
觸到模製層143的模製材料。為了模製,一模製輔助膜可被用來容許外部的引線接合線131o的尖端148、以及微電子裝置271的墊或是其它互連(未顯示),能夠延伸在模製層143的上表面202之上。在另一實施方式中,模製層143可以暫時完全地覆蓋長度261,接著是一回蝕以露出其之上方的末端148。
微電子裝置271可以耦接至微電子裝置145而且位在微電子裝置145之上,並且可以至少部分地重疊微電子裝置145。以此種方式,微電子裝置271可以橫向地延伸在微電子裝置145的一周邊之外,以用於內部的引線接合線131i在基板19的上表面132與微電子裝置271的一面對此種上表面132的下表面之間的互連。引線接合線131i以及引線接合線131o可被設置在微電子裝置145的側壁203的周圍,儘管在此範例實施方式中並非用於干擾的屏蔽。
同樣地,一被動微電子裝置145可以耦接至封裝基板19的上表面132。微電子裝置145可包含導電線路,並且可以只包含被動構件、只包含被動構件、或是其之一組合。一被動構件可包含一電容器、一電感器、或是一電阻器、或是其之任意組合。如先前所述,微電子裝置145可以利用球體或是凸塊互連及/或引線接合線來耦接至封裝基板19。再者,微電子裝置145可以利用一黏著劑或是一底膠填充層(未顯示)來耦接至上表面132。
模製層143可以具有一最上面的表面202以及一與該最上面的表面相對的最下面的表面252。模製層143可被設置以用於圍繞引線接合線131o的長度261的部分,並且用於圍繞引線接合線131i及231兩者的長
度263及264。
在垂直整合的微電子封裝200的一實施方式中,微電子裝置145可被設置在模製層143中,並且完全位在模製層143的最上面的表面202與最下面的表面252之間。微電子裝置271可被設置在模製層143中,並且至少部分地位在模製層143的最上面的表面202與最下面的表面252之間。微電子裝置165可以被耦接在模製層143的最上面的表面202之上。
對於一被動微電子裝置271而言,微電子裝置271可包含導電線路,並且可以只包含被動構件。微電子裝置271可包含一RDL。一被動構件可以是一電容器、一電感器、或是一電阻器、或是其之任意組合。在此實施方式中,微電子裝置145及271、以及微電子裝置165係具有面向下的朝向,亦即朝向基板19的上表面132之面朝下的朝向。然而,在另一實施方式中,微電子裝置165及/或微電子裝置271可以具有從基板19的一上表面132面向上的一正面的側面。
在垂直整合的微電子封裝200的一實施方式中,本身是一被動微電子裝置的微電子裝置165可被使用。然而,在垂直整合的微電子封裝200的另一實施方式中,本身是一主動微電子裝置的微電子裝置165可被使用。一微電子裝置165可以耦接在模製層143的最上面的表面202之上,以用於與微電子裝置271的互連。在一實施方式中,一微電子裝置165可以利用用於導電的共晶體204或是其它的機械式互連來耦接至微電子裝置271的一上表面。
微電子裝置165可以是位在微電子裝置271之上,並且至少部分地重疊此種微電子裝置271。以此種方式,一微電子裝置165可以耦接
在模製層143的最上面的表面202之上,以用於與外部的引線接合線131o的上方的末端148的互連、以及與微電子裝置271的一上表面的互連。
引線接合線131i及131o可以耦接至接地面140,以用於從封裝基板19的上表面132向上地突出或延伸,並且可加以排列。以此種方式,即使引線接合線131i、131o及/或231的一BVA®配置的單一列與行在一實施方式中可以存在,但是多個列及/或多個行的此種引線接合線可以是在一BVA®配置中。
圖12A是描繪另一不具有引線接合線EMI屏蔽之SiP 100的一範例的部分的側視橫截面方塊圖。除了以下的細節之外,圖12A的SiP 100可以是與在圖11A中的相同。在一垂直整合的微電子封裝200的此實施方式中,微電子裝置165可以懸臂伸出,以用於橫向地延伸超過一引線接合線131並且在其之上。以此種方式,引線接合線131的上方的末端148可以利用共晶體204來互連至一微電子裝置165的一下表面。
圖12B是描繪另一不具有引線接合線EMI屏蔽之SiP 100的一範例的部分的側視橫截面方塊圖。除了以下的細節之外,圖12B的SiP 100可以是與在圖11B中的相同。在一垂直整合的微電子封裝200的此實施方式中,微電子裝置165並未懸臂伸出以用於橫向地延伸超過一引線接合線131o並且在其之上。以此種方式,微電子裝置165以及微電子裝置271對於其分別的下表面以及上表面可以具有大致相等的表面積。
圖12C是描繪另一具有或是不具有整合的引線接合線EMI屏蔽之SiP 100的一範例的部分的側視橫截面方塊圖。除了以下的細節之外,圖12C的SiP 100可以是與在圖12A中的相同。在一垂直整合的微電子
封裝200的此實施方式中,微電子裝置165係懸臂伸出以用於在微電子裝置145在該圖中的一右側以及一左側上橫向地延伸超過引線接合線131並且在其之上。以此種方式,引線接合線131的上方的末端148可以利用共晶體204來互連至一微電子裝置165的一下表面。於是,應該體認到的是,被設置在一微電子裝置的周圍並且互連接至一微電子裝置165的引線接合線131可被使用於扇出。
圖12D是描繪另一具有或是不具有整合的引線接合線EMI屏蔽之SiP 100的一範例的部分的側視橫截面方塊圖。除了以下的細節之外,圖12D的SiP 100可以是與在圖12B中的相同。在一垂直整合的微電子封裝200的此實施方式中,微電子裝置165係並未懸臂伸出以用於橫向地延伸超過一引線接合線131o並且在其之上。以此種方式,微電子裝置165以及微電子裝置271對於其分別的下表面以及上表面可以具有大致相等的表面積。以此種方式,引線接合線131i的上方的末端148可以利用共晶體274來互連至一微電子裝置271的一下表面。於是,應該體認到的是,被設置在一微電子裝置145的周圍並且互連接至一微電子裝置271的引線接合線131i可被使用於扇出。
圖13A是描繪一具有一垂直整合的微電子封裝200之範例的SiP 100的側視橫截面方塊圖。在此實施方式中,一垂直整合的微電子封裝200可以是一耦接至基板19的獨立的封裝,即如同在圖12D中的一SiP 100。由於SiP 100的構件先前已經例如是參考圖4來加以敘述,因而此種說明並未予以重複。
在此實施方式中,例如是焊料球的共晶體274係被形成在模
製層143的一上表面202上、在一重分佈層上、或是在該些引線接合線131i及231的尖端上。共晶體274係將引線接合線131i及231的上方的末端148互連至微電子裝置271的一下表面。在另一實施方式中,共晶體274可被封入在模製層143中。在此例子中,微電子裝置271的一下表面並未接觸模製層143的一上表面202。
再者,在此範例實施方式中,信號引線接合線131s可被封入在模製層143的模製材料中,但不包括其之接觸末端。信號引線接合線131s可以是短於內部的引線接合線131i,並且可以是如先前所述的用於與一微電子裝置145的互連。以此種方式,微電子裝置271可以耦接至例如是引線接合線131i之被耦接到上表面132的引線接合線131的一較高的部分的上方的末端148。微電子裝置271可以進一步耦接至引線接合線231的上方的末端148。例如是先前所敘述的,引線接合線131的另一耦接至上表面132的部分(例如是信號引線接合線131s)可以使得其之上方的末端148耦接至微電子裝置145的一上表面。
選配的是,引線接合線331可以耦接至主動微電子裝置11及/或被動微電子裝置12的一或多個上表面,該微電子裝置11及/或12係直接被耦接到一基板19的上表面132。
有關圖13A的SiP 100的其它細節先前已經加以敘述,並且因此為了清楚且非限制性的目的起見而未予以重複。
圖13B是描繪一不具有EMI屏蔽而具有一垂直整合的微電子封裝200之範例的SiP 100的側視橫截面方塊圖。在此實施方式中,如同在圖13A中的一SiP 100,一垂直整合的微電子封裝200可以是一耦接至基
板19之獨立的封裝。由於SiP 100的構件先前已經例如參考圖4來加以敘述,因而此種說明並不予以重複。
除了以下的差異之外,圖13B的SiP 100係類似於圖13A的SiP 100。在圖13B的SiP 100中,垂直整合的微電子封裝200係省略微電子裝置271。因此,例如是先前敘述的,一微電子裝置165可以利用共晶體204來直接耦接至模製層143的一上表面202。
圖13C是描繪一具有一垂直整合的微電子封裝200的範例的SiP 100的側視橫截面方塊圖。在此實施方式中,如同在圖13A中的一SiP 100,一垂直整合的微電子封裝200可以是一耦接至基板19的獨立的封裝。由於SiP 100的構件先前已經例如參考圖4來加以敘述,因而此種說明並不予以重複。
除了以下的差異之外,圖13C的SiP 100係類似於圖13A的SiP 100。在圖13C的SiP 100中,垂直整合的微電子封裝200係具有某些如先前所述的被封入在模製層143的模製材料中的引線接合線131i,並且具有某些並未被封入在模製層143的模製材料中的引線接合線131i。
圖13D是描繪一具有一垂直整合的微電子封裝200之範例的SiP 100的側視橫截面方塊圖。在此實施方式中,如同在圖13B中的一SiP 100,一垂直整合的微電子封裝200可以是一耦接至基板19的獨立的封裝。由於SiP 100的構件先前已經例如參考圖4來加以敘述,因而此種說明並不予以重複。
除了以下的差異之外,圖13D的SiP 100係類似於圖13B的SiP 100。在圖13D的SiP 100中,垂直整合的微電子封裝200並不具有被封
入在模製層143的模製材料中的引線接合線131。
圖14A是描繪一具有一垂直整合的微電子封裝200之範例的SiP 100的側視橫截面方塊圖。由於圖14A的SiP 100係類似於先前在此所述的SiP 100,因此為了清楚的目的起見,大致只有差異才在以下用額外的細節來加以描述。
在此範例實施方式中,一電路平台400例如可以是一像是封裝基板19的封裝基板、一晶粒基板或中介體、一導線架、或是例如一RDL的一繞線層。在此例子中,一被動微電子裝置271係大致被表示為一電路平台401,其可以是一繞線層、一晶粒基板或中介體、或是一封裝基板。垂直的引線接合線131i可以互連電路平台400的一上表面405至電路平台401的一下表面403。在此例子中,微電子裝置145是一個只有引線接合的裝置,其係利用一環氧樹脂或是其它的黏著層402,以使得其之一下表面406耦接至電路平台400的一上表面405,該環氧樹脂或其它的黏著層402係在此種面對的表面之間。
微電子裝置145可以是處於一面朝上的朝向。引線接合線131s可以互連電路平台400的一上表面405至微電子裝置145的一上表面407。較短的垂直的引線接合線231可以互連微電子裝置145的一上表面407以及電路平台401的一下表面403。
介電保護材料模製層143可以是一模製層或是一圍堰填入的層,並且儘管展示只覆蓋該SiP的一部分,但可以替代的是覆蓋在該SiP 100中的構件的任一個或是全部。微電子裝置145可以利用黏著層402來耦接至電路平台400,接著是將引線接合線131s及231引線接合。引線接合線
231及131i可以在加入介電保護材料模製層143的一模製或圍堰填入的層之前,先耦接至電路平台401的一下表面403。介電保護材料可以提供一比只是使得引線接合線131i及231支撐電路平台401更加剛性的結構,因為一下表面403以及側壁表面404的至少部分可以被此種介電保護材料模製層143所覆蓋。
圖14B是描繪一具有一垂直整合的微電子封裝200之範例的SiP 100的側視橫截面方塊圖。由於圖14B的SiP 100係類似於圖14A的SiP 100,因此大致只有差異才在以下用額外的細節來加以描述。
除了在微電子裝置145的一上表面407上的引線接合線231以外,另一微電子裝置410可以利用另一環氧樹脂或是其它的黏著層402以使得其之一下表面耦接至微電子裝置145的一上表面,該環氧樹脂或是其它的黏著層402係在此種面對的表面之間。由垂直的引線接合線432所提供的另一組的互連可以耦接在微電子裝置410的一上表面與電路平台401的一下表面403之間,以用於在微電子裝置410與電路平台401之間的電性通訊。微電子裝置145及410可以組合地形成一晶粒堆疊,其中此種裝置都處於一面朝上的朝向,以用於引線接合至其之上表面。
再者,除了具有引線接合線231以及微電子裝置410在微電子裝置145的上表面407上的一開始的設置以外,另一組的引線接合線431可以耦接至上表面407,以用於與微電子裝置410的一上表面408的互連。引線接合線431可以在向上彎弧以用於耦接至上表面408。這些引線接合線431因此可以將微電子裝置145及410的上表面彼此互連。微電子裝置145及410可以是主動裝置、被動裝置、或是主動及被動裝置的一組合。
同時參考到圖14A及14B,耦接至電路平台401的可以是一表面安裝技術("SMT")的構件(其可以是一主動或一被動SMT微電子裝置165)、以及一引線接合安裝的構件(例如是一主動或一被動引線接合的微電子裝置411)的任一種或是兩者。一主動或一被動SMT微電子裝置165可以面向下地被安裝至電路平台401的一上表面441,並且一主動或一被動引線接合的微電子裝置411可以面向上地被安裝至電路平台401的上表面441。
圖14C是描繪一具有一垂直整合的微電子封裝200之範例的SiP 100的側視橫截面方塊圖。由於圖14B的SiP 100係類似於圖14A及14B的SiP 100,因此大致只有差異才在以下用額外的細節來加以描述。
在此範例實施方式中,一中介體或是其它的電路平台414的一下表面係利用微凸塊或是其它的小形狀因數的互連413來互連接至一面朝上的微電子裝置145的一上表面上的接點。中介體414的一上表面係利用微凸塊或是其它的小形狀因數的互連415來互連接至一面朝下的微電子裝置416的一下表面上的接點。引線接合線131s的遠端可以耦接至中介體414的一上表面,以用於互連至電路平台400的一上表面405。引線接合線231的近端或下方的末端可以耦接至中介體414的一上表面,其中此種引線接合線的遠端或上方的末端係耦接至電路平台401的下表面403。藉由利用一中介體414以及覆晶或類似的微電子裝置416,更多用於引線接合線231及/或131s的區域以及更多在微電子裝置145及416之間的互連線可加以提供。
圖14D是圖14C的方塊圖,儘管是利用一保護介電材料的一模製層143覆蓋電路平台400。此保護介電材料的模製層143係在電路平
台400的一上表面405之上提供互連表面418。引線接合線131及331可以使得其之尖端或上方的末端延伸超出表面418,以用於一或多個被動或主動電路的互連。
這些是用於一SiP 100的一垂直整合的微電子封裝200的各種實施方式中的一些實施方式。這些或其它的實施方式亦可以根據在此的說明來加以提供。
焊料上的引線接合
已經假設引線接合線是被引線接合到一例如是銅的導電金屬層之上。然而,如同在以下用額外的細節敘述的,引線接合線可被引線接合到焊料之上。以此種方式,無電電鍍鎳(Ni)無電電鍍鈀(Pd)浸金(Au)("ENEPIG")是一種用於基板製造(例如是用於IC)的表面處理。然而,由於IC製造商拋棄ENEPIG基板而不用於覆晶的應用,因此使得一基板具有帶有一有機表面保護("OSP")層的銅以及一ENEPIG處理的混合是有問題的。以此種方式,如同在以下以額外的細節敘述的,一銅OSP係對於一疊層的表面使用一種焊料加在墊上("SOP")的技術,其中例如是BVATM接腳的引線接合線係接合到此種焊料之上。
圖15A至15D是描繪引線接合墊以及覆晶的墊在一相同的基板600上的漸進的形成的側視方塊圖。基板600可以是一如上所述的封裝基板或是其它基板,以用於一SiP或是其它的微電子構件650。以此種方式,如同在以下用額外的細節敘述的,具有焊料的引線接合墊可被使用於上述的引線接合線,例如是被球體接合至此種墊。
參考圖15A,基板600可以具有被沉積、電鍍、或是以其它
方式形成在其之一上表面605上的一導電層603,例如是一層的銅或是其它的導電金屬層。導電層603可被圖案化,以用於在上表面605上提供引線接合墊601以及覆晶或類似的小形狀因數的墊602兩者。
一焊料遮罩604可加以沉積及圖案化。以此種方式,導電層603的一上表面616可以是低於焊料遮罩604的一上表面615,並且焊料遮罩604的部分可以是位在相鄰的墊的墊601及602之間。以此種方式,焊料遮罩604可以具有用於接達引線接合墊601的間隙606、以及用於接達覆晶的墊602之較窄的間隙607。
參考圖15B,一焊料或其它的共晶層之焊料或其它的共晶墊608及609可以被印刷到墊601及602的上表面616之上。一引線接合墊601的一被露出的上表面616的表面積相對一置放於其上的焊料墊608的一下表面617的表面積之比例可以是實質小於一引線接合墊602的一被露出的上表面616的表面積相對一置放於其上的焊料墊609的一下表面617的表面積之比例。焊料墊608及609的每一個的一部分可以是高於焊料遮罩604的上表面615,並且焊料墊609的一部分可以重疊到上表面615之上。上表面615係在上表面616之上、或是高於上表面616。
參考圖15C,在焊料墊608及609的回焊之後,其之焊料可以散開,並且一助焊劑的量可被消除。以此種方式,一焊料墊608可以散開在原先是對應至其的引線接合墊601的一露出的表面區域之上。以此種方式,焊料墊608在回焊之後的上表面611可以是在焊料遮罩層604的上表面615之下、或是低於該上表面615。然而,焊料墊609在回焊之後的上表面613可以是在焊料遮罩層604的上表面615之上,並且可以重疊該上表面
615。選配的是,在回焊之後,焊料墊609可以被壓實以用於平坦化。
參考圖15D,例如是引線接合線131的引線接合線可被例如是球體、針腳或是其它方式的接合至焊料墊608。以此種方式,沿著焊料墊608的上表面611的焊料可以附接至引線接合線131的銅、鈀、或是其它材料。一覆晶的IC晶粒649可以使得例如是微凸塊的覆晶的接點648分別耦接至焊料墊609。
儘管前述內容係描述根據本發明的一或多個特點的範例實施例,但是根據本發明的該一或多個特點的其它及進一步的實施例可以在不脫離本發明的範疇下而被設計出,該範疇係藉由以下的申請專利範圍以及其等同物來加以決定。申請專利範圍所列的步驟並不意指該些步驟的任何順序。商標則是其個別的擁有者之財產權。
11‧‧‧主動微電子裝置
12‧‧‧被動微電子裝置
100‧‧‧系統級封裝(SiP)
131i‧‧‧內部的引線接合線
131s‧‧‧信號引線接合線
143‧‧‧介電保護材料模製層
145‧‧‧微電子裝置
165‧‧‧微電子裝置
200‧‧‧垂直整合的微電子封裝
231‧‧‧引線接合線
400‧‧‧電路平台
401‧‧‧電路平台
402‧‧‧黏著層
403‧‧‧下表面
404‧‧‧側壁表面
405‧‧‧上表面
406‧‧‧下表面
407‧‧‧上表面
411‧‧‧微電子裝置
441‧‧‧上表面
Claims (28)
- 一種垂直整合的微電子封裝,其係包括:一基板,其係具有一上表面以及一與該上表面相對的下表面;一第一微電子裝置,其係耦接至該基板的該上表面,該第一微電子裝置是一被動微電子裝置;第一引線接合線,其係耦接至該基板的該上表面,並且從該基板的該上表面延伸離開;第二引線接合線,其係耦接至該第一微電子裝置的一上表面,並且從該第一微電子裝置的該上表面延伸離開,該些第二引線接合線係比該些第一引線接合線短;以及一第二微電子裝置,其係耦接至該些第一引線接合線以及該些第二引線接合線的上方的末端,該第二微電子裝置係位在該第一微電子裝置之上,並且至少部分地重疊該第一微電子裝置。
- 根據申請專利範圍第1項之垂直整合的微電子封裝,其進一步包括一模製層,其係具有一最上面的表面以及一與該最上面的表面相對的最下面的表面,其係被設置以用於圍繞該些第一引線接合線以及該些第二引線接合線的長度的部分。
- 根據申請專利範圍第2項之垂直整合的微電子封裝,其中:該第一微電子裝置係被設置在該模製層中,並且完全位在該模製層的該最上面的表面與該最下面的表面之間;以及該第二微電子裝置係被耦接在該模製層的該最上面的表面之上。
- 根據申請專利範圍第3項之垂直整合的微電子封裝,其中該第二微電 子裝置是一被動微電子裝置。
- 根據申請專利範圍第3項之垂直整合的微電子封裝,其中該第二微電子裝置是一主動微電子裝置。
- 根據申請專利範圍第3項之垂直整合的微電子封裝,其中該第一微電子裝置以及該第二微電子裝置都處於一面朝下的朝向,以用於面對該基板的該上表面。
- 根據申請專利範圍第1項之垂直整合的微電子封裝,其進一步包括:一第三微電子裝置,其係耦接至該第二微電子裝置而且位在該第二微電子裝置之上,並且至少部分地重疊該第二微電子裝置。
- 根據申請專利範圍第7項之垂直整合的微電子封裝,其進一步包括:一模製層,其係具有一最上面的表面以及一與該最上面的表面相對的最下面的表面;該第一微電子裝置係被設置在該模製層中並且完全地位在該模製層的該最上面的表面與該最下面的表面之間;該第二微電子裝置係被設置在該模製層中並且至少部分地位在該模製層的該最上面的表面與該最下面的表面之間;以及該第三微電子裝置係耦接在該模製層的該最上面的表面之上。
- 根據申請專利範圍第8項之垂直整合的微電子封裝,其中該第二微電子裝置以及該第三微電子裝置分別是被動微電子裝置。
- 根據申請專利範圍第8項之垂直整合的微電子封裝,其中該第二微電子裝置以及該第三微電子裝置分別是另一被動微電子裝置以及一主動微電子裝置。
- 根據申請專利範圍第8項之垂直整合的微電子封裝,其中:該第一微電子裝置以及該第三微電子裝置都處於一面朝下的朝向,以用於面對該基板的該上表面;以及該第二微電子裝置係包含一重分佈層。
- 一種系統級封裝,其係包括根據申請專利範圍第1項之垂直整合的微電子封裝,其中該系統級封裝係包括:一第三微電子裝置,其係耦接至該基板的該上表面;以及第三引線接合線係耦接至該第三微電子裝置的一上表面,並且從該第三微電子裝置的該上表面延伸離開;以及該第三微電子裝置是一主動微電子裝置。
- 一種垂直整合的微電子封裝,其係包括:一基板,其係具有一上表面以及一與該上表面相對的下表面;一第一微電子裝置,其係耦接至該基板的該上表面,該第一微電子裝置是一被動微電子裝置;第一引線接合線係耦接至該基板的該上表面,並且從該基板的該上表面延伸離開;第二引線接合線係耦接至該第一微電子裝置的一上表面,並且從該第一微電子裝置的該上表面延伸離開;該些第一引線接合線的一第一部分係高於該些第二引線接合線;一第二微電子裝置係耦接至該些第一引線接合線的該第一部分的第一上方的末端,並且耦接至該些第二引線接合線的上方的末端,該第二微電子裝置係位在該第一微電子裝置之上並且至少部分地重疊該第一微電子裝 置;以及該些第一引線接合線的一第二部分係使得其之第二上方的末端耦接至該第一微電子裝置的上表面。
- 根據申請專利範圍第13項之垂直整合的微電子封裝,其進一步包括一模製層,其係具有一最上面的表面以及一與該最上面的表面相對的最下面的表面,其係被設置以用於圍繞該些第一引線接合線以及該些第二引線接合線兩者的長度。
- 根據申請專利範圍第14項之垂直整合的微電子封裝,其進一步包括:該第一微電子裝置係被設置在該模製層中,並且完全地位在該模製層的該最上面的表面與該最下面的表面之間;以及該第二微電子裝置係耦接在該模製層的該最上面的表面之上。
- 根據申請專利範圍第13項之垂直整合的微電子封裝,其進一步包括一第三微電子裝置,其係耦接至該第二微電子裝置而且位在該第二微電子裝置之上,並且至少部分地重疊該第二微電子裝置。
- 根據申請專利範圍第16項之垂直整合的微電子封裝,其進一步包括:一模製層,其係具有一最上面的表面以及一與該最上面的表面相對的最下面的表面;該第一微電子裝置係被設置在該模製層中,並且完全地位在該模製層的該最上面的表面與該最下面的表面之間;該第二微電子裝置係被設置在該模製層中,並且至少部分地位在該模製層的該最上面的表面與該最下面的表面之間;以及該第三微電子裝置係耦接在該模製層的該最上面的表面之上。
- 根據申請專利範圍第17項之垂直整合的微電子封裝,其中該第二微電子裝置以及該第三微電子裝置分別是被動微電子裝置。
- 根據申請專利範圍第17項之垂直整合的微電子封裝,其中該第二微電子裝置以及該第三微電子裝置分別是另一被動微電子裝置以及一主動微電子裝置。
- 根據申請專利範圍第17項之垂直整合的微電子封裝,其中:該第一微電子裝置以及該第三微電子裝置都處於一面朝下的朝向,以用於面對該基板的該上表面;以及該第二微電子裝置係包含一重分佈層。
- 一種垂直整合的微電子封裝,其係包括:一第一電路平台,其係具有一上表面以及一與該上表面相對的下表面;一微電子裝置,其係耦接至該第一電路平台的上表面;第一引線接合線,其係耦接至該第一電路平台的上表面,並且從該第一電路平台的該上表面延伸離開;第二引線接合線,其係耦接至該微電子裝置的一上表面,並且從該微電子裝置的該上表面延伸離開,該些第二引線接合線係比該些第一引線接合線短;以及一第二電路平台,其係耦接至該些第一引線接合線以及該些第二引線接合線的上方的末端,該第二電路平台係位在該第一微電子裝置之上並且至少部分地重疊該第一微電子裝置。
- 根據申請專利範圍第21項之垂直整合的微電子封裝,其中該微電子裝置係處於一面朝上的朝向。
- 根據申請專利範圍第22項之垂直整合的微電子封裝,其進一步包括:至少一處於一面朝下的朝向的被動或主動電路裝置係耦接至該第二電路平台的一上表面。
- 根據申請專利範圍第22項之垂直整合的微電子封裝,其進一步包括:至少一處於一面朝上的朝向的被動或主動電路裝置係耦接至該第二電路平台的一上表面。
- 根據申請專利範圍第22項之垂直整合的微電子封裝,其進一步包括:該微電子裝置是一第一微電子裝置;一第二微電子裝置係耦接至處於一面朝上的朝向的該第一微電子裝置的一上表面;第三引線接合線係耦接至該第二微電子裝置的一上表面並且從該第二微電子裝置的該上表面延伸離開,該些第三引線接合線係比該些第二引線接合線短;以及該第二電路平台係耦接至該第三引線接合的上方的末端。
- 根據申請專利範圍第22項之垂直整合的微電子封裝,其進一步包括一模製或圍堰填充層的一介電材料,以用於覆蓋該第一微電子裝置以及該第二微電子裝置,並且用於覆蓋該些第一引線接合線、該些第二引線接合線、以及該些第三引線接合線的垂直的範圍。
- 根據申請專利範圍第22項之垂直整合的微電子封裝,其進一步包括:該微電子裝置是一第一微電子裝置;一第三電路平台,其係在該些第一引線接合線與該第一微電子裝置的上表面之間耦接至該第一微電子裝置的上表面; 該些第一引線接合線係被接合到該第三電路平台的一上表面;以及一第二微電子裝置,其係處於一面朝下的朝向來耦接至該第三電路平台的上表面。
- 根據申請專利範圍第27項之垂直整合的微電子封裝,其進一步包括:第三引線接合線,其係接合至第一電路平台的上表面,並且耦接至該第三電路平台的上表面。
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-
2016
- 2016-01-12 US US14/993,586 patent/US10490528B2/en active Active
- 2016-10-12 TW TW105132856A patent/TW201724428A/zh unknown
- 2016-10-12 KR KR1020187011622A patent/KR102562518B1/ko active IP Right Grant
- 2016-10-12 EP EP16856062.1A patent/EP3363047A4/en not_active Withdrawn
- 2016-10-12 CN CN201680058261.6A patent/CN108431952A/zh active Pending
- 2016-10-12 WO PCT/US2016/056526 patent/WO2017066239A1/en unknown
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EP3363047A4 (en) | 2019-06-19 |
CN108431952A (zh) | 2018-08-21 |
WO2017066239A1 (en) | 2017-04-20 |
KR102562518B1 (ko) | 2023-08-01 |
EP3363047A1 (en) | 2018-08-22 |
US20170103968A1 (en) | 2017-04-13 |
KR20180054832A (ko) | 2018-05-24 |
US10490528B2 (en) | 2019-11-26 |
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