WO2019066870A1

WO2019066870A1 - Faraday cage comprising through-silicon-vias

Info

Publication number: WO2019066870A1
Application number: PCT/US2017/054111
Authority: WO
Inventors: Krishna Bharath; Kaladhar Radhakrishnan; William Lambert; Michael Hill; Beomseok CHOI
Original assignee: Intel Corporation
Priority date: 2017-09-28
Filing date: 2017-09-28
Publication date: 2019-04-04

Abstract

An apparatus is provided which comprises: a substrate; a die coupled to the substrate; at least two active devices positioned in the substrate; a plurality of vias surrounding at least one of the two active devices such that a Faraday cage is formed around the at least one of the two active devices.

Description

FARADAY CAGE COMPRISING THROUGH-SILICON- VIAS

BACKGROUND

[0001] As radio frequency (RF) processors are being positioned in close proximity to other processors (e.g., general computer processing unit, an application specific processor, a digital signal processor, etc.), electromagnetic interference (EMI) becomes an issue. In one instance, switching noise from digital circuits in the other neighboring processors may result in an EMI that interferes with the highly sensitive RF analog circuits of the RF processor. In another example, RF energy from the RF processor may also create an EMI that impacts the sensitive analog circuits of other neighboring processors.

BRIEF DESCRIPTION OF THE DRAWINGS

[0002] The embodiments of the disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.

[0003] Fig. 1 illustrates a top view of an integrated circuit (IC) package comprising a

Faraday cage, according to some embodiments of the disclosure.

[0004] Fig. 2A-B illustrate a cross-section of the IC package along a cut, according to some embodiments of the disclosure.

[0005] Fig. 3 illustrates a method flowchart for forming an IC package with a Faraday cage, according to some embodiments.

[0006] Fig. 4 illustrates a cross-section of an IC package with a stacked die and interposer having a Faraday cage, according to some embodiments of the disclosure.

[0007] Fig. 5 illustrates a smart device or a computer system or a SoC (System-on-

Chip) which is coupled to one or more circuitries surrounded by a Faraday cage, according to some embodiments.

DETAILED DESCRIPTION

[0008] Current techniques for noise isolation include, for example, splitting up and isolating power rails, and adding additional decoupling elements such as on-die metal- insulator-metal (MIM) capacitor devices and finger capacitors. Splitting up power rails results in the need for additional platform voltage regulators, and adding on-die capacitors requires additional silicon area or MIM layers, all of which add cost. [0009] Some embodiments use vias such as through-silicon-vias (TSVs) on an active interposer architecture to create an electromagnetic interference (EMI) shield, also referred to as a Faraday Cage to isolate noise sensitive analog and RF circuitry from switching noise generated by digital circuits. In an active interposer architecture, a stack (vertical or horizontal) of dies of same or different processor technologies are assembled. For instance, a die designed on a latest processor technology node is stacked on top of a base die that is a lower cost die and designed on an older generation process technology node. In this example, the base die may be optimized for low leakage digital circuits as well as for analog and RF circuits which do not scale well on leading edge process technology nodes. The analog and RF circuitry are sensitive to switching noise coupled from the adjacent digital logic. The TSVs of the some embodiments create an EMI shield to isolate noise sensitive analog and RF circuitry from the switching noise generated by the digital circuits. Other technical effects will be evident from the various embodiments and figures.

[0010] In the following description, numerous details are discussed to provide a more thorough explanation of embodiments of the present disclosure. It will be apparent, however, to one skilled in the art, that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present disclosure.

[0011] Note that in the corresponding drawings of the embodiments, signals are represented with lines. Some lines may be thicker, to indicate more constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or a logical unit. Any represented signal, as dictated by design needs or preferences, may actually comprise one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme.

[0012] Throughout the specification, and in the claims, the term "connected" means a direct connection, such as electrical, mechanical, or magnetic connection between the things that are connected, without any intermediary devices. The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected or an indirect connection, through one or more passive or active intermediary devices. The term "circuit" or "module" may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on."

[0013] The term "scaling" generally refers to converting a design (schematic and layout) from one process technology to another process technology and subsequently being reduced in layout area. The term "scaling" generally also refers to downsizing layout and devices within the same technology node. The term "scaling" may also refer to adjusting (e.g., slowing down or speeding up - i.e. scaling down, or scaling up respectively) of a signal frequency relative to another parameter, for example, power supply level. The terms "substantially," "close," "approximately," "near," and "about," generally refer to being within +/- 10% of a target value.

[0014] Unless otherwise specified the use of the ordinal adjectives "first," "second," and "third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

[0015] For the purposes of the present disclosure, phrases "A and/or B" and "A or B" mean (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C). The terms "left," "right," "front," "back," "top," "bottom," "over," "under," and the like in the

description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions.

[0016] As used herein the terms "top," "bottom," "upper," "lower," "lowermost," and

"uppermost" when used in relationship to one or more elements are intended to convey a relative rather than absolute physical configuration. Thus, an element described as an "upper film layer" or a "top element" in a device may instead form the "lowermost element" or "bottom element" in the device when the device is inverted. Similarly, an element described as the "lowermost element" or "bottom element" in the device may instead form the

"uppermost element" or "top element" in the device when the device is inverted.

[0017] As used herein, the term "logically associated" when used in reference to a number of objects, systems, or elements, is intended to convey the existence of a relationship between the objects, systems, or elements such that access to one object, system, or element exposes the remaining objects, systems, or elements having a "logical association" with or to the accessed object, system, or element. An example "logical association" exists between relational databases where access to an element in a first database may provide information and/or data from one or more elements in a number of additional databases, each having an identified relationship to the accessed element. In another example, if "A" is logically associated with "B," accessing "A" will expose or otherwise draw information and/or data from "B," and vice-versa.

[0018] It is pointed out that those elements of a figure having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0019] Fig. 1 illustrates a top view 100 of an integrated circuit (IC) package comprising a Faraday cage, according to some embodiments of the disclosure. A Faraday cage or shield protects a device or circuit inside or outside the cage from radio frequency interference (RFI) or EMI. A typical example of a Faraday cage is a mesh of conductors configured as a box, for example, that distributes charge on the conductors caused by external fields (e.g., RFI or EMI) such that the charge effects are cancelled by the conductors. As such, the device or circuit inside the cage is protected from the adverse effects of external RFI or EMI. In another such example, circuits outside the cage are protected from RFI or EMI generated by the circuit inside the cage. In various embodiments, the technical effect of a Faraday cage or shield is realized in an IC package having a mix of noisy and noise- sensitive circuits and/or dies such that the noise-sensitive circuits (that may be a separate die or a group of circuits) are shielded from the adverse effects of noisy circuits that otherwise generate EMI/RFI.

[0020] The apparatus in top view 100 comprises an IC package 101, die 102 (also referred to as the bottom die), die 103 (e.g., a general purpose processor, a graphics processor, an application specific integrated circuit (ASIC), a digital signal processor (DSP), etc.), die 104 (e.g., a modem, a communication chip, baseband processor, etc.), and vias 105 that form the Faraday cage.

[0021] In some embodiments, vias 105 are through-silicon-vias (TSVs) that penetrate through a field of devices in die 102. In various embodiments, die 102 is formed in a substrate package. In some embodiments, die 102 is a substrate having interconnect layers along with noisy and noise-sensitive circuits. In some embodiments, the substrate is an active interposer. In some embodiments, die 102 is formed in an interposer of IC package 101. In some embodiments, die 102 is an interposer having interconnect layers along with noisy and noise-sensitive circuits.

[0022] In some embodiments, the switching activity of the logic circuits in die 102 can generate EMI or RFI. In some embodiments, vias 105 significantly attenuate this EMI/RFI from coupling to the adjacent noise-sensitive circuits (e.g., RF circuits that are generally noise-sensitive circuits). As such, more noisy or EMI/RFI generating circuits can be packed in die 102 while protecting other noise-sensitive circuits. This allows for increased performance from die 103 by allowing its circuits to be clocked at higher frequency. The Faraday cage implemented by vias 105 allow for increased density of transistors without the adverse effects of RFI/EMI. In some embodiments, the spacing 'w' between vias 105 is selected based on simulations that estimate EMI/RFI and their attenuation by vias 105. In general, as vias 105 are closely positioned (e.g., when 'w' is smaller), then more EMI/RFI attenuation is achieved.

[0023] Fig. 2A illustrates a cross-section 200 of the IC package of Fig. 1 along cut

AA', according to some embodiments of the disclosure. Cross-section 200 provides more details about the organization of vias 105 relative to other circuits. In some embodiments, vias 105 (e.g., TSVs 105) are metal columns (e.g., comprising one of W, Al, Au, Au, Co, their alloys, or Graphene). In some embodiments, vias 105 are separated from one another by a distance 'w' which is sufficient to cancel the fields generated by EMI/EFI. In some embodiments, die 102 is a substrate comprising noisy and noise-sensitive circuits. In this example, the noisy circuits are 203a (e.g., high frequency switching circuits such as cache) positioned in substrate 102, while noise-sensitive circuits are 203b (e.g., RF IC). As such, the substrate 102 is an active substrate. The active substrate is also referred to as an active interposer in that it performs the function of an interposer as well as carrying active devices or circuits.

[0024] Here, circuits 203a may be communicatively coupled to die 103 and package

101 through solder balls (e.g., 202 and 208), vias (e.g., 204), layers of conductors (e.g., 205, 206, and 207) coupled by vias (not shown). In this example, conductors 206 run on extend orthogonal to conductors 205 and 207. However, these layers can be all parallel too. In some embodiments, circuits 203b may be communicatively coupled to die 104 and package 101 through solder balls (e.g., 202 and 209), vias (e.g., 204), layers of conductors (e.g., 205, 206, and 207) coupled by vias (not shown). Package 101 is then attached to a printed circuit board (PCB) 201 using any known technology. [0025] In some embodiments, circuits and dies in this apparatus may be fabricated on different process technology nodes. For example, die 102 may be fabricated on a process technology node which is a generation older than a process technology node used to fabricate die 103. In some embodiments, circuits 203 a/b in substrate 102 are fabricated using different process technology nodes. For example, circuit 203a may be a cache memory fabricated on a 14 nm process technology node, while circuit 203b may be an RF IC fabricated on 22 nm process technology node which is specially tailored for analog/RF circuits. In some embodiments, dies 103 and 104 are also fabricated on different process technology nodes. For example, die 103 is a graphics processor fabricated an advanced process technology node (e.g., on a 10 nm or 7 nm process technology node). The use of Faraday cage allows for packaging circuits/logic and dies of different or same process technology nodes while providing the necessary RFI/EMI protection.

[0026] While various embodiments illustrate square or rectangular pattern for the layout of TSVs 105, other patterns can also be used. For example, round, oval, trapezoidal, or any arbitrary shape for the layout of TSVs 105 that can enclose the circuit that need to be shielded or that needs to be shielded from can be used. The separation or distance of the TSVs along the x-axis from the boundary of the circuits of interest (e.g., circuit that need to be shielded or that needs to be shielded from) can be determined according to simulations. For example, the separation or distance of the TSVs 105 along the x-axis from the boundary of the circuits of interest can be enough so that the electric fields being cancelled by the TSVs 105 do not interfere with any circuit property of the circuits of interest.

[0027] In some embodiments, the spacing 'w' between the TSVs 105 is related to the wavelength of the interfering signal and/or the wavelength of the signals of interest. In some embodiments, the spacing 'w' between the TSVs is about one tenth of the wavelength for effective cancelling of waves. For example, for millimeter wave RF circuits operating at 60 GHz, the wavelength in silicon is 1.5 mm. In this example, the spacing 'w' between vias would be 150 μιτι. In another example, for logic circuits, for creating a Faraday shield that is effective at about 5 GHz, 'w' can be 1 mm.

[0028] Fig. 2B illustrates a cross-section 220 of the IC package along cut AA', according to some embodiments of the disclosure. Fig. 2B is similar to Fig. 2A except for additional conductors placed over noisy circuit 203a to provide additional EMI/RFI protection to die 102. In this example, layers 206 are used to provide rows of conductors orthogonal to vias 105. In some embodiments, similar conductors can also be routed underneath noisy circuit 203a so as to fully encase or cage noisy circuit 203a. In some embodiments, a Faraday cage is formed around noise-sensitive circuits along with around noisy circuits. As such, an added level of RFI/EMI migration is achieved.

[0029] In some embodiments, TSVs 105 are punched all the way through substrate

102. For example, TSVs 105 may have stubs along the z-direction on the top and bottom surfaces of substrate 102. In some embodiments, TSVs 105 are punched through one surface of substrate 102. For example, TSVs 105 are punched through the top surface of substrate 102 such that the punched through TSVs 105 are still a distance away from die 103 and its solder balls 208. The other end of the TSVs 105 in this example would terminate near or at the bottom layer of substrate 102. In some embodiments, TSVs 105 are not punched through substrate 102. For example, TSVs 105 stop at the upper and lower surfaces or layers of substrate 102 and may not extend along the z-direction through substrate 102. The length of TSVs along the z-direction depends on how much the bottom die substrate 102 is thinned and where the TSVs 105 stop. For example, for an 80 μηι thickness of substrate 102, TSVs 105 can have a length of approximately 70 μηι along the z-direction. Any suitable scheme or process mechanism can be used for fabricating TSVs 105. For example, laser drilling and etching can be used for manufacturing TSVs 105.

[0030] Fig. 3 illustrates a method flowchart 300 for forming an IC package with a

Faraday cage, according to some embodiments. The various blocks (or operations) in flowchart 300 can be performed together (e.g., simultaneously), in different order, or in the same order as presented. At block 301, substrate 102 is formed which may comprise interconnect layers (e.g., 205, 206, 207). At block 302, circuits/logics 203a/b are positioned in substrate 102 (e.g., organic or inorganic substrate) which may be fabricated on same or different process technology nodes. As such, substrate 102 is an active substrate. In some embodiments, circuits/logics 203a/b are fabricated in substrate 102 instead of being dropped into substrate 102 and then interconnected. At block 303, a plurality of vias 105 are fabricated and surrounded around one of the circuits/logic 203a/b to realize a Faraday cage. In some embodiments, these vias are TSVs that punch through the transistor layer in a bottom die of a stack of dies to create an effective shield. At block 304, substrate 102 is then coupled to dies 103/104. The stack of substrate 102 and dies 103/104 is then hooked up in an IC package 101 as indicated by block 305. The IC package 101 is then attached to a circuit board 201 (e.g., a printed circuit board 201). [0031] Fig. 4 illustrates a cross-section 400 of an IC package with a stacked die and interposer having a Faraday cage, according to some embodiments of the disclosure. In some embodiments, IC (integrated circuit) package assembly may include first die 401, package substrate 404, interposer 405, and circuit board 422. IC package assembly of cross-sectional view 400 is one example of a stacked die configuration in which first die 401 is coupled to package substrate 404, and second die 402 is coupled with first die 401 , in accordance with some embodiments.

[0032] In some embodiments, first die 401 may have a first side SI and a second side

S2 opposite to the first side S I . In some embodiments, the first side S I may be the side of the die commonly referred to as the "inactive" or "back" side of the die. In some embodiments, the second side S2 may include one or more transistors, and may be the side of the die commonly referred to as the "active" or "front" side of the die. In some embodiments, second side S 2 of first die 401 may include one or more electrical routing features 406. In some embodiments, second die 402 may include an "active" or "front" side with one or more electrical routing features 606. In some embodiments, electrical routing features 406 may be bond pads (e.g., formed from a combination of bumps and solder balls 403).

[0033] In some embodiments, second die 402 may be coupled to first die 401 in a front-to-back configuration (e.g., the "front" or "active" side of second die 402 is coupled to the "back" or "inactive" side S I of first die 401 ). In some embodiments, dies may be coupled with one another in a front-to-front, back-to-back, or side-to-side arrangement. In some embodiments, one or more additional dies may be coupled with first die 401 , second die 402, and/or with package substrate 404. Other embodiments may lack second die 402. In some embodiments, first die 401 may include one or more TSVs (through-silicon-vias). In some embodiments, second die 402 is coupled to first die 401 by die interconnects formed from combination of bumps and solder bails 403. In some embodiments, solder bails 403 are formed using a solder-on-die (SOD) process.

[0034] In some embodiments, inter-die interconnects may be solder bumps, copper pillars, or other electrically conductive features. In some embodiments, an interface layer 424 may be provided between first die 401 and second die 402. In some embodiments, interface layer 424 may be, or may include, a layer of under-fill, adhesive, dielectric, or other material. In some embodiments, interface layer 424 may serve various functions, such as providing mechanical strength, conductivity, heat dissipation, or adhesion. [0035] In some embodiments, first die 401 and second die 402 may be single dies

(e.g., first die 401 is a single die instead of multiple dies). In other embodiments, first die

401 and/or second die 402 may include two or more dies. For example, in some

embodiments first die 401 and/or second die 402 may be a wafer (or portion of a wafer) having two or more dies formed on it. In some embodiments, first die 401 and/or second die

402 includes two or more dies embedded in an encapsulant. In some embodiments, the two or more dies are arranged side-by-side, vertically stacked, or positioned in any other suitable arrangement. In some embodiments, the IC package assembly may include, for example, combinations of flip-chip and wire-bonding techniques, interposers, multi-chip package configurations including system-on-chip (SoC) and/or package-on-package (PoP) configurations to route electrical signals.

[0036] In some embodiments, first die 401 and/or second die 402 may be a primary logic die. In some embodiments, first die 401 and/or second die 402 may be configured to function as memory, an application specific circuit (ASIC), a processor, or some combination of such functions. For example, first die 401 may include a processor and second die 402 may include memory. In some embodiments, one or both of first die 401 and second die 402 may be embedded in encapsulant 1008. In some embodiments, encapsulant 408 can be any suitable material, such as an Ajinomoto Build-up Film (ABF) substrate, other

dielectric/organic materials, resins, epoxies, polymer adhesives, silicones, acrylics, polyimides, cyanate esters, thermoplastics, and/or thermosets.

[0037] In some embodiments, first die 401 may be coupled to package substrate 404

(e.g., CPU substrate). In some embodiments, package substrate 404 may be a coreless substrate. For example, package substrate 404 may be a bumpless build-up layer (BBUL) assembly that includes a plurality of '"bumpless" build-up layers. Here, the term "bumpless build-up layers" generally refers to layers of substrate and components embedded therein without the use of solder or other attaching means that may be considered "bumps."

[0038] In some embodiments, the one or more build-up layers may have material properties that may be altered and/or optimized for reliability, warpage reduction, etc. In some embodiments, package substrate 404 may be composed of a polymer, ceramic, glass, or semiconductor material. In some embodiments, package substrate 404 may be a conventional cored substrate and/or an interposer.

[0039] In some embodiments, interposer 405 is provided between circuit board 422 and substrate 404. Interposer 405 of the various embodiments may be formed of a variety of materials. For example, interposer 405 may be formed of an epoxy resin, a fiberglass- reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some embodiments, interposer 405 may be formed of alternate rigid or flexible materials, such as silicon, germanium, and other group III-V and group IV materials of the Periodic Table. In some embodiments, interposer 405 may include metal interconnects and vias including but not limited to TSVs.

[0040] In some embodiments, interposer 405 may include embedded devices including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, ESD (electrostatic discharge diode) devices, and memory devices. In some embodiments, interposer 405 may include complex devices such as RF devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices, etc. In some embodiments, package interconnects 412a may couple electrical routing features 41.0a disposed on the second side of package substrate 404 to corresponding electrical routing features 416a on interposer 405. In some embodiments, noisy circuits in interposer 405 such as circuits 4405 (e.g., 203a) are shielded by TSVs 4402/105. As such, RF I/EMI effects are minimized for other neighboring circuits such as noise-sensitive circuit 4404/203b (e.g., RF IC).

[0041] In some embodiments, circuit board (or motherboard) 422 may be a PCB

(printed circuit board) composed of an electrically insulating material such as an epoxy laminate. For example, circuit board 422 may include electrically insulating layers composed of materials such as, for example, polytetrafluoroethylene, phenolic cotton paper materials such as Flame Retardant 4 (FR-4), FR-1 , cotton paper and epoxy materials such as CEM-1 or CEM-3, or woven glass materials that are laminated together using an epoxy resin prepreg material.

[0042] Structures such as traces, trenches, and vias (which are not shown here) may be formed through the electrically insulating layers to route the electrical signals of first die 401 through the circuit board 422. Circuit board 422 may be composed of other suitable materials in other embodiments. In some embodiments, circuit board 422 may include other electrical devices coupled to the circuit board that are configured to route electrical signals to or from first die 401 through circuit board 422. In some embodiments, circuit board 422 may be a motherboard. [0043] In some embodiments, a one side of interposer 405 is coupled to the second side of substrate 404 via routings 416a, 412a, and 410a, In some embodiments, another side of interposer 405 is coupled to circuit board 422 by package interconnects 410b, 412b, and 416b.

[0044] In some embodiments, package substrate 404 may have electrical routing features formed therein to route electrical signals between first die 401 (and/or the second die 402) and circuit board 422 and/or other electrical components external to the IC package assembly. In some embodiments, package interconnects 412a/b and die interconnects 406 include any of a wide variet ' of suitable structures and/or materials including, for example, bumps, pillars or balls formed using metals, alloys, solderable material, or their

combinations. In some embodiments, electrical routing features 410 may be arranged in a ball grid array ("BGA") or other configuration.

[0045] Fig. 5 illustrates a smart device or a computer system or a SoC (System-on-

Chip) 2100 which is coupled to one or more circuitries surrounded by a Faraday cage, according to some embodiments. In this example, a block diagram of an embodiment of a mobile device is provided in which flat surface interface connectors could be used. In some embodiments, computing device 2100 represents a mobile computing device, such as a computing tablet, a mobile phone or smart-phone, a wireless-enabled e-reader, or other wireless mobile device. It will be understood that certain components are shown generally, and not all components of such a device are shown in computing device 2100.

[0046] For purposes of the embodiments, the transistors in various circuits and logic blocks described here are metal oxide semiconductor (MOS) transistors or their derivatives, where the MOS transistors include drain, source, gate, and bulk terminals. The transistors and/or the MOS transistor derivatives also include Tri-Gate and FinFET transistors, Gate All Around Cylindrical Transistors, Tunneling FET (TFET), Square Wire, or Rectangular Ribbon Transistors, ferroelectric FET (FeFETs), or other devices implementing transistor functionality like carbon nanotubes or spintronic devices. MOSFET symmetrical source and drain terminals i.e., are identical terminals and are interchangeably used here. A TFET device, on the other hand, has asymmetric Source and Drain terminals. Those skilled in the art will appreciate that other transistors, for example, Bi-polar junction transistors— BJT PNP/NPN, BiCMOS, CMOS, etc., may be used without departing from the scope of the disclosure. [0047] In some embodiments, computing device 2100 includes a first processor 2110

(e.g., first die 401). The various embodiments of the present disclosure may also comprise a network interface within 2170 such as a wireless interface so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant.

[0048] In one embodiment, processor 2110 can include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means. The processing operations performed by processor 2110 include the execution of an operating platform or operating system on which applications and/or device functions are executed. The processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, and/or operations related to connecting the computing device 2100 to another device. The processing operations may also include operations related to audio I/O and/or display I/O.

[0049] In one embodiment, computing device 2100 includes audio subsystem 2120, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device 2100, or connected to the computing device 2100. In one embodiment, a user interacts with the computing device 2100 by providing audio commands that are received and processed by processor 2110.

[0050] Display subsystem 2130 represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device 2100. Display subsystem 2130 includes display interface 2132, which includes the particular screen or hardware device used to provide a display to a user. In one embodiment, display interface 2132 includes logic separate from processor 2110 to perform at least some processing related to the display. In one embodiment, display subsystem 2130 includes a touch screen (or touch pad) device that provides both output and input to a user.

[0051] I/O controller 2140 represents hardware devices and software components related to interaction with a user. I/O controller 2140 is operable to manage hardware that is part of audio subsystem 2120 and/or display subsystem 2130. Additionally, I/O controller 2140 illustrates a connection point for additional devices that connect to computing device 2100 through which a user might interact with the system. For example, devices that can be attached to the computing device 2100 might include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.

[0052] As mentioned above, I/O controller 2140 can interact with audio subsystem

2120 and/or display subsystem 2130. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device 2100. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display subsystem 2130 includes a touch screen, the display device also acts as an input device, which can be at least partially managed by I/O controller 2140. There can also be additional buttons or switches on the computing device 2100 to provide I/O functions managed by I/O controller 2140.

[0053] In one embodiment, I/O controller 2140 manages devices such as

accelerometers, cameras, light sensors or other environmental sensors, or other hardware that can be included in the computing device 2100. The input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features).

[0054] In one embodiment, computing device 2100 includes power management 2150 that manages battery power usage, charging of the battery, and features related to power saving operation. Memory subsystem 2160 includes memory devices for storing information in computing device 2100. Memory can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory subsystem 2160 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of the computing device 2100.

[0055] Elements of embodiments are also provided as a machine-readable medium

(e.g., memory 2160) for storing the computer-executable instructions. The machine-readable medium (e.g., memory 2160) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer-executable instructions. For example, embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection).

[0056] Connectivity 2170 includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable the computing device 2100 to communicate with external devices. The computing device 2100 could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices.

[0057] Connectivity 2170 can include multiple different types of connectivity. To generalize, the computing device 2100 is illustrated with cellular connectivity 2172 and wireless connectivity 2174. Cellular connectivity 2172 refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, or other cellular service standards. Wireless connectivity (or wireless interface) 2174 refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), or other wireless communication.

[0058] Peripheral connections 2180 include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be understood that the computing device 2100 could both be a peripheral device ("to" 2182) to other computing devices, as well as have peripheral devices ("from" 2184) connected to it. The computing device 2100 commonly has a "docking" connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on computing device 2100. Additionally, a docking connector can allow computing device 2100 to connect to certain peripherals that allow the computing device 2100 to control content output, for example, to audiovisual or other systems.

[0059] In addition to a proprietary docking connector or other proprietary connection hardware, the computing device 2100 can make peripheral connections 1680 via common or standards-based connectors. Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types.

[0060] Reference in the specification to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of "an embodiment," "one embodiment," or "some embodiments" are not necessarily all referring to the same embodiments. If the specification states a component, feature, structure, or characteristic "may," "might," or "could" be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to "a" or "an" element, that does not mean there is only one of the elements. If the specification or claims refer to "an additional" element, that does not preclude there being more than one of the additional element.

[0061] Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[0062] While the disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. The embodiments of the disclosure are intended to embrace all such alternatives, modifications, and variations as to fall within the broad scope of the appended claims.

[0063] In addition, well known power/ground connections to integrated circuit (IC) chips and other components may or may not be shown within the presented figures, for simplicity of illustration and discussion, and so as not to obscure the disclosure. Further, arrangements may be shown in block diagram form in order to avoid obscuring the disclosure, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the present disclosure is to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.

[0064] The following examples pertain to further embodiments. Specifics in the examples may be used anywhere in one or more embodiments. All optional features of the apparatus described herein may also be implemented with respect to a method or process.

The various examples here can be interdependent on each other.

[0065] Example 1. An apparatus comprising: a substrate; a die coupled to the substrate; at least two active devices positioned in the substrate; and a plurality of vias surrounding at least one of the two active devices such that a Faraday cage is formed around the at least one of the two active devices.

[0066] Example 2. The apparatus of example 1, wherein the at least one active device is part of a logic that is fabricated on a process technology node different from the process technology node for fabricating the die.

[0067] Example 3. The apparatus of example 1, wherein the substrate is an active interposer.

[0068] Example 4. The apparatus according to any of examples 1 to 2, comprises an interposer coupled to the substrate.

[0069] Example 5. The apparatus of example 4 comprises a second of at least two active devices positioned in the interposer.

[0070] Example 6. The apparatus of example 5 comprises a second plurality of vias surrounding at least one of the second of the at least two active devices such that a Faraday cage is formed around the at least one of the second of the at least two active devices.

[0071] Example 7. The apparatus of example 6, wherein the second plurality of vias are through-silicon-vias (TSVs).

[0072] Example 8. The apparatus of example 6, wherein the at least one active device of the second of the at least two devices is part of a logic that is fabricated on a process technology node different from the process technology node for fabricating the die.

[0073] Example 9. The apparatus of example 1 , wherein the plurality of vias comprise through-silicon-vias (TSVs).

[0074] Example 10. An apparatus comprising: a first die; a second die stacked under the first die, wherein the second die comprises a first circuitry and a second circuitry; and a plurality of vias in the second die surrounding the first circuitry such that the second circuitry is outside of the plurality of vias. [0075] Example 1 1. The apparatus of example 10, wherein the second die is to function as an interposer of an integrated circuit (IC) package.

[0076] Example 12. The apparatus according to any one of examples 10 to 11 , wherein the second die is fabricated on a process technology node different from the process technology node for fabricating the first die.

[0077] Example 13. The apparatus according to any one of examples 10 to 12, wherein the plurality of vias comprise through-silicon-vias (TSVs).

[0078] Example 14. The apparatus of example 10, wherein the first circuitry is predominantly a digital circuitry, and wherein the second circuitry is a communication circuitry.

[0079] Example 15. The apparatus of example 14, wherein the communication circuitry comprises an RF integrated circuit (RFIC).

[0080] Example 16. The apparatus according to any one of examples 10 to 15, wherein the first die comprises one of: a graphics processor, general purpose processor, an application specific integrated circuit, or a digital signal processor.

[0081] Example 17. An apparatus comprising: a plurality of layers providing interconnects; a first circuitry coupled to at least one of the layers of the plurality; a second circuitry coupled to at least another of layers of the plurality; and a plurality of vias surrounding the first circuitry such that the second circuitry is outside the plurality of vias.

[0082] Example 18. The apparatus of example 17, wherein the plurality of layers, first circuitry, second circuitry and plurality of vias are positioned in an interposer.

[0083] Example 19. The apparatus of example 17, wherein the plurality of layers, first circuitry, second circuitry and plurality of vias are positioned in a package substrate.

[0084] Example 20. The apparatus according to any of examples 17 to 19, wherein the first circuitry is coupled to a first die.

[0085] Example 21. The apparatus according to any of examples 17 to 19, wherein the second circuitry is coupled to a second die.

[0086] Example 22. The apparatus according to any of examples 17 to 19, wherein the first and second dies are fabricated on first and second process technology nodes.

[0087] Example 23. The apparatus of example 17, wherein the first and second dies are fabricated on a same process technology node. [0088] Example 24. The apparatus of example 23, wherein the first circuitry is fabricated on a process technology node different than a processor technology node of the first die.

[0089] Example 25. A system comprising: an integrated circuit (IC) package comprising: an interposer coupled to a printed circuit board; a substrate coupled to the interposer layer; one or more dies coupled to the substrate, wherein the substrate comprises: at least two active devices, one of which is coupled to the one or more dies; and a plurality of vias surrounding at least one of the two active devices such that a Faraday cage is formed around the at least one of the two active devices; and a wireless interface to allow the one or more dies to communicate with another device.

[0090] Example 26. The system of example 25, wherein the plurality of vias comprise through-silicon-vias (TSVs).

[0091] Example 27. A method comprising: forming a substrate; coupling a die to the substrate; positioning at least two active devices in the substrate; and surrounding a plurality of vias around at least one of the two active devices such that a Faraday cage is formed around the at least one of the two active devices.

[0092] Example 28. The method of example 26, wherein the at least one active device is part of a logic that is fabricated on a process technology node different from the process technology node for fabricating the die.

[0093] Example 29. The method according to any of examples 27 to 28, comprises coupling an interposer to the substrate.

[0094] Example 30. The method of example 29 comprises positioning a second of at least two active devices in the interposer.

[0095] Example 31. The method of example 30 comprises surrounding a second plurality of vias around at least one of the second of the at least two active devices such that a Faraday cage is formed around the at least one of the second of the two active devices.

[0096] Example 32. The method of example 31, wherein the second plurality of vias are through-silicon-vias (TSVs).

[0097] Example 33. The method of example 32, wherein the at least one active device of the second of the at least two devices is part of a logic that is fabricated on a process technology node different from the process technology node for fabricating the die.

[0098] Example 34. The method of example 27, wherein the plurality of vias comprise through-silicon-vias (TSVs). [0099] Example 35. The method of example 27, wherein the substrate is an active interposer.

[00100] Example 36. An apparatus comprising: a plurality of layers providing interconnects; a first means coupled to at least one of the layers of the plurality; a second means coupled to at least another of layers of the plurality; and a plurality of means surrounding the first means such that the second means is outside the plurality of means.

[00101] Example 37. The apparatus of example 36, wherein the plurality of layers, first means, second means and plurality of means are positioned in an interposer.

[00102] Example 38. The apparatus of example 36, wherein the plurality of layers, first means, second means and plurality of means are positioned in a package substrate.

[00103] Example 39. The apparatus according to any of examples 36 to 38, wherein the first means is coupled to a first die.

[00104] Example 40. The apparatus according to any of examples 36 to 38, wherein the second means is coupled to a second die.

[00105] Example 41. The apparatus according to any of examples 36 to 38, wherein the first and second dies are fabricated on first and second process technology nodes.

[00106] Example 42. The apparatus of example 36, wherein the first and second dies are fabricated on a same process technology node.

[00107] Example 43. The apparatus of example 42, wherein the first circuitry is fabricated on a process technology node different than a processor technology node of the first die.

[00108] An abstract is provided that will allow the reader to ascertain the nature and gist of the technical disclosure. The abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.

Claims

CLAIMS We claim:

1. An apparatus comprising:

a substrate;

a die coupled to the substrate;

at least two active devices positioned in the substrate; and

a plurality of vias surrounding at least one of the two active devices such that a Faraday cage is formed around the at least one of the two active devices.

2. The apparatus of claim 1, wherein the at least one active device is part of a logic that is fabricated on a process technology node different from the process technology node for fabricating the die.

3. The apparatus of claim 1, wherein the substrate is an active interposer.

4. The apparatus according to any of claims 1 to 2, comprises an interposer coupled to the substrate.

5. The apparatus of claim 4 comprises a second of at least two active devices positioned in the interposer.

6. The apparatus of claim 5 comprises a second plurality of vias surrounding at least one of the second of the at least two active devices such that a Faraday cage is formed around the at least one of the second of the at least two active devices.

7. The apparatus of claim 6, wherein the second plurality of vias are through-silicon-vias (TSVs).

8. The apparatus of claim 6, wherein the at least one active device of the second of the at least two devices is part of a logic that is fabricated on a process technology node different from the process technology node for fabricating the die.

9. The apparatus of claim 1, wherein the plurality of vias comprise through-silicon-vias (TSVs).

10. An apparatus comprising:

a first die;

a second die stacked under the first die, wherein the second die comprises a first circuitry and a second circuitry; and

a plurality of vias in the second die surrounding the first circuitry such that the second circuitry is outside of the plurality of vias.

1 1. The apparatus of claim 10, wherein the second die is to function as an interposer of an integrated circuit (IC) package.

12. The apparatus according to any one of claims 10 to 11 , wherein the second die is

fabricated on a process technology node different from the process technology node for fabricating the first die.

13. The apparatus according to any one of claims 10 to 12, wherein the plurality of vias comprise through-silicon-vias (TSVs).

14. The apparatus of claim 10, wherein the first circuitry is predominantly a digital circuitry, and wherein the second circuitry is a communication circuitry.

15. The apparatus of claim 14, wherein the communication circuitry comprises an RF

integrated circuit (RFIC).

16. The apparatus according to any one of claims 10 to 15, wherein the first die comprises one of: a graphics processor, general purpose processor, an application specific integrated circuit, or a digital signal processor.

17. An apparatus comprising:

a plurality of layers providing interconnects;

a first circuitry coupled to at least one of the layers of the plurality;

a second circuitry coupled to at least another of layers of the plurality; and a plurality of vias surrounding the first circuitry such that the second circuitry is outside the plurality of vias.

18. The apparatus of claim 17, wherein the plurality of layers, first circuitry, second circuitry and plurality of vias are positioned in an interposer.

19. The apparatus of claim 17, wherein the plurality of layers, first circuitry, second circuitry and plurality of vias are positioned in a package substrate.

20. The apparatus according to any of claims 17 to 19, wherein the first circuitry is coupled to a first die.

21. The apparatus according to any of claims 17 to 19, wherein the second circuitry is

coupled to a second die.

22. The apparatus according to any of claims 17 to 19, wherein the first and second dies are fabricated on first and second process technology nodes.

23. The apparatus of claim 17, wherein the first and second dies are fabricated on a same process technology node.

24. The apparatus of claim 23, wherein the first circuitry is fabricated on a process

technology node different than a processor technology node of the first die.

25. A system comprising:

an integrated circuit (IC) package comprising:

an interposer coupled to a printed circuit board;

a substrate coupled to the interposer layer;

one or more dies coupled to the substrate, wherein the substrate comprises: at least two active devices, one of which is coupled to the one or more dies; and

a plurality of vias surrounding at least one of the two active devices such that a Faraday cage is formed around the at least one of the two active devices; and

a wireless interface to allow the one or more dies to communicate with another device.