WO2011052787A1 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
- Publication number
- WO2011052787A1 WO2011052787A1 PCT/JP2010/069528 JP2010069528W WO2011052787A1 WO 2011052787 A1 WO2011052787 A1 WO 2011052787A1 JP 2010069528 W JP2010069528 W JP 2010069528W WO 2011052787 A1 WO2011052787 A1 WO 2011052787A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- layer
- semiconductor layer
- broad buffer
- atoms
- semiconductor device
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 249
- 238000004519 manufacturing process Methods 0.000 title claims description 68
- 238000000034 method Methods 0.000 title claims description 36
- 239000012535 impurity Substances 0.000 claims abstract description 76
- 230000015556 catabolic process Effects 0.000 claims description 78
- 238000009826 distribution Methods 0.000 claims description 46
- 230000005684 electric field Effects 0.000 claims description 37
- 230000002829 reductive effect Effects 0.000 claims description 34
- 239000000758 substrate Substances 0.000 claims description 32
- 239000001301 oxygen Substances 0.000 claims description 26
- 229910052760 oxygen Inorganic materials 0.000 claims description 26
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 25
- 239000001257 hydrogen Substances 0.000 claims description 25
- 229910052739 hydrogen Inorganic materials 0.000 claims description 25
- 238000010438 heat treatment Methods 0.000 claims description 24
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 17
- 229910052710 silicon Inorganic materials 0.000 claims description 17
- 239000010703 silicon Substances 0.000 claims description 17
- 230000002441 reversible effect Effects 0.000 claims description 16
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 15
- 230000007423 decrease Effects 0.000 claims description 15
- 230000015572 biosynthetic process Effects 0.000 claims description 12
- -1 hydrogen ions Chemical class 0.000 claims description 12
- 239000012298 atmosphere Substances 0.000 claims description 5
- 230000001590 oxidative effect Effects 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 296
- 235000012431 wafers Nutrition 0.000 description 132
- 238000010586 diagram Methods 0.000 description 30
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 16
- 229910052698 phosphorus Inorganic materials 0.000 description 16
- 239000011574 phosphorus Substances 0.000 description 16
- 230000000694 effects Effects 0.000 description 15
- 230000007547 defect Effects 0.000 description 13
- 230000002093 peripheral effect Effects 0.000 description 10
- 230000001133 acceleration Effects 0.000 description 9
- 238000000227 grinding Methods 0.000 description 9
- 238000001039 wet etching Methods 0.000 description 8
- 230000008569 process Effects 0.000 description 7
- 238000011084 recovery Methods 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 230000008859 change Effects 0.000 description 6
- 239000013078 crystal Substances 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 6
- 230000001678 irradiating effect Effects 0.000 description 6
- 239000006096 absorbing agent Substances 0.000 description 5
- 230000004913 activation Effects 0.000 description 5
- 239000000969 carrier Substances 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 230000007935 neutral effect Effects 0.000 description 5
- 230000010355 oscillation Effects 0.000 description 5
- 230000001681 protective effect Effects 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 230000009467 reduction Effects 0.000 description 4
- 229910018125 Al-Si Inorganic materials 0.000 description 3
- 229910018520 Al—Si Inorganic materials 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 239000012299 nitrogen atmosphere Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000007613 environmental effect Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000005224 laser annealing Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000002994 raw material Substances 0.000 description 2
- 238000001004 secondary ion mass spectrometry Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910052720 vanadium Inorganic materials 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- HBBGRARXTFLTSG-UHFFFAOYSA-N Lithium ion Chemical compound [Li+] HBBGRARXTFLTSG-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- JJWKPURADFRFRB-UHFFFAOYSA-N carbonyl sulfide Chemical compound O=C=S JJWKPURADFRFRB-UHFFFAOYSA-N 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910001385 heavy metal Inorganic materials 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 230000009191 jumping Effects 0.000 description 1
- 229910001416 lithium ion Inorganic materials 0.000 description 1
- 238000000691 measurement method Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 231100000989 no adverse effect Toxicity 0.000 description 1
- 230000008520 organization Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000002244 precipitate Substances 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0804—Emitter regions of bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0821—Collector regions of bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1004—Base region of bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
- H01L29/32—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/868—PIN diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/88—Tunnel-effect diodes
- H01L29/885—Esaki diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
Definitions
- the present invention relates to a semiconductor device such as a diode or IGBT (insulated gate bipolar transistor) having not only high speed and low loss but also soft recovery characteristics, and a method for manufacturing the semiconductor device.
- a semiconductor device such as a diode or IGBT (insulated gate bipolar transistor) having not only high speed and low loss but also soft recovery characteristics, and a method for manufacturing the semiconductor device.
- IGBT insulated gate bipolar transistor
- power semiconductor devices are power converters such as converters and inverters that are highly efficient and power-saving, and are indispensable for controlling rotary motors and servo motors.
- Such a power control device is required to have characteristics such as low loss and power saving, high speed and high efficiency, and environmental friendliness, that is, no adverse effect on the surroundings.
- a diode having a broad buffer structure has been proposed as an improvement plan of the diode used in this device.
- the broad buffer structure is a broad buffer region including a region where the impurity concentration distribution of the n ⁇ drift layer has a peak (maximum value) near the middle of the same layer and decreases with an inclination toward the anode and cathode. It is the structure which has.
- the conventional emitter injection efficiency is lowered, and the soft recovery characteristic and the oscillation suppressing effect at a high speed operation (for example, carrier frequency: 5 kHz or more) which is difficult with the lifetime distribution control technology. Can be realized.
- FZ floating zone
- H + protons
- n ⁇ drift layer n-type doping element (phosphorus, arsenic) ion implantation method.
- Proton H + is allowed to reach to form lattice defects, and heat treatment is performed.
- a donor referred to as hydrogen-induced donor, hydrogen-related donor, or the like
- a complex lattice defect defect complex
- Patent Document 1 paragraphs 0020 and 0021
- Patent Document 2 summary
- Patent Document 3 paragraph 0011) below.
- a method of manufacturing an IGBT or a diode using an FZ wafer that is lower in cost than an epitaxial wafer is already common from an economical viewpoint.
- a method for forming phosphorus as an impurity in a wafer by irradiating a silicon wafer with neutron rays to transform silicon into phosphorus (P), which is a stable isotope is a wafer (hereinafter referred to as a neutron irradiated wafer). It is known that it is excellent from the viewpoint that the impurities can be uniformly distributed.
- the variation in specific resistance of the neutron-irradiated wafer is about ⁇ 8% for a 6-inch diameter wafer.
- the breakdown voltage V B (V) of the semiconductor device can be expressed by the following equation (1) in the case of a semiconductor device having a non-punch through structure.
- V B W 2 /(0.29 ⁇ 0 ) (1)
- W is the depletion layer width ( ⁇ m)
- ⁇ 0 is the specific resistance (bulk specific resistance) of the silicon wafer.
- the above formula (1) shows that, for example, in a non-punch through structure semiconductor device manufactured using a gas-doped FZ wafer, if the specific resistance ⁇ 0 varies by ⁇ 12%, the breakdown voltage V B also varies by 12%. Yes. Furthermore, not only the breakdown voltage but also the switching characteristics vary to the same extent. The variation of the switching characteristic by 12% or more is a problem level in assuring the operation of the device.
- One method of suppressing the variation in switching characteristics to 12% or less is to make the variation in specific resistance lower than ⁇ 12%. For that purpose, for example, it is effective to use a neutron-irradiated wafer whose specific resistance is controlled by neutron irradiation whose specific resistance variation is smaller than ⁇ 12% as described above.
- An object of the present invention is to provide a semiconductor device and a method of manufacturing a semiconductor device that can reduce variations in breakdown voltage and switching characteristics in order to eliminate the above-described problems caused by the prior art. It is another object of the present invention to provide a semiconductor device and a method for manufacturing the semiconductor device that can reduce manufacturing costs.
- a semiconductor device includes a first semiconductor layer provided on one main surface side of a first semiconductor layer of a first conductivity type.
- a first buffer type buffer region having a lower first conductivity type, and a total net doping concentration of the broad buffer region is 4.8 ⁇ 10 11 atoms / cm 2 or more and 1.0 ⁇ 10 12 atoms / cm 2 or less.
- the specific resistance of the first semiconductor layer [rho 0 [Omega] cm) is the rated voltage V 0 (V), and satisfies the 0.12V 0 ⁇ ⁇ 0 ⁇ 0.25V 0 .
- the total net doping concentration in the broad buffer region is 5.2 ⁇ 10 11 atoms / cm 2 or more and 1.0 ⁇ 10 12 atoms / cm 2 or less
- the specific resistance ⁇ of the first semiconductor layer is 0 with respect to the rated voltage V 0 (V), and satisfies the 0.133V 0 ⁇ ⁇ 0 ⁇ 0.25V 0 .
- a plurality of the broad buffer regions are provided inside the first semiconductor layer.
- the critical electric field strength is increased when a ratio ⁇ of the total width occupied by the plurality of broad buffer regions with respect to the width of the first semiconductor layer and a reverse voltage having the same value as the breakdown voltage are applied.
- the ratio ⁇ occupied by the total electric field intensity decrease in the plurality of broad buffer regions and the ratio ⁇ of the deviation of the measured value from the standard value of the donor concentration of the substrate serving as the first semiconductor layer are 4 ⁇ ( ⁇ / ⁇ ) / ⁇ (2- ⁇ ) (2 + ⁇ ) ⁇ ⁇ .
- the first semiconductor layer is made of an FZ silicon substrate.
- a semiconductor device is provided on the first main surface side of the drift layer of the first conductivity type and the drift layer.
- the base layer and the collector layer of the total amount of net doping concentrations of the broad buffer area 4.8 ⁇ 10 11 atoms / cm 2 to 1.0 ⁇ 10 12 atoms / cm 2 , and the specific resistance ⁇ 0 ( ⁇ cm) of the drift layer is 0.12 V 0 ⁇ ⁇ 0 ⁇ 0.25 V with respect to the rated voltage V 0 (V). It is characterized by satisfying 0 .
- the total net doping concentration of the broad buffer region is 5.2 ⁇ 10 11 atoms / cm 2 or more and 1.0 ⁇ 10 12 atoms / cm 2 or less
- the specific resistance ⁇ 0 [Omega] cm) is the rated voltage V 0 (V), and satisfies the 0.133V 0 ⁇ ⁇ 0 ⁇ 0.25V 0 .
- a plurality of the broad buffer regions are provided inside the drift layer.
- the ratio ⁇ of the total width occupied by the plurality of broad buffer regions with respect to the width of the drift layer and the critical electric field strength when a voltage having the same value as the breakdown voltage is applied is applied.
- the ratio ⁇ occupied by the total value of the reduced electric field strength in the plurality of broad buffer regions and the ratio ⁇ of the measured value deviation with respect to the standard value of the donor concentration of the substrate serving as the drift layer are 4 ⁇ ( ⁇ / ⁇ ) / ⁇ (2- ⁇ ) (2 + ⁇ ) ⁇ ⁇ is satisfied.
- a first conductivity type field stop layer in contact with the drift layer or the broad buffer region on the first main surface side of the substrate and in contact with the collector layer on the second main surface side is preferably provided. It is further provided with the feature.
- a first conductivity type field stop layer in contact with the drift layer or the broad buffer region on the first main surface side of the substrate and in contact with the collector layer on the second main surface side is preferably provided. Further prepare. At this time, the total net doping concentration of the drift layer, the broad buffer region, and the field stop layer is 1.2 ⁇ 10 12 atoms / cm 2 or more and 2.0 ⁇ 10 12 atoms / cm 2 or less. And
- the drift layer is made of an FZ silicon substrate.
- a semiconductor device manufacturing method has the following characteristics.
- the impurity concentration is higher than that of the first semiconductor layer, and the maximum value of the impurity concentration distribution is lower than the impurity concentrations of the second semiconductor layer and the third semiconductor layer.
- a first forming step of forming the second semiconductor layer on one main surface side of the first semiconductor layer is performed.
- hydrogen ions are irradiated from the second semiconductor layer side of the first semiconductor layer at a range distance reaching the first semiconductor layer, and heat treatment is performed at 300 ° C. to 550 ° C.
- a second forming step for forming the broad buffer region therein is performed.
- the broad buffer region having a total net doping concentration of 4.8 ⁇ 10 11 atoms / cm 2 or more and 1.0 ⁇ 10 12 atoms / cm 2 or less in the first semiconductor layer.
- the specific resistance [rho 0 of the first semiconductor layer is a rated voltage V 0 with respect to (V), satisfy 0.12V 0 ⁇ ⁇ 0 ⁇ 0.25V 0 .
- a heat treatment at 1000 ° C. or higher is performed in an oxidizing atmosphere to introduce oxygen into the first semiconductor layer.
- oxygen is introduced into the first semiconductor layer at a concentration of 1 ⁇ 10 16 atoms / cm 3 or more.
- a semiconductor device manufacturing method has the following characteristics.
- a first conductivity type broad buffer region having an impurity concentration higher than that of the first semiconductor layer and having a maximum impurity concentration distribution lower than that of the second semiconductor layer and the third semiconductor layer;
- the hydrogen has a range that reaches from the other main surface side of the first semiconductor layer to a location deeper than the location where the third semiconductor layer is formed in a later step of the first semiconductor layer.
- a second forming step of forming the broad buffer region in the first semiconductor layer is performed.
- the broad buffer region having a total net doping concentration of 4.8 ⁇ 10 11 atoms / cm 2 or more and 1.0 ⁇ 10 12 atoms / cm 2 or less in the first semiconductor layer.
- the specific resistance [rho 0 of the first semiconductor layer is a rated voltage V 0 with respect to (V), satisfy 0.12V 0 ⁇ ⁇ 0 ⁇ 0.25V 0 .
- a heat treatment at 1000 ° C. or higher is performed in an oxidizing atmosphere to introduce oxygen into the first semiconductor layer.
- oxygen is introduced into the first semiconductor layer at a concentration of 1 ⁇ 10 16 atoms / cm 3 or more.
- the broad buffer region is formed by forming a hydrogen-induced donor by irradiation with the hydrogen ions.
- the first semiconductor layer is made of an FZ silicon substrate.
- the specific resistance [rho 0 first semiconductor layer ([Omega] cm) is satisfying 0.12V 0 ⁇ ⁇ 0 ⁇ 0.25V 0 the rated voltage V 0 (V) (drift layer), broad A buffer area is provided.
- the total net doping concentration in the broad buffer region is 4.8 ⁇ 10 11 atoms / cm 2 or more and 1.0 ⁇ 10 12 atoms / cm 2 or less.
- the second semiconductor layer is formed from one main surface side or the other main surface side of the first semiconductor layer.
- the semiconductor layer or a third semiconductor layer (canode / collector layer) formed in a later step is irradiated with hydrogen ions at a distance that reaches a deeper position, and heat treatment is performed at 300 ° C. to 550 ° C.
- the broad buffer region having the above-described conditions can be formed inside the first semiconductor layer (drift layer).
- the specific resistance [rho 0 of the first semiconductor layer ([Omega] cm) above satisfies the rated voltage V 0 (V).
- the range in which the breakdown voltage of the semiconductor device changes according to the variation in specific resistance of the first semiconductor layer can be reduced.
- the range in which the switching characteristics of the semiconductor device change according to variations in the specific resistance of the first semiconductor layer can be reduced.
- the second formation step it is possible to suppress a decrease in the mobility of electrons and holes in the broad buffer region when the substrate is irradiated with hydrogen ions.
- a semiconductor device having a broad buffer structure can be manufactured at low cost using an FZ wafer.
- the present invention it is possible to reduce variations in breakdown voltage and switching characteristics. In addition, the manufacturing cost can be reduced.
- FIG. 1 is a diagram illustrating a configuration of a semiconductor device according to the first embodiment and a net doping concentration distribution.
- FIG. 2 is a diagram illustrating a manufacturing process of the semiconductor device according to the first embodiment.
- FIG. 3 is a diagram illustrating a manufacturing process of the semiconductor device according to the first embodiment.
- FIG. 4 is a characteristic diagram showing the relationship between the bulk specific resistance and the breakdown voltage of the semiconductor device.
- FIG. 5 is a characteristic diagram showing the relationship between the bulk specific resistance and the breakdown voltage variation width of the semiconductor device.
- FIG. 6 is a diagram showing a configuration of a conventional semiconductor device and a net doping concentration distribution.
- FIG. 7 is a diagram illustrating the configuration of the semiconductor device according to the second embodiment and the net doping concentration distribution.
- FIG. 1 is a diagram illustrating a configuration of a semiconductor device according to the first embodiment and a net doping concentration distribution.
- FIG. 2 is a diagram illustrating a manufacturing process of the semiconductor device according to the first embodiment.
- FIG. 8 is a diagram illustrating the configuration of the semiconductor device according to the third embodiment and the net doping concentration distribution.
- FIG. 9 is a diagram illustrating a manufacturing process of the semiconductor device according to the third embodiment.
- FIG. 10 is a diagram illustrating another example of the manufacturing process of the semiconductor device according to the third embodiment.
- FIG. 11 is a diagram illustrating another example of the manufacturing process of the semiconductor device according to the third embodiment.
- FIG. 12 is a diagram illustrating another example of the manufacturing process of the semiconductor device according to the third embodiment.
- FIG. 13 is a diagram illustrating the configuration of the semiconductor device according to the fourth embodiment and the net doping concentration distribution.
- FIG. 14 is a characteristic diagram showing the relationship between the net doping concentration distribution of the drift layer and the internal electric field strength distribution when a reverse voltage is applied.
- the present invention is not limited to the description of the examples described below unless it exceeds the gist.
- the one conductivity type is n-type and the other conductivity type is p-type, but the same effect can be obtained with the opposite polarity.
- FIG. 1 is a diagram illustrating a configuration of a semiconductor device according to the first embodiment and a net doping concentration distribution.
- the diode according to the first embodiment is formed on an n-type semiconductor substrate (wafer).
- the specific resistance of the bulk of the wafer is ⁇ 0 ( ⁇ cm).
- a p anode layer 2 is formed on one main surface side of the wafer.
- An n + cathode layer 3 is formed on the other main surface side of the wafer.
- the portion of the semiconductor substrate (first semiconductor layer) sandwiched between the p anode layer 2 (second semiconductor layer) and the n + cathode layer 3 (third semiconductor layer) is the n ⁇ drift layer 1.
- An anode electrode 4 is formed on the surface of the p anode layer 2.
- a cathode electrode 5 is formed on the surface of the n + cathode layer 3.
- n - net doping concentration of the drift layer 1 As shown in the characteristic diagram of the net doping concentration (log) (lower side), n - net doping concentration of the drift layer 1, n - substantially drift layer 1 A mountain-shaped, mound-like region having a concentration higher than that of the n ⁇ drift layer 1, which has a peak near the middle and decreases toward the p anode layer 2 and the n + cathode layer 3, is formed. Yes.
- This n-type mound-shaped area is called a broad buffer area 6.
- the maximum value of the impurity concentration distribution in the broad buffer region 6 is lower than the impurity concentrations of the n + cathode layer 3 and the p anode layer 2.
- the broad buffer region 6 is a region provided inside the n ⁇ drift layer 1 and having a net doping concentration higher than the bulk impurity concentration of the wafer and lower than the n + cathode layer 3 and the p anode layer 2. It is.
- the important point according to the present invention is that the bulk specific resistance ⁇ 0 ( ⁇ cm) of the semiconductor substrate (wafer) has the following (2) with respect to the rated voltage V 0 (V) of this diode. ) And the effective dose of the broad buffer region 6 (total amount of net doping concentration in the same layer) is 4.8 ⁇ 10 11 atoms / cm 2 or more and 1.0 ⁇ 10 12 atoms / cm 2 or less. It is two points of being in the range.
- FIGS. 2 and 3 are diagrams illustrating a manufacturing process of the semiconductor device according to the first embodiment.
- the broad buffer region 6 has proton H + 11 from the anode electrode side to the wafer provided with the p anode layer 2 and the anode electrode 4 on one main surface side of the wafer (FIGS. 2C and 3C). Reference)) and irradiation and heat treatment.
- FIGS. 2 and 3 are diagrams illustrating a manufacturing process of the semiconductor device according to the first embodiment.
- the broad buffer region 6 has proton H + 11 from the anode electrode side to the wafer provided with the p anode layer 2 and the anode electrode 4 on one main surface side of the wafer (FIGS. 2C and 3C). Reference)) and irradiation and heat treatment.
- an FZ wafer 10 having a specific resistance of 144 ⁇ cm to 300 ⁇ cm, for example, 150 ⁇ cm (phosphorus concentration 2.0 ⁇ 10 13 atoms / cm 3 ) and a thickness of about 500 ⁇ m is prepared.
- This FZ wafer 10 is used as a first semiconductor layer.
- the impurity concentration of the FZ wafer 10 itself is referred to as a bulk concentration, and the specific resistance thereof is referred to as a bulk specific resistance (FIG. 2A).
- the p anode layer 2 serving as the second semiconductor layer, the peripheral breakdown voltage structure including a guard ring (not shown), the insulating film 12, and the anode electrode 4 are formed.
- the impurity concentration of the p anode layer 2 is, for example, 5 ⁇ 10 16 atoms / cm 3 , and the junction depth is, for example, 3 ⁇ m from the surface.
- the material of the anode electrode 4 is, for example, an aluminum alloy such as aluminum silicon (AlSi) having a silicon concentration of about 1 wt% (hereinafter referred to as Al—Si (1%)) (FIG. 2B).
- proton H + 11 accelerated by a cyclotron is irradiated from the surface on the anode electrode 4 side.
- the acceleration voltage of the cyclotron is, for example, 7.9 MeV
- the dose amount of the proton H + 11 is, for example, 2.0 ⁇ 10 12 atoms / cm 2 .
- the range of the proton H + 11 is changed to the FZ wafer. 10 ⁇ m from the surface.
- FIG. 2C the crystal defect 13 generated in the FZ wafer by irradiation with proton H + 11 is indicated by a cross (FIG. 2C).
- n-type impurities such as phosphorus are ion-implanted into the surface (back surface) of the FZ wafer 10 on which grinding and wet etching 30 have been performed.
- the acceleration voltage at that time is, for example, 50 keV, and the dose amount is, for example, 1 ⁇ 10 15 atoms / cm 2 (impurity concentration; 1 ⁇ 10 19 atoms / cm 3 ) (FIG. 2F).
- the ion-implanted surface is irradiated with a laser beam such as a YAG second harmonic laser by, for example, a double pulse method.
- a laser beam such as a YAG second harmonic laser
- the double pulse method is a method of continuously irradiating a plurality of pulse lasers by shifting the irradiation timing by a predetermined delay time from a plurality of laser irradiation apparatuses for each laser light irradiation area.
- the double pulse method is described in detail in JP-A-2005-223301.
- the energy density when laser light is irradiated by the double pulse method is, for example, 3 J / cm 2 in total for each laser light irradiation area.
- the delay time of the double pulse is, for example, 300 nsec.
- a characteristic diagram (g-1) shown on the right side of FIG. 2 (g) is a net doping concentration profile corresponding to the cross-sectional view of the diode shown in (g).
- phosphorus glass is applied to the FZ wafer 10 in FIG. 2A, and phosphorus and oxygen are diffused and introduced from both sides of the wafer by drive-in at 1300 ° C. for 10 hours. Thereafter, the phosphorus diffusion layer on one main surface of the wafer is scraped off, and then mirror polishing is performed.
- oxygen is introduced only to the other main surface (for example, the back surface) of the wafer up to 1 ⁇ 10 18 atoms / cm 3 corresponding to the solid solubility at 1300 ° C., and the impurity concentration is higher than the concentration of the wafer.
- a phosphorous diffusion layer (surface layer concentration of 1 ⁇ 10 20 atoms / cm 3 , depth of about 80 ⁇ m) is formed.
- the above-described diode manufacturing process (the process after FIG. 2B) is performed using this wafer.
- the reason why it is preferable to add the above process is that, as disclosed in Patent Document 3 described above, the phosphorus diffusion layer formed on the back surface of the wafer and having a higher impurity concentration than the wafer concentration is an impurity such as heavy metal.
- the oxygen concentration between the anode layer surface and the peak of the net doping concentration in the broad buffer region (hereinafter referred to as the peak concentration) (that is, the range Rp distance of proton H + ) is increased. This is because the decrease in mobility of electrons and holes in the broad buffer region due to irradiation with proton H + 11 can be suppressed.
- a drive-in process at a high temperature of 1000 ° C. or higher in an atmosphere containing oxygen and a thermal oxidation process are performed. May be. This is because these heat treatments allow oxygen to enter and diffuse into the silicon substrate and increase the oxygen concentration in the wafer.
- Oxygen in this case is distributed at a concentration of 1 ⁇ 10 16 atoms / cm 3 or more and 1 ⁇ 10 17 atoms / cm 3 or less, and has a high impurity concentration that can be detected by SIMS (Secondary Ion Mass Spectrometry).
- the oxygen concentration can be increased to 1 ⁇ 10 18 atoms / cm 3 or higher by heat treatment at 1300 ° C. or higher. However, if this value is exceeded, oxygen precipitates and oxygen-induced defects may occur, and therefore 1 ⁇ 10 18 Atoms / cm 3 or less is desirable. That is, the oxygen concentration from the anode layer surface to the broad buffer region peak concentration (that is, the range Rp distance of proton H + ) is set to 1 ⁇ 10 16 atoms / cm 3 or more and 1 ⁇ 10 18 atoms / cm 3 or less. It is desirable.
- the composite defects including vacancies formed when hydrogen is introduced into the wafer by irradiating the wafer with proton H + are not only the active part where the main current of the semiconductor device flows, but also the donor due to the introduced oxygen.
- the n-type phosphorous diffusion layer having an impurity concentration higher than that of the wafer is also formed immediately below the peripheral breakdown voltage structure portion. As a result, the specific resistance of the wafer is increased and the impurity concentration immediately below the peripheral breakdown voltage structure is increased, so that the equipotential line density of the depletion layer that expands when the pn main junction is reversely biased is increased.
- H + hydrogen
- Li + lithium ions
- O ⁇ oxygen ions
- the mass is heavier than hydrogen ions, and a sufficiently wide range cannot be obtained with the same irradiation energy. Therefore, hydrogen ions (H + ) are most preferable when ion implantation needs to be performed to a depth of about 60 ⁇ m from the surface of the wafer.
- FIG. 4 is a characteristic diagram showing the relationship between the bulk specific resistance and the breakdown voltage of the semiconductor device.
- FIG. 6 is a diagram showing a configuration of a conventional semiconductor device and a net doping concentration distribution.
- FIG. 4 shows, in comparison with a diode having a broad buffer region 6 according to the present invention in the n ⁇ drift layer 1 (diode shown in the cross-sectional view of the main part of FIG. 1, hereinafter referred to as an example).
- the buffer region n - drift layer - a diode with the drift layer (first conventional example), n of the planar doping concentration distribution of the conventional without the broad buffer region (described as flat density distribution in FIG. 4) 1 (a diode shown in the cross-sectional view of the main part of FIG.
- the thickness of the n ⁇ drift layer 1 is 120 ⁇ m (hereinafter, as shown in FIG. Strictly speaking, the thickness of the n ⁇ drift layer 1 is 116.5 ⁇ m obtained by subtracting the thickness of the p anode layer 2 and the n + cathode layer 3 from 120 ⁇ m, but is expressed as 120 ⁇ m for convenience).
- the effective dose of the broad buffer region 6 is variously changed to 1.0 ⁇ 10 11 atoms / cm 2.
- change in breakdown voltage of the semiconductor device with respect to the specific resistance (horizontal axis) of the wafer (substrate) respectively Indicates.
- the effective dose amount of the broad buffer region 6 is 4.8 ⁇ 10 11 atoms / cm 2 or more.
- the conventional diode having the flat doping concentration distribution in the n ⁇ drift layer 1 (second conventional example)
- the thickness and specific resistance of the n ⁇ drift layer are selected in consideration of the balance between breakdown voltage, loss during conduction, and switching characteristics.
- the thickness of the n ⁇ drift layer is selected to be about 0.1 V 0 ( ⁇ m) with respect to the rated voltage V 0 (V).
- the rated voltage V 0 (V) and the typical specific resistance ⁇ 0 ( ⁇ cm) of the substrate are empirically expressed by the following equation (3).
- the setting may be set 1.5 times higher than these.
- the value may be lowered to 80% of the above value.
- the specific resistance of the substrate with an actual breakdown voltage of 1400 V is 46 ⁇ cm.
- the effective dose amount of the broad buffer region is 1 ⁇ 10 11 atoms / cm 2 , 2.5 ⁇ 10 11 atoms / cm 2 , 4 ⁇ 10 11 atoms / cm 2 , 4.8 ⁇ 10 11 atoms.
- the specific resistance at which the actual withstand voltage is 1400 V is 55 ⁇ cm, 68 ⁇ cm, 100 ⁇ cm, 144 ⁇ cm, 150 ⁇ cm, 160 ⁇ cm, 200 ⁇ cm, and 250 ⁇ cm, respectively.
- the range of variation in breakdown voltage of the semiconductor device strongly reflects the range of variation in specific resistance (hereinafter referred to as specific resistance variation range) according to the specific resistance of the wafer.
- specific resistance variation width when the specific resistance of the wafer varies with a certain width (hereinafter referred to as specific resistance variation width), the specific resistance variation width is directly linked to the breakdown voltage variation width (hereinafter referred to as breakdown voltage variation width) of the semiconductor device.
- the specific resistance at a withstand voltage of 1400 V is 46 ⁇ cm. In the range of about 30 ⁇ cm to 80 ⁇ cm before and after the specific resistance value of 46 ⁇ cm, the withstand voltage value changes greatly.
- the breakdown voltage variation range the range of variation in breakdown voltage corresponding to this specific resistance variation range (hereinafter referred to as the breakdown voltage variation range) is about 1290V to 1480V. That is, this breakdown voltage variation range corresponds to a breakdown voltage variation width of about 13.7% with respect to the center value 1385V.
- the withstand voltage variation width is required to be a smaller value required by the market, for example, 5% or less. For this reason, in order to satisfy the withstand voltage variation width required by the market, the specific resistance variation width must be further reduced.
- the specific resistance variation width of the current high specific resistance (for example, 20 ⁇ cm or more) FZ wafer is ⁇ 12% or less for gas dope (variation width is 24%) or less, and ⁇ 8% (variation for neutron irradiation wafer) as described above.
- the width of 16% or less is the guaranteed range of the wafer manufacturer, and even a neutron irradiated wafer far exceeds the tolerance of the breakdown voltage variation width.
- the withstand voltage variation range corresponding to the specific resistance variation ⁇ 12% is 1340V to 1430V, and the withstand voltage variation width is about 6.5%, so that it still cannot satisfy the withstand voltage variation width of 5% or less required by the market. .
- To 1400 V has a specific resistance of 144 ⁇ cm.
- the specific resistance varies by 12%
- the specific resistance variation range is 126.7 ⁇ cm to 161.3 ⁇ cm.
- the corresponding withstand voltage variation range is 1363V to 1425V. That is, the withstand voltage variation width is 4.4% with respect to the center value 1394V.
- the withstand voltage variation ranges corresponding to these specific resistance variation ranges are 1371 V to 1431 V, 1378 V to 1422 V, and 1380 V to 1415 V, respectively. That is, the withstand voltage variation width is 4.3% for the center value 1401V, 3.1% for the center value 1400V, and 2.5% for the center value 1397V, respectively. Therefore, the withstand voltage variation width is reduced to a little over 2% to a little over 4%. For this reason, in any of the examples, it can be seen that the breakdown voltage variation width required by the market is 5% or less.
- FIG. 5 is a characteristic diagram showing the relationship between the bulk specific resistance and the breakdown voltage variation width of the semiconductor device.
- the relationship between the bulk specific resistance shown in FIG. 4 and the breakdown voltage variation width (%) of the semiconductor device is summarized in FIG. That is, as described with reference to FIG. 4, the effective dose amount of the broad buffer region is selected so that the actual breakdown voltage is 1400 V with respect to a certain bulk specific resistance value, and the respective bulk specific resistance varies by 12%.
- the breakdown voltage variation width (%) obtained from the breakdown voltage variation range is plotted on the vertical axis (the horizontal axis is the bulk specific resistance ( ⁇ cm)).
- the withstand voltage variation width is as large as 13.7%, which does not satisfy the withstand voltage variation width required by the market.
- the drift layer has a broad buffer region (first conventional example)
- the bulk specific resistance is as small as 55 ⁇ cm, 68 ⁇ cm, and 100 ⁇ cm
- the withstand voltage variation widths are about 11.5% and about 10.1 respectively. %, Approximately 6.5%, which is larger than 5.0% and does not satisfy the withstand voltage variation width required by the market, and is not included in the present invention.
- the drift layer has a broad buffer region, if the effective dose is too high, for example, if it exceeds 1.0 ⁇ 10 12 atoms / cm 2 , the bulk resistivity reaching 1400 V will exceed 300 ⁇ cm. Therefore, it is not included in the present invention. The reason will be described later.
- the withstand voltage variation width is 4.4% at the bulk specific resistance of 144 ⁇ cm, 4.3% at the 150 ⁇ cm, and 4 at the 160 ⁇ cm. It can be seen that the breakdown voltage variation width of the semiconductor device can be reduced to 5.0% or less, which is required by the market, as 3.1% at 0.0% and 200 ⁇ cm and 2.5% at 250 ⁇ cm.
- the effective dose amount of the broad buffer region according to the present invention is 4.8 ⁇ 10 11 atoms / cm 2 or more and 6.0 ⁇ 10 11 atoms / cm 2 or less. Furthermore, even when the effective dose of the broad buffer region was increased to 1.0 ⁇ 10 12 atoms / cm 2 , it was confirmed that the withstand voltage variation width was further reduced and the bulk specific resistance was 300 ⁇ cm or less.
- the semiconductor device according to the present invention has a broad buffer structure with an effective dose amount of 4.8 ⁇ 10 11 atoms / cm 2 or more and 1.0 ⁇ 10 12 atoms / cm 2 or less, so that the withstand voltage variation width is broad. It can be seen that the current can be reduced to 1/3 or less as compared with a conventional diode having no buffer region. More preferably, the effective dose amount is 5.0 ⁇ 10 11 atoms / cm 2 or more and 1.0 ⁇ 10 12 atoms / cm 2 or less, and further preferably 5.2 ⁇ 10 11 atoms / cm 2 or more and 1.0 ⁇ 10 10.
- the withstand voltage variation width of the semiconductor device can be surely reduced to 4% or less.
- the withstand voltage variation width of the semiconductor device does not depend on the bulk specific resistance.
- the withstand voltage variation width naturally includes variations in parameters such as the thickness of the n ⁇ drift layer or the effective dose amount due to the formation of the broad buffer region.
- the thickness variation of the drift layer can be reduced to 3% or less by the combination of wafer back grinding and etching, and the effective dose control can be reduced to 1% or less by proton H + implantation and annealing temperature control.
- the largest factor is the specific resistance variation width, and it can be seen that the effect of reducing the withstand voltage variation width is great.
- the breakdown voltage variation width is 5% or less as required by the market is the bulk specific resistance of 144 ⁇ cm or more, and this value 144 is about 12% of the rated voltage value 1200. ( ⁇ 144 / 1200 ⁇ 100%). Further, as shown in FIG.
- the bulk specific resistance according to the semiconductor device of the present invention that is, the specific resistance ⁇ 0 of the semiconductor substrate is required to satisfy the following formula (4).
- the withstand voltage variation width can be more reliably set to 5% or less.
- the broad buffer region is formed in a part of the n ⁇ drift layer and is in contact with a portion having a net doping concentration of the substrate concentration (bulk impurity concentration) or lower. .
- the breakdown voltage can be determined independently of the bulk concentration, and as a result, the breakdown voltage variation width can be reduced. If the broad buffer region has a structure distributed over the entire n ⁇ drift layer, the impurity concentration control and breakdown voltage depend only on the ion implantation and drive.
- the main rated voltage V 0 can be determined based on the bulk resistivity ⁇ 0 .
- the actual breakdown voltage is determined by adding the impurity concentration of the hydrogen-induced donor to the bulk net doping concentration (that is, the specific resistance). Therefore, the present invention can be applied regardless of the withstand voltage of the semiconductor device, and can reduce the influence of the specific resistance variation width on the withstand voltage variation width with an effective dose of a hydrogen-related donor with a relatively small error. . This makes it possible to manufacture a diode having a small withstand voltage variation width very easily.
- FIG. 2 (c) the was irradiated with protons H + 11 from the surface side (the anode electrode side), as shown in FIG. 3 (c), the proton H + 11 backside (cathode electrode side ).
- Other steps of the manufacturing method shown in FIG. 3 are the same as those of the manufacturing method shown in FIG. That is, the difference between FIG. 2 and FIG. 3 is the step (c).
- the bulk resistivity ⁇ 0 ( ⁇ cm) is an n ⁇ made of a substrate that satisfies the above expression (2) with respect to the rated voltage V 0 (V).
- a broad buffer region 6 is provided in the drift layer 1. The total net doping concentration of the broad buffer region 6 is within the above range. As a result, even if the variation in bulk specific resistance is about ⁇ 12%, the range in which the withstand voltage of the diode changes according to the variation in bulk specific resistance can be reduced. In addition, the range in which the switching characteristics of the semiconductor device change according to the variation in bulk resistivity can be reduced. Therefore, variations in breakdown voltage and switching characteristics can be reduced.
- the front of the FZ wafer 10 is formed.
- Proton H + 11 is irradiated from the surface or the back surface with a range distance reaching the p anode layer 2 or a deeper position than the n + cathode layer 3 formed in a later step, and heat treatment is performed at 300 ° C. or higher and 550 ° C. or lower.
- the broad buffer region 6 having the above-described conditions can be formed inside the n ⁇ drift layer 1.
- the specific resistance (bulk specific resistance) ⁇ 0 of the FZ wafer 10 satisfies the above condition with respect to the rated voltage V 0 .
- the range in which the breakdown voltage of the semiconductor device changes according to the variation in specific resistance of the FZ wafer 10 can be reduced.
- the range in which the switching characteristics of the semiconductor device change according to variations in the specific resistance of the FZ wafer 10 can be reduced. Therefore, variations in breakdown voltage and switching characteristics can be reduced.
- oxygen is introduced into the FZ wafer 10 under the above conditions before irradiation with proton H + 11 for forming the broad buffer region 6.
- oxygen is introduced into the FZ wafer 10 under the above conditions before irradiation with proton H + 11 for forming the broad buffer region 6.
- a broad buffer structure diode can be manufactured at low cost using the FZ wafer 10. Thereby, manufacturing cost can be reduced.
- FIG. 7 is a diagram illustrating the configuration of the semiconductor device according to the second embodiment and the net doping concentration distribution.
- a plurality of broad buffer regions 6 in the first embodiment may be provided in n ⁇ drift layer 1.
- a plurality of broad buffer regions 6 are formed.
- a broad buffer region having a higher impurity concentration is more easily formed according to the number of the broad buffer regions than when one broad buffer region is formed. The decrease in the electric field strength in the space charge region is more likely to be larger than in the case of one.
- the breakdown voltage of the semiconductor device may be lowered, so that the bulk specific resistance is preferably further increased, and as a guideline, it is more preferably 0.15 V 0 or more. It is the same that the upper limit is 0.25V 0 described above. Other configurations are the same as those in the first embodiment.
- FIG. 14 is a characteristic diagram showing the relationship between the net doping concentration distribution of the drift layer and the internal electric field strength distribution when a reverse voltage is applied.
- a conventional diode having a drift layer with a flat concentration distribution and a diode of the present invention having a plurality of broad buffer regions in the drift layer the net doping concentration distribution of the drift layer and the internal electric field when a reverse voltage is applied It is the figure which matched intensity distribution.
- FIGS. 14C and 14D show the case where the diode of the present invention having a plurality of broad buffer regions is applied with a reverse voltage having the same value as the withstand voltage, and the maximum value of the electric field strength is the critical electric field strength E C. It is an electric field strength distribution diagram ((c)) and a donor concentration distribution ((d)).
- the standard value of the donor concentration of the FZ bulk wafer is N 0, and the measured value of the donor concentration of the actual FZ bulk wafer is (1 + ⁇ ) N 0 (or (1- ⁇ ) N 0 , ⁇ > 0).
- the standard deviation of the measured value of the donor concentration of the FZ bulk wafer in the number of processed FZ bulk wafers (for example, 50) as a unit that flows simultaneously is (1 + ⁇ ) N 0 (or (1- ⁇ ) N 0 , ⁇ > 0).
- the variation rate of the donor concentration is ⁇ ⁇ ( ⁇ > 0).
- q is the elementary charge
- ⁇ 0 is the dielectric constant of vacuum
- ⁇ Si is the relative dielectric constant of silicon.
- ⁇ is 0 or more and 1 or less.
- the voltage value variation width ⁇ / ⁇ 0 becomes smaller.
- the ratio ⁇ of the “loss” of the electric field strength increases as the bulk concentration N 0 of the broad buffer region increases (that is, ⁇ increases) or as the number n of broad buffer regions increases.
- the width W 0 of the broad buffer area ⁇ increases as the value is increased. Therefore, theoretically, as the number of broad buffer regions having a higher concentration and a wider width are formed, the variation ratio ⁇ / ⁇ 0 of the voltage (withstand voltage) becomes smaller.
- the variation rate ⁇ of N 0 is 12%
- the number n of broad buffer regions formed is three
- the multiple ⁇ of the concentration of the broad buffer region with respect to N 0 is 10.
- the variation ratio ⁇ / ⁇ 0 of the breakdown voltage is 0.047 (4.7%), which can be sufficiently smaller than ⁇ , and It can also meet the 5% breakdown voltage variation required by the market.
- the variation ratio ⁇ / ⁇ 0 of the withstand voltage value can be made smaller than the variation ratio of the FZ bulk wafer. It is preferable because it is possible.
- the variation ratio ⁇ / ⁇ 0 of the withstand voltage value is It is still preferable because it can be surely made smaller than the variation ratio of the FZ bulk wafer.
- each broad buffer region becomes close to a Gaussian distribution by proton irradiation.
- the full width at half maximum indicating the extent of the Gaussian distribution corresponds to the above W 0 and depends on the acceleration energy of protons.
- the above consideration is considered to be, for example, that the value obtained by integrating the donor concentration over a certain broad buffer region is averaged by the half width.
- the “reduction” ⁇ E of the electric field strength is determined by the total amount (effective dose amount) of the integral value in the broad buffer region, and thus does not greatly depend on the difference in individual shapes (rectangular or Gaussian distribution). Therefore, the selection of ⁇ , W 0 , and n actually determines the total amount of integrated density in each broad buffer region. Further, the above-described equation (6) is established regardless of the rated voltage. The reason for this is that the critical electric field strength E c is less dependent on the bulk wafer concentration determined according to the rated voltage, and may be considered to be a constant value. This is because it depends on the integrated value (total amount or effective dose amount) of these concentrations, not the concentration of individual broad buffer regions or the concentration of bulk wafers.
- the effective dose of the broad buffer region 6 is 4.8 ⁇ 10 11 atoms / cm 2 or more and 1.0 ⁇ 10 12 atoms / cm 2 or less as the sum of the plurality of doses as shown in the first embodiment. If it is.
- the integrated concentration is 4 ⁇ 10 11 atoms / sequentially from the side closer to the anode electrode 4.
- the number of broad buffer regions 6 is preferably 2 or more and about 5 at maximum so as to satisfy the effective dose.
- the total thickness of the drift region is 300 ⁇ m or more, and the thickness has a sufficient margin. Therefore, if necessary, five or more broad buffer regions may be formed. Further, as described above, the variation ratio of the withstand voltage does not change so much even if the shape or position of each broad buffer region is changed as long as the total amount of integrated concentration in the broad buffer region is constant.
- the depth of the broad buffer region closest to the anode electrode from the anode electrode is made deeper than W d / 2, thereby securing a low impurity concentration (high resistance) region of the drift layer in the vicinity of the pn junction.
- the number of broad buffer regions on the side close to the cathode electrode side from the position just in the middle of the drift layer is larger than the number of broad buffer regions on the side close to the anode electrode from the intermediate position (including zero).
- protons may be irradiated from the front surface or from the back surface in order to form each broad buffer region 6.
- at least the broad buffer region 6 closest to the anode layer is irradiated from the surface of the anode layer 2 so that the carrier lifetime values of the proton passage region and the stop region are lower than the bulk. desirable.
- the same effect as in the first embodiment can be obtained.
- the same effect as in the first embodiment can be obtained.
- FIG. 8 is a diagram illustrating the configuration of the semiconductor device according to the third embodiment and the net doping concentration distribution.
- the configuration of the semiconductor device according to the first and second embodiments may be applied to the IGBT.
- the IGBT according to the third embodiment has a p-base on the front surface (first main surface) side of the n-type semiconductor substrate (wafer).
- Layer 22 is formed.
- a p collector layer 28 is formed on the back surface (second main surface) side of the wafer.
- the portion of the semiconductor substrate between the p base layer 22 and the p collector layer 28 becomes the n ⁇ drift layer 21.
- Bulk specific resistance ⁇ 0 ( ⁇ cm) is the same as that in the first embodiment. That is, the bulk specific resistance is in the above formula (2) or the more preferable range.
- An emitter electrode 24 is formed on the surface of the p base layer 22.
- a collector electrode 25 is formed on the surface of the p collector layer 28.
- a trench that penetrates the p base layer 22 and reaches the n ⁇ drift layer 21 is formed on the front surface side of the wafer, and a gate insulating film 31 is formed on the inner wall thereof.
- a gate electrode 27 is embedded in the trench through the gate insulating film 31.
- An n emitter layer 29 is formed in the p base layer 22.
- the emitter electrode 24 electrically connects the p base layer 22 and the n emitter layer 29.
- the emitter electrode 24 is insulated from the gate electrode 27 by an interlayer insulating film 32 formed on the gate insulating film 31 and the gate electrode 27.
- n - the net doping concentration of the drift layer 21, n - substantially drift layer 21 It has a peak near the middle and decreases toward the p base layer 22 and the p collector layer 28 with an inclination. That, n - in the interior of the drift layer 21, n - higher than the impurity concentration of the drift layer 21, and the p base layer 22 and the lower n-type broad buffer region 26 of the net doping concentration than the p-type collector layer 28 is formed Has been.
- the effective dose amount of the broad buffer region 26 (total amount of net doping concentration in the same layer) is 4.8 ⁇ 10 11 atoms / cm 2 or more and 1.0 ⁇ 10 12 atoms / cm 2 or less, or in the more preferable range described above.
- the broad buffer region 26 can be formed by irradiating the wafer provided with the p base layer 22 and the emitter electrode 24 with proton H + 11 from the collector electrode 25 side and heat treatment.
- FIG. 8 shows a trench gate structure IGBT, a planar gate structure IGBT may be used.
- the p collector layer 28 is formed on the back surface side, minority carriers are injected from the back surface side. Therefore, at the time of turn-off, it is necessary to stop the injected minority carriers from reaching the space charge region through the charge neutral region.
- the charge neutral region that is not depleted is, for example, about 5 to 20 ⁇ m from the back side when a voltage corresponding to the withstand voltage is applied. . Therefore, by providing the peak of the net doping concentration distribution of the broad buffer region 26 on the collector electrode 25 side from the depth of the center of the n ⁇ drift layer 21, the depletion layer is reliably stopped, and the charge neutral region described above is formed. It is desirable to ensure.
- FIG. 9 is a diagram illustrating a manufacturing process of the semiconductor device according to the third embodiment.
- 10 to 12 are diagrams showing another example of the manufacturing process of the semiconductor device according to the third embodiment.
- an FZ wafer 10 having a bulk specific resistance of 144 ⁇ cm to 300 ⁇ cm, for example, 150 ⁇ cm (phosphorus concentration 2.0 ⁇ 10 13 atoms / cm 3 ) and a thickness of about 500 ⁇ m is prepared as a wafer (semiconductor substrate).
- This FZ wafer 10 is used as a first semiconductor layer (FIG. 9A).
- the FZ wafer 10 may be introduced in advance by diffusing oxygen having a concentration higher than the solid solubility of about room temperature (for example, 20 ° C.) by drive-in.
- a p base layer 22 a peripheral breakdown voltage structure including a guard ring (not shown), a trench, a gate insulating film 31 in the trench, and a gate electrode are formed on one main surface side of the FZ wafer 10.
- n emitter layer 29, and interlayer insulating film 32 are formed (FIG. 9B).
- the impurity concentration of the p base layer 22 is, for example, 2 ⁇ 10 17 atoms / cm 3 , and the junction depth is, for example, 3 ⁇ m from the surface.
- the impurity concentration of the n emitter layer 29 is 1 ⁇ 10 20 atoms / cm 3 , and the junction depth is, for example, 0.5 ⁇ m from the surface.
- the material of the gate electrode 27 may be polysilicon, for example.
- the proton H + 11 accelerated by the cyclotron is irradiated from the surface of the other main surface side (the side on which the collector electrode 25 will be formed later) of the FZ wafer 10 (FIG. 9C).
- the acceleration voltage of the cyclotron is, for example, 7.9 MeV
- the dose amount of the proton H + 11 is 1.0 ⁇ 10 14 atoms / cm 2 .
- an aluminum absorber is used and the thickness thereof is adjusted so as to be 90 ⁇ m from the silicon substrate surface.
- the thickness of the FZ wafer 10 is 500 ⁇ m, for example, the range of the proton H + 11 is adjusted to 410 ⁇ m.
- This range may be adjusted with an acceleration voltage using an electrostatic accelerator, and the acceleration voltage in this case is 7.5 MeV.
- the crystal defect 13 generated in the FZ wafer 10 by irradiation with proton H + 11 is indicated by a cross.
- n-type high concentration regions are formed around the depth of 30 ⁇ m from the back surface of the wafer.
- a desired broad buffer region 26 is formed by this high concentration region (FIG. 9D).
- the emitter electrode 24 in contact with the n emitter layer 29 is formed. Further, a protective film (not shown) is formed on the peripheral pressure-resistant structure including the guard ring (FIG. 9E).
- the emitter electrode 24 is, for example, Al—Si (1%), and the protective film is, for example, a polyimide or silicon nitride (SiN) film.
- the FZ wafer 10 is irradiated with an n-type impurity such as proton H + or phosphorus + 15 which becomes the n field stop layer 23 from the FZ wafer surface (back surface) on which the above-described grinding and wet etching 30 are performed.
- the impurity concentration after activation (described later) is set to a dose amount of 2 ⁇ 10 16 atoms / cm 3 , for example (FIG. 9G).
- ions of a p-type impurity such as boron + 14 to be the p collector layer 28 are implanted (FIG. 9H).
- the acceleration voltage at that time is, for example, 50 keV, and the dose is such that the impurity concentration after activation is 3 ⁇ 10 17 atoms / cm 3 .
- the effective dose amount of the n field stop layer 23 is set to a range that satisfies the effective dose amount condition including the broad buffer region 26.
- the p collector layer 28 is formed by performing electrical activation by laser annealing on the ion implantation surface.
- the activation may be furnace annealing instead of laser annealing.
- furnace annealing for example, heat treatment is performed at 450 ° C. for 5 hours in a nitrogen atmosphere (which may contain hydrogen) and activation is performed.
- a metal film is formed on the surface of the p collector layer 28 in the order of, for example, Al—Si (1%), titanium, nickel, and gold, and the collector electrode 25 is formed in ohmic contact with the surface of the p collector layer 28 Then, the IGBT is completed (FIG. 9 (i)).
- a modified example (hereinafter referred to as manufacturing method 2) of the IGBT manufacturing method (hereinafter referred to as manufacturing method 1) shown in FIG. 9 will be described with reference to FIGS. 10 (a) to 10 (h).
- the difference from the manufacturing method 1 shown in FIG. 9 is that irradiation with proton H + 11 (see FIG. 9C) forms an emitter electrode 24 and a protective film, and grinding and wet etching of the back surface of the FZ wafer 10. It is a point to be implemented after 30.
- Method 2 shown in FIG. 10 is effective when the heat resistance temperature of the emitter electrode 24 and the protective film of the peripheral breakdown voltage structure is higher than the heat treatment temperature after irradiation with proton H + .
- the preparation from the preparation of the FZ wafer 10 to the formation of the MOS gate and the peripheral breakdown voltage structure portion which are the element surface structures are the same as (a) and (b) of FIG.
- a protective film (not shown) such as an emitter electrode 24 and polyimide is formed (FIG. 10B).
- grinding of the back surface of the FZ wafer 10 and wet etching 30 are performed to make the FZ wafer 10 have a required thickness (FIG. 10C).
- proton H + 11 is irradiated from the back side of the wafer (FIG. 10D), and heat treatment is performed (FIG. 10E).
- the range of proton H + 11 is adjusted within the range of the acceleration voltage upper limit value by the irradiation accelerator.
- the irradiation accelerator when the range from the back surface is 30 ⁇ m, the acceleration energy is 1.5 MeV.
- the range may be adjusted by the above-described aluminum absorber using a cyclotron accelerator.
- the processes after FIG. 10F are the same as those after FIG. 9G of manufacturing method 1.
- the IGBT is formed as in manufacturing method 2 above, the number of steps after thinning the FZ wafer 10 can be reduced, and defects such as wafer cracking due to handling of the thin wafer can be reduced.
- FIGS. 9 differs from the first manufacturing method shown in FIG. 9 in that the back surface grinding and wet etching 30 in FIG. 9 (FIG. 9F) and the step of forming the emitter electrode 24 (FIG. 9E) are interchanged. (Refer to FIG. 11 (e) and FIG. 11 (f), respectively). Other steps are the same as those in the manufacturing method 1 shown in FIG.
- the heat treatment temperature after irradiation with proton H + 11 is higher than the heat-resistant temperature of the emitter electrode 24, it is preferable to manufacture the IGBT according to the third embodiment using the manufacturing method No. 3 shown in FIG.
- FIG. 10 A modified example of the manufacturing method 2 shown in FIG. 10 (hereinafter referred to as manufacturing method 4) will be described with reference to FIGS.
- the difference from the manufacturing method 2 shown in FIG. 10 is that an n-field stop layer introduction step (introduction of phosphorus or proton H + into the wafer) adjacent to the p collector layer 28 shown in FIG.
- the depletion layer is stopped at the broad buffer region 26 to produce an IGBT having a configuration that does not reach the p collector layer.
- the hole injection efficiency can be achieved only by adjusting the concentration and introduction depth of the p collector layer 28 on the back surface of the wafer.
- the other steps are the same as in manufacturing method 2 shown in FIG.
- the trench gate structure IGBT has been described.
- the present invention may be applied to a planar gate structure IGBT.
- the same effect as in the first embodiment can be obtained also in the IGBT.
- FIG. 13 is a diagram illustrating the configuration of the semiconductor device according to the fourth embodiment and the net doping concentration distribution.
- a plurality of broad buffer regions 26 in the third embodiment may be provided in n ⁇ drift layer 21.
- a plurality of broad buffer regions 26 are formed.
- a broad buffer region having a higher impurity concentration is more easily formed according to the number than when one broad buffer region is formed. The decrease in the electric field strength in the space charge region is likely to be larger than in the case of one.
- the breakdown voltage of the semiconductor device may be lowered, so that the bulk specific resistance is preferably further increased, and as a guideline, it is more preferably 0.15 V 0 or more. It is the same that the upper limit is 0.25V 0 described above. Other configurations are the same as those in the third embodiment.
- the effective dose amount of the broad buffer region 26 is such that the sum of the plurality is 4.8 ⁇ 10 11 atoms / cm 2 or more and 1.0 ⁇ 10 12 atoms / cm 2 or less as shown in the first embodiment. Good.
- the peak concentration is 4 ⁇ 10 14 atoms / sequentially from the side closer to the emitter electrode 24.
- the half width is 10 ⁇ m at cm 3
- the peak concentration is 1.5 ⁇ 10 15 atoms / cm 3
- the half width is 5 ⁇ m
- the peak concentration is 3.5 ⁇ 10 15 atoms / cm 3
- the half width is 3 ⁇ m.
- the integrated concentrations of the respective broad buffer regions 26 are 2 ⁇ 10 11 atoms / cm 2 , 3 ⁇ 10 11 atoms / cm 2 , and 4 ⁇ 10 11 atoms / cm 2 in order from the side closer to the emitter electrode 24, for a total of 8 ⁇ 10 11 atoms / cm 2
- the effective dose of the n-type layer is set so that the n field stop layer 23 becomes approximately 1.0 ⁇ 10 12 atoms / cm 2.
- the total of (integrated concentration) is 1.8 ⁇ 10 12 atoms / cm 2 .
- the snap-back phenomenon occurs in the IV output waveform when the gate is on (conductivity modulation occurs after the voltage drop between the collector and emitter electrodes has greatly increased without any conductivity modulation due to a small current. Therefore, it is necessary to design so as not to cause a negative resistance phenomenon in which the voltage drop suddenly decreases and current flows. Therefore, the total integrated concentration of the three n-type layers should not exceed 2.0 ⁇ 10 12 atoms / cm 2 . On the other hand, the depletion layer in the off state must not reach the p collector layer 28. Therefore, the total integrated concentration of the three n-type layers must be larger than 1.2 ⁇ 10 12 atoms / cm 2 .
- the total integrated concentration of the three n-type layers may be 1.2 ⁇ 10 12 atoms / cm 2 or more and 2.0 ⁇ 10 12 atoms / cm 2 or less.
- the n field stop layer 23 in contact with the p collector layer 28 may satisfy the range of the integrated concentration.
- the n field stop layer 23 may be formed by introducing phosphorus, or the n field stop layer 23 may be formed by introducing proton H + .
- the operational effects achieved by providing a plurality of broad buffer regions are basically the same as the operational effects of the diode shown in the second embodiment. That is, in forming a plurality of broad buffer regions, the proportion of the donor concentration variation of the FZ bulk wafer is ⁇ ⁇ ( ⁇ > 0), the proportion of the total length of the bulk portion that is not the broad buffer region is ⁇ , and the critical electric field strength The condition of 4 ⁇ ( ⁇ / ⁇ ) / ⁇ (2- ⁇ ) (2 + ⁇ ) ⁇ ⁇ , where ⁇ is the ratio of electric field intensity ⁇ E reduced by n times in the broad buffer region to E C It is preferable to form so as to satisfy.
- the p collector layer 28 is formed on the back surface side in the IGBT, minority carriers are injected from the back surface side, so that the charge neutral region that is not depleted is formed from the back surface side. It is desirable to secure 5 to 20 ⁇ m. Therefore, by providing the peak of the net doping concentration distribution of the broad buffer region 26 on the collector electrode 25 side from the depth of the center of the n ⁇ drift layer 21, the depletion layer is reliably stopped and the above neutral region is secured. It is desirable to do. That is, if a plurality of broad buffer regions 26 are formed more in the region closer to the collector electrode than in the middle of the drift layer, the “reduction” ⁇ E (see FIG.
- the number of broad buffer regions on the side close to the collector electrode side from the position just in the middle of the drift layer is equal to the number of broad buffer regions on the side close to the emitter electrode from the intermediate position (including zero). More than that.
- the fourth embodiment when a plurality of broad buffer regions 26 are formed, it is preferable to irradiate proton H + from the back surface side (the side where the p collector layer 28 is formed) of the FZ wafer 10.
- the reason for this is that when irradiated from the surface of the wafer, crystal defects are formed at the interface between the gate oxide film and silicon, which may affect the gate voltage characteristics. Further, if the trap level remains in the vicinity of the p base layer 22, the carrier distribution in the on state changes, and the trade-off characteristic between the on voltage and the turn-off loss may be deteriorated.
- the n-type field stop layer has been described only in the IGBTs of the third and fourth embodiments, but can be applied to the diodes of the first and second embodiments. That is, between the n + cathode layer 3 and the n ⁇ drift layer 1, the n field stop layer is implanted with phosphorus or proton H + so as to have an impurity concentration lower than that of the n + cathode layer 3 and adjacent to the same layer. May be formed by irradiation.
- the present invention it is possible to realize a diode or IGBT having a small withstand voltage variation width, a turn-off loss greatly reduced as compared with the conventional product, and having a soft switching characteristic, with more precise control. Therefore, it is possible to provide an IGBT module and an IPM (Intelligent Power Module) that take into consideration environmental problems with low electrical loss. Furthermore, in a power converter such as a PWM inverter using the IGBT module having the above characteristics, it is possible to suppress the occurrence of overvoltage breakdown and EMI and to reduce the heat loss. Examples of the power conversion device include the following.
- Converter-inverter circuits can efficiently control induction motors, servo motors, and the like, and are widely used in industries, electric railways, and the like.
- the power factor correction circuit is a circuit that improves the waveform by controlling the AC input current in a sine wave shape, and is used for a switching power supply.
- a p-type separation layer is formed on the chip end face of the IGBT of the present invention to form a reverse blocking IGBT, it can also be used for a matrix converter. Since the matrix converter does not require a DC link capacitor, it can be used for applications that require a compact converter such as an elevator.
- the n field stop layer has an impurity concentration lower than or lower than the concentration of the third embodiment (for example, 2 ⁇ 10 16 atoms / cm 3 ).
- concentration of one or more broad buffer regions is adjusted so that the forward depleted depletion layer does not reach the p collector layer.
- the semiconductor device and the method for manufacturing the semiconductor device according to the present invention are useful for a power semiconductor device used for a power conversion device such as a converter or an inverter.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- High Energy & Nuclear Physics (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thyristors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
シリコンウエハのn-ドリフト層の不純物濃度を制御するために、シリコンウエハにプロトンイオン(H+)を照射して、n-ドリフト層中にブロードバッファ構造を形成したダイオードおよびその製造方法について説明する。
図7は、実施の形態2にかかる半導体装置の構成、ネットドーピング濃度分布を示す図である。実施の形態1におけるブロードバッファ領域6を、n-ドリフト層1中に複数備えてもよい。
図8は、実施の形態3にかかる半導体装置の構成、ネットドーピング濃度分布を示す図である。実施の形態1,2にかかる半導体装置の構成をIGBTに適用してもよい。
図13では、実施の形態4にかかる半導体装置の構成、ネットドーピング濃度分布を示す図である。実施の形態3におけるブロードバッファ領域26を、n-ドリフト層21中に複数備えていてもよい。
2 pアノード層
3 n+カソード層
4 アノード電極
5 カソード電極
6,26 ブロードバッファ領域
10 FZウエハ
11 プロトンH+
12 絶縁膜
13 結晶欠陥
14 ボロン+
15 リン+
22 pベース層
23 nフィールドストップ層
24 エミッタ電極
25 コレクタ電極
27 ゲート電極
28 pコレクタ層
29 nエミッタ層
30 研削およびウェットエッチング
31 ゲート絶縁膜
32 層間絶縁膜
Claims (20)
- 第1導電型の第1半導体層と、
前記第1半導体層の一方の主面側に設けられた、該第1半導体層よりも不純物濃度の高い第2導電型の第2半導体層と、
前記第1半導体層の他方の主面側に設けられた、該第1半導体層よりも不純物濃度の高い第1導電型の第3半導体層と、
前記第1半導体層の内部に設けられた、該第1半導体層よりも不純物濃度が高く、かつ不純物濃度分布の極大値が前記第2半導体層および前記第3半導体層の不純物濃度よりも低い第1導電型のブロードバッファ領域と、
を備え、
該ブロードバッファ領域のネットドーピング濃度の総量が4.8×1011atoms/cm2以上1.0×1012atoms/cm2以下であり、
前記第1半導体層の比抵抗ρ0(Ωcm)が定格電圧V0(V)に対して、
0.12V0≦ρ0≦0.25V0
を満たすことを特徴とする半導体装置。 - 前記ブロードバッファ領域のネットドーピング濃度の総量が5.2×1011atoms/cm2以上1.0×1012atoms/cm2以下であり、
前記第1半導体層の比抵抗ρ0が定格電圧V0(V)に対して、
0.133V0≦ρ0≦0.25V0
を満たすことを特徴とする請求項1に記載の半導体装置。 - 前記ブロードバッファ領域を前記第1半導体層の内部に複数備えていることを特徴とする請求項1に記載の半導体装置。
- 前記第1半導体層の幅に対して前記複数のブロードバッファ領域が占める幅の合計値の割合γと、耐圧と同じ値の逆電圧が印加されたときに、臨界電界強度に対して前記複数のブロードバッファ領域における電界強度の目減り分の合計値が占める割合ηと、前記第1半導体層となる基板のドナー濃度の規格値に対する測定値のずれの割合αが、
4α(γ/η)/[(2-α)(2+α)]<α
を満たすことを特徴とする請求項3に記載の半導体装置。 - 前記第1半導体層はFZシリコン基板からなることを特徴とする請求項1~4のいずれか一つに記載の半導体装置。
- 第1導電型のドリフト層と、
前記ドリフト層の第1の主面側に設けられた、該ドリフト層よりも不純物濃度の高い第2導電型のベース層と、
前記ドリフト層の第1の主面側に、前記ベース層と接して設けられた、該ベース層よりも不純物濃度の高い第1導電型のエミッタ層と、
前記ドリフト層、前記ベース層および前記エミッタ層に接する絶縁膜と、
前記絶縁膜を介して、前記ドリフト層、前記ベース層および前記エミッタ層と隣り合うゲート電極と、
前記ドリフト層の第2の主面側に設けられた、該ドリフト層よりも不純物濃度の高い第2導電型のコレクタ層と、
前記ドリフト層の内部に設けられた、該ドリフト層よりも不純物濃度が高く、かつ不純物濃度分布の極大値が前記ベース層およびコレクタ層よりも低い第1導電型のブロードバッファ領域と、を備え、
該ブロードバッファ領域のネットドーピング濃度の総量が4.8×1011atoms/cm2以上1.0×1012atoms/cm2以下であり、
前記ドリフト層の比抵抗ρ0(Ωcm)が定格電圧V0(V)に対して、
0.12V0≦ρ0≦0.25V0
を満たすことを特徴とする半導体装置。 - 前記ブロードバッファ領域のネットドーピング濃度の総量が5.2×1011atoms/cm2以上1.0×1012atoms/cm2以下であり、
前記ドリフト層の比抵抗ρ0が定格電圧V0(V)に対して、
0.133V0≦ρ0≦0.25V0
を満たすことを特徴とする請求項6に記載の半導体装置。 - 前記ブロードバッファ領域を前記ドリフト層の内部に複数備えていることを特徴とする請求項6に記載の半導体装置。
- 前記ドリフト層の幅に対して前記複数のブロードバッファ領域が占める幅の合計値の割合γと、耐圧と同じ値の電圧が印加されたときに、臨界電界強度に対して前記複数のブロードバッファ領域における電界強度の目減り分の合計値が占める割合ηと、前記ドリフト層となる基板のドナー濃度の規格値に対する測定値のずれの割合αが、
4α(γ/η)/[(2-α)(2+α)]<α
を満たすことを特徴とする請求項8に記載の半導体装置。 - 前記基板の第1の主面側にて前記ドリフト層または前記ブロードバッファ領域と接し、かつ前記第2の主面側にて前記コレクタ層と接する第1導電型フィールドストップ層をさらに備えることを特徴とする請求項6~9のいずれか一つに記載の半導体装置。
- 前記基板の第1の主面側にて前記ドリフト層または前記ブロードバッファ領域と接し、かつ前記第2の主面側にて前記コレクタ層と接する第1導電型フィールドストップ層をさらに備え、
前記ドリフト層、前記ブロードバッファ領域および前記フィールドストップ層のネットドーピング濃度の総量が1.2×1012atoms/cm2以上2.0×1012atoms/cm2以下であることを特徴とする請求項6~9のいずれか一つに記載の半導体装置。 - 前記ドリフト層はFZシリコン基板からなることを特徴とする請求項6~9のいずれか一つに記載の半導体装置。
- 第1導電型の第1半導体層と、前記第1半導体層の一方の主面側に設けられた、該第1半導体層よりも不純物濃度の高い第2導電型の第2半導体層と、前記第1半導体層の他方の主面側に設けられた、該第1半導体層よりも不純物濃度の高い第1導電型の第3半導体層と、前記第1半導体層の内部に設けられた、該第1半導体層よりも不純物濃度が高く、かつ不純物濃度分布の極大値が前記第2半導体層および前記第3半導体層の不純物濃度より低い第1導電型のブロードバッファ領域と、を備える半導体装置を製造するにあたって、
前記第1半導体層の一方の主面側に、前記第2半導体層を形成する第1の形成工程と、
前記第1半導体層の前記第2半導体層側から、前記第1半導体層に達する飛程距離で水素イオンを照射し、300℃以上550℃以下の熱処理を行い、前記第1半導体層の内部に前記ブロードバッファ領域を形成する第2の形成工程と、
を含み、
前記第2の形成工程では、前記第1半導体層の内部に、ネットドーピング濃度の総量が4.8×1011atoms/cm2以上1.0×1012atoms/cm2以下の前記ブロードバッファ領域を形成し、
前記第1半導体層の比抵抗ρ0は定格電圧V0(V)に対して、
0.12V0≦ρ0≦0.25V0
を満たすことを特徴とする半導体装置の製造方法。 - 前記第1の形成工程の前に、酸化雰囲気で1000℃以上の熱処理を行い、前記第1半導体層に酸素を導入する導入工程をさらに含むことを特徴とする請求項13に記載の半導体装置の製造方法。
- 前記導入工程では、前記第1半導体層に、1×1016atoms/cm3以上の濃度で酸素を導入することを特徴とする請求項14に記載の半導体装置の製造方法。
- 第1導電型の第1半導体層と、前記第1半導体層の一方の主面側に設けられた、該第1半導体層よりも不純物濃度の高い第2導電型の第2半導体層と、前記第1半導体層の他方の主面側に設けられた、該第1半導体層よりも不純物濃度の高い第1導電型の第3半導体層と、前記第1半導体層の内部に設けられた、該第1半導体層よりも不純物濃度が高く、かつ不純物濃度分布の極大値が前記第2半導体層および前記第3半導体層の不純物濃度より低い第1導電型のブロードバッファ領域と、を備える半導体装置を製造するにあたって、
前記第1半導体層の他方の主面側から、該第1半導体層の、後の工程で前記第3半導体層が形成される箇所よりも深い箇所に達する飛程距離で水素イオンを照射して、300℃以上550℃以下の熱処理を行い、前記第1半導体層の内部に、前記ブロードバッファ領域を形成する第2の形成工程を含み、
前記第2の形成工程では、前記第1半導体層の内部に、ネットドーピング濃度の総量が4.8×1011atoms/cm2以上1.0×1012atoms/cm2以下の前記ブロードバッファ領域を形成し、
前記第1半導体層の比抵抗ρ0は定格電圧V0(V)に対して、
0.12V0≦ρ0≦0.25V0
を満たすことを特徴とする半導体装置の製造方法。 - 前記第2の形成工程の前に、酸化雰囲気で1000℃以上の熱処理を行い、前記第1半導体層に酸素を導入する導入工程をさらに含むことを特徴とする請求項16に記載の半導体装置の製造方法。
- 前記導入工程では、前記第1半導体層に、1×1016atoms/cm3以上の濃度で酸素を導入することを特徴とする請求項17に記載の半導体装置の製造方法。
- 前記第2の形成工程では、前記水素イオンの照射により水素誘起ドナーを形成することによって前記ブロードバッファ領域を形成することを特徴とする請求項13~18のいずれか一つに記載の半導体装置の製造方法。
- 前記第1半導体層はFZシリコン基板からなることを特徴とする請求項13~18のいずれか一つに記載の半導体装置の製造方法。
Priority Applications (11)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/505,294 US8766413B2 (en) | 2009-11-02 | 2010-11-02 | Semiconductor device and method for manufacturing semiconductor device |
CN201080049553.6A CN102687277B (zh) | 2009-11-02 | 2010-11-02 | 半导体器件以及用于制造半导体器件的方法 |
KR1020127012023A KR101794182B1 (ko) | 2009-11-02 | 2010-11-02 | 반도체 장치 및 반도체 장치의 제조 방법 |
JP2011538528A JP5569532B2 (ja) | 2009-11-02 | 2010-11-02 | 半導体装置および半導体装置の製造方法 |
DE112010004241.1T DE112010004241B4 (de) | 2009-11-02 | 2010-11-02 | Halbleiterbauelemente und Verfahren zur Herstellung von Halbleiterbauelementen |
US14/283,578 US9070658B2 (en) | 2009-11-02 | 2014-05-21 | Semiconductor device and method for manufacturing semiconductor device |
US14/730,940 US9252209B2 (en) | 2009-11-02 | 2015-06-04 | Semiconductor device and method for manufacturing semiconductor device |
US14/980,433 US10043865B2 (en) | 2009-11-02 | 2015-12-28 | Semiconductor device and method for manufacturing semiconductor device |
US16/047,057 US10868111B2 (en) | 2009-11-02 | 2018-07-27 | Semiconductor device and method for manufacturing semiconductor device |
US16/825,365 US10847608B2 (en) | 2009-11-02 | 2020-03-20 | Semiconductor device and method for manufacturing semiconductor device |
US16/952,725 US10998398B2 (en) | 2009-11-02 | 2020-11-19 | Semiconductor device and method for manufacturing semiconductor device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009251944 | 2009-11-02 | ||
JP2009-251944 | 2009-11-02 |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/505,294 A-371-Of-International US8766413B2 (en) | 2009-11-02 | 2010-11-02 | Semiconductor device and method for manufacturing semiconductor device |
US14/283,578 Continuation US9070658B2 (en) | 2009-11-02 | 2014-05-21 | Semiconductor device and method for manufacturing semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2011052787A1 true WO2011052787A1 (ja) | 2011-05-05 |
Family
ID=43922208
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2010/069528 WO2011052787A1 (ja) | 2009-11-02 | 2010-11-02 | 半導体装置および半導体装置の製造方法 |
Country Status (6)
Country | Link |
---|---|
US (7) | US8766413B2 (ja) |
JP (6) | JP5569532B2 (ja) |
KR (1) | KR101794182B1 (ja) |
CN (2) | CN102687277B (ja) |
DE (1) | DE112010004241B4 (ja) |
WO (1) | WO2011052787A1 (ja) |
Cited By (42)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011222550A (ja) * | 2010-04-02 | 2011-11-04 | Toyota Central R&D Labs Inc | Pinダイオード |
WO2012157772A1 (ja) * | 2011-05-18 | 2012-11-22 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
CN102832122A (zh) * | 2011-06-14 | 2012-12-19 | Abb技术有限公司 | 双极穿通半导体器件及这种半导体器件的制造方法 |
CN103035676A (zh) * | 2011-09-28 | 2013-04-10 | 丰田自动车株式会社 | 半导体装置及其制造方法 |
CN103199107A (zh) * | 2012-01-06 | 2013-07-10 | 上海华虹Nec电子有限公司 | 半导体器件及制造方法 |
WO2013141141A1 (ja) * | 2012-03-19 | 2013-09-26 | 富士電機株式会社 | 半導体装置の製造方法 |
WO2013141221A1 (ja) * | 2012-03-19 | 2013-09-26 | 富士電機株式会社 | 半導体装置の製造方法 |
WO2013147274A1 (ja) * | 2012-03-30 | 2013-10-03 | 富士電機株式会社 | 半導体装置の製造方法 |
JP2014007254A (ja) * | 2012-06-22 | 2014-01-16 | Sanken Electric Co Ltd | 半導体装置及びその製造方法 |
WO2014065080A1 (ja) * | 2012-10-23 | 2014-05-01 | 富士電機株式会社 | 半導体装置およびその製造方法 |
JP2014107278A (ja) * | 2012-11-22 | 2014-06-09 | Shi Exaination & Inspection Ltd | 半導体装置の製造方法、基板処理システム、及び基板処理装置 |
CN103890920A (zh) * | 2011-11-15 | 2014-06-25 | 富士电机株式会社 | 半导体装置以及半导体装置的制造方法 |
CN103946983A (zh) * | 2011-12-15 | 2014-07-23 | 富士电机株式会社 | 半导体装置和半导体装置的制造方法 |
US20140217463A1 (en) * | 2013-02-07 | 2014-08-07 | Infineon Technologies Ag | Bipolar Semiconductor Switch and a Manufacturing Method Therefor |
US20140291723A1 (en) * | 2012-01-19 | 2014-10-02 | Fuji Electric Co., Ltd. | Semiconductor device and method for producing the same |
CN104106139A (zh) * | 2012-06-01 | 2014-10-15 | 富士电机株式会社 | 半导体装置 |
KR20140141572A (ko) * | 2012-03-30 | 2014-12-10 | 후지 덴키 가부시키가이샤 | 반도체 장치의 제조 방법 |
US20150069462A1 (en) * | 2012-03-23 | 2015-03-12 | Fuji Electric Co., Ltd. | Semiconductor device and semiconductor device manufacturing method |
JPWO2013100155A1 (ja) * | 2011-12-28 | 2015-05-11 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
WO2015118713A1 (ja) * | 2014-02-10 | 2015-08-13 | トヨタ自動車株式会社 | 半導体装置及び半導体装置の製造方法 |
US20150287786A1 (en) * | 2012-04-24 | 2015-10-08 | Fairchild Korea Semiconductor Ltd. | Power device and method for fabricating the same |
JP2016184713A (ja) * | 2015-03-27 | 2016-10-20 | 株式会社日立製作所 | 半導体装置およびその製造方法、並びに電力変換システム |
WO2016204126A1 (ja) * | 2015-06-17 | 2016-12-22 | 富士電機株式会社 | 半導体装置 |
JPWO2015087507A1 (ja) * | 2013-12-10 | 2017-03-16 | 株式会社アルバック | 絶縁ゲートバイポーラトランジスタおよびその製造方法 |
JPWO2016147264A1 (ja) * | 2015-03-13 | 2017-09-07 | 三菱電機株式会社 | 半導体装置及びその製造方法 |
JP2017168776A (ja) * | 2016-03-18 | 2017-09-21 | 三菱電機株式会社 | 半導体素子 |
EP3300121A1 (en) | 2016-09-27 | 2018-03-28 | Hitachi Power Semiconductor Device, Ltd. | Semiconductor device, method for manufacturing the same, and power conversion system |
US9960250B2 (en) | 2012-04-24 | 2018-05-01 | Semiconductor Components Industries Llc | Power device and method of manufacturing the same |
US10109719B2 (en) | 2012-04-24 | 2018-10-23 | Semiconductor Components Industries, Llc | Power device and fabricating method thereof |
JP2019087635A (ja) * | 2017-11-07 | 2019-06-06 | 富士電機株式会社 | 半導体装置の製造方法および半導体装置 |
JP2019121797A (ja) * | 2017-12-27 | 2019-07-22 | インフィニオン テクノロジーズ アクチエンゲゼルシャフトInfineon Technologies AG | ワイドバンドギャップ半導体デバイスおよびワイドバンドギャップ半導体デバイスの形成方法 |
JP2020027921A (ja) * | 2018-08-17 | 2020-02-20 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
WO2020095899A1 (ja) * | 2018-11-07 | 2020-05-14 | 株式会社デンソー | 半導体装置 |
JP2020182009A (ja) * | 2020-08-12 | 2020-11-05 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
JP2020198433A (ja) * | 2019-03-07 | 2020-12-10 | ローム株式会社 | スイッチング素子 |
WO2021049499A1 (ja) | 2019-09-11 | 2021-03-18 | 富士電機株式会社 | 半導体装置および製造方法 |
JPWO2021070584A1 (ja) * | 2019-10-11 | 2021-04-15 | ||
JP2021086949A (ja) * | 2019-11-28 | 2021-06-03 | ラピスセミコンダクタ株式会社 | 半導体装置の製造方法、及び半導体装置 |
JPWO2021186944A1 (ja) * | 2020-03-17 | 2021-09-23 | ||
WO2021199687A1 (ja) * | 2020-04-02 | 2021-10-07 | 信越半導体株式会社 | シリコン単結晶基板中のドナー濃度の制御方法 |
DE112020001040T5 (de) | 2019-10-17 | 2021-12-23 | Fuji Electric Co., Ltd. | Halbleitervorrichtung und herstellungsverfahren einer halbleitervorrichtung |
US11342186B2 (en) | 2018-10-18 | 2022-05-24 | Fuji Electric Co., Ltd. | Semiconductor device and manufacturing method thereof |
Families Citing this family (90)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101794182B1 (ko) * | 2009-11-02 | 2017-11-06 | 후지 덴키 가부시키가이샤 | 반도체 장치 및 반도체 장치의 제조 방법 |
EP2654084B1 (en) | 2010-12-17 | 2019-09-25 | Fuji Electric Co. Ltd. | Method of manufacturing a semiconductor device |
US8829609B2 (en) * | 2011-07-28 | 2014-09-09 | Stmicroelectronics S.R.L. | Insulated gate semiconductor device with optimized breakdown voltage, and manufacturing method thereof |
US8836066B1 (en) * | 2011-09-23 | 2014-09-16 | Rockwell Collins, Inc. | Avalanche photodiode configured for an image sensor |
US8987787B2 (en) * | 2012-04-10 | 2015-03-24 | Macronix International Co., Ltd. | Semiconductor structure and method for manufacturing the same |
DE102012020785B4 (de) | 2012-10-23 | 2014-11-06 | Infineon Technologies Ag | Erhöhung der Dotierungseffizienz bei Protonenbestrahlung |
US9263271B2 (en) * | 2012-10-25 | 2016-02-16 | Infineon Technologies Ag | Method for processing a semiconductor carrier, a semiconductor chip arrangement and a method for manufacturing a semiconductor device |
CN103035693B (zh) * | 2012-11-06 | 2016-02-10 | 上海华虹宏力半导体制造有限公司 | 场截止型绝缘栅双极晶体管及其制造方法 |
JP6265594B2 (ja) | 2012-12-21 | 2018-01-24 | ラピスセミコンダクタ株式会社 | 半導体装置の製造方法、及び半導体装置 |
CN104969360B (zh) | 2013-03-25 | 2018-04-20 | 富士电机株式会社 | 半导体装置 |
KR101742416B1 (ko) * | 2013-06-12 | 2017-05-31 | 미쓰비시덴키 가부시키가이샤 | 반도체 장치 |
KR102206507B1 (ko) | 2013-06-26 | 2021-01-22 | 후지 덴키 가부시키가이샤 | 반도체 장치 및 반도체 장치의 제조 방법 |
CN104716040B (zh) * | 2013-12-13 | 2017-08-08 | 上海华虹宏力半导体制造有限公司 | 有效降低功耗的igbt器件的制作方法 |
CN105531825B (zh) * | 2013-12-16 | 2019-01-01 | 富士电机株式会社 | 半导体装置及半导体装置的制造方法 |
CN103730356A (zh) * | 2013-12-31 | 2014-04-16 | 上海集成电路研发中心有限公司 | 功率半导体器件背面制造方法 |
KR102360695B1 (ko) | 2014-01-23 | 2022-02-08 | 글로벌웨이퍼스 씨오., 엘티디. | 고 비저항 soi 웨이퍼 및 그 제조 방법 |
JP6287407B2 (ja) * | 2014-03-19 | 2018-03-07 | サンケン電気株式会社 | 半導体装置 |
CN105428404B (zh) * | 2014-06-17 | 2021-02-19 | 快捷韩国半导体有限公司 | 功率器件及其制造方法 |
JP2016042498A (ja) * | 2014-08-13 | 2016-03-31 | キヤノン株式会社 | インプリント装置および物品製造方法 |
US9899499B2 (en) | 2014-09-04 | 2018-02-20 | Sunedison Semiconductor Limited (Uen201334164H) | High resistivity silicon-on-insulator wafer manufacturing method for reducing substrate loss |
US9853133B2 (en) * | 2014-09-04 | 2017-12-26 | Sunedison Semiconductor Limited (Uen201334164H) | Method of manufacturing high resistivity silicon-on-insulator substrate |
DE112015000670T5 (de) | 2014-09-17 | 2016-11-03 | Fuji Electric Co., Ltd. | Halbleitervorrichtungsverfahren zur Herstellung einer Halbleitervorrichtung |
JP6237921B2 (ja) * | 2014-09-30 | 2017-11-29 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
WO2016051973A1 (ja) * | 2014-10-03 | 2016-04-07 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
JP6269858B2 (ja) * | 2014-11-17 | 2018-01-31 | 富士電機株式会社 | 炭化珪素半導体装置の製造方法 |
WO2016081367A1 (en) | 2014-11-18 | 2016-05-26 | Sunedison Semiconductor Limited | HIGH RESISTIVITY SILICON-ON-INSULATOR SUBSTRATE COMPRISING A CHARGE TRAPPING LAYER FORMED BY He-N2 CO-IMPLANTATION |
JP6650463B2 (ja) | 2014-11-18 | 2020-02-19 | グローバルウェーハズ カンパニー リミテッドGlobalWafers Co.,Ltd. | 電荷トラップ層を備えた高抵抗率の半導体・オン・インシュレーターウェハーの製造方法 |
JP6726180B2 (ja) | 2014-11-18 | 2020-07-22 | グローバルウェーハズ カンパニー リミテッドGlobalWafers Co.,Ltd. | 高抵抗率半導体・オン・インシュレータウエハおよび製造方法 |
US10283402B2 (en) | 2015-03-03 | 2019-05-07 | Globalwafers Co., Ltd. | Method of depositing charge trapping polycrystalline silicon films on silicon substrates with controllable film stress |
US9881832B2 (en) | 2015-03-17 | 2018-01-30 | Sunedison Semiconductor Limited (Uen201334164H) | Handle substrate for use in manufacture of semiconductor-on-insulator structure and method of manufacturing thereof |
CN107408532A (zh) | 2015-03-17 | 2017-11-28 | 太阳能爱迪生半导体有限公司 | 用于绝缘体上半导体结构的制造的热稳定电荷捕获层 |
DE102015017423B4 (de) | 2015-04-30 | 2024-07-25 | Infineon Technologies Ag | Herstellen einer halbleitervorrichtung durch epitaxie |
DE102015208097B4 (de) | 2015-04-30 | 2022-03-31 | Infineon Technologies Ag | Herstellen einer Halbleitervorrichtung durch Epitaxie |
EP3739620B1 (en) | 2015-06-01 | 2022-02-16 | GlobalWafers Co., Ltd. | A silicon germanium-on-insulator structure |
JPWO2016194116A1 (ja) * | 2015-06-01 | 2018-03-29 | 株式会社日立製作所 | 半導体装置、基板および電力変換装置 |
WO2016196060A1 (en) | 2015-06-01 | 2016-12-08 | Sunedison Semiconductor Limited | A method of manufacturing semiconductor-on-insulator |
DE102015114177A1 (de) | 2015-08-26 | 2017-03-02 | Infineon Technologies Ag | Halbleitervorrichtung, Siliziumwafer und Verfahren zum Herstellen eines Siliziumwafers |
WO2017047276A1 (ja) * | 2015-09-16 | 2017-03-23 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
CN106558616B (zh) * | 2015-09-24 | 2019-11-12 | 丰田合成株式会社 | 纵型场效应晶体管以及电力转换装置 |
JP6749394B2 (ja) | 2015-11-20 | 2020-09-02 | グローバルウェーハズ カンパニー リミテッドGlobalWafers Co.,Ltd. | 滑らかな半導体表面の製造方法 |
US10415154B2 (en) * | 2015-12-02 | 2019-09-17 | Mitsubishi Electric Corporation | Silicon carbide epitaxial substrate and silicon carbide semiconductor device |
US10411093B2 (en) | 2015-12-28 | 2019-09-10 | Mitsubishi Electric Corporation | Semiconductor device and method for manufacturing semiconductor device |
JP6676988B2 (ja) | 2016-01-29 | 2020-04-08 | 株式会社デンソー | 半導体装置 |
WO2017142849A1 (en) | 2016-02-19 | 2017-08-24 | Sunedison Semiconductor Limited | Semiconductor on insulator structure comprising a buried high resistivity layer |
US9831115B2 (en) | 2016-02-19 | 2017-11-28 | Sunedison Semiconductor Limited (Uen201334164H) | Process flow for manufacturing semiconductor on insulator structures in parallel |
WO2017142704A1 (en) | 2016-02-19 | 2017-08-24 | Sunedison Semiconductor Limited | High resistivity silicon-on-insulator substrate comprising a charge trapping layer formed on a substrate with a rough surface |
JP6610768B2 (ja) | 2016-02-23 | 2019-11-27 | 富士電機株式会社 | 半導体装置 |
US10593748B2 (en) | 2016-03-07 | 2020-03-17 | Globalwafers Co., Ltd. | Semiconductor on insulator structure comprising a low temperature flowable oxide layer and method of manufacture thereof |
WO2017155806A1 (en) | 2016-03-07 | 2017-09-14 | Sunedison Semiconductor Limited | Semiconductor on insulator structure comprising a plasma oxide layer and method of manufacture thereof |
WO2017155808A1 (en) | 2016-03-07 | 2017-09-14 | Sunedison Semiconductor Limited | Semiconductor on insulator structure comprising a plasma nitride layer and method of manufacture thereof |
US11848227B2 (en) | 2016-03-07 | 2023-12-19 | Globalwafers Co., Ltd. | Method of manufacturing a semiconductor on insulator structure by a pressurized bond treatment |
JP6846119B2 (ja) * | 2016-05-02 | 2021-03-24 | 株式会社 日立パワーデバイス | ダイオード、およびそれを用いた電力変換装置 |
US20180145130A1 (en) * | 2016-05-17 | 2018-05-24 | Littelfuse, Inc. | Igbt with improved reverse blocking capability |
KR102439602B1 (ko) | 2016-06-08 | 2022-09-01 | 글로벌웨이퍼스 씨오., 엘티디. | 높은 비저항의 단결정 실리콘 잉곳 및 개선된 기계적 강도를 갖는 웨이퍼 |
US10269617B2 (en) | 2016-06-22 | 2019-04-23 | Globalwafers Co., Ltd. | High resistivity silicon-on-insulator substrate comprising an isolation region |
DE102016112139B3 (de) * | 2016-07-01 | 2018-01-04 | Infineon Technologies Ag | Verfahren zum Reduzieren einer Verunreinigungskonzentration in einem Halbleiterkörper |
DE102016114389B3 (de) * | 2016-08-03 | 2017-11-23 | Infineon Technologies Austria Ag | Halbleitervorrichtung mit Driftzone und rückseitigem Emitter und Verfahren zur Herstellung |
JP6724993B2 (ja) * | 2016-08-12 | 2020-07-15 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
JP6733739B2 (ja) * | 2016-10-17 | 2020-08-05 | 富士電機株式会社 | 半導体装置 |
SG10201913373WA (en) | 2016-10-26 | 2020-03-30 | Globalwafers Co Ltd | High resistivity silicon-on-insulator substrate having enhanced charge trapping efficiency |
JP6784148B2 (ja) * | 2016-11-10 | 2020-11-11 | 三菱電機株式会社 | 半導体装置、絶縁ゲート型バイポーラトランジスタ、絶縁ゲート型バイポーラトランジスタの製造方法 |
KR102587815B1 (ko) | 2016-12-05 | 2023-10-10 | 글로벌웨이퍼스 씨오., 엘티디. | 높은 저항률 실리콘-온-절연체 구조 및 그의 제조 방법 |
EP3653761B1 (en) | 2016-12-28 | 2024-02-28 | Sunedison Semiconductor Limited | Silicon wafers with intrinsic gettering and gate oxide integrity yield |
JP6661575B2 (ja) | 2017-06-20 | 2020-03-11 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
US20190006461A1 (en) * | 2017-06-29 | 2019-01-03 | Alpha And Omega Semiconductor (Cayman) Ltd. | Semiconductor device incorporating epitaxial layer field stop zone |
CN107507870A (zh) * | 2017-07-06 | 2017-12-22 | 全球能源互联网研究院有限公司 | 二极管 |
SG10201913850VA (en) | 2017-07-14 | 2020-03-30 | Sunedison Semiconductor Ltd | Method of manufacture of a semiconductor on insulator structure |
JP6873937B2 (ja) * | 2018-02-20 | 2021-05-19 | 株式会社東芝 | 半導体装置 |
KR102562239B1 (ko) | 2018-04-27 | 2023-07-31 | 글로벌웨이퍼스 씨오., 엘티디. | 반도체 도너 기판으로부터의 층 전이를 용이하게 하는 광 지원형 소판 형성 |
CN112262467A (zh) | 2018-06-08 | 2021-01-22 | 环球晶圆股份有限公司 | 将硅薄层移转的方法 |
DE102018132236B4 (de) | 2018-12-14 | 2023-04-27 | Infineon Technologies Ag | Leistungshalbleiterbauelement und Verfahren zu dessen Herstellung |
CN112204710B (zh) | 2018-12-28 | 2024-07-09 | 富士电机株式会社 | 半导体装置及制造方法 |
JP2020188168A (ja) * | 2019-05-15 | 2020-11-19 | トヨタ自動車株式会社 | 絶縁ゲート型バイポーラトランジスタ |
US11450734B2 (en) | 2019-06-17 | 2022-09-20 | Fuji Electric Co., Ltd. | Semiconductor device and fabrication method for semiconductor device |
DE112020000333T5 (de) * | 2019-08-09 | 2021-09-16 | Fuji Electric Co., Ltd. | Halbleitervorrichtung |
US11233158B2 (en) * | 2019-08-16 | 2022-01-25 | Semiconductor Components Industries, Llc | Semiconductor power device and method for manufacture |
US20210116888A1 (en) * | 2019-10-21 | 2021-04-22 | Semiconductor Components Industries, Llc | Systems and methods for system optimization and/or failure detection |
JP7297654B2 (ja) * | 2019-12-11 | 2023-06-26 | 株式会社東芝 | 半導体装置、インバータ回路、駆動装置、車両、及び、昇降機 |
JP2021132073A (ja) * | 2020-02-18 | 2021-09-09 | 株式会社デンソー | 半導体装置 |
CN114303246A (zh) * | 2020-03-04 | 2022-04-08 | 富士电机株式会社 | 半导体装置、半导体装置的制造方法及具备半导体装置的电力变换装置 |
CN113471273A (zh) * | 2020-03-31 | 2021-10-01 | 比亚迪半导体股份有限公司 | 绝缘栅双极型晶体管及制备方法、电子设备 |
DE102020118404A1 (de) * | 2020-07-13 | 2022-01-13 | Infineon Technologies Ag | Vertikale leistungs-halbleitervorrichtung und herstellungsverfahren |
JP7374054B2 (ja) * | 2020-08-20 | 2023-11-06 | 三菱電機株式会社 | 半導体装置 |
CN112599587B (zh) * | 2020-12-08 | 2022-04-29 | 清华大学 | 一种具有缓冲层结构的半导体器件 |
CN116978937A (zh) * | 2021-02-07 | 2023-10-31 | 华为技术有限公司 | 半导体器件及相关模块、电路、制备方法 |
CN113206013A (zh) * | 2021-04-27 | 2021-08-03 | 上海积塔半导体有限公司 | 具有背面缓冲层结构的igbt器件及其制备方法 |
CN113517333A (zh) * | 2021-06-07 | 2021-10-19 | 西安电子科技大学 | 一种具有超结结构的mosfet器件及其制备方法 |
CN113644123A (zh) * | 2021-06-28 | 2021-11-12 | 华为技术有限公司 | 半导体器件及相关芯片和制备方法 |
CN115472668A (zh) * | 2022-05-05 | 2022-12-13 | 安世半导体科技(上海)有限公司 | 半导体器件及其制造方法 |
JP2023172669A (ja) | 2022-05-24 | 2023-12-06 | 三菱電機株式会社 | 半導体装置及びその製造方法 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58216473A (ja) * | 1982-06-11 | 1983-12-16 | Hitachi Ltd | ダイオ−ド |
JPH08125200A (ja) * | 1994-10-25 | 1996-05-17 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
JP2000223720A (ja) * | 1999-01-29 | 2000-08-11 | Meidensha Corp | 半導体素子およびライフタイム制御方法 |
JP2003152198A (ja) * | 2001-02-23 | 2003-05-23 | Fuji Electric Co Ltd | 半導体装置およびその製造方法 |
JP2003318412A (ja) * | 2002-02-20 | 2003-11-07 | Fuji Electric Co Ltd | 半導体装置およびその製造方法 |
JP2004039842A (ja) * | 2002-07-03 | 2004-02-05 | Fuji Electric Holdings Co Ltd | 半導体装置およびその製造方法 |
JP2007158320A (ja) * | 2005-11-10 | 2007-06-21 | Fuji Electric Device Technology Co Ltd | 半導体装置およびその製造方法 |
Family Cites Families (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3988262B2 (ja) * | 1998-07-24 | 2007-10-10 | 富士電機デバイステクノロジー株式会社 | 縦型超接合半導体素子およびその製造方法 |
US6482681B1 (en) | 2000-05-05 | 2002-11-19 | International Rectifier Corporation | Hydrogen implant for buffer zone of punch-through non epi IGBT |
DE10207522B4 (de) * | 2001-02-23 | 2018-08-02 | Fuji Electric Co., Ltd. | Halbleiterbauelement und Verfahren zu dessen Herstellung |
DE102004030268B4 (de) | 2003-06-24 | 2013-02-21 | Fuji Electric Co., Ltd | Verfahren zum Herstellen eines Halbleiterelements |
JP4590880B2 (ja) | 2003-06-24 | 2010-12-01 | 富士電機システムズ株式会社 | 半導体素子の製造方法 |
DE102005041335B4 (de) | 2004-08-31 | 2007-05-24 | Infineon Technologies Ag | Randstruktur und Verfahren zur Herstellung einer Randstruktur für ein Leistungshalbleiterbauelement |
DE102004047749B4 (de) | 2004-09-30 | 2008-12-04 | Infineon Technologies Austria Ag | Halbleiterbauteil Diode und IGBT sowie dafür geeignetes Herstellungsverfahren |
JP4843253B2 (ja) * | 2005-05-23 | 2011-12-21 | 株式会社東芝 | 電力用半導体装置 |
US7728409B2 (en) * | 2005-11-10 | 2010-06-01 | Fuji Electric Device Technology Co., Ltd. | Semiconductor device and method of manufacturing the same |
WO2007055352A1 (ja) | 2005-11-14 | 2007-05-18 | Fuji Electric Device Technology Co., Ltd. | 半導体装置およびその製造方法 |
JP5358189B2 (ja) | 2006-01-20 | 2013-12-04 | インフィネオン テクノロジーズ オーストリア アクチエンゲゼルシャフト | 酸素含有半導体ウェハの処理方法 |
JP5228282B2 (ja) | 2006-03-28 | 2013-07-03 | トヨタ自動車株式会社 | 電力用半導体装置及びその製造方法 |
US7538412B2 (en) | 2006-06-30 | 2009-05-26 | Infineon Technologies Austria Ag | Semiconductor device with a field stop zone |
US7989888B2 (en) * | 2006-08-31 | 2011-08-02 | Infineon Technologies Autria AG | Semiconductor device with a field stop zone and process of producing the same |
JP5396689B2 (ja) * | 2006-09-07 | 2014-01-22 | 富士電機株式会社 | 半導体装置およびその製造方法 |
EP2045844A1 (en) * | 2007-10-03 | 2009-04-08 | ABB Technology AG | Semiconductor Module |
JP5365009B2 (ja) * | 2008-01-23 | 2013-12-11 | 富士電機株式会社 | 半導体装置およびその製造方法 |
JP5374883B2 (ja) | 2008-02-08 | 2013-12-25 | 富士電機株式会社 | 半導体装置およびその製造方法 |
JP4743447B2 (ja) * | 2008-05-23 | 2011-08-10 | 三菱電機株式会社 | 半導体装置 |
JP4929304B2 (ja) | 2009-03-13 | 2012-05-09 | 株式会社東芝 | 半導体装置 |
KR101794182B1 (ko) | 2009-11-02 | 2017-11-06 | 후지 덴키 가부시키가이샤 | 반도체 장치 및 반도체 장치의 제조 방법 |
JP5925991B2 (ja) | 2010-05-26 | 2016-05-25 | 三菱電機株式会社 | 半導体装置 |
KR101825500B1 (ko) * | 2011-12-15 | 2018-02-05 | 후지 덴키 가부시키가이샤 | 반도체 장치 및 반도체 장치의 제조방법 |
CN104969360B (zh) | 2013-03-25 | 2018-04-20 | 富士电机株式会社 | 半导体装置 |
-
2010
- 2010-11-02 KR KR1020127012023A patent/KR101794182B1/ko not_active Application Discontinuation
- 2010-11-02 JP JP2011538528A patent/JP5569532B2/ja active Active
- 2010-11-02 CN CN201080049553.6A patent/CN102687277B/zh active Active
- 2010-11-02 US US13/505,294 patent/US8766413B2/en active Active
- 2010-11-02 WO PCT/JP2010/069528 patent/WO2011052787A1/ja active Application Filing
- 2010-11-02 DE DE112010004241.1T patent/DE112010004241B4/de active Active
- 2010-11-02 CN CN201510906782.XA patent/CN105552115B/zh active Active
-
2014
- 2014-01-20 JP JP2014008160A patent/JP5900521B2/ja active Active
- 2014-05-21 US US14/283,578 patent/US9070658B2/en active Active
-
2015
- 2015-06-04 US US14/730,940 patent/US9252209B2/en active Active
- 2015-12-28 US US14/980,433 patent/US10043865B2/en active Active
-
2016
- 2016-01-06 JP JP2016001397A patent/JP6264382B2/ja active Active
-
2017
- 2017-12-21 JP JP2017245588A patent/JP6515990B2/ja active Active
-
2018
- 2018-07-27 US US16/047,057 patent/US10868111B2/en active Active
-
2019
- 2019-02-21 JP JP2019029872A patent/JP6844635B2/ja active Active
-
2020
- 2020-03-20 US US16/825,365 patent/US10847608B2/en active Active
- 2020-11-19 US US16/952,725 patent/US10998398B2/en active Active
-
2021
- 2021-02-25 JP JP2021028884A patent/JP7147891B2/ja active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58216473A (ja) * | 1982-06-11 | 1983-12-16 | Hitachi Ltd | ダイオ−ド |
JPH08125200A (ja) * | 1994-10-25 | 1996-05-17 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
JP2000223720A (ja) * | 1999-01-29 | 2000-08-11 | Meidensha Corp | 半導体素子およびライフタイム制御方法 |
JP2003152198A (ja) * | 2001-02-23 | 2003-05-23 | Fuji Electric Co Ltd | 半導体装置およびその製造方法 |
JP2003318412A (ja) * | 2002-02-20 | 2003-11-07 | Fuji Electric Co Ltd | 半導体装置およびその製造方法 |
JP2004039842A (ja) * | 2002-07-03 | 2004-02-05 | Fuji Electric Holdings Co Ltd | 半導体装置およびその製造方法 |
JP2007158320A (ja) * | 2005-11-10 | 2007-06-21 | Fuji Electric Device Technology Co Ltd | 半導体装置およびその製造方法 |
Cited By (143)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011222550A (ja) * | 2010-04-02 | 2011-11-04 | Toyota Central R&D Labs Inc | Pinダイオード |
JP5874723B2 (ja) * | 2011-05-18 | 2016-03-02 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
WO2012157772A1 (ja) * | 2011-05-18 | 2012-11-22 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
US9324847B2 (en) | 2011-05-18 | 2016-04-26 | Fuji Electric Co., Ltd. | Semiconductor device and semiconductor device manufacturing method |
US9818852B2 (en) | 2011-05-18 | 2017-11-14 | Fuji Electric Co., Ltd. | Semiconductor device and semiconductor device manufacturing method |
US9812561B2 (en) | 2011-05-18 | 2017-11-07 | Fuji Electric Co., Ltd. | Semiconductor device manufacturing method, including substrate thinning and ion implanting |
CN106128946A (zh) * | 2011-05-18 | 2016-11-16 | 富士电机株式会社 | 半导体装置及半导体装置的制造方法 |
CN102832122A (zh) * | 2011-06-14 | 2012-12-19 | Abb技术有限公司 | 双极穿通半导体器件及这种半导体器件的制造方法 |
CN102832122B (zh) * | 2011-06-14 | 2016-08-03 | Abb技术有限公司 | 双极穿通半导体器件及这种半导体器件的制造方法 |
CN103035676A (zh) * | 2011-09-28 | 2013-04-10 | 丰田自动车株式会社 | 半导体装置及其制造方法 |
JP2013074181A (ja) * | 2011-09-28 | 2013-04-22 | Toyota Motor Corp | 半導体装置とその製造方法 |
US10720330B2 (en) | 2011-11-15 | 2020-07-21 | Fuji Electric Co., Ltd. | Semiconductor device and method of manufacturing semiconductor device |
CN103890920A (zh) * | 2011-11-15 | 2014-06-25 | 富士电机株式会社 | 半导体装置以及半导体装置的制造方法 |
EP2782121A4 (en) * | 2011-11-15 | 2015-05-27 | Fuji Electric Co Ltd | SEMICONDUCTOR COMPONENT AND MANUFACTURING METHOD THEREFOR |
US10049880B2 (en) | 2011-11-15 | 2018-08-14 | Fuji Electric Co., Ltd. | Semiconductor device and method of manufacturing semiconductor device |
US9443774B2 (en) | 2011-11-15 | 2016-09-13 | Fuji Electric Co., Ltd. | Semiconductor device and method of manufacturing semiconductor device |
US10199453B2 (en) | 2011-12-15 | 2019-02-05 | Fuji Electric Co., Ltd. | Semiconductor device and method for producing semiconductor device |
JP2015130523A (ja) * | 2011-12-15 | 2015-07-16 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
US9368577B2 (en) | 2011-12-15 | 2016-06-14 | Fuji Electric Co., Ltd. | Semiconductor device and method for producing semiconductor device |
US10056449B2 (en) | 2011-12-15 | 2018-08-21 | Fuji Electric Co., Ltd. | Semiconductor device and method for producing semiconductor device |
KR101825500B1 (ko) * | 2011-12-15 | 2018-02-05 | 후지 덴키 가부시키가이샤 | 반도체 장치 및 반도체 장치의 제조방법 |
US10651269B2 (en) | 2011-12-15 | 2020-05-12 | Fuji Electric Co., Ltd. | Semiconductor device and method for producing semiconductor device |
KR20140101733A (ko) * | 2011-12-15 | 2014-08-20 | 후지 덴키 가부시키가이샤 | 반도체 장치 및 반도체 장치의 제조방법 |
KR101702942B1 (ko) * | 2011-12-15 | 2017-02-06 | 후지 덴키 가부시키가이샤 | 반도체 장치 및 반도체 장치의 제조방법 |
CN103946983A (zh) * | 2011-12-15 | 2014-07-23 | 富士电机株式会社 | 半导体装置和半导体装置的制造方法 |
JPWO2013089256A1 (ja) * | 2011-12-15 | 2015-04-27 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
CN103946983B (zh) * | 2011-12-15 | 2017-05-31 | 富士电机株式会社 | 半导体装置和半导体装置的制造方法 |
US9722016B2 (en) | 2011-12-15 | 2017-08-01 | Fuji Electric Co., Ltd. | Semiconductor device and method for producing semiconductor device |
EP2793266A4 (en) * | 2011-12-15 | 2015-07-22 | Fuji Electric Co Ltd | SEMICONDUCTOR COMPONENT AND MANUFACTURING METHOD THEREFOR |
JP2017034273A (ja) * | 2011-12-28 | 2017-02-09 | 富士電機株式会社 | 半導体装置の製造方法 |
US10930733B2 (en) | 2011-12-28 | 2021-02-23 | Fuji Electric Co., Ltd. | Semiconductor device and method for producing semiconductor device |
US9768246B2 (en) | 2011-12-28 | 2017-09-19 | Fuji Electric Co., Ltd. | Semiconductor device and method for producing semiconductor device |
US10355079B2 (en) | 2011-12-28 | 2019-07-16 | Fuji Electric Co., Ltd. | Semiconductor device and method for producing semiconductor device |
JPWO2013100155A1 (ja) * | 2011-12-28 | 2015-05-11 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
US9276071B2 (en) | 2011-12-28 | 2016-03-01 | Fuji Electric Co., Ltd. | Semiconductor device and method for producing semiconductor device |
US10056451B2 (en) | 2011-12-28 | 2018-08-21 | Fuji Electric Co., Ltd. | Semiconductor device and method for producing semiconductor device |
US11469297B2 (en) | 2011-12-28 | 2022-10-11 | Fuji Electric Co., Ltd. | Semiconductor device and method for producing semiconductor device |
JP2015130524A (ja) * | 2011-12-28 | 2015-07-16 | 富士電機株式会社 | 半導体装置 |
CN103199107A (zh) * | 2012-01-06 | 2013-07-10 | 上海华虹Nec电子有限公司 | 半导体器件及制造方法 |
US9842918B2 (en) | 2012-01-19 | 2017-12-12 | Fuji Electric Co., Ltd. | Semiconductor device and method for producing the same |
US9520475B2 (en) | 2012-01-19 | 2016-12-13 | Fuji Electric Co., Ltd. | Semiconductor device and method for producing the same |
US10128360B2 (en) | 2012-01-19 | 2018-11-13 | Fuji Electric Co., Ltd. | Semiconductor device and method for producing the same |
US20140291723A1 (en) * | 2012-01-19 | 2014-10-02 | Fuji Electric Co., Ltd. | Semiconductor device and method for producing the same |
JPWO2013108911A1 (ja) * | 2012-01-19 | 2015-05-11 | 富士電機株式会社 | 半導体装置およびその製造方法 |
CN107195544A (zh) * | 2012-03-19 | 2017-09-22 | 富士电机株式会社 | 半导体装置的制造方法 |
CN106887385A (zh) * | 2012-03-19 | 2017-06-23 | 富士电机株式会社 | 半导体装置的制造方法 |
US9947761B2 (en) | 2012-03-19 | 2018-04-17 | Fuji Electric Co., Ltd. | Production method for semiconductor device |
US10566440B2 (en) | 2012-03-19 | 2020-02-18 | Fuji Electric Co., Ltd. | Production method for semiconductor device |
US20140357026A1 (en) * | 2012-03-19 | 2014-12-04 | Fuji Electric Co., Ltd. | Production method for semiconductor device |
CN106887385B (zh) * | 2012-03-19 | 2020-06-12 | 富士电机株式会社 | 半导体装置的制造方法 |
CN104054159B (zh) * | 2012-03-19 | 2017-06-30 | 富士电机株式会社 | 半导体装置的制造方法 |
US20180226486A1 (en) * | 2012-03-19 | 2018-08-09 | Fuji Electric Co., Ltd. | Production method for semiconductor device |
JPWO2013141141A1 (ja) * | 2012-03-19 | 2015-08-03 | 富士電機株式会社 | 半導体装置の製造方法 |
CN104040692A (zh) * | 2012-03-19 | 2014-09-10 | 富士电机株式会社 | 半导体装置的制造方法 |
WO2013141141A1 (ja) * | 2012-03-19 | 2013-09-26 | 富士電機株式会社 | 半導体装置の製造方法 |
WO2013141221A1 (ja) * | 2012-03-19 | 2013-09-26 | 富士電機株式会社 | 半導体装置の製造方法 |
CN104054159A (zh) * | 2012-03-19 | 2014-09-17 | 富士电机株式会社 | 半导体装置的制造方法 |
US9530672B2 (en) | 2012-03-19 | 2016-12-27 | Fuji Electric Co., Ltd. | Production method for a semiconductor device |
JPWO2013141221A1 (ja) * | 2012-03-19 | 2015-08-03 | 富士電機株式会社 | 半導体装置の製造方法 |
US20150069462A1 (en) * | 2012-03-23 | 2015-03-12 | Fuji Electric Co., Ltd. | Semiconductor device and semiconductor device manufacturing method |
US11152224B2 (en) | 2012-03-23 | 2021-10-19 | Fuji Electric Co., Ltd. | Semiconductor device with field stop layer and semiconductor device manufacturing method thereof |
WO2013147274A1 (ja) * | 2012-03-30 | 2013-10-03 | 富士電機株式会社 | 半導体装置の製造方法 |
JPWO2013147274A1 (ja) * | 2012-03-30 | 2015-12-14 | 富士電機株式会社 | 半導体装置の製造方法および半導体装置 |
JP2017183749A (ja) * | 2012-03-30 | 2017-10-05 | 富士電機株式会社 | 半導体装置の製造方法 |
US10050106B2 (en) | 2012-03-30 | 2018-08-14 | Fuji Electric Co., Ltd. | Manufacturing method for semiconductor device |
JPWO2013147275A1 (ja) * | 2012-03-30 | 2015-12-14 | 富士電機株式会社 | 半導体装置の製造方法および半導体装置 |
EP2790209A4 (en) * | 2012-03-30 | 2015-07-29 | Fuji Electric Co Ltd | MANUFACTURING METHOD FOR SEMICONDUCTOR COMPONENT |
US9466689B2 (en) | 2012-03-30 | 2016-10-11 | Fuji Electric Co., Ltd. | Method for manufacturing a semiconductor device and semiconductor device manufactured thereby |
KR20140138598A (ko) * | 2012-03-30 | 2014-12-04 | 후지 덴키 가부시키가이샤 | 반도체 장치의 제조방법 |
KR20140141572A (ko) * | 2012-03-30 | 2014-12-10 | 후지 덴키 가부시키가이샤 | 반도체 장치의 제조 방법 |
KR102023175B1 (ko) * | 2012-03-30 | 2019-09-19 | 후지 덴키 가부시키가이샤 | 반도체 장치의 제조 방법 |
KR101982737B1 (ko) * | 2012-03-30 | 2019-05-27 | 후지 덴키 가부시키가이샤 | 반도체 장치의 제조방법 |
CN104145326A (zh) * | 2012-03-30 | 2014-11-12 | 富士电机株式会社 | 半导体装置的制造方法 |
US9385211B2 (en) | 2012-03-30 | 2016-07-05 | Fuji Electric Co., Ltd. | Manufacturing method for semiconductor device |
JP2016015513A (ja) * | 2012-03-30 | 2016-01-28 | 富士電機株式会社 | 半導体装置の製造方法 |
US10707321B2 (en) | 2012-04-24 | 2020-07-07 | Semiconductor Components Industries, Llc | Power device with multiple field stop layers |
US10181513B2 (en) * | 2012-04-24 | 2019-01-15 | Semiconductor Components Industries, Llc | Power device configured to reduce electromagnetic interference (EMI) noise |
US20150287786A1 (en) * | 2012-04-24 | 2015-10-08 | Fairchild Korea Semiconductor Ltd. | Power device and method for fabricating the same |
US9960250B2 (en) | 2012-04-24 | 2018-05-01 | Semiconductor Components Industries Llc | Power device and method of manufacturing the same |
US10109719B2 (en) | 2012-04-24 | 2018-10-23 | Semiconductor Components Industries, Llc | Power device and fabricating method thereof |
EP2790226A4 (en) * | 2012-06-01 | 2015-08-12 | Fuji Electric Co Ltd | SEMICONDUCTOR COMPONENT |
CN104106139A (zh) * | 2012-06-01 | 2014-10-15 | 富士电机株式会社 | 半导体装置 |
JP2014007254A (ja) * | 2012-06-22 | 2014-01-16 | Sanken Electric Co Ltd | 半導体装置及びその製造方法 |
US20150179441A1 (en) * | 2012-10-23 | 2015-06-25 | Fuji Electric Co., Ltd. | Semiconductor device and method for manufacturing the same |
WO2014065080A1 (ja) * | 2012-10-23 | 2014-05-01 | 富士電機株式会社 | 半導体装置およびその製造方法 |
US10867790B2 (en) | 2012-10-23 | 2020-12-15 | Fuji Electric Co., Ltd. | Semiconductor device and method for manufacturing the same |
US20210098252A1 (en) * | 2012-10-23 | 2021-04-01 | Fuji Electric Co., Ltd. | Semiconductor device and method for manufacturing the same |
US11823898B2 (en) | 2012-10-23 | 2023-11-21 | Fuji Electric Co., Ltd. | Semiconductor device and method for manufacturing the same |
TWI637527B (zh) * | 2012-10-23 | 2018-10-01 | 日商富士電機股份有限公司 | 半導體裝置及其製造方法 |
JPWO2014065080A1 (ja) * | 2012-10-23 | 2016-09-08 | 富士電機株式会社 | 半導体装置およびその製造方法 |
US20190115211A1 (en) * | 2012-10-23 | 2019-04-18 | Fuji Electric Co., Ltd. | Semiconductor device and method for manufacturing the same |
US10176986B2 (en) | 2012-10-23 | 2019-01-08 | Fuji Electric Co., Ltd. | Semiconductor device and method for manufacturing the same |
EP2913854A4 (en) * | 2012-10-23 | 2016-07-20 | Fuji Electric Co Ltd | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME |
JP2014107278A (ja) * | 2012-11-22 | 2014-06-09 | Shi Exaination & Inspection Ltd | 半導体装置の製造方法、基板処理システム、及び基板処理装置 |
US9627517B2 (en) * | 2013-02-07 | 2017-04-18 | Infineon Technologies Ag | Bipolar semiconductor switch and a manufacturing method therefor |
US20140217463A1 (en) * | 2013-02-07 | 2014-08-07 | Infineon Technologies Ag | Bipolar Semiconductor Switch and a Manufacturing Method Therefor |
US9882038B2 (en) | 2013-02-07 | 2018-01-30 | Infineon Technologies Ag | Method of manufacturing a bipolar semiconductor switch |
JPWO2015087507A1 (ja) * | 2013-12-10 | 2017-03-16 | 株式会社アルバック | 絶縁ゲートバイポーラトランジスタおよびその製造方法 |
WO2015118713A1 (ja) * | 2014-02-10 | 2015-08-13 | トヨタ自動車株式会社 | 半導体装置及び半導体装置の製造方法 |
JP2015153788A (ja) * | 2014-02-10 | 2015-08-24 | トヨタ自動車株式会社 | 半導体装置及び半導体装置の製造方法 |
US10176994B2 (en) | 2015-03-13 | 2019-01-08 | Mitsubishi Electric Corporation | Semiconductor device and method of manufacturing the same |
JPWO2016147264A1 (ja) * | 2015-03-13 | 2017-09-07 | 三菱電機株式会社 | 半導体装置及びその製造方法 |
JP2016184713A (ja) * | 2015-03-27 | 2016-10-20 | 株式会社日立製作所 | 半導体装置およびその製造方法、並びに電力変換システム |
JP2018082191A (ja) * | 2015-06-17 | 2018-05-24 | 富士電機株式会社 | 半導体装置 |
WO2016204126A1 (ja) * | 2015-06-17 | 2016-12-22 | 富士電機株式会社 | 半導体装置 |
JP2019096897A (ja) * | 2015-06-17 | 2019-06-20 | 富士電機株式会社 | 半導体装置 |
CN107004716B (zh) * | 2015-06-17 | 2020-12-18 | 富士电机株式会社 | 半导体装置 |
US10229972B2 (en) | 2015-06-17 | 2019-03-12 | Fuji Electric Co., Ltd. | Semiconductor device |
CN107004716A (zh) * | 2015-06-17 | 2017-08-01 | 富士电机株式会社 | 半导体装置 |
JPWO2016204126A1 (ja) * | 2015-06-17 | 2017-09-14 | 富士電機株式会社 | 半導体装置 |
JP2017168776A (ja) * | 2016-03-18 | 2017-09-21 | 三菱電機株式会社 | 半導体素子 |
EP3300121A1 (en) | 2016-09-27 | 2018-03-28 | Hitachi Power Semiconductor Device, Ltd. | Semiconductor device, method for manufacturing the same, and power conversion system |
US9991336B2 (en) | 2016-09-27 | 2018-06-05 | Hitachi Power Semiconductor Device Ltd. | Semiconductor device, method for manufacturing the same, and power conversion system |
JP7073681B2 (ja) | 2017-11-07 | 2022-05-24 | 富士電機株式会社 | 半導体装置の製造方法および半導体装置 |
JP2019087635A (ja) * | 2017-11-07 | 2019-06-06 | 富士電機株式会社 | 半導体装置の製造方法および半導体装置 |
JP2019121797A (ja) * | 2017-12-27 | 2019-07-22 | インフィニオン テクノロジーズ アクチエンゲゼルシャフトInfineon Technologies AG | ワイドバンドギャップ半導体デバイスおよびワイドバンドギャップ半導体デバイスの形成方法 |
JP7215898B2 (ja) | 2017-12-27 | 2023-01-31 | インフィニオン テクノロジーズ アクチエンゲゼルシャフト | ワイドバンドギャップ半導体デバイスおよびワイドバンドギャップ半導体デバイスの形成方法 |
CN110838517A (zh) * | 2018-08-17 | 2020-02-25 | 三菱电机株式会社 | 半导体装置及其制造方法 |
JP2020027921A (ja) * | 2018-08-17 | 2020-02-20 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
CN110838517B (zh) * | 2018-08-17 | 2024-02-06 | 三菱电机株式会社 | 半导体装置及其制造方法 |
US11735424B2 (en) | 2018-10-18 | 2023-08-22 | Fuji Electric Co., Ltd. | Semiconductor device and manufacturing method thereof |
US11342186B2 (en) | 2018-10-18 | 2022-05-24 | Fuji Electric Co., Ltd. | Semiconductor device and manufacturing method thereof |
JP2020077742A (ja) * | 2018-11-07 | 2020-05-21 | 株式会社デンソー | 半導体装置 |
JP7024688B2 (ja) | 2018-11-07 | 2022-02-24 | 株式会社デンソー | 半導体装置 |
WO2020095899A1 (ja) * | 2018-11-07 | 2020-05-14 | 株式会社デンソー | 半導体装置 |
JP2020198433A (ja) * | 2019-03-07 | 2020-12-10 | ローム株式会社 | スイッチング素子 |
WO2021049499A1 (ja) | 2019-09-11 | 2021-03-18 | 富士電機株式会社 | 半導体装置および製造方法 |
JP7420132B2 (ja) | 2019-09-11 | 2024-01-23 | 富士電機株式会社 | 半導体装置 |
JPWO2021049499A1 (ja) * | 2019-09-11 | 2021-10-21 | 富士電機株式会社 | 半導体装置および製造方法 |
JP2022019921A (ja) * | 2019-09-11 | 2022-01-27 | 富士電機株式会社 | 半導体装置 |
JPWO2021070584A1 (ja) * | 2019-10-11 | 2021-04-15 | ||
JP7279806B2 (ja) | 2019-10-11 | 2023-05-23 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
WO2021070584A1 (ja) * | 2019-10-11 | 2021-04-15 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
DE112020001040T5 (de) | 2019-10-17 | 2021-12-23 | Fuji Electric Co., Ltd. | Halbleitervorrichtung und herstellungsverfahren einer halbleitervorrichtung |
US11894426B2 (en) | 2019-10-17 | 2024-02-06 | Fuji Electric Co., Ltd. | Semiconductor device and manufacturing method for semiconductor device |
JP2021086949A (ja) * | 2019-11-28 | 2021-06-03 | ラピスセミコンダクタ株式会社 | 半導体装置の製造方法、及び半導体装置 |
WO2021186944A1 (ja) * | 2020-03-17 | 2021-09-23 | 信越半導体株式会社 | シリコン単結晶基板中のドナー濃度の制御方法 |
JPWO2021186944A1 (ja) * | 2020-03-17 | 2021-09-23 | ||
JP7334849B2 (ja) | 2020-03-17 | 2023-08-29 | 信越半導体株式会社 | シリコン単結晶基板中のドナー濃度の制御方法 |
JP2021163929A (ja) * | 2020-04-02 | 2021-10-11 | 信越半導体株式会社 | シリコン単結晶基板中のドナー濃度の制御方法 |
WO2021199687A1 (ja) * | 2020-04-02 | 2021-10-07 | 信越半導体株式会社 | シリコン単結晶基板中のドナー濃度の制御方法 |
JP7264100B2 (ja) | 2020-04-02 | 2023-04-25 | 信越半導体株式会社 | シリコン単結晶基板中のドナー濃度の制御方法 |
JP2020182009A (ja) * | 2020-08-12 | 2020-11-05 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
Also Published As
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6264382B2 (ja) | 半導体装置 | |
US10867790B2 (en) | Semiconductor device and method for manufacturing the same | |
JP5374883B2 (ja) | 半導体装置およびその製造方法 | |
EP2706576A2 (en) | Diode and power conversion system | |
JP6268117B2 (ja) | 半導体装置およびその製造方法、並びに電力変換システム | |
WO2018207394A1 (ja) | 半導体装置及びその製造方法 | |
WO2021177422A1 (ja) | 半導体装置、半導体装置の製造方法および半導体装置を備えた電力変換装置 | |
JP2018011030A (ja) | 逆阻止mos型半導体装置および逆阻止mos型半導体装置の製造方法 | |
CN104716174B (zh) | 半导体器件以及用于制造半导体器件的方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 201080049553.6 Country of ref document: CN |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 10826917 Country of ref document: EP Kind code of ref document: A1 |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2011538528 Country of ref document: JP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 112010004241 Country of ref document: DE Ref document number: 1120100042411 Country of ref document: DE |
|
ENP | Entry into the national phase |
Ref document number: 20127012023 Country of ref document: KR Kind code of ref document: A |
|
WWE | Wipo information: entry into national phase |
Ref document number: 13505294 Country of ref document: US |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 10826917 Country of ref document: EP Kind code of ref document: A1 |