WO2013147274A1 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- WO2013147274A1 WO2013147274A1 PCT/JP2013/059775 JP2013059775W WO2013147274A1 WO 2013147274 A1 WO2013147274 A1 WO 2013147274A1 JP 2013059775 W JP2013059775 W JP 2013059775W WO 2013147274 A1 WO2013147274 A1 WO 2013147274A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- layer
- semiconductor substrate
- annealing
- semiconductor
- irradiation
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 276
- 238000004519 manufacturing process Methods 0.000 title claims description 65
- 239000000758 substrate Substances 0.000 claims abstract description 173
- 238000000137 annealing Methods 0.000 claims abstract description 138
- 230000001133 acceleration Effects 0.000 claims abstract description 48
- 238000000034 method Methods 0.000 claims description 36
- 239000012535 impurity Substances 0.000 claims description 33
- 230000001678 irradiating effect Effects 0.000 claims description 11
- 230000005684 electric field Effects 0.000 claims description 4
- 229920006395 saturated elastomer Polymers 0.000 claims description 4
- 230000003213 activating effect Effects 0.000 claims 2
- 239000010410 layer Substances 0.000 abstract description 293
- 239000013078 crystal Substances 0.000 abstract description 13
- 230000007547 defect Effects 0.000 abstract description 13
- 239000002344 surface layer Substances 0.000 abstract description 7
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 230000005855 radiation Effects 0.000 abstract 4
- 230000001668 ameliorated effect Effects 0.000 abstract 1
- 230000010355 oscillation Effects 0.000 description 30
- 239000000386 donor Substances 0.000 description 14
- 238000010586 diagram Methods 0.000 description 12
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 9
- 229910052739 hydrogen Inorganic materials 0.000 description 9
- 239000001257 hydrogen Substances 0.000 description 9
- 239000000969 carrier Substances 0.000 description 6
- 238000009826 distribution Methods 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 6
- 230000007423 decrease Effects 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 230000004913 activation Effects 0.000 description 3
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000000227 grinding Methods 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 238000003892 spreading Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- SLXKOJJOQWFEFD-UHFFFAOYSA-N 6-aminohexanoic acid Chemical compound NCCCCCC(O)=O SLXKOJJOQWFEFD-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 238000000691 measurement method Methods 0.000 description 2
- 238000011084 recovery Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000001629 suppression Effects 0.000 description 2
- 238000010408 sweeping Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- -1 boron ions Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000000852 hydrogen donor Substances 0.000 description 1
- 238000001802 infusion Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/15—Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
- H01L29/151—Compositional structures
- H01L29/152—Compositional structures with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
- H01L29/155—Comprising only semiconductor materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
Definitions
- the present invention relates to a method of manufacturing a semiconductor device.
- IGBTs Insulated Gate Bipolar Transistors
- diodes Diodes
- breakdown voltage classes for example, breakdown voltages of 400 V, 600 V, 1200 V, 1700 V, 3300 V or more. Is known.
- power semiconductor devices are used in power converters such as converters and inverters.
- the following method is known as a method of manufacturing the power semiconductor device.
- a front surface element structure is formed on the front surface of the semiconductor substrate.
- the back surface of the semiconductor substrate is removed by grinding or the like to thin the semiconductor substrate.
- impurity ions are implanted into the ground back surface of the semiconductor substrate.
- the impurity implanted into the back surface of the semiconductor substrate is activated by heat treatment to form a back surface element structure.
- various methods have been proposed in which a semiconductor substrate is irradiated with protons and a high concentration n + layer is formed inside the semiconductor substrate by utilizing the phenomenon of proton activation (donation) by heat treatment. ing.
- n + layers composed of hydrogen donors are formed by plural times of proton irradiation, and a depth of the deepest n + layer from the back surface of the substrate is 15 ⁇ m (for example, See Patent Document 3 below).
- Patent Document 2 describes that the crystal defects generated at the time of proton irradiation are recovered under a predetermined heat treatment condition, the proton irradiation is two irradiation conditions, which is a difference in dose amount , With different acceleration voltages.
- FIG. 15 is a characteristic diagram showing the relationship between the average range of conventional proton irradiation and the carrier concentration.
- FIG. 15 shows carrier concentration distributions when annealing treatment is performed at the same temperature for each average range when the average range Rp of proton irradiation is around 15 ⁇ m and deeper.
- FIG. 15 (a) shows the case where the average range Rp of proton irradiation is 50 ⁇ m
- FIG. 15 (b) shows the case where the average range of proton irradiation is 20 ⁇ m
- FIG. 15 (c) The case where the average range of proton irradiation is 15 micrometers is shown.
- the average range Rp of proton irradiation in FIG. 15C is 15 ⁇ m
- the carrier concentration in the vicinity of the irradiation surface (depth: 0 ⁇ m to 5 ⁇ m) and in the proton passage region is 1 ⁇ 10 14 It is higher than cm 3 ) and disorder is sufficiently reduced.
- the average range Rp of proton irradiation exceeds 15 ⁇ m, the decrease in carrier mobility due to residual disorder becomes remarkable.
- the proton irradiation for forming the deepest n + layer from the irradiation surface is made the first time by three times of proton irradiation, and the second and third proton irradiations are performed in the order of shallowing toward the irradiation surface.
- the case of performing will be described as an example.
- n + layer by proton irradiation is formed in the deepest position from the irradiation surface than the n + layer by 2,3 th proton irradiation. Therefore, the proton acceleration energy of the first proton irradiation is set to the highest of the first to third proton irradiations. Therefore, the crystallinity damage of the semiconductor substrate given to the passage region of protons from the irradiated surface to the average range Rp of protons is the highest among the three proton irradiations.
- the annealing temperatures required to form the plurality of n + layers are often different. Therefore, in the case where annealing is performed collectively after a plurality of proton irradiations, maintaining a high carrier concentration in the n + layer by proton irradiation and reducing the disorder of the proton passage region can be sufficiently achieved at the same time. It becomes difficult.
- the present invention recovers each crystal defect formed by each proton irradiation by annealing using annealing conditions adapted to the conditions of a plurality of proton irradiations in order to solve the problems due to the prior art described above.
- An object of the present invention is to provide a method of manufacturing a semiconductor device in which a plurality of regions with high carrier concentration can be formed.
- Another object of the present invention is to provide a method of manufacturing a semiconductor device capable of improving the electrical characteristic failure such as the increase of the leakage current.
- a method of manufacturing a semiconductor device has the following features. First, an irradiation step of irradiating protons from the back surface of the semiconductor substrate of the first conductivity type is performed. Next, an annealing process is performed to activate the protons irradiated to the back surface of the semiconductor substrate to form a first semiconductor layer of the first conductivity type having a higher impurity concentration than the semiconductor substrate. Then, a plurality of the first semiconductor layers are formed in the depth direction of the semiconductor substrate by performing the irradiation process and the annealing process a plurality of times in combination according to the irradiation conditions of the irradiation process.
- the irradiating step sets the acceleration voltage higher as the depth of the region where the first semiconductor layer is formed from the back surface of the semiconductor substrate is deeper.
- the annealing temperature is set higher as the depth of the region for forming the first semiconductor layer from the back surface of the semiconductor substrate is deeper.
- the combination of the irradiation step and the annealing step is characterized in that the combination is performed in order from the combination where the first semiconductor layer is at the deepest position from the back surface of the semiconductor substrate.
- one annealing is performed after a plurality of irradiation steps in the set of irradiation steps and the annealing step.
- the first semiconductor layer is a field stop layer which suppresses the spread of a depletion layer.
- the number of first semiconductor layers formed by the irradiation step and the annealing step may be the thickness of the semiconductor substrate or the rated voltage or both of them.
- the semiconductor device is an insulated gate bipolar transistor.
- the semiconductor device is a diode.
- the method of manufacturing a semiconductor device further has the following features in the above-described invention.
- a drift layer of the first conductivity type comprising the semiconductor substrate is provided, a second semiconductor layer of the second conductivity type is formed on the front surface of the semiconductor substrate, q is a charge, N d is the drift layer average density, the dielectric constant of the epsilon S the semiconductor substrate, the rated voltage V rate, the rated current density J F, the v sat as saturation velocity the speed of the carrier is saturated at a predetermined field strength, the distance index L is below the It is expressed by equation (1).
- the depth from the back surface of the semiconductor substrate at a position where the carrier concentration of the first semiconductor layer closest to the second semiconductor layer is a peak concentration is X, and the thickness of the semiconductor substrate is W 0
- the ⁇ is 0.9 or more and 1.4 or less.
- the ⁇ is 1.0 or more and 1.3 or less.
- a method of manufacturing a semiconductor device has the following features. First, an irradiation step of irradiating protons from the back surface of the semiconductor substrate of the first conductivity type is performed. Next, an annealing process is performed to activate the protons irradiated to the back surface of the semiconductor substrate to form a first semiconductor layer of the first conductivity type having a higher impurity concentration than the semiconductor substrate. Then, a plurality of the first semiconductor layers are formed in the depth direction of the semiconductor substrate by performing the irradiation step and the annealing step as a set a plurality of times.
- the first annealing step among the plurality of annealing steps which is a set of first irradiation steps for irradiating protons to the deepest position from the back surface of the semiconductor substrate among the plurality of irradiation steps.
- the annealing temperature is set to 380 ° C. or more and 450 ° C. or less.
- Annealing in the second annealing step among the plurality of annealing steps which is a set of second irradiation steps in which protons are irradiated to the second deepest position from the back surface of the semiconductor substrate among the plurality of irradiation steps.
- the temperature is set to 350 ° C. or more and 420 ° C. or less.
- Annealing in the third annealing step among the plurality of annealing steps which is a set of third irradiation steps in which protons are irradiated to the third deepest position from the back surface of the semiconductor substrate among the plurality of irradiation steps.
- the temperature is set to 340 ° C. or more and 400 ° C. or less.
- the annealing temperature in the first annealing step is 400 ° C. or more and 420 ° C. or less
- the annealing temperature in the second annealing step is 370 ° C. or more
- the annealing temperature of the third annealing step is set higher than 350.degree. C. and lower than 370.degree. C.
- a method of manufacturing a semiconductor device has the following features. First, an irradiation step of irradiating protons from the back surface of the semiconductor substrate of the first conductivity type is performed. Next, an annealing process is performed to activate the protons irradiated to the back surface of the semiconductor substrate to form a first semiconductor layer of the first conductivity type having a higher impurity concentration than the semiconductor substrate. At this time, depending on the irradiation conditions of the irradiation step, the irradiation step and the annealing step are performed in combination one or more times, thereby performing the process in the depth direction of the semiconductor substrate a plurality of times. A plurality of first semiconductor layers are formed.
- acceleration energy E of protons when forming the first semiconductor layer of the range Rp by irradiation of protons The following equation (2) is satisfied, where x is the logarithm log (Rp) of Rp and y is the logarithm log (E) of the acceleration energy E.
- a plurality of first semiconductors are formed by combining proton irradiation and annealing, and defining the conditions of proton irradiation and annealing according to the position of the first semiconductor layer to be formed on the semiconductor substrate. Any impurity concentration in the layer can be increased. Then, by performing annealing using annealing conditions adapted to a plurality of times of proton irradiation, each crystal defect formed by each proton irradiation can be recovered and each carrier concentration can be increased. In addition, it is possible to improve the electrical characteristic failure such as the increase of the leakage current.
- each crystal defect formed by each proton irradiation is recovered by annealing using annealing conditions adapted to a plurality of times of proton irradiation, and thus a high carrier concentration is obtained. There is an effect that a plurality of regions can be formed. In addition, it is possible to improve the electric characteristic failure such as the increase of the leakage current.
- FIG. 1 is a cross-sectional view showing an example of a semiconductor device manufactured by the method of manufacturing a semiconductor device according to the first embodiment.
- FIG. 2 is a flowchart showing an outline of a method of manufacturing a semiconductor device according to the first embodiment.
- FIG. 3 is a cross-sectional view showing the semiconductor device in the process of manufacturing according to the first embodiment.
- FIG. 4 is a cross-sectional view showing the semiconductor device in the process of manufacturing according to the first embodiment.
- FIG. 5 is a cross-sectional view showing the semiconductor device in the process of manufacturing according to the first embodiment.
- FIG. 6 is a cross-sectional view showing the semiconductor device in the process of manufacturing according to the first embodiment.
- FIG. 1 is a cross-sectional view showing an example of a semiconductor device manufactured by the method of manufacturing a semiconductor device according to the first embodiment.
- FIG. 2 is a flowchart showing an outline of a method of manufacturing a semiconductor device according to the first embodiment.
- FIG. 3 is a cross-
- FIG. 7 is a cross-sectional view showing the semiconductor device in the process of manufacturing according to the first embodiment.
- FIG. 8 is a cross-sectional view showing the semiconductor device in the process of manufacturing according to the first embodiment.
- FIG. 9 is a cross-sectional view showing the semiconductor device in the process of manufacturing according to the first embodiment.
- FIG. 10 is a cross-sectional view showing the semiconductor device in the process of manufacturing according to the first embodiment.
- FIG. 11 is a cross-sectional view showing the semiconductor device during manufacture according to the first embodiment.
- FIG. 12 is a cross-sectional view showing the semiconductor device in the process of manufacturing according to the first embodiment.
- FIG. 13 is a cross-sectional view showing an example of a semiconductor device manufactured by the method of manufacturing a semiconductor device according to the second embodiment.
- FIG. 14 is a characteristic diagram showing carrier concentration distribution of the semiconductor device according to the example.
- FIG. 15 is a characteristic diagram showing the relationship between the average range of conventional proton irradiation and the carrier concentration.
- FIG. 16 is a characteristic diagram showing the threshold voltage at which the voltage waveform starts to vibrate.
- FIG. 17 is a characteristic diagram showing the turn-off oscillation waveform of a general IGBT.
- FIG. 18 is a characteristic diagram showing the relationship between the average range of protons and the acceleration energy of protons in the semiconductor device according to the present invention.
- FIG. 19 is a chart showing the position condition of the field stop layer which the depletion layer first reaches in the semiconductor device according to the present invention.
- FIG. 20 is an explanatory drawing showing the depth from the interface between the emitter electrode of the field stop layer of the semiconductor device according to the first embodiment and the front surface of the substrate.
- FIG. 21 is an explanatory drawing showing the depth from the interface between the anode electrode of the field stop layer of the semiconductor device according to the second embodiment and the front surface of the substrate.
- n and p in the layer or region having n or p, it is meant that electrons or holes are majority carriers, respectively.
- + and-attached to n and p mean that the impurity concentration is higher and the impurity concentration is lower than that of the layer or region to which it is not attached, respectively.
- FIG. 1 is a cross-sectional view showing an example of a semiconductor device manufactured by the method of manufacturing a semiconductor device according to the first embodiment.
- the impurity concentration distribution in the depth direction of the semiconductor substrate from the boundary between the emitter electrode 7 and the n ++ emitter region 3 is shown.
- the p base region 2 is formed on the surface layer on the front side inside the semiconductor substrate to be the n ⁇ drift layer 1. Is provided.
- An n ++ emitter region 3 is provided in the p base region 2 so as to be exposed to the front surface of the semiconductor substrate.
- the impurity concentration of the n ++ emitter region 3 is higher than the impurity concentration of the n ⁇ drift layer 1.
- a trench 4 which penetrates the n ++ emitter region 3 and the p base region 2 to reach the n ⁇ drift layer 1 is provided.
- a gate insulating film 5 is provided along the sidewalls and the bottom of trench 4. Inside the trench 4, a gate electrode 6 is provided inside the gate insulating film 5 so as to be embedded in the trench 4.
- Emitter electrode 7 is in contact with p base region 2 and n ++ emitter region 3. Emitter electrode 7 is electrically insulated from gate electrode 6 by interlayer insulating film 8. Further, p + collector layer 9 is provided in the surface layer on the back surface side inside the semiconductor substrate to be n ⁇ drift layer 1, and as a first semiconductor layer in a region deeper than p + collector layer 9 on the back surface side. An n + field stop (FS) layer 10 is provided. The n + field stop layer 10 is composed of a plurality of n + layers 10 a to 10 c formed at different positions in the depth direction of the semiconductor substrate. Collector electrode 11 is in contact with p + collector layer 9. The impurity concentration of the p + collector layer 9 is high enough to obtain an ohmic contact with the collector electrode 11.
- each of the n + layers 10a to 10c is provided with a uniform thickness.
- the n + layer 10 c located on the backmost side of the semiconductor substrate may be separated from the p + collector layer 9 or may be in contact with the p + collector layer 9.
- the impurity concentration of the n + field stop layer 10 is higher than the impurity concentration of the n ⁇ drift layer 1.
- the n + field stop layer 10 is a semiconductor layer by a hydrogen induced donor.
- the hydrogen-induced donor is a donor induced from a complex lattice defect including hydrogen atoms introduced in the depth direction of the semiconductor substrate by proton irradiation and vacancies and double vacancies around the hydrogen atom.
- FIG. 2 is a flowchart showing an outline of a method of manufacturing a semiconductor device according to the first embodiment.
- each semiconductor region to be a contact of the front surface electrode is formed on the front surface of the semiconductor substrate (step S1). ).
- a front surface electrode is formed on the front surface of the semiconductor substrate (step S2).
- a surface protection film is formed on the front surface of the semiconductor substrate (step S3).
- the back surface of the semiconductor substrate is removed by grinding or etching to uniformly thin (thin) the thickness of the semiconductor substrate (step S4).
- step S5 proton irradiation for forming an n + field stop layer is performed on the back surface of the semiconductor substrate (step S5).
- the proton irradiation in step S5 is performed with irradiation energy capable of irradiating a region deeper than the semiconductor layer to be in contact with the back electrode.
- the protons irradiated in step S5 are activated (donated) by the first annealing (step S6).
- activation means, in addition to forming hydrogen-induced donors, also reducing a large amount of crystal defects (crystal disorder, disorder) introduced into the semiconductor substrate by proton irradiation. Remaining disorder causes an increase in leakage current and on voltage (voltage drop when conducting).
- an n + field stop layer is formed in the deep region on the back surface side inside the semiconductor substrate.
- the temperature of the first annealing in step S6 is preferably, for example, a temperature that does not reduce or eliminate the hydrogen-induced donor formed by proton irradiation.
- n + layer 10a to 10c in the case of forming a plurality of n + layers 10a to 10c in the depth direction of the semiconductor substrate, proton irradiation is performed from the back surface side of the semiconductor substrate.
- the n + layer 10b is formed from the n + layer 10a closer to the p base region 2 to the back surface side of the semiconductor substrate, the n + layer 10c is formed.
- the proton irradiation in step S5 and the first annealing in step S6 are combined to repeat steps S5 and S6 for the number of n + layers provided.
- the acceleration voltage for proton irradiation in step S5 is higher as the depth is higher
- the annealing temperature in step S6 is higher as the depth is higher, corresponding to the depth of the n + layers 10a to 10c.
- the higher the annealing temperature the lower the donor conversion rate.
- the n + layer 10a at a deep position as viewed in the depth direction from the back surface of the semiconductor substrate is formed first, and then the back surface of the semiconductor substrate After the n + layer 10 b is formed on the side, the n + layer 10 c on the back surface side is formed. Adjacent n + layers may be in contact with or separated from each other.
- the donor rate, in one of the n + layer, irradiation (infusion) was in a dose of protons
- the integration density obtained by integrating the doping concentration of the n + layer in the depth direction in a range of width of the n + layer It is a rate when it was divided.
- the dose amount of protons is 1 ⁇ 10 14 / cm 2
- the integrated concentration of one n + layer is 1 ⁇ 10 13 / cm 2
- the donor conversion rate is 10%.
- the width of the n + layer refers to, for example, the distance between two intersection points when the doping concentration of the n + layer decreases from the peak concentration toward the surface and the back, respectively, and extrapolated to the same value as the doping concentration of the semiconductor substrate. You can think of it as the distance of
- step S7 impurity ions for forming a semiconductor layer to be in contact with the back electrode are ion-implanted on the back surface of the thinned semiconductor substrate (step S7).
- the ion implantation in step S7 is performed at a dose high enough to obtain an ohmic contact with a back electrode to be formed in a later step.
- the impurity ions implanted in step S7 are activated by the second annealing (step S8).
- step S8 a semiconductor layer (for example, a collector layer) to be in contact with the back electrode is formed on the back surface side surface layer inside the semiconductor substrate.
- a back surface electrode is formed on the back surface of the semiconductor substrate by physical vapor deposition such as sputtering (step S9), and the semiconductor device according to the first embodiment is completed.
- FIG. 3 to 12 are cross-sectional views showing the semiconductor device in the process of manufacturing according to the first embodiment.
- a semiconductor substrate to be the n ⁇ drift layer 1 is prepared.
- a gate-type MOS (metal-oxide-semiconductor insulated gate) structure is formed.
- an aluminum silicon (AlSi) film to be the emitter electrode 7 is deposited on the front surface of the semiconductor substrate by sputtering.
- AlSi aluminum silicon
- annealing is performed.
- the emitter electrode 7 is formed on the front surface of the semiconductor substrate.
- a polyimide film to be a surface protective film (not shown) is coated on the front surface of the semiconductor substrate so as to cover the emitter electrode 7.
- the polyimide film is patterned to expose a part of the emitter electrode 7, and then the polyimide film is cured (baked).
- the back surface of the semiconductor substrate is ground, for example, to thin the semiconductor substrate, and then the semiconductor substrate is washed to remove deposits.
- n + layers 10 a to 10 c are formed in the depth direction of the n ⁇ drift layer 1 of the semiconductor substrate.
- the first n + layer 10a is formed.
- protons 21a are irradiated to the deepest region separated by a predetermined amount from the back surface of the semiconductor substrate.
- the acceleration voltage for proton irradiation is performed at the highest value according to the depth from the back surface of the semiconductor substrate.
- the depth from the back surface of the n + layer may be 3 MeV when the depth is about 100 ⁇ m, 2 MeV when the depth is about 50 ⁇ m, and 1 MeV or less when the depth is about 20 ⁇ m or less.
- the acceleration energy of the corresponding proton is 2.31 MeV.
- the depth from the back surface of the substrate of the n + layer 10a is, depending on the rated voltage of the device, a typical range of 20 ⁇ m to 100 ⁇ m.
- the range of acceleration energy of protons corresponding to this depth range is, for example, 1.17 MeV to 3.13 MeV.
- the dose of proton irradiation may be determined according to the peak concentration of the n + layer to be formed.
- the dose of proton irradiation may be 1 ⁇ 10 11 / cm 2 or more and 1 ⁇ 10 15 / cm 2 or less.
- the irradiated protons 21a are activated by the first annealing to form an n + layer 10a in a deep region separated by a predetermined amount from the back surface of the semiconductor substrate.
- the n + layer 10a is formed at the highest temperature among the plurality of n + layers 10a to 10c to be formed, corresponding to the depth from the back surface of the semiconductor substrate. For example, it is 400 ° C.
- the first n + layer 10a having a high impurity concentration is formed on the side closest to the p base region 2 on the surface side of the semiconductor substrate.
- the annealing temperature required for the deepest n + layer 10a from the back surface of the substrate is, for example, 380 ° C. or more and 450 ° C. or less, preferably 400 ° C. or more and 420 ° C. or less.
- the second n + layer 10 b is formed. Specifically, as shown in FIG. 8, protons 21b are irradiated to a region shallower than the n + layer 10a by a predetermined distance from the back surface of the semiconductor substrate.
- the acceleration voltage for proton irradiation is a value corresponding to the depth from the back surface of the semiconductor substrate, and is a medium value lower than the acceleration voltage at the time of forming the n + layer 10a. For example, when the depth from the back surface of the substrate of the n + layer 10b is 30 ⁇ m, the acceleration energy of the corresponding proton is 1.5 MeV.
- the depth from the back surface of the substrate of the n + layer 10b is typically in the range of 10 ⁇ m to 50 ⁇ m, although it depends on the rated voltage of the device.
- the range of acceleration energy of protons corresponding to this depth range is, for example, 0.74 MeV to 2.07 MeV.
- the irradiated protons 21b are activated by the first annealing, separated from the back surface of the semiconductor substrate by a predetermined amount, and an n + layer 10b is formed at a position shallower than the n + layer 10a.
- the n + layer 10 b is formed at a middle temperature among the plurality of n + layers 10 a to 10 c to be formed, corresponding to the depth from the back surface of the semiconductor substrate (n + Temperature below the annealing temperature when forming the layer 10a).
- the annealing temperature for forming the n + layer 10 b is 380 ° C.
- the second n + layer 10b having a high impurity concentration is formed in a region further away from the n + layer 10a when viewed from the p base region 2 on the front surface side of the semiconductor substrate. It can be formed.
- the annealing temperature required for the second deep n + layer 10b from the rear surface of the substrate is, for example, 350 ° C. or more and 420 ° C. or less, preferably 370 ° C. or more and 390 ° C. or less.
- a third n + layer 10c is formed.
- protons 21c are irradiated to a region shallower than the n + layer 10b by a predetermined distance from the back surface of the semiconductor substrate.
- the acceleration voltage for proton irradiation is a value corresponding to the depth from the back surface of the semiconductor substrate, and is lower than the acceleration voltage at the time of the formation of the n + layer 10b, and is the lowest value.
- the acceleration energy of the corresponding proton is 0.74 MeV.
- the depth of the n + layer 10c from the back surface of the substrate is typically 5 ⁇ m to 20 ⁇ m.
- the range of acceleration energy at this time is, for example, 0.45 MeV to 1.17 MeV.
- the irradiated protons 21c are activated by the first annealing to form an n + layer 10c at a position shallower than the n + layer 10b away from the back surface of the semiconductor substrate by a predetermined amount.
- the n + layer 10 c is formed at the lowest temperature among the plurality of n + layers 10 a to 10 c to be formed corresponding to the depth from the back surface of the semiconductor substrate (n + Temperature below the annealing temperature when forming the layer 10 b).
- the annealing temperature for forming the n + layer 10 c is 360 ° C.
- a third n + layer 10c having a high impurity concentration is formed in a region further away from the n + layer 10b when viewed from the p base region 2 on the surface side of the semiconductor substrate.
- the annealing temperature required for the n + layer 10c which is third deep from the back surface of the substrate is, for example, 340 ° C. or more and 400 ° C. or less, preferably 350 ° C. or more and 370 ° C. or less, more preferably Is to make the lower limit value greater than 350.degree.
- the first annealing performed a plurality of times is preferably performed, for example, at a temperature that does not reduce or eliminate the hydrogen-induced donor formed by proton irradiation.
- the annealing time may be 0.5 hours to 10 hours.
- p-type impurity ions such as boron ions (B.sup. + ) are ion-implanted on the ground back surface of the semiconductor substrate.
- p-type impurity ions implanted into the back surface of the semiconductor substrate are activated by the second annealing to form the p + collector layer 9 in the surface layer on the back surface of the semiconductor substrate.
- a hydrogen fluoride (HF) treatment for reducing the contact resistance between the silicon (Si) semiconductor layer and the aluminum film as a pretreatment for forming the collector electrode 11 made of a metal mainly composed of aluminum I do.
- proton irradiation and annealing are alternately performed by combining proton irradiation and first annealing.
- the combination of the proton irradiation step and the annealing step was sequentially performed from the pair where the n + field stop layer 10 is at the deepest position from the back surface of the semiconductor substrate.
- the annealing temperature required to form the n + layers 10a to 10c is the same among the first annealing performed a plurality of times, one annealing is performed after a plurality of proton irradiations to perform a plurality of n + Layer may be formed.
- annealing temperatures of the n + layers 10 b and 10 c are the same, proton irradiation is performed twice for the n + layers 10 b and 10 c under different conditions, and then collectively 1 under one condition (annealing temperature). Annealing may be performed, in which case the number of annealings can be reduced and the number of manufacturing steps can be reduced.
- the part of the first annealing and the second annealing may be performed simultaneously.
- the temperatures of the first annealing and the second annealing are lower than the previously performed annealing.
- the second annealing may be performed simultaneously with the metal annealing.
- a plurality of (multi-stage) n + layers may be formed using, for example, the following three conditions.
- the first condition is that the dose of protons in n + layer per unit is lower (5 ⁇ 10 12 / cm 2 to 5 ⁇ ) as the n + layer is located deeper from the irradiated surface (substrate back surface) 10 13 / cm 2 ).
- the dose amount low, the crystalline damage due to the high acceleration energy is reduced by the low dose amount.
- the second condition is, the n + layer is closer to the irradiation surface, that is, as an n + layer becomes shallow, the dose of the proton of the n + layer per one enhances (3 ⁇ 10 13 / cm 2 ⁇ 3 ⁇ 10 14 / cm 2 ).
- the damage to the crystallinity is smaller than when the acceleration energy is high, and therefore the dose amount of proton may be increased accordingly.
- the third condition is that the disorder in the vicinity of (the most shallow) n + layer 10c closest to the irradiated surface is higher in residual amount compared to the n + layers 10a and 10b deep from the back side of other substrates. It is a good point.
- the residual amount of disorder may be considered to be a rate at which the carrier mobility is lower than the theoretical value of the crystal in a flat state.
- the depletion layer extending from the pn junction between the p base region 2 and the n ⁇ drift layer 1 may be designed not to spread further deeper by suppressing its extension with the shallowest n + layer 10 c.
- the plurality of n + layers 10 a to 10 c having high impurity concentrations in the depth direction of the semiconductor substrate are formed as the n + field stop layer 10.
- the (multistage) n + layers 10a to 10c prevent the depletion layer extending from the pn junction between the p base region 2 and the n ⁇ drift layer 1 from reaching the p + collector layer 9.
- the impurity concentrations of the plurality of n + layers can be all Will be able to enhance.
- annealing using annealing conditions adapted to the conditions of multiple proton irradiations it is possible to recover each crystal defect formed by each proton irradiation and to increase each carrier concentration.
- electrical characteristic failure such as the increase of the leakage current.
- the number of the plurality of n + layers 10a to 10c formed as the n + field stop layer 10 can be set according to the thickness of the semiconductor substrate, the withstand voltage class (or rated voltage) of the semiconductor element, or the like.
- FIG. 13 is a cross-sectional view showing an example of a semiconductor device manufactured by the method of manufacturing a semiconductor device according to the second embodiment.
- the semiconductor device manufacturing method according to the second embodiment is different from the semiconductor device manufacturing method according to the first embodiment in that a diode is manufactured instead of the IGBT.
- p + anode region 32 is formed in the surface layer on the front surface side inside n ⁇ type semiconductor substrate 31. It is provided selectively.
- Reference numeral 34 denotes an interlayer insulating film.
- the anode electrode (input electrode) 33 is in contact with the p + anode region 32.
- an n + cathode layer (first semiconductor layer) 35 is provided in the surface layer on the back surface side inside the n ⁇ -type semiconductor substrate 31, and n + in a region deeper than the n + cathode layer 35 on the back surface side.
- a field stop layer 36 is provided.
- the n + field stop layer 36 is composed of a plurality of n + layers 36 a to 36 c in the depth direction of the semiconductor substrate.
- the cathode electrode (output electrode) 37 is in contact with the n + cathode layer 35.
- the impurity concentration of the n + cathode layer 35 is high enough to obtain ohmic contact with the cathode electrode 37.
- the above-described second embodiment can also be manufactured by the same process as the first embodiment.
- a plurality of n + layers can be formed by performing proton irradiation and annealing as a set and changing the conditions a plurality of times. Then, by performing annealing using annealing conditions adapted to a plurality of times of proton irradiation, the concentration (doping concentration) of the hydrogen-induced donor layer formed by each proton irradiation can be increased. In addition, by recovering each crystal defect (disorder) introduced by proton irradiation, it is possible to improve the electrical characteristic failure such as the increase of the leakage current. Then, according to the second embodiment, even in forming a diode, an n + field stop layer having a desired doping concentration can be formed.
- FIG. 14 is a characteristic diagram showing the carrier concentration distribution of the semiconductor device according to the example measured by the well-known spread resistance measurement method.
- a sample subjected to proton irradiation (step S5) and first annealing (step S6) was prepared (hereinafter referred to as an example).
- the depth of the n + layer 10a from the back surface of the semiconductor substrate is the deepest, and the accelerating voltage at the time of proton irradiation is the highest.
- the depth of the n + layer 10c from the back surface of the semiconductor substrate is the smallest, and the accelerating voltage at the time of proton irradiation is the lowest.
- the values of the acceleration voltage are the n + layer 10 a, the n + layer 10 b, and the n + layer 10 c in descending order according to the depth.
- the annealing temperature the higher order n + layer 10a, the n + layer 10b, the n + layer 10c.
- the annealing temperature is, the n + layer 10a is 450 ° C., the n + layer 10b and the n + layer 10c is 380 ° C..
- the n + layer 10 b and the n + layer 10 c can be performed by one annealing (temperature 380 ° C.) after two proton irradiations.
- the impurity concentration can be increased as the plurality of n + layers 10a to 10c in the depth direction of the semiconductor substrate.
- the disorder introduced by proton irradiation can be sufficiently reduced.
- a hydrogen induced donor layer having a high activation rate can be obtained since each of the regions of the n + layers 10a to 10c shows a high impurity concentration.
- n + layers 10a to 10c are collectively annealed at one and the same temperature, and when the annealing temperature is low, the disordered layer is formed by proton irradiation, so that electrons and holes are generated. Since the mobility is lowered, there is a region where the impurity concentration is extremely lowered except at the portions of the n + layers 10a to 10c. However, this can be prevented in the embodiment of the present invention.
- the concentration of the hydrogen-induced donor layer decreases or disappears, and the semiconductor
- the impurity concentration of the n + layer 10c shallower than the back surface of the substrate is reduced.
- the reduction of hydrogen induced donors could be suppressed.
- the first n + field stop layer is the n + field stop layer located at the deepest position in the substrate depth direction from the back surface of the substrate on the cathode layer side in the case of a diode and the collector layer side in the case of an IGBT It is
- FIG. 17 is a characteristic diagram showing the turn-off oscillation waveform of a general IGBT. If the collector current is 1/10 or less of the rated current, oscillation may occur before the turn-off ends because the accumulated carriers are small. With the collector current fixed at a certain value, the IGBT is turned off at different power supply voltages V CC . At this time, when the power supply voltage V CC exceeds a predetermined value, an additional overshoot occurs in the collector-emitter voltage waveform after exceeding the peak value of the normal overshoot voltage. Then, this additional overshoot (voltage) triggers the subsequent waveform to vibrate.
- the threshold voltage at which the voltage waveform starts to oscillate is called the oscillation start threshold V RRO . It is preferable that the higher the oscillation start threshold value V RRO is, because it indicates that the IGBT does not oscillate at turn-off.
- V RRO is p base region of the IGBT and the n - n from the pn junction between the drift layer - depletion layer extending the drift layer (strictly speaking, the space charge region so that holes are present), more It depends on the position of the proton peak of the first stage (most p base region side) which reaches first among the proton peaks of. The reason is as follows.
- the depletion layer extends along the depth direction from the pn junction between the p base region and the n ⁇ drift layer toward the collector electrode. Therefore, the peak position of the n + field stop layer depletion end first reaches the, p base region and the n - the nearest n + field stop layer pn junction between the drift layer. Therefore, the thickness of the semiconductor substrate (the thickness of the portion sandwiched between the emitter electrode and the collector electrode) is set to W 0, and the collector electrode and the semiconductor substrate at the peak position of the n + field stop layer where the depletion layer edge first reaches
- X be the depth from the interface (boundary) with the back surface (hereinafter referred to as the distance from the back surface).
- the distance index L is introduced.
- the distance index L is expressed by the following equation (3).
- the distance index L shown in the above equation (3) is derived from the pn junction between the p base region and the n ⁇ drift layer when the increasing collector-emitter voltage V CE matches the power supply voltage V CC at turn-off. It is an index indicating the distance from the pn junction to the end (depletion layer end) of the depletion layer (correctly, space charge region) spreading in the n ⁇ drift layer 1. In the interior fraction of the square root, the denominator indicates the space charge density of the space charge region (depletion layer) at turn-off.
- q is elementary charge
- p hole concentration
- n electron concentration
- N d donor concentration
- N a acceptor concentration
- ⁇ S is the dielectric constant of the semiconductor.
- the donor concentration N d is an average concentration obtained by integrating the n ⁇ drift layer in the depth direction and dividing by the distance of the integrated section.
- the space charge density ⁇ is described by the hole concentration p running through the space charge region (depletion layer) at turn-off and the average donor concentration N d of the n ⁇ drift layer, and the electron concentration is negligibly lower than these Since there is no acceptor, it can be expressed as ⁇ q q (p + N d ).
- the n + field stop layer has a function of making it difficult for the n + field stop layer to extend the expansion of the space charge region spreading at turn-off by making the doping concentration higher than that of the n ⁇ drift layer.
- FIG. 19 is a chart showing the position condition of the field stop layer which the depletion layer first reaches in the semiconductor device according to the present invention.
- n - the average drift layer Let it be resistivity. Average is the average concentration and resistivity of the entire n ⁇ drift layer including the n + field stop layer.
- the rated voltage V rate the typical values shown in the rated current density J F also Figure 19.
- the rated current density J F is set such that the energy density determined by the product of the rated voltage V rate and the rated current density J F has a substantially constant value, and is approximately the value shown in FIG.
- the distance index L is calculated according to the equation (3) using these values, the values are as shown in FIG.
- the distance X from the back surface of the peak position of the n + field stop layer reached by the end of the depletion layer first is the thickness W 0 of the semiconductor substrate with a value of ⁇ of 0.7 to 1.6 with respect to the distance index L It is the value subtracted from.
- FIG. 16 is a characteristic diagram showing the threshold voltage at which the voltage waveform starts to vibrate. Specifically, FIG. 16 shows the dependence of the oscillation start threshold V RRO on ⁇ , for several typical rated voltages V rate (600 V, 1200 V, 3300 V). Here, the vertical axis normalizes the oscillation start threshold V RRO with the rated voltage V rate . It can be seen that the oscillation start threshold V RRO can be rapidly increased when ⁇ is 1.5 or less for all three rated voltages.
- the operating voltage (power supply voltage V CC ) to be the voltage V is about half of the rated voltage V rate. Therefore, when the power supply voltage V CC is half the rated voltage V rate At least turn-off oscillation of the IGBT should be prevented. That is, the value of V RRO / V rate needs to be 0.5 or more. From FIG. 16, it is preferable that at least ⁇ be 0.2 to 1.5 because ⁇ is 0.2 or more and 1.5 or less for the value of V RRO / V rate to be 0.5 or more. .
- any rated voltage V rate is an area where the oscillation start threshold V RRO can be sufficiently high when ⁇ is in the range of 0.7 to 1.4.
- ⁇ is smaller than 0.7, although the oscillation start threshold V RRO is about 80% or more of the rated voltage V rate , the n + field stop layer becomes close to the p base region. It may be smaller than the rate . Therefore, ⁇ is preferably 0.7 or more. In addition, when ⁇ becomes larger than 1.4, the oscillation start threshold V RRO rapidly decreases from about 70% of the rated voltage V rate , and turn-off oscillation tends to occur. Therefore, ⁇ is preferably 1.4 or less. More preferably, the avalanche breakdown voltage of the element is sufficiently higher than the rated voltage V rate when ⁇ is in the range of 0.8 to 1.3, and more preferably in the range of 0.9 to 1.2. At the same time, the oscillation start threshold V RRO can be maximized .
- the distance (depth) of the space charge region end becomes about the distance index L shown in the above equation (3). If there is a peak position of the n + field stop layer which is deepest from the back surface at the position of L (ie, ⁇ is about 1.0), it is possible to suppress oscillation at the time of switching. And, since the power density is substantially constant, the distance index L becomes proportional to the rated voltage V rate . As a result, at any rated voltage V rate , the oscillation start threshold value V RRO can be sufficiently increased if ⁇ is set in a range substantially centered on 1.0, and the oscillation suppression effect at the time of switching can be maximized .
- the IGBT can sufficiently retain accumulated carriers at turn-off, and oscillation at turn-off The phenomenon can be suppressed. Therefore, at any rated voltage V rate , the distance X from the back surface of the peak position of the n + field stop layer to which the depletion layer edge first reaches is preferably such that the coefficient ⁇ of the distance index L is in the above range. Thereby, the oscillation phenomenon at turn-off can be effectively suppressed.
- the distance index L it can be seen that any rated voltage V rate is deeper than 20 ⁇ m. That is, the reason for setting the average range Rp of protons to form the deepest first-stage proton peak from the back of the substrate to be 20 ⁇ m or more deeper than 15 ⁇ m from the back of the substrate is just to maximize this oscillation suppression effect. is there.
- n + field stop layer in a region deeper than at least 15 ⁇ m from the back surface of the semiconductor substrate.
- index L and the preferable range of (gamma)
- FIG. 20 is an explanatory drawing showing the depth from the interface between the emitter electrode of the field stop layer of the semiconductor device according to the first embodiment and the front surface of the substrate.
- FIG. 20A shows a cross-sectional view of an IGBT in which a plurality of n + field stop layers are formed.
- the net doping concentration distribution along the cutting line AA 'in FIG. 20 (a) is the specific distance (depth) from the interface between the emitter electrode 7 and the front surface of the substrate. ) Is shown. Inside the p + collector layer 9 side of the n ⁇ drift layer 1, for example, three stages of n + field stop layers 10 having different depths from the back surface of the substrate are formed.
- the distance X from the rear surface of the substrate to the peak position of the deepest n + field stop layer 10 (n + layer 10a) from the rear surface of the substrate is 50 ⁇ m. This is the case where the distance index L is 58.2 ⁇ m and ⁇ is 1.2 based on the chart shown in FIG.
- the arrow L shown in FIG. 20B indicates, for example, the distance (length) from the pn junction 13 between the p base region 2 and the n ⁇ drift layer 1.
- Reference numeral 12 is an n buffer layer.
- FIG. 21 is an explanatory drawing showing the depth from the interface between the anode electrode of the field stop layer of the semiconductor device according to the second embodiment and the front surface of the substrate.
- FIG. 21A shows a cross-sectional view of a diode in which a plurality of n + field stop layers are formed.
- the net doping concentration distribution along the cutting line BB 'in FIG. 21 (a) is the specific distance (depth) from the interface between the anode electrode 33 and the front surface of the substrate. ) Is shown.
- n + cathode layer 35 side of the semiconductor substrate 31 to be an n ⁇ drift layer n + field stop layers 36 having different depths from the back surface are formed, for example, in three stages.
- the distance X from the back surface of the substrate to the peak position of the deepest n + field stop layer 36 (n + layer 36a) from the back surface of the substrate is 50 ⁇ m. This is a case where the distance index L is 58.2 ⁇ m and ⁇ is 1.2 based on the chart shown in FIG. Further, the arrow L illustrated in FIG. 21B indicates, for example, the distance (length) from the pn junction 38 between the p + anode region 32 and the n ⁇ drift layer.
- Embodiment 4 The acceleration energy of protons in the method of manufacturing a semiconductor device according to the present invention will be described as Embodiment 4.
- the acceleration energy of protons may be determined from the characteristic diagram of FIG. 18 shown below.
- FIG. 18 is a characteristic diagram showing the relationship between the average range of protons and the acceleration energy of protons in the semiconductor device according to the present invention.
- FIG. 18 is a characteristic diagram showing the above equation (4), which shows acceleration energy of protons for obtaining a desired average range Rp of protons.
- the horizontal axis of FIG. 18 is the logarithm log (Rp) of the average range Rp of protons, and shows the average range Rp ( ⁇ m) corresponding to the parenthesis below the axis value of log (Rp).
- the vertical axis is the logarithm log (E) of the acceleration energy E of proton, and the acceleration energy E of the corresponding proton is shown in the parentheses on the left side of the axis value of log (E).
- the acceleration energy E of proton irradiation is calculated (hereinafter referred to as a calculated value E) from the average range Rp of desired protons using the fitting formula shown in the above equation (4), and the calculated value E of this acceleration energy
- a calculated value E the acceleration energy E of proton irradiation is calculated (hereinafter referred to as a calculated value E) from the average range Rp of desired protons using the fitting formula shown in the above equation (4), and the calculated value E of this acceleration energy
- the actual average range Rp ′ is also about ⁇ 10% of the desired average range Rp It falls within the range and falls within the range of measurement error. Therefore, the variation of the actual average range Rp 'from the desired average range Rp has a negligible effect on the electrical characteristics of the diode or IGBT. Therefore, if the actual acceleration energy E 'is in the range of the calculated value E ⁇ 10%, it can be judged that the actual average range Rp' is substantially the average range Rp as set. Alternatively, there is no problem if the actual average range Rp 'falls within ⁇ 10% of the average range Rp calculated by applying the actual acceleration energy E' to the equation (4).
- the acceleration energy E and the average range Rp can fall within the above range ( ⁇ 10%)
- the actual acceleration energy E ′ and the actual average range Rp ′ are desired average ranges
- the range of the variation or error may be ⁇ 10% or less with respect to the average range Rp, and preferably within ⁇ 5%, it can be considered that the above equation (4) is satisfactorily followed.
- the acceleration energy E of protons necessary to obtain the average proton range Rp of the desired protons can be determined.
- Each acceleration energy E of the proton for forming the n + field stop layer described above also uses the above equation (4), and the spread resistance measurement of the sample actually irradiated with the proton with the above acceleration energy E ′ is known It agrees well with the measured value measured by the method. Therefore, by using the above equation (4), it is possible to predict the acceleration energy E of the necessary proton based on the average range Rp of the proton with extremely high accuracy.
- the present invention is not limited to the above embodiments, and can be applied to various semiconductor devices in which a field stop layer can be provided.
- the trench gate type IGBT has been described as an example in the first embodiment, it may be applied to a planar gate type IGBT.
- the impurity introduction method for forming the semiconductor layer (collector layer, cathode layer) to be in contact with the output electrode is not limited to ion implantation, and various changes can be made.
- the first conductivity type is n-type
- the second conductivity type is p-type.
- the present invention similarly applies the first conductivity type to p-type and the second conductivity type to n-type. It holds.
- the manufacturing method of the semiconductor device concerning the present invention is useful to the semiconductor device used for power conversion devices, such as a converter and an inverter.
Abstract
Description
まず、実施の形態1にかかる半導体装置の製造方法により作製(製造)される半導体装置の一例としてトレンチゲート型IGBTの構造について説明する。図1は、実施の形態1にかかる半導体装置の製造方法により製造される半導体装置の一例を示す断面図である。図1の紙面左側には、エミッタ電極7とn++エミッタ領域3との境界から半導体基板の深さ方向における不純物濃度分布を示す。図1に示す実施の形態1にかかる半導体装置の製造方法により製造される半導体装置において、n-ドリフト層1となる半導体基板の内部には、おもて面側の表面層にpベース領域2が設けられている。
図13は、実施の形態2にかかる半導体装置の製造方法により製造される半導体装置の一例を示す断面図である。実施の形態2にかかる半導体装置の製造方法が実施の形態1にかかる半導体装置の製造方法と異なる点は、IGBTに代えてダイオードを作製する点である。
次に、半導体層のドーピング濃度について検証した。図14は、周知の広がり抵抗(Spread Resistance)測定法によって測定した、実施例にかかる半導体装置のキャリア濃度分布を示す特性図である。実施の形態1にかかる半導体装置の製造方法に従い、プロトン照射(ステップS5)および第1アニール(ステップS6)を行った試料を用意した(以下、実施例とする)。
次に、本発明にかかる半導体装置の製造方法の複数回のプロトン注入において、1段目のn+フィールドストップ層のプロトンピーク位置の好ましい位置について、実施の形態3として説明する。1段目のn+フィールドストップ層とは、ダイオードの場合はカソード層側、IGBTの場合はコレクタ層側となる基板裏面から、基板の深さ方向で最も深い箇所に位置するn+フィールドストップ層のことである。
本発明にかかる半導体装置の製造方法におけるプロトンの加速エネルギーについて、実施の形態4として説明する。上記のγの範囲を満たすように、空乏層が最初に達するn+フィールドストップ層のピーク位置が基板裏面からの距離Xを有するように当該n+フィールドストップ層を実際にプロトン照射で形成するには、プロトンの加速エネルギーを、以下に示す図18の特性図から決めればよい。図18は、本発明にかかる半導体装置のプロトンの平均飛程とプロトンの加速エネルギーとの関係を示す特性図である。
2 pベース領域
3 n++エミッタ領域
4 トレンチ
5 ゲート絶縁膜
6 ゲート電極
7 エミッタ電極
8 層間絶縁膜
9 p+コレクタ層
10 n+フィールドストップ層
10a~10c n+層
11 コレクタ電極
Claims (14)
- 第1導電型の半導体基板の裏面から、プロトンを照射する照射工程と、
前記半導体基板の裏面に照射されたプロトンを活性化し、前記半導体基板よりも不純物濃度が高い第1導電型の第1半導体層を形成するアニール工程と、を含み、
前記照射工程の照射条件に応じて、前記照射工程と前記アニール工程とを組にして複数回行うことにより、前記半導体基板の深さ方向に、前記第1半導体層を複数形成することを特徴とする半導体装置の製造方法。 - 前記照射工程は、前記半導体基板の裏面から前記第1半導体層を形成する領域の深さが深いほど高い加速電圧とし、
前記アニール工程は、前記半導体基板の裏面から前記第1半導体層を形成する領域の深さが深いほど高いアニール温度とし、
前記照射工程および前記アニール工程の組は、前記第1半導体層が前記半導体基板の裏面から最も深い位置となる組から順に行うことを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記一組の照射工程とアニール工程において、複数回の照射工程の後に1回のアニールを行うことを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記第1半導体層は、空乏層の広がりを抑制するフィールドストップ層であることを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記照射工程および前記アニール工程により形成する前記第1半導体層の数は、前記半導体基板の厚さもしくは定格電圧あるいはこれらの両方に基づくことを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記半導体装置は、絶縁ゲート型バイポーラトランジスタであることを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記半導体装置は、ダイオードであることを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記半導体基板からなる第1導電型のドリフト層を備え、
前記半導体基板のおもて面には第2導電型の第2半導体層が形成され、
qを電荷素量、Ndを前記ドリフト層の平均濃度、εSを前記半導体基板の誘電率、Vrateを定格電圧、JFを定格電流密度、vsatをキャリアの速度が所定の電界強度で飽和した飽和速度として、距離指標Lが下記式(1)で表され、
前記第2半導体層に最も近い前記第1半導体層のキャリア濃度がピーク濃度となる位置の前記半導体基板の裏面からの深さをXとし、
前記半導体基板の厚さをW0としたときに、
X=W0-γLであり、γが0.2以上1.5以下となるように前記第2半導体層に最も近い前記第1半導体層のピーク濃度となる位置とすることを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記γが0.9以上1.4以下であることを特徴とする請求項8に記載の半導体装置の製造方法。
- 前記γが1.0以上1.3以下であることを特徴とする請求項9に記載の半導体装置の製造方法。
- 第1導電型の半導体基板の裏面からプロトンを照射する照射工程と、
前記半導体基板の裏面に照射されたプロトンを活性化し、前記半導体基板よりも不純物濃度が高い第1導電型の第1半導体層を形成するアニール工程と、
を含み、
前記照射工程と前記アニール工程とを組にして複数回行うことにより、前記半導体基板の深さ方向に、前記第1半導体層を複数形成し、
複数回の前記照射工程のうち前記半導体基板の裏面から最も深い位置にプロトンを照射する第1の照射工程の組となる、複数回の前記アニール工程のうちの第1のアニール工程のアニール温度を380℃以上450℃以下とし、
複数回の前記照射工程のうち前記半導体基板の裏面から2番目に深い位置にプロトンを照射する第2の照射工程の組となる、複数回の前記アニール工程のうちの第2のアニール工程のアニール温度を350℃以上420℃以下とし、
複数回の前記照射工程のうち前記半導体基板の裏面から3番目に深い位置にプロトンを照射する第3の照射工程の組となる、複数回の前記アニール工程のうちの第3のアニール工程のアニール温度を340℃以上400℃以下とすることを特徴とする半導体装置の製造方法。 - 前記第1のアニール工程のアニール温度を400℃以上420℃以下とし、
前記第2のアニール工程のアニール温度を370℃以上390℃以下とし、
前記第3のアニール工程のアニール温度を350℃よりも高く370℃以下とすることを特徴とする請求項11に記載の半導体装置の製造方法。 - 第1導電型の半導体基板の裏面からプロトンを照射する照射工程と、
前記半導体基板の裏面に照射されたプロトンを活性化し、前記半導体基板よりも不純物濃度が高い第1導電型の第1半導体層を形成するアニール工程と、
を含み、
前記照射工程の照射条件に応じて、1回または複数回の前記照射工程と1回の前記アニール工程とを組にして複数回行うことにより、前記半導体基板の深さ方向に、前記第1半導体層を複数形成することを特徴とする半導体装置の製造方法。 - 前記照射工程において、プロトンの照射により飛程Rpの前記第1半導体層を形成するときのプロトンの加速エネルギーEは、前記飛程Rpの対数log(Rp)をx、前記加速エネルギーEの対数log(E)をyとして、下記式(2)を満たすことを特徴とする請求項1に記載の半導体装置の製造方法。
y=-0.0047x4+0.0528x3-0.2211x2+0.9923x+5.0474 ・・・(2)
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014508242A JP5880690B2 (ja) | 2012-03-30 | 2013-03-29 | 半導体装置の製造方法 |
US14/372,453 US9385211B2 (en) | 2012-03-30 | 2013-03-29 | Manufacturing method for semiconductor device |
EP13767446.1A EP2790209B1 (en) | 2012-03-30 | 2013-03-29 | Manufacturing method for semiconductor device |
CN201380005484.2A CN104145326B (zh) | 2012-03-30 | 2013-03-29 | 半导体装置的制造方法 |
KR1020147019422A KR101982737B1 (ko) | 2012-03-30 | 2013-03-29 | 반도체 장치의 제조방법 |
US15/172,273 US10050106B2 (en) | 2012-03-30 | 2016-06-03 | Manufacturing method for semiconductor device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012-080684 | 2012-03-30 | ||
JP2012080684 | 2012-03-30 |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/372,453 A-371-Of-International US9385211B2 (en) | 2012-03-30 | 2013-03-29 | Manufacturing method for semiconductor device |
US15/172,273 Division US10050106B2 (en) | 2012-03-30 | 2016-06-03 | Manufacturing method for semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2013147274A1 true WO2013147274A1 (ja) | 2013-10-03 |
Family
ID=49260512
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2013/059775 WO2013147274A1 (ja) | 2012-03-30 | 2013-03-29 | 半導体装置の製造方法 |
Country Status (6)
Country | Link |
---|---|
US (2) | US9385211B2 (ja) |
EP (1) | EP2790209B1 (ja) |
JP (2) | JP5880690B2 (ja) |
KR (1) | KR101982737B1 (ja) |
CN (1) | CN104145326B (ja) |
WO (1) | WO2013147274A1 (ja) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2015087439A1 (ja) * | 2013-12-13 | 2015-06-18 | 三菱電機株式会社 | 半導体装置の製造方法 |
WO2016042954A1 (ja) * | 2014-09-17 | 2016-03-24 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
WO2016147264A1 (ja) * | 2015-03-13 | 2016-09-22 | 三菱電機株式会社 | 半導体装置及びその製造方法 |
US20190115211A1 (en) * | 2012-10-23 | 2019-04-18 | Fuji Electric Co., Ltd. | Semiconductor device and method for manufacturing the same |
JP2020027921A (ja) * | 2018-08-17 | 2020-02-20 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
WO2021070539A1 (ja) * | 2019-10-11 | 2021-04-15 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
JPWO2021125140A1 (ja) * | 2019-12-17 | 2021-12-16 | 富士電機株式会社 | 半導体装置 |
US11824095B2 (en) | 2018-03-19 | 2023-11-21 | Fuji Electric Co., Ltd. | Semiconductor device and semiconductor device manufacturing method |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6265594B2 (ja) * | 2012-12-21 | 2018-01-24 | ラピスセミコンダクタ株式会社 | 半導体装置の製造方法、及び半導体装置 |
DE112014003712T5 (de) * | 2013-12-16 | 2016-04-28 | Fuji Electric Co., Ltd. | Halbleitervorrichtung und Verfahren zum Herstellen einer Halbleitervorrichtung |
JP6287407B2 (ja) * | 2014-03-19 | 2018-03-07 | サンケン電気株式会社 | 半導体装置 |
WO2016051970A1 (ja) * | 2014-09-30 | 2016-04-07 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
CN105814694B (zh) * | 2014-10-03 | 2019-03-08 | 富士电机株式会社 | 半导体装置以及半导体装置的制造方法 |
US10497570B2 (en) * | 2015-06-16 | 2019-12-03 | Mitsubishi Electric Corporation | Method for manufacturing semiconductor device having buffer layer |
DE102015109661A1 (de) | 2015-06-17 | 2016-12-22 | Infineon Technologies Ag | Verfahren zum Bilden eines Halbleiterbauelements und Halbleiterbauelement |
DE112016000168T5 (de) * | 2015-06-17 | 2017-08-03 | Fuji Electric Co., Ltd. | Halbleitervorrichtung |
CN107851584B (zh) * | 2016-02-23 | 2021-06-11 | 富士电机株式会社 | 半导体装置 |
JP6846119B2 (ja) * | 2016-05-02 | 2021-03-24 | 株式会社 日立パワーデバイス | ダイオード、およびそれを用いた電力変換装置 |
DE102016112139B3 (de) * | 2016-07-01 | 2018-01-04 | Infineon Technologies Ag | Verfahren zum Reduzieren einer Verunreinigungskonzentration in einem Halbleiterkörper |
JP7361634B2 (ja) * | 2020-03-02 | 2023-10-16 | 三菱電機株式会社 | 半導体装置及び半導体装置の製造方法 |
JP7257984B2 (ja) * | 2020-03-24 | 2023-04-14 | 株式会社東芝 | 半導体装置及びその製造方法 |
US11527618B2 (en) * | 2020-07-18 | 2022-12-13 | Semiconductor Components Industries, Llc | Up-diffusion suppression in a power MOSFET |
CN111900087B (zh) * | 2020-08-31 | 2022-09-20 | 华虹半导体(无锡)有限公司 | Igbt器件的制造方法 |
CN113421827A (zh) * | 2021-07-09 | 2021-09-21 | 弘大芯源(深圳)半导体有限公司 | 一种采用辐照技术制造的抗辐射双极晶体管的生产方法 |
US11948799B2 (en) * | 2021-09-21 | 2024-04-02 | Applied Materials, Inc. | Minority carrier lifetime reduction for SiC IGBT devices |
CN115472668A (zh) * | 2022-05-05 | 2022-12-13 | 安世半导体科技(上海)有限公司 | 半导体器件及其制造方法 |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004079878A (ja) * | 2002-08-21 | 2004-03-11 | Toshiba Corp | 半導体装置及びその製造方法 |
US20050116249A1 (en) | 2003-10-24 | 2005-06-02 | Infineon Technologies Ag | Semiconductor diode and production method suitable therefor |
US20060081923A1 (en) | 2004-09-30 | 2006-04-20 | Infineon Technologies Ag | Semiconductor device and fabrication method suitable therefor |
JP2006344977A (ja) * | 2005-06-08 | 2006-12-21 | Infineon Technologies Ag | 阻止ゾーンを半導体基板に製造する方法、および、阻止ゾーンを有する半導体部品 |
JP2007266233A (ja) * | 2006-03-28 | 2007-10-11 | Toyota Central Res & Dev Lab Inc | 電力用半導体装置及びその製造方法 |
JP2009176892A (ja) * | 2008-01-23 | 2009-08-06 | Fuji Electric Device Technology Co Ltd | 半導体装置およびその製造方法 |
JP2010541266A (ja) * | 2007-10-03 | 2010-12-24 | アーベーベー・テヒノロギー・アーゲー | 半導体モジュール |
WO2011052787A1 (ja) * | 2009-11-02 | 2011-05-05 | 富士電機システムズ株式会社 | 半導体装置および半導体装置の製造方法 |
Family Cites Families (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4752818A (en) | 1985-09-28 | 1988-06-21 | Kabushiki Kaisha Toyota Chuo Kenkyusho | Semiconductor device with multiple recombination center layers |
JPH01128521A (ja) * | 1987-11-13 | 1989-05-22 | Fuji Electric Co Ltd | イオン注入方法 |
DE10055446B4 (de) | 1999-11-26 | 2012-08-23 | Fuji Electric Co., Ltd. | Halbleiterbauelement und Verfahren zu seiner Herstellung |
JP3684962B2 (ja) * | 1999-12-01 | 2005-08-17 | 富士電機デバイステクノロジー株式会社 | 半導体装置の製造方法 |
US6482681B1 (en) | 2000-05-05 | 2002-11-19 | International Rectifier Corporation | Hydrogen implant for buffer zone of punch-through non epi IGBT |
JP2002093813A (ja) * | 2000-09-13 | 2002-03-29 | Toyota Motor Corp | 半導体装置の製造方法 |
JP4750933B2 (ja) * | 2000-09-28 | 2011-08-17 | 株式会社東芝 | 薄型パンチスルー型パワーデバイス |
JP3951738B2 (ja) * | 2001-02-23 | 2007-08-01 | 富士電機デバイステクノロジー株式会社 | 半導体装置の製造方法 |
DE10207522B4 (de) | 2001-02-23 | 2018-08-02 | Fuji Electric Co., Ltd. | Halbleiterbauelement und Verfahren zu dessen Herstellung |
DE102005009000B4 (de) * | 2005-02-28 | 2009-04-02 | Infineon Technologies Austria Ag | Vertikales Halbleiterbauelement vom Grabenstrukturtyp und Herstellungsverfahren |
DE102005049506B4 (de) | 2005-10-13 | 2011-06-09 | Infineon Technologies Austria Ag | Vertikales Halbleiterbauelement |
DE102006046844B4 (de) * | 2006-10-02 | 2013-08-01 | Infineon Technologies Austria Ag | Leistungshalbleiterbauelement mit Feldstoppzone und Verfahren zur Herstellung eines solchen Leistungshalbleiterbauelements |
DE102006046845B4 (de) * | 2006-10-02 | 2013-12-05 | Infineon Technologies Austria Ag | Halbleiterbauelement mit verbesserter Robustheit |
JP5326217B2 (ja) | 2007-03-15 | 2013-10-30 | 富士電機株式会社 | 半導体装置およびその製造方法 |
DE102007037858B4 (de) * | 2007-08-10 | 2012-04-19 | Infineon Technologies Ag | Halbleiterbauelement mit verbessertem dynamischen Verhalten |
JP2010056134A (ja) * | 2008-08-26 | 2010-03-11 | Mitsubishi Electric Corp | 半導体装置 |
JP5648379B2 (ja) * | 2010-06-14 | 2015-01-07 | 富士電機株式会社 | 半導体装置の製造方法 |
JP5708788B2 (ja) * | 2011-03-16 | 2015-04-30 | 富士電機株式会社 | 半導体装置およびその製造方法 |
JP5741712B2 (ja) * | 2011-12-15 | 2015-07-01 | 富士電機株式会社 | 半導体装置の製造方法 |
JP5741716B2 (ja) * | 2012-01-19 | 2015-07-01 | 富士電機株式会社 | 半導体装置およびその製造方法 |
CN106887385B (zh) * | 2012-03-19 | 2020-06-12 | 富士电机株式会社 | 半导体装置的制造方法 |
KR102023175B1 (ko) * | 2012-03-30 | 2019-09-19 | 후지 덴키 가부시키가이샤 | 반도체 장치의 제조 방법 |
WO2014065080A1 (ja) * | 2012-10-23 | 2014-05-01 | 富士電機株式会社 | 半導体装置およびその製造方法 |
CN109065441B (zh) * | 2013-06-26 | 2023-06-30 | 富士电机株式会社 | 半导体装置及半导体装置的制造方法 |
-
2013
- 2013-03-29 WO PCT/JP2013/059775 patent/WO2013147274A1/ja active Application Filing
- 2013-03-29 CN CN201380005484.2A patent/CN104145326B/zh active Active
- 2013-03-29 EP EP13767446.1A patent/EP2790209B1/en active Active
- 2013-03-29 US US14/372,453 patent/US9385211B2/en active Active
- 2013-03-29 JP JP2014508242A patent/JP5880690B2/ja active Active
- 2013-03-29 KR KR1020147019422A patent/KR101982737B1/ko active IP Right Grant
-
2015
- 2015-09-16 JP JP2015182763A patent/JP6103011B2/ja active Active
-
2016
- 2016-06-03 US US15/172,273 patent/US10050106B2/en active Active
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004079878A (ja) * | 2002-08-21 | 2004-03-11 | Toshiba Corp | 半導体装置及びその製造方法 |
US20050116249A1 (en) | 2003-10-24 | 2005-06-02 | Infineon Technologies Ag | Semiconductor diode and production method suitable therefor |
US20060081923A1 (en) | 2004-09-30 | 2006-04-20 | Infineon Technologies Ag | Semiconductor device and fabrication method suitable therefor |
JP2006344977A (ja) * | 2005-06-08 | 2006-12-21 | Infineon Technologies Ag | 阻止ゾーンを半導体基板に製造する方法、および、阻止ゾーンを有する半導体部品 |
US20060286753A1 (en) | 2005-06-08 | 2006-12-21 | Reiner Barthelmess | Method for Producing a Stop Zone in a Semiconductor Body and Semiconductor Component Having a Stop Zone |
JP2007266233A (ja) * | 2006-03-28 | 2007-10-11 | Toyota Central Res & Dev Lab Inc | 電力用半導体装置及びその製造方法 |
JP2010541266A (ja) * | 2007-10-03 | 2010-12-24 | アーベーベー・テヒノロギー・アーゲー | 半導体モジュール |
JP2009176892A (ja) * | 2008-01-23 | 2009-08-06 | Fuji Electric Device Technology Co Ltd | 半導体装置およびその製造方法 |
WO2011052787A1 (ja) * | 2009-11-02 | 2011-05-05 | 富士電機システムズ株式会社 | 半導体装置および半導体装置の製造方法 |
Non-Patent Citations (1)
Title |
---|
See also references of EP2790209A4 |
Cited By (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20190115211A1 (en) * | 2012-10-23 | 2019-04-18 | Fuji Electric Co., Ltd. | Semiconductor device and method for manufacturing the same |
US11823898B2 (en) | 2012-10-23 | 2023-11-21 | Fuji Electric Co., Ltd. | Semiconductor device and method for manufacturing the same |
US10867790B2 (en) * | 2012-10-23 | 2020-12-15 | Fuji Electric Co., Ltd. | Semiconductor device and method for manufacturing the same |
US9673308B2 (en) | 2013-12-13 | 2017-06-06 | Mitsubishi Electric Corporation | Semiconductor device manufacturing method |
KR101838829B1 (ko) * | 2013-12-13 | 2018-03-14 | 미쓰비시덴키 가부시키가이샤 | 반도체 장치의 제조 방법 |
JPWO2015087439A1 (ja) * | 2013-12-13 | 2017-03-16 | 三菱電機株式会社 | 半導体装置の製造方法 |
CN105830220A (zh) * | 2013-12-13 | 2016-08-03 | 三菱电机株式会社 | 半导体装置的制造方法 |
WO2015087439A1 (ja) * | 2013-12-13 | 2015-06-18 | 三菱電機株式会社 | 半導体装置の製造方法 |
TWI553714B (zh) * | 2013-12-13 | 2016-10-11 | 三菱電機股份有限公司 | 半導體裝置之製造方法 |
US9954053B2 (en) | 2014-09-17 | 2018-04-24 | Fuji Electric Co., Ltd. | Semiconductor device and method of manufacturing semiconductor device |
WO2016042954A1 (ja) * | 2014-09-17 | 2016-03-24 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
US10431650B2 (en) | 2014-09-17 | 2019-10-01 | Fuji Electric Co., Ltd. | Method of manufacturing semiconductor device |
JPWO2016042954A1 (ja) * | 2014-09-17 | 2017-04-27 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
US20180019131A1 (en) * | 2015-03-13 | 2018-01-18 | Mitsubishi Electric Corporation | Semiconductor device and method of manufacturing the same |
CN107431087A (zh) * | 2015-03-13 | 2017-12-01 | 三菱电机株式会社 | 半导体装置及其制造方法 |
US10176994B2 (en) | 2015-03-13 | 2019-01-08 | Mitsubishi Electric Corporation | Semiconductor device and method of manufacturing the same |
WO2016147264A1 (ja) * | 2015-03-13 | 2016-09-22 | 三菱電機株式会社 | 半導体装置及びその製造方法 |
JPWO2016147264A1 (ja) * | 2015-03-13 | 2017-09-07 | 三菱電機株式会社 | 半導体装置及びその製造方法 |
CN107431087B (zh) * | 2015-03-13 | 2020-12-11 | 三菱电机株式会社 | 半导体装置及其制造方法 |
US11824095B2 (en) | 2018-03-19 | 2023-11-21 | Fuji Electric Co., Ltd. | Semiconductor device and semiconductor device manufacturing method |
JP2020027921A (ja) * | 2018-08-17 | 2020-02-20 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
CN110838517A (zh) * | 2018-08-17 | 2020-02-25 | 三菱电机株式会社 | 半导体装置及其制造方法 |
CN110838517B (zh) * | 2018-08-17 | 2024-02-06 | 三菱电机株式会社 | 半导体装置及其制造方法 |
JPWO2021070539A1 (ja) * | 2019-10-11 | 2021-04-15 | ||
JP7222435B2 (ja) | 2019-10-11 | 2023-02-15 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
WO2021070539A1 (ja) * | 2019-10-11 | 2021-04-15 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
US11901419B2 (en) | 2019-10-11 | 2024-02-13 | Fuji Electric Co., Ltd. | Semiconductor device and manufacturing method of semiconductor device |
JP7476996B2 (ja) | 2019-10-11 | 2024-05-01 | 富士電機株式会社 | 半導体装置 |
JPWO2021125140A1 (ja) * | 2019-12-17 | 2021-12-16 | 富士電機株式会社 | 半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
EP2790209A1 (en) | 2014-10-15 |
JP6103011B2 (ja) | 2017-03-29 |
KR101982737B1 (ko) | 2019-05-27 |
JP5880690B2 (ja) | 2016-03-09 |
EP2790209B1 (en) | 2019-09-25 |
US20140374793A1 (en) | 2014-12-25 |
JP2016015513A (ja) | 2016-01-28 |
CN104145326B (zh) | 2017-11-17 |
KR20140138598A (ko) | 2014-12-04 |
CN104145326A (zh) | 2014-11-12 |
EP2790209A4 (en) | 2015-07-29 |
US20160284796A1 (en) | 2016-09-29 |
JPWO2013147274A1 (ja) | 2015-12-14 |
US9385211B2 (en) | 2016-07-05 |
US10050106B2 (en) | 2018-08-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6103011B2 (ja) | 半導体装置の製造方法 | |
JP6460153B2 (ja) | 半導体装置の製造方法 | |
US10867790B2 (en) | Semiconductor device and method for manufacturing the same | |
JP6512314B2 (ja) | 半導体装置 | |
JP6020553B2 (ja) | 半導体装置の製造方法 | |
JP6015745B2 (ja) | 半導体装置の製造方法 | |
JP5741716B2 (ja) | 半導体装置およびその製造方法 | |
JP6269858B2 (ja) | 炭化珪素半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 13767446 Country of ref document: EP Kind code of ref document: A1 |
|
ENP | Entry into the national phase |
Ref document number: 2014508242 Country of ref document: JP Kind code of ref document: A |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2013767446 Country of ref document: EP |
|
ENP | Entry into the national phase |
Ref document number: 20147019422 Country of ref document: KR Kind code of ref document: A |
|
WWE | Wipo information: entry into national phase |
Ref document number: 14372453 Country of ref document: US |
|
NENP | Non-entry into the national phase |
Ref country code: DE |