JP7257984B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP7257984B2 JP7257984B2 JP2020052497A JP2020052497A JP7257984B2 JP 7257984 B2 JP7257984 B2 JP 7257984B2 JP 2020052497 A JP2020052497 A JP 2020052497A JP 2020052497 A JP2020052497 A JP 2020052497A JP 7257984 B2 JP7257984 B2 JP 7257984B2
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- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Description
図面は模式的または概念的なものであり、各部分の厚みと幅との関係、部分間の大きさの比率などは、必ずしも現実のものと同一とは限らない。同じ部分を表す場合であっても、図面により互いの寸法や比率が異なって表される場合もある。
本願明細書と各図において、既に説明したものと同様の要素には同一の符号を付して詳細な説明は適宜省略する。
以下の説明及び図面において、n+、n、n-及びp+、p、p-の表記は、各不純物濃度の相対的な高低を表す。すなわち、「+」が付されている表記は、「+」及び「-」のいずれも付されていない表記よりも不純物濃度が相対的に高く、「-」が付されている表記は、いずれも付されていない表記よりも不純物濃度が相対的に低いことを示す。これらの表記は、それぞれの領域にp形不純物とn形不純物の両方が含まれている場合には、それらの不純物が補償しあった後の正味の不純物濃度の相対的な高低を表す。
以下で説明する各実施形態について、各半導体領域のp形とn形を反転させて各実施形態を実施してもよい。
図2は、図1のII-II断面図である。図1は、図2のI-I断面図である。
実施形態に係る半導体装置は、MOSFETである。図1及び図2に表した半導体装置100は、n形(第1導電形)バッファ領域1(第1半導体領域)、接合領域JR、n-形外周領域4(第4半導体領域)、p形(第2導電形)ベース領域5(第5半導体領域)、n+形ソース領域6(第6半導体領域)、n+形ドレイン領域7(第7半導体領域)、p+形コンタクト領域8、ゲート電極10、ドレイン電極21(第1電極)、ソース電極22(第2電極)、及び絶縁部30を含む。
ソース電極22に対してドレイン電極21に正電圧が印加された状態で、ゲート電極10に閾値以上の電圧を印加する。これにより、p形ベース領域5のゲート絶縁層11近傍の領域にチャネル(反転層)が形成され、半導体装置100がオン状態となる。電子は、このチャネル及びn-形ピラー領域2を通ってソース電極22からドレイン電極21へ流れる。その後、ゲート電極10に印加される電圧が閾値よりも低くなると、p形ベース領域5におけるチャネルが消滅し、半導体装置100がオフ状態になる。
n形バッファ領域1、n-形ピラー領域2、p-形ピラー領域3、n-形外周領域4、p形ベース領域5、n+形ソース領域6、n+形ドレイン領域7、p+形コンタクト領域8、及びn-形半導体領域9は、半導体材料として、シリコン、炭化シリコン、窒化ガリウム、またはガリウムヒ素を含む。半導体材料としてシリコンが用いられる場合、n形不純物として、ヒ素、リン、またはアンチモンを用いることができる。p形不純物として、ボロンを用いることができる。
ゲート電極10は、ポリシリコンなどの導電材料を含む。導電材料には、不純物が添加されていても良い。ゲート絶縁層11及び絶縁部30は、酸化シリコン、窒化シリコンなどの絶縁材料を含む。ドレイン電極21及びソース電極22は、アルミニウム、チタンなどの金属を含む。
まず、n+形半導体基板7aを用意する。n+形半導体基板7aの上に、n形半導体層1a及びn-形半導体層2aを順次エピタキシャル成長させる。反応性イオンエッチング(RIE)により、図3(a)に表したように、Y方向に延びる複数の開口OP1をn-形半導体層2aに形成する。開口OP1は、n-形半導体層2aを貫通しても良い、n-形半導体層2aを貫通していなくても良い。
図7及び図8は、図6に表した電気回路の動作を表す模式図である。
例えば、実施形態に係る半導体装置は、コンバータに適用できる。図6に表した例では、電気機器200は、降圧コンバータである。電気機器200は、実施形態に係る2つの半導体装置と、それぞれの半導体装置を制御する2つの制御部と、を含む。
具体的には、図9は、図6に表した電気機器200において、図8(b)及び図8(c)に表したようにリカバリー電流IRが流れたときの半導体装置100bの特性を表している。図9において、実線は、ダイオードを流れる電流を表す。電流は、順方向に流れるときを正として表している。破線は、ソース電極22に対するドレイン電極21の電圧を表している。横軸は、時間を表している。
半導体装置100の消費電力を低減するためには、リカバリー電流IRの積分値で表される蓄積電荷Qrrが小さいことが望ましい。リカバリー電流IRが小さくなると(ゼロに近づくと)、蓄積電荷Qrrは小さくなる。実施形態に係る半導体装置100では、接合領域JRにおける第1元素の濃度は、n形バッファ領域1における第1元素の濃度よりも高く、且つn-形外周領域4における第1元素の濃度よりも高い。第1元素の濃度が高いほど、その領域におけるキャリアライフタイムは短くなる。接合領域JRのキャリアライフタイムが短いと、蓄積電荷Qrrがより早く減少し、リカバリー電流IRを低減できる。
図10は、半導体装置100の一部を二次イオン質量分析法(SIMS)により分析した結果を表す。図10(a)は、半導体装置100の一部を表す。図10(b)は、図10(a)に表した領域において、Z方向における各点の白金の原子数を表す。接合領域JRでは、n-形ピラー領域2及びp-形ピラー領域3のそれぞれにおける原子数の和が表されている。図10(b)において、破線は検出限界を表す。
Claims (6)
- 第1電極と、
前記第1電極の上に設けられ、前記第1電極と電気的に接続された第1導電形の第1半導体領域と、
前記第1半導体領域よりも低い第1導電形の不純物濃度を有する第1導電形の第2半導体領域と、
第2導電形の第3半導体領域と、
を含み、前記第1半導体領域の上に設けられ、前記第1電極から前記第1半導体領域へ向かう第1方向に垂直な第2方向において複数の前記第2半導体領域と複数の前記第3半導体領域とが交互に設けられた接合領域と、
前記第1方向に垂直な第1面に沿って前記接合領域の周りに設けられ、前記第1半導体領域よりも低い第1導電形の不純物濃度を有する第1導電形の第4半導体領域と、
前記複数の第3半導体領域の1つの上に設けられた第2導電形の第5半導体領域と、
前記第5半導体領域の上に設けられた第1導電形の第6半導体領域と、
前記第5半導体領域とゲート絶縁層を介して対向するゲート電極と、
前記第5半導体領域及び前記第6半導体領域の上に設けられ、前記第5半導体領域及び前記第6半導体領域と電気的に接続された第2電極と、
を備え、
前記接合領域における、重金属元素及びプロトンからなる群より選択された少なくとも1つの第1元素の濃度は、前記第1半導体領域における前記第1元素の濃度よりも高く、前記第4半導体領域における前記第1元素の濃度よりも高く、前記接合領域の上部における前記第1元素の濃度に対する前記接合領域の中間部における前記第1元素の濃度の比は0.6以上1.4以下であり、前記上部及び前記中間部のそれぞれにおける前記第1元素の濃度に対する前記接合領域の下部における前記第1元素の濃度の比は0.1以下である、半導体装置。 - 前記第2半導体領域及び前記第3半導体領域のそれぞれにおける前記第1元素の濃度は、前記第1半導体領域における前記第1元素の濃度よりも高く、前記第4半導体領域における前記第1元素の濃度よりも高い、請求項1記載の半導体装置。
- 前記第1元素は、金、ルテニウム、ロジウム、パラジウム、オスミウム、イリジウム、及び白金からなる群より選択された少なくとも1つである、請求項1又は2に記載の半導体装置。
- 前記接合領域における前記第1元素の濃度は、前記第1半導体領域における前記第1元素の濃度及び前記第4半導体領域における前記第1元素の濃度のそれぞれの4倍以上50倍以下である、請求項1~3のいずれか1つに記載の半導体装置。
- 前記第1電極と前記第1半導体領域との間に設けられ、前記第1半導体領域よりも高い第1導電形の不純物濃度を有する第1導電形の第7半導体領域をさらに備えた、請求項1~4のいずれか1つに記載の半導体装置。
- 第1導電形の第1半導体領域と、
前記第1半導体領域よりも低い第1導電形の不純物濃度を有する第1導電形の第2半導体領域、及び、第2導電形の第3半導体領域を含む接合領域であって、前記第1半導体領域の上に設けられ、前記第1半導体領域から前記接合領域へ向かう第1方向に垂直な第2方向において複数の前記第2半導体領域と複数の前記第3半導体領域とが交互に設けられた、前記接合領域と、
前記第1方向に垂直な第1面に沿って前記接合領域の周りに設けられ、前記第1半導体領域よりも低い第1導電形の不純物濃度を有する第1導電形の第4半導体領域と、
前記複数の第3半導体領域の上にそれぞれ設けられ第2導電形の複数の第5半導体領域と、
前記複数の第5半導体領域の上にそれぞれ設けられた第1導電形の複数の第6半導体領域と、
前記複数の第5半導体領域及び前記複数の第6半導体領域の上に設けられ、複数のゲート絶縁層を介して前記複数の第5半導体領域とそれぞれ対向する複数のゲート電極と、
前記複数のゲート電極の周りにおいて、前記接合領域及び前記第4半導体領域の上に設けられた絶縁層と、
を含む構造体に対して、前記ゲート電極同士の間の間隙を通して、重金属元素及びプロトンからなる群より選択された少なくとも1つの第1元素を前記接合領域に拡散させることで、前記接合領域における前記第1元素の濃度を、前記第1半導体領域における前記第1元素の濃度よりも高く、且つ前記第4半導体領域における前記第1元素の濃度よりも高くする、半導体装置の製造方法。
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