CN107431087B - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN107431087B
CN107431087B CN201580077781.7A CN201580077781A CN107431087B CN 107431087 B CN107431087 B CN 107431087B CN 201580077781 A CN201580077781 A CN 201580077781A CN 107431087 B CN107431087 B CN 107431087B
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semiconductor device
protons
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CN107431087A (zh
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铃木健司
楢崎敦司
上马场龙
深田祐介
中村胜光
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Mitsubishi Electric Corp
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Abstract

在n型硅衬底(1)的表面形成有p型基极层(2)。在n型硅衬底(1)的背面形成有第一及第二n+型缓冲层(8、9)。第一n+型缓冲层(8)是通过加速电压不同的多次质子注入形成的，具有从n型硅衬底(1)的背面算起的深度不同的多个峰值浓度。第二n+型缓冲层(9)是通过磷注入形成的。从n型硅衬底(1)的背面算起，磷的峰值浓度的位置比质子的峰值浓度的位置浅。磷的峰值浓度比质子的峰值浓度高。在质子的峰值浓度的位置处，质子的浓度比磷的浓度高。

Description

半导体装置及其制造方法
技术领域
本发明涉及二极管或绝缘栅型双极晶体管(IGBT)等半导体装置及其制造方法，特别涉及能够降低泄漏电流，抑制截止时、恢复时的振荡，在一般的半导体工厂也能容易地通过质子注入而形成n型缓冲层的半导体装置及其制造方法。
背景技术
根据节能的观点，在通用逆变器、AC伺服等领域中，在用于进行三相电动机的可变速控制的功率模块等中使用IGBT、二极管。为了减少逆变器损耗，作为IGBT、二极管而言，要求通断损耗和导通电压低的器件
导通电压的大半是耐压保持所需的厚的n型基极层的电阻，为了减小该电阻，将晶片变薄是有效的。然而，在将晶片变薄的情况下，如果在集电极施加电压，则耗尽层到达背面，产生耐压的下降、泄漏电流的增大。因此，一般会在衬底背面通过离子注入机形成有比衬底浓度高的浅n+型缓冲层。
然而，伴随IGBT的制造技术的技术革新，晶片厚度已变薄至能够确保耐压的厚度附近，因此，在浅n+型缓冲层的情况下，在IGBT、二极管进行通断动作时，由电源电压+L*di/dt决定的浪涌电压施加于集电极-发射极间、阴极-阳极间，如果耗尽层到达背面侧，则载流子枯竭，产生电压及电流的振荡。如果产生振荡，则产生辐射噪声，对周围的电子器件产生不良影响。
另一方面，通过在衬底背面形成浓度低、30μm左右的深n+型缓冲层，从而即使在通断时在集电极或阴极施加有大电压，也能够平缓地阻止耗尽层。其结果，防止了背面侧的载流子的枯竭，通过使其滞留，从而能够防止急剧的电压的上升。
图23是表示在器件模拟中通过耐压1200V级别的IGBT实施的L负载通断的截止波形的图。通断条件是，由磷形成的n+型缓冲层的深度是2μm和30μm、Vce＝900V、Ic＝150A。在深度2μm的情况下波形发生了振荡，但30μm的情况下没有产生振荡。
如果通过磷的扩散而制作30μm左右的深n+型缓冲层，则在诸如1100℃这样的通常的热处理温度下需要花费大于或等于24小时，量产性低。除此之外，存在使用回旋加速器、范德格拉夫加速器等加速器的方法(例如，参照专利文献1)。例如在通过8MeV的加速电压将质子照射至硅衬底的情况下，射程约480μm，半高宽约20μm。为了调整射程的位置，不直接打入至硅衬底，而是越过吸收器打入，从而能够使照射能量减速，在硅的表面附近形成宽的质子的峰。之后，以350至450℃实施1至5小时的热处理，从而能够激活质子而形成n型区域。此外，虽然质子的激活率也依赖于注入条件、热处理条件，但该激活率为1％左右。
专利文献1：日本特开2013-138172号公报
发明内容
质子施主化为n型的机制是由下述的复合的主要原因决定的，即，注入的氢原子、在注入时形成的晶体缺陷、以及残留于衬底的氧原子，激活率根据硅衬底的形成方法、固溶的氧浓度、质子注入条件等而改变。如果通过质子注入而形成的n+型缓冲层的浓度改变，则产生泄漏电流、导通电压的波动增大、短路耐量的恶化等。
另外，对于IGBT、二极管，为了制作深度30μm左右的宽的背面n+型缓冲层，需要通过8MeV左右的高加速电压将半高宽变大而注入质子。与此相对，当前使用的是回旋加速器、范德格拉夫加速器等加速器。然而，这些加速器本体由于辐射的问题，需要由1至4m厚的混凝土掩体包围，在通常的半导体工厂内不能容易地使用。
本发明就是为了解决上述课题而提出的，其目的在于得到一种能够减少泄漏电流，抑制截止时、恢复时的振荡，在一般的半导体工厂也能容易地通过质子注入而形成n型缓冲层的半导体装置及其制造方法。
本发明涉及的半导体装置的特征在于，具有：半导体衬底；p型层，其形成于所述半导体衬底的表面；以及第一及第二n型缓冲层，它们形成于所述半导体衬底的背面，所述第一n型缓冲层是通过加速电压不同的多次质子注入形成的，具有从所述半导体衬底的背面算起的深度不同的多个峰值浓度，所述第二n型缓冲层是通过磷注入形成的，从所述半导体衬底的背面算起，所述磷的峰值浓度的位置比所述质子的峰值浓度的位置浅，所述磷的峰值浓度比所述质子的峰值浓度高，在所述质子的峰值浓度的位置处，质子的浓度比磷的浓度高。
发明的效果
在本发明中，能够通过由质子注入形成的低浓度、扩散深度深的第一n型缓冲层防止IGBT截止时和二极管恢复时的振荡。另外，能够通过注入了磷的高浓度的第二n型缓冲层而阻止耗尽层，防止泄漏电流的增加。另外，不使用回旋加速器，在一般的半导体工厂也能容易地通过质子注入而形成n型缓冲层。
附图说明
图1是表示本发明的实施方式1涉及的半导体装置的剖视图。
图2是表示本发明的实施方式1涉及的半导体装置的背面分布(profile)的图。
图3是表示本发明的实施方式1涉及的半导体装置的制造工序的剖视图。
图4是表示本发明的实施方式1涉及的半导体装置的制造工序的剖视图。
图5是表示本发明的实施方式1涉及的半导体装置的制造工序的剖视图。
图6是表示本发明的实施方式1涉及的半导体装置的制造工序的剖视图。
图7是表示本发明的实施方式1涉及的半导体装置的制造工序的剖视图。
图8是表示本发明的实施方式1涉及的半导体装置的制造工序的剖视图。
图9是表示本发明的实施方式1涉及的半导体装置的制造工序的剖视图。
图10是表示本发明的实施方式1涉及的半导体装置的制造工序的剖视图。
图11是表示对比例1涉及的半导体装置的剖视图。
图12是表示对比例1涉及的半导体装置的背面分布的图。
图13是表示本发明的实施方式2涉及的半导体装置的剖视图。
图14是表示本发明的实施方式2涉及的半导体装置的背面分布的图。
图15是表示本发明的实施方式2涉及的半导体装置的制造工序的剖视图。
图16是表示本发明的实施方式2涉及的半导体装置的制造工序的剖视图。
图17是表示本发明的实施方式2涉及的半导体装置的制造工序的剖视图。
图18是表示本发明的实施方式2涉及的半导体装置的制造工序的剖视图。
图19是表示本发明的实施方式2涉及的半导体装置的制造工序的剖视图。
图20是表示本发明的实施方式2涉及的半导体装置的制造工序的剖视图。
图21是表示对比例2涉及的半导体装置的剖视图。
图22是表示对比例2涉及的半导体装置的背面分布的图。
图23是表示在器件模拟中通过耐压1200V级别的IGBT实施的L负载通断的截止波形的图。
具体实施方式
参照附图对本发明的实施方式涉及的半导体装置及其制造方法进行说明。对相同或对应的结构要素标注相同的标号，有时省略重复的说明。
实施方式1.
图1是表示本发明的实施方式1涉及的半导体装置的剖视图。该半导体装置是IGBT。在n型硅衬底1的表面形成有p型基极层2。在p型基极层2之上形成有n+型发射极层3和p+型接触层4。在贯穿p型基极层2与n+型发射极层3的沟槽内，隔着栅极绝缘膜形成有沟槽栅极5。在沟槽栅极5之上形成有层间绝缘膜6。发射极电极7形成于n型硅衬底1的表面，与p+型接触层4连接。
在n型硅衬底1的背面形成有第一及第二n+型缓冲层8、9。第一n+型缓冲层8是通过加速电压不同的多次质子注入形成的。第二n+型缓冲层9是通过磷注入形成的。从n型硅衬底1的背面算起，在比第一及第二n+型缓冲层8、9浅的位置形成有深度1.0μm左右的p型集电极层10。集电极电极(collector electrode)11形成于n型硅衬底1的背面，与p型集电极层10连接。
图2是表示本发明的实施方式1涉及的半导体装置的背面分布的图。第一n+型缓冲层8的质子具有从n型硅衬底1的背面算起的深度不同的多个峰值浓度。从n型硅衬底1的背面算起，第二n+型缓冲层9的磷的峰值浓度的位置比第一n+型缓冲层8的质子的峰值浓度的位置浅。磷的峰值浓度比质子的峰值浓度高。在质子的峰值浓度的位置处，质子的浓度比磷的浓度高。
图3至图10是表示本发明的实施方式1涉及的半导体装置的制造工序的剖视图。首先，如图3所示，通过通常的表面工艺形成IGBT的表面构造。此时，晶片厚度是700μm左右，与裸晶片大致相同。
接下来，如图4所示，通过研磨机、湿蚀刻将n型硅衬底1的背面侧研磨至希望的厚度为止。接下来，如图5所示，使用一般的半导体制造用离子注入装置，在n型硅衬底1的背面通过大于或等于500keV而小于或等于1.5MeV的不同的加速电压进行多次注入。质子的射程在500keV的情况下是6μm左右,在1500keV的情况下是30μm左右。
接下来，如图6所示，通过350℃至450℃的炉内退火实施质子的激活而形成第一n+型缓冲层8。接下来，如图7所示，通过小于或等于1MeV的加速电压将磷注入至n型硅衬底1的背面的浅的区域。接下来，如图8所示，通过激光退火实施磷的激活而形成第二n+型缓冲层9。
接下来，如图9所示，将B注入至n型硅衬底1的背面。接下来，如图10所示，实施激光退火而形成p+型接触层4。之后，在n型硅衬底1的背面通过溅射形成Al/Ti/Ni/Au、AlSi/Ti/Ni/Au等集电极电极11。最后，为了取得集电极电极11与n型硅衬底1的欧姆接触而减小接触电阻，实施350℃左右的热处理。此时，通过将用于质子的激活的热处理也兼由同一工序实施，从而能够削减1次热处理工序，因此能够削减加工费。
下面，与对比例进行比较而对本实施方式的效果进行说明。图11是表示对比例1涉及的半导体装置的剖视图。图12是表示对比例1涉及的半导体装置的背面分布的图。在对比例1中，通过使用了回旋加速器、范德格拉夫加速器等加速器的质子注入，将n+型缓冲层12以30μm左右较深地形成。
在以1.5MeV注入了质子的情况下，射程为30μm左右，能够形成可期待振荡抑制效果的深的缓冲层。一般的半导体制造用离子注入装置也能够将加速电压提高至1.5MeV左右。然而，通过半导体制造用离子注入装置以低加速电压形成的扩散层的半高宽小，因此难以制作像通过回旋加速器制作出的扩散层那样的宽的扩散层。
在这里，在本实施方式中，通过诸如500keV、1000keV、1500keV这样不同的加速电压实施多次质子注入，从而能够如图2所示形成具有比较宽的分布的第一n+型缓冲层8。
然而，如果实施多次注入，则从衬底背面算起，越是浅处，越会产生非常多的晶体缺陷。质子的激活也依赖于晶体缺陷量，因此n型层的浓度有可能产生波动。在这里，在背面附近形成通过注入磷形成的高浓度的第二n+型缓冲层9，从而防止施加电压时耗尽层到达集电极侧，能够抑制耐压下降、泄漏电流增大。
另外，磷与质子相比原子半径大，在注入时由于原子核的碰撞，大量地发生注入损伤，如果质子的注入分布与磷的注入分布重叠，则有可能对质子的施主化产生影响。在这里，在本实施方式中，以在质子的峰值浓度的位置处质子的浓度比磷的浓度高的方式设定峰值的位置。由此，能够防止相互干渉，能够将由质子的激活形成的第一n+型缓冲层8设为希望的浓度。
如上所述，在本实施方式中，能够通过由质子注入形成的低浓度、扩散深度深的第一n+型缓冲层8防止IGBT截止时的振荡。另外，能够通过注入了磷的高浓度的第二n+型缓冲层9阻止耗尽层而防止泄漏电流的增加。
另外，使用一般的半导体制造用离子注入装置以不同的加速电压实施多次质子注入而形成第一n+型缓冲层8。由此，并未使用回旋加速器，在一般的半导体工厂也能够容易地通过质子注入形成第一n+型缓冲层8。
另外，优选在多次质子注入中，加速电压越高，越降低注入量。由此，能够使通过多次质子注入形成的第一n+型缓冲层8的分布接近高斯分布。
另外，优选在多次质子注入中，加速电压最高的分布的注入量与加速电压其次高的分布的注入量相同。由此，形成梯度非常缓的分布，从而能够平缓地阻止在IGBT截止时或二极管恢复时扩展的耗尽层，能够防止载流子被急剧地清出、枯竭。
另外，磷的注入量比质子的注入量低，通过激光退火实施磷的激活，通过350℃至450℃的炉内退火实施质子的激活。通过如上述那样利用激光退火实施磷的激活，从而使激活率提高至70％左右。另一方面，质子的通过炉内退火得到的激活率是1％左右。因此，即使将磷的注入量降低至比质子的注入量低，也能够使磷的峰值浓度比质子的峰值浓度充分高。其结果，能够抑制由磷注入产生的伤害的影响，且实施与磷注入区域接近的质子注入区域的施主化。
实施方式2.
图13是表示本发明的实施方式2涉及的半导体装置的剖视图。该半导体装置是二极管。在n型硅衬底1的表面形成有p型阳极层13。阳极电极14形成于n型硅衬底1的表面，与p型阳极层13连接。与实施方式1相同地，在n型硅衬底1的背面形成有第一及第二n+型缓冲层8、9。阴极电极15形成于n型硅衬底1的背面，与第二n+型缓冲层9连接。
图14是表示本发明的实施方式2涉及的半导体装置的背面分布的图。与实施方式1相同地，第一n+型缓冲层8的质子具有从n型硅衬底1的背面算起的深度不同的多个峰值浓度。从n型硅衬底1的背面算起，第二n+型缓冲层9的磷的峰值浓度的位置比第一n+型缓冲层8的质子的峰值浓度的位置浅。磷的峰值浓度比质子的峰值浓度高。在质子的峰值浓度的位置处，质子的浓度比磷的浓度高。
图15至图20是表示本发明的实施方式2涉及的半导体装置的制造工序的剖视图。首先，如图15所示，通过通常的表面工艺形成二极管的表面构造。在该时刻，晶片厚度是700μm左右，与裸晶片大致相同。
接下来，如图16所示，通过研磨机、湿蚀刻将n型硅衬底1的背面侧研磨至希望的厚度为止。接下来，如图17所示，使用一般的半导体制造用离子注入装置，在n型硅衬底1的背面通过大于或等于500keV而小于或等于1.5MeV的不同的加速电压进行多次注入。质子的射程在500keV的情况下是6μm左右,在1500keV的情况下是30μm左右。
接下来，如图18所示，通过350℃至450℃的炉内退火实施质子的激活而形成第一n+型缓冲层8。接下来，如图19所示，通过小于或等于1MeV的加速电压将磷注入至n型硅衬底1的背面的浅的区域。接下来，如图20所示，通过激光退火实施磷的激活而形成第二n+型缓冲层9。
之后，在n型硅衬底1的背面通过溅射形成Al/Ti/Ni/Au、AlSi/Ti/Ni/Au等阴极电极15。最后，为了取得阴极电极15与n型硅衬底1的欧姆接触而减小接触电阻，实施350℃左右的热处理。此时，通过将用于质子的激活的热处理也兼由同一工序实施，从而能够削减1次热处理工序，因此能够削减加工费。
下面，与对比例进行比较而对本实施方式的效果进行说明。图21是表示对比例2涉及的半导体装置的剖视图。图22是表示对比例2涉及的半导体装置的背面分布的图。在对比例2中，通过使用了回旋加速器、范德格拉夫加速器等加速器的质子注入，将n+型缓冲层12以30μm左右较深地形成。
与此相对，在本实施方式中，与实施方式1相同地，能够通过由质子注入形成的低浓度、扩散深度深的第一n+型缓冲层8防止二极管恢复时的振荡。另外，能够通过注入了磷的高浓度的第二n+型缓冲层9阻止耗尽层而防止泄漏电流的增加。另外，并未使用回旋加速器，在一般的半导体工厂也能够容易地通过质子注入形成第一n+型缓冲层8。
此外，半导体衬底不限定于由硅形成，也可以由带隙比硅宽的宽带隙半导体形成。宽带隙半导体是例如碳化硅、氮化镓类材料或者金刚石。关于这样的由宽带隙半导体形成的功率半导体元件，耐电压性、容许电流密度高，因此能够小型化。通过使用该小型化的元件，从而组装有该元件的半导体模块也能够小型化。另外，元件的耐热性高，因此能够将散热器的散热鳍片小型化，能够将水冷部风冷化，因此半导体模块能够进一步小型化。另外，元件的电力损耗低且高效率，因此能够将半导体模块高效率化。
标号的说明
1n型硅衬底(半导体衬底)，2p型基极层(p型层)，8第一n+型缓冲层(第一n型缓冲层)，9第二n+型缓冲层(第二n型缓冲层)，11集电极电极(背面电极)，13p型阳极层(p型层)，15阴极电极(背面电极)。

Claims (10)

1.一种半导体装置，其特征在于，
具有：
半导体衬底；
p型层，其形成于所述半导体衬底的表面；以及
第一及第二n型缓冲层，它们形成于所述半导体衬底的背面，
所述第一n型缓冲层是通过加速电压不同的多次质子注入形成的，具有从所述半导体衬底的背面算起的深度不同且从所述半导体衬底的背面算起的深度越深注入量越低的多个峰值浓度，
所述第二n型缓冲层是通过磷注入形成的，
从所述半导体衬底的背面算起，所述磷的峰值浓度的位置比所述质子的峰值浓度的位置浅，
所述磷的峰值浓度比所述质子的峰值浓度高，
在所述质子的峰值浓度的位置处，质子的浓度比磷的浓度高，
所述质子的所述多个峰值浓度仅位于从所述半导体衬底的背面算起大于或等于6μm而小于或等于30μm的深度，
所述第二n型缓冲层设置于所述第一n型缓冲层的所述背面侧即下方。
2.根据权利要求1所述的半导体装置，其特征在于，
所述半导体装置是二极管或绝缘栅型双极晶体管。
3.一种半导体装置的制造方法，其是权利要求1或2所述的半导体装置的制造方法，
该半导体装置的制造方法的特征在于，
使用半导体制造用离子注入装置，通过不同的加速电压实施多次质子注入而形成所述第一n型缓冲层。
4.根据权利要求3所述的半导体装置的制造方法，其特征在于，
在所述多次质子注入中，加速电压越高，越降低注入量。
5.根据权利要求3所述的半导体装置的制造方法，其特征在于，
在所述多次质子注入中，加速电压最高的分布的注入量与加速电压其次高的分布的注入量相同。
6.根据权利要求3至5中任一项所述的半导体装置的制造方法，其特征在于，
磷的注入量比质子的注入量低，通过激光退火实施磷的激活。
7.根据权利要求3至5中任一项所述的半导体装置的制造方法，其特征在于，
通过350℃至450℃的炉内退火实施所述质子的激活。
8.根据权利要求3至5中任一项所述的半导体装置的制造方法，其特征在于，
所述磷的注入的加速电压小于或等于1MeV。
9.根据权利要求3至5中任一项所述的半导体装置的制造方法，其特征在于，
所述质子的注入的加速电压大于或等于500keV而小于或等于1.5MeV。
10.根据权利要求3至5中任一项所述的半导体装置的制造方法，其特征在于，
在所述半导体衬底的背面形成背面电极，
将用于所述质子的激活的热处理和用于取得所述背面电极与所述半导体衬底的欧姆接触的热处理由同一工序实施。
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