WO2016042954A1 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- WO2016042954A1 WO2016042954A1 PCT/JP2015/072916 JP2015072916W WO2016042954A1 WO 2016042954 A1 WO2016042954 A1 WO 2016042954A1 JP 2015072916 W JP2015072916 W JP 2015072916W WO 2016042954 A1 WO2016042954 A1 WO 2016042954A1
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- 239000004065 semiconductor Substances 0.000 title claims description 287
- 238000004519 manufacturing process Methods 0.000 title claims description 34
- 238000000034 method Methods 0.000 title claims description 21
- 238000009826 distribution Methods 0.000 claims abstract description 49
- 239000010410 layer Substances 0.000 claims description 469
- 239000000758 substrate Substances 0.000 claims description 49
- 238000010438 heat treatment Methods 0.000 claims description 38
- 239000002344 surface layer Substances 0.000 claims description 17
- 125000004435 hydrogen atom Chemical group [H]* 0.000 claims description 9
- 238000002513 implantation Methods 0.000 claims description 8
- 230000007423 decrease Effects 0.000 claims description 6
- 239000012535 impurity Substances 0.000 claims description 6
- 230000001737 promoting effect Effects 0.000 claims description 2
- 238000005224 laser annealing Methods 0.000 description 34
- 230000007547 defect Effects 0.000 description 17
- 238000005468 ion implantation Methods 0.000 description 13
- 239000000852 hydrogen donor Substances 0.000 description 10
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 description 10
- 229910052739 hydrogen Inorganic materials 0.000 description 9
- 239000001257 hydrogen Substances 0.000 description 9
- 230000008569 process Effects 0.000 description 8
- 239000007924 injection Substances 0.000 description 7
- 238000002347 injection Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 239000000386 donor Substances 0.000 description 6
- 238000000137 annealing Methods 0.000 description 5
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 4
- 125000004429 atom Chemical group 0.000 description 3
- 239000000969 carrier Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 150000002431 hydrogen Chemical class 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 230000001678 irradiating effect Effects 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 230000035515 penetration Effects 0.000 description 2
- 239000011669 selenium Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 238000001994 activation Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000002109 crystal growth method Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- -1 hydrogen ions Chemical class 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910052711 selenium Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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Definitions
- the present invention relates to a semiconductor device and a method of manufacturing the semiconductor device.
- an IGBT Insulated Gate Bipolar Transistor
- FS field stop
- the field stop layer has a function of suppressing the spread of the depletion layer extending from the emitter side to the collector side at the time of turn-off, and increasing the carriers remaining on the collector side.
- injection of carriers from the collector side to the drift layer can be controlled, so that the withstand voltage can be maintained even when the thickness of the drift layer is reduced to lower the on-state voltage. be able to.
- FS-IGBT As an IGBT (hereinafter referred to as FS-IGBT) provided with this field stop layer, conventionally, it has a concentration peak higher than the carrier concentration of the drift layer, and the carrier concentration from the concentration peak toward the collector side and the emitter side
- An apparatus provided with a field stop layer having a low carrier concentration distribution has been proposed (eg, Patent Document 1 (page 3 right lower column, lines 16 to 20, page 4 upper right column, lines 5 to 11, See Figures 1 and 2).
- Patent Document 1 page 3 right lower column, lines 16 to 20, page 4 upper right column, lines 5 to 11, See Figures 1 and 2.
- the carrier concentration of the field stop layer is equal to the carrier concentration of the drift layer at the interface with the drift layer, and increases from the interface with the drift layer toward the collector to exhibit a peak. Gradually decreases toward the collector layer.
- a method of forming a field stop layer having such a carrier concentration distribution conventionally, a method of forming a field stop layer using the effect of donor conversion is known.
- a layer of defects vacancy (V)
- V vacancy
- the hydrogen (H) atom irradiated to this defect and the oxygen (O) atom in the n - type semiconductor substrate are combined to generate a composite defect (VOH (Vacancy-Oxide-Hydrogen) defect). Since this VOH defect acts as a donor (hereinafter referred to as a hydrogen donor) supplying electrons, the VOH defect layer functions as an n-type field stop layer.
- the heat treatment after proton irradiation can increase the VOH defect density and increase the hydrogen donor concentration (VOH defect concentration).
- This activation process for increasing the hydrogen donor concentration can be realized by low temperature annealing at 400 ° C. or less. Therefore, for example, in manufacturing (manufacturing) a thin IGBT or thin diode in which the product thickness is reduced by grinding, the process after reducing the thickness of the semiconductor wafer can be significantly shortened.
- a broad n-type field stop layer (a wide carrier concentration profile in the depth direction) is formed by a plurality of n-type layers having carrier concentration peaks at different depths by plural times of proton irradiation with different accelerating voltages. It can be formed (see, for example, Patent Document 2 below).
- n-type field stop layer by proton irradiation
- n-type using a proton donor effect by irradiating protons from the back surface of a semiconductor wafer and simultaneously irradiating two types of lasers of different wavelengths There has been proposed a method of forming a p + -type collector layer in a region through which protons pass (hereinafter referred to as a proton-permeable region) on the back surface side of a semiconductor wafer after forming a field stop layer (for example, See 3).
- the carrier concentration of the portion (tail portion) near the pn junction between the n-type field stop layer and the p + -type collector layer is greater than the carrier concentration of the n ⁇ -type drift layer Is also high.
- a region on the back side of the substrate (proton permeable region) where protons have passed once by proton irradiation for forming an n-type field stop layer is likely to be hydrogen donor. Therefore, when a plurality of proton irradiations with different accelerating voltages are performed in order to form a broad n-type field stop layer, the collector side is most among the plurality of n-type layers constituting the broad n-type field stop layer.
- the carrier concentration of the p + -type collector layer in order to speed up the switching speed of the IGBT, it is necessary to lower the carrier concentration of the p + -type collector layer in order to suppress the hole injection efficiency (hole) from the collector side, the p + -type collector
- the carrier concentration of the layer is lowered, the carrier concentration difference from the n-type layer closest to the collector side is reduced, and thus there is a problem that the variation of the on voltage becomes large.
- the n-type field stop layer is formed by ion implantation of n-type impurities such as phosphorus (P) and selenium (Se), the carrier concentration of the n-type field stop layer near the boundary with the collector layer is high. As a result, the same problem arises.
- n-type impurities such as phosphorus (P) and selenium (Se)
- An object of the present invention is to provide a semiconductor device and a method of manufacturing the semiconductor device, which can reduce variations in on voltage in order to solve the above-mentioned problems of the prior art.
- a method of manufacturing a semiconductor device includes a front element structure, a second semiconductor layer of a first conductivity type, and a second conductivity type of a second conductivity type.
- a method of manufacturing a semiconductor device provided with a semiconductor layer which has the following features.
- the front surface element structure is provided on one main surface side of the first semiconductor layer of the first conductivity type.
- the second semiconductor layer is provided on the surface layer of the other main surface of the first semiconductor layer.
- the carrier concentration of the second semiconductor layer is higher than the carrier concentration of the first semiconductor layer.
- the third semiconductor layer is provided at a position shallower than the second semiconductor layer in a surface layer of the other main surface of the first semiconductor layer.
- hydrogen atoms are implanted from the other main surface side of the semiconductor substrate of the first conductivity type to be the first semiconductor layer, and the other main surface of the semiconductor substrate is formed in the surface layer of the other main surface of the semiconductor substrate.
- a first implantation step is performed to form a plurality of the second semiconductor layers of the first conductivity type having a peak of carrier concentration at different depths from the surface.
- a first heat treatment step of promoting donorization of the hydrogen atoms by the first heat treatment is performed.
- a second conductivity type impurity is implanted from the other main surface side of the semiconductor substrate, and the surface layer of the other main surface of the semiconductor substrate is more than the second semiconductor layer.
- a second implantation step is performed to form the third semiconductor layer of the second conductivity type at a shallow position.
- the semiconductor substrate is locally heated by a second heat treatment to activate the third semiconductor layer, and the third semiconductor of the second semiconductor layer disposed closest to the third semiconductor layer
- a second heat treatment step is performed to reduce the carrier concentration at the boundary with the layer.
- the difference between the carrier concentration of the third semiconductor layer and the peak value of the carrier concentration is the boundary between the second semiconductor layer disposed closest to the third semiconductor layer and the third semiconductor layer.
- the carrier concentration is reduced so as to be a predetermined value or more with respect to the carrier concentration of
- the second heat treatment step is performed by heating the other main surface side of the semiconductor substrate to eliminate the hydrogen atoms.
- the carrier concentration of the boundary between the second semiconductor layer disposed on the third semiconductor layer side and the third semiconductor layer is reduced.
- the position of the peak of the carrier concentration of the second semiconductor layer disposed closest to the third semiconductor layer is lowered.
- the first heat treatment step a carrier concentration distribution decreasing from the position of the peak toward the third semiconductor layer is obtained.
- the gradient of the carrier concentration distribution of the second portion from the predetermined position toward the third semiconductor layer is gentler than the gradient of the carrier concentration distribution from the predetermined position toward the third semiconductor layer toward the predetermined position away from the position of Forming a plurality of the second semiconductor layers.
- the carrier concentration of the second portion of the second semiconductor layer arranged closest to the third semiconductor layer is lowered.
- the carrier concentration distribution of the second portion of the second semiconductor layer disposed closest to the third semiconductor layer in the second heat treatment step. Is made steeper than the state before the second heat treatment.
- the second semiconductor layer disposed closest to the third semiconductor layer may be the third semiconductor layer It is characterized in that the carrier concentration at the boundary is reduced to less than or equal to the carrier concentration at the boundary with the other second semiconductor layer adjacent to the second semiconductor layer.
- the difference in concentration from the peak value of the carrier concentration of the third semiconductor layer is the most toward the third semiconductor layer.
- the carrier concentration is lowered to be five or more times the carrier concentration at the boundary between the second semiconductor layer and the third semiconductor layer arranged.
- the carrier concentration peak value or more of the second semiconductor layer disposed closest to the third semiconductor layer is the carrier. It is characterized in that the third semiconductor layer having a peak value of concentration is formed.
- the second semiconductor layer disposed closest to the third semiconductor layer may be the third semiconductor layer It is characterized in that the carrier concentration at the boundary is lowered to about the carrier concentration of the first semiconductor layer.
- the semiconductor device has the following features.
- a front surface element structure is provided on one main surface side of the first semiconductor layer of the first conductivity type.
- a plurality of second semiconductor layers of the first conductivity type are provided on the surface layer of the other main surface of the first semiconductor layer.
- the second semiconductor layer has a carrier concentration higher than that of the first semiconductor layer, and has a peak of carrier concentration at different depths from the other main surface of the first semiconductor layer. Furthermore, the second semiconductor layer has a carrier concentration distribution which decreases from the position of the peak toward the third semiconductor layer.
- the second semiconductor layer other than the second semiconductor layer disposed closest to the third semiconductor layer has a carrier concentration distribution of a first portion from the position of the peak to a predetermined position separated to the third semiconductor layer side
- the gradient of the carrier concentration distribution of the second portion on the third semiconductor layer side from the predetermined position is gentler than the gradient of.
- the gradient of the carrier concentration distribution of the second semiconductor layer disposed closest to the third semiconductor layer is steeper than the gradient of the carrier concentration distribution of the second portion.
- the second conductive third semiconductor layer is provided at a position shallower than the second semiconductor layer in the surface layer on the other main surface of the first semiconductor layer.
- the carrier concentration at the boundary between the second semiconductor layer disposed closest to the third semiconductor layer and the third semiconductor layer is the second semiconductor.
- the carrier concentration is lower than the carrier concentration at the boundary with the other second semiconductor layer adjacent to the layer.
- the peak value of the carrier concentration of the third semiconductor layer may be the third semiconductor of the second semiconductor layer disposed closest to the third semiconductor layer. It is characterized in that it is five times or more the carrier concentration at the boundary with the layer.
- the front surface element structure includes a first semiconductor region of the second conductivity type, a second semiconductor region of the first conductivity type, a gate insulating film and a gate electrode. And further comprising a first electrode and a second electrode.
- the first semiconductor region is provided on a surface layer of one of the main surfaces of the first semiconductor layer.
- the second semiconductor region is provided inside the first semiconductor region.
- the gate insulating film is provided in contact with a region of the first semiconductor region between the first semiconductor layer and the second semiconductor region.
- the gate electrode is provided on the opposite side of the first semiconductor region with the gate insulating film interposed therebetween.
- the first electrode is in contact with the first semiconductor region and the second semiconductor region.
- the second electrode is in contact with the other main surface of the first semiconductor layer.
- the carrier concentration at the boundary of the second semiconductor layer closest to the third semiconductor layer to the third semiconductor layer can be reduced. Therefore, regardless of the carrier concentration of the third semiconductor layer, the carrier peak concentration of the third semiconductor layer and the carrier concentration of the boundary of the second semiconductor layer closest to the third semiconductor layer to the third semiconductor layer The difference can be secured to a predetermined value or more.
- the semiconductor device and the method of manufacturing the semiconductor device according to the present invention it is possible to reduce the variation of the on voltage.
- FIG. 1 is a cross-sectional view showing the structure of the semiconductor device according to the embodiment.
- FIG. 2 is a characteristic diagram showing the carrier concentration distribution along the cutting line A-A 'of FIG.
- FIG. 3 is a characteristic diagram showing the carrier concentration distribution on the collector side of FIG. 2 in an enlarged manner.
- FIG. 4 is a characteristic diagram showing the variation of the on voltage of the semiconductor device according to the embodiment.
- FIG. 5 is a flowchart showing an outline of a method of manufacturing a semiconductor device according to the embodiment.
- n and p in the layer or region having n or p, it is meant that electrons or holes are majority carriers, respectively.
- + and-attached to n and p mean that the carrier concentration is higher and the carrier concentration is lower than that of the layer or region to which it is not attached.
- FIG. 1 is a cross-sectional view showing the structure of the semiconductor device according to the embodiment.
- FIG. 1 shows one unit cell (functional unit of the element) of an active region (a region through which current flows in the on state) responsible for current driving, and another unit cell repeatedly arranged to be adjacent to this unit cell.
- the unit cell and a termination voltage withstanding structure surrounding the active region are not shown.
- the termination withstand voltage structure is a region that relaxes the electric field on the front surface side of the substrate of the n ⁇ -type drift layer 1 and holds the withstand voltage, and has, for example, a withstand voltage structure combining a guard ring, a field plate, a resurf, or the like.
- the semiconductor device shown in FIG. 1 is an FS-IGBT provided with an n-type field stop layer 10 having a carrier concentration higher than that of the n ⁇ -type drift layer 1 on the collector side of the n ⁇ -type drift layer 1.
- the first semiconductor layer of the first conductivity type according to the present invention is realized by the n ⁇ type drift layer 1
- the second semiconductor of the first conductivity type according to the present invention is realized by the n type field stop layer 10. Layers are realized.
- the other main surface is realized by the collector side of the n ⁇ -type drift layer 1.
- the front surface side (one main surface side) of the n ⁇ type semiconductor substrate (semiconductor chip) to be the n ⁇ type drift layer 1, the p type base region 2, the trench 3, and the gate insulating film A MOS gate structure comprising the gate electrode 5 and the n + -type emitter region 6 is provided.
- the front surface element structure according to the present invention is realized by the MOS gate structure.
- the p-type base region 2 is provided on the surface layer of the front surface of the n ⁇ -type semiconductor substrate.
- Trench 3 penetrates p type base region 2 in the depth direction to reach n ⁇ type drift layer 1.
- a gate insulating film 4 is provided along the inner wall of the trench 3
- a gate electrode 5 is provided inside the gate insulating film 4.
- n + -type emitter region 6 is selectively provided inside the p-type base region 2 so as to face the gate electrode 5 with the gate insulating film 4 provided on the side wall of the trench 3 interposed therebetween.
- a p + -type contact region (not shown) may be selectively provided in the p-type base region 2 so as to be in contact with the n + -type emitter region 6.
- Emitter electrode 8 is in contact with p-type base region 2 (or p + -type contact region) and n + -type emitter region 6 and is electrically isolated from gate electrode 5 by interlayer insulating film 7.
- a p + -type collector layer 9 is provided on the surface layer on the back surface of the n ⁇ -type semiconductor substrate.
- the p + -type collector layer 9 realizes the third semiconductor layer of the second conductivity type according to the present invention.
- the n-type field stop layer 10 is provided deeper than the p + -type collector layer 9 from the rear surface of the substrate.
- the p + -type collector layer 9 is a region (hereinafter referred to as a hydrogen-permeable region) through which hydrogen atoms pass during ion implantation (hereinafter referred to as hydrogen ion implantation) of hydrogen (H) to form an n-type field stop layer 10 described later. Provided).
- the n-type field stop layer 10 is composed of a plurality of n-type layers each having a carrier concentration peak (hereinafter referred to as a carrier peak concentration) at different depths from the back surface of the n ⁇ -type semiconductor substrate.
- FIG. 1 shows an n-type field stop layer 10 consisting of four n-type layers.
- the n-type field stop layer 10 has a broad (wide in the depth direction) carrier concentration profile.
- the n-type field stop layer 10 comprises four n-type layers (hereinafter referred to as first to fourth n-type layers) 10a to 10d having carrier peak concentrations at different depths from the back surface of the n - type semiconductor substrate Will be described by way of example.
- the first n-type layer 10 a is disposed closest to the collector and is in contact with the p + -type collector layer 9.
- the second n-type layer 10 b is disposed closer to the emitter than the first n-type layer 10 a and is in contact with the first n-type layer 10 a.
- the third n-type layer 10c is disposed closer to the emitter than the second n-type layer 10b, and is in contact with the second n-type layer 10b.
- the fourth n-type layer 10d is disposed closer to the emitter than the third n-type layer 10c, and is in contact with the third n-type layer 10c.
- the tail part mentioned later is not formed in the 1st n type layer 10a.
- the carrier concentration at the boundary between the first n-type layer 10 a and the p + -type collector layer 9 is lower than that in the case where the tail portion is formed.
- 1 shows a state in which the carrier concentration of the p + -type collector layer 9 side not tail portion is formed to a 1n-type layer 10a is lower, of the 1n-type layer 10a, the p + -type collector layer 9 It shows by making hatching near the border with.
- tail portions are formed in the second to fourth n-type layers 10b to 10d, respectively.
- the tail portions of the second to fourth n-type layers 10b to 10d are in contact with the first to third n-type layers 10a to 10c on the collector side, respectively.
- the thicknesses of the first to fourth n-type layers 10a to 10d may be different from or equal to one another.
- FIG. 2 is a characteristic diagram showing the carrier concentration distribution along the cutting line AA ′ of FIG.
- FIG. 3 is a characteristic diagram showing the carrier concentration distribution on the collector side of FIG. 2 in an enlarged manner.
- FIG. 4 is a characteristic diagram showing the variation of the on voltage of the semiconductor device according to the embodiment.
- the carrier concentration in the depth (the portion indicated by the arrow 21) from the back surface of the substrate (the junction interface between the p + -type collector layer 9 and the collector electrode 11) of FIG. 2 to the vicinity of the tail portion of the second n-type layer 10b. It shows the distribution.
- No laser annealing is a state before laser annealing, and is a carrier concentration distribution of the n-type field stop layer 10 in the process of manufacture.
- With laser annealing is a state after laser annealing and is a carrier concentration distribution of the n-type field stop layer 10 when the device (product) is completed. The carrier concentration distribution of the n-type field stop layer 10 when the product is completed will be described below.
- the carrier peak concentrations C npk1 to C npk4 are higher (C n pk 1 > C n pk 2 > C n pk 3 > C n pk 4 ). That is, of the carrier peak concentration C npk1 ⁇ C npk4 of the 1 ⁇ 4n-type layer 10a ⁇ 10d, the carrier peak concentration C Npk1 of the 1n-type layer 10a disposed on the most collector side is the highest.
- Carrier peak concentration C Npk1 of the 1n-type layer 10a is, for example, p + -type carrier peak of the collector layer 9 is concentration C ppk following (C ppk / C npk1 ⁇ 1 ). If p + -type collector layer 9 carrier peak concentration C ppk of less than the carrier peak concentration C Npk1 of the 1n-type layer 10a, although the ohmic contact between the collector electrode 11 can be secured, the injection efficiency of holes is low It is because there is a possibility that it does not operate as IGBT because it becomes too much.
- a carrier peak concentration C ppk of p + -type collector layer 9 by appropriately setting the density difference C pn1 the carrier peak concentration C Npk1 of the 1n-type layer 10a, inhibit the efficiency of hole injection from the collector .
- a carrier peak concentration C ppk of p + -type collector layer 9 by lowering the carrier peak concentration C ppk of p + -type collector layer 9, a carrier peak concentration C ppk of p + -type collector layer 9, a carrier peak concentration C Npk1 of the 1n-type layer 10a
- Fast switching can be achieved by reducing the concentration difference C pn1 of
- the carrier peak concentration C Npk1 of the 1n-type layer 10a is, of the 1n-type layer 10a, is preferably about 10 times or more of the carrier concentration C n1a boundary 12a between the p + -type collector layer 9 (C npk1 / C n1a 1010 ).
- the reason is that high speed switching can be achieved.
- the boundary 12a of the first n-type layer 10a to the p + -type collector layer 9 is the carrier concentration (donor concentration) C n1a of the first n-type layer 10a and the carrier concentration (acceptor concentration) of the p + -type collector layer 9 Almost equal depth positions.
- the depth from the back surface of the substrate of the peak position 20a of the first n-type layer 10a is considered to reduce the thickness of the n -- type semiconductor substrate in order to miniaturize the p + -type collector of the first n-type layer 10a Preferably as far as possible from the boundary 12 a with the layer 9. The reason is that the variation ⁇ Von of the on voltage can be reduced.
- Tail portions are formed in the second to fourth n-type layers 10b to 10d, respectively.
- the tail portions of the second to fourth n-type layers 10b to 10d are in contact with the first to third n-type layers 10a to 10c on the collector side, respectively.
- the tail portion is the portion where the carrier concentration is decreasing with a gentle gradient so that the tail is from the inflection point (the change point of the concentration gradient) away from the peak position by a predetermined width on the collector side to the collector side. is there.
- the slope of the carrier concentration distribution in the tail portion is gradually reduced toward the collector side than the slope of the carrier concentration distribution from the peak position to the inflection point (between the peak position and the tail portion).
- the carrier concentration C n2 of the boundary 12b between the first n-type layer 10a and the tail portion of the second n-type layer 10b is lower than the carrier peak concentration C npk1 of the first n-type layer 10a, and the second n-type layer 10b and the third n It is higher than the carrier concentration C n3 of the boundary 12c with the tail portion of the mold layer 10c.
- the carrier concentration C n3 of the boundary 12c between the second n-type layer 10b and the tail portion of the third n-type layer 10c is higher than the carrier concentration C n4 of the boundary 12d between the third n-type layer 10c and the tail portion of the fourth n-type layer 10d. high.
- the carrier concentration C n4 of the boundary 12 d of the third n-type layer 10 c and the tail portion of the fourth n-type layer 10 d is the carrier concentration of the boundary 12 e of the fourth n-type layer 10 d and the n ⁇ drift layer 1 (ie, n ⁇ drift Carrier concentration (C n5 ) of layer 1 is higher (C npk1 > C n2 > C n3 > C n4 > C n5 ).
- a tail portion is not formed in the first n-type layer 10a. That is, the carrier concentration of the portion 22 on the collector side from the peak position 20a of the first n-type layer 10a decreases with a substantially constant gradient from the peak position 20a to the collector side.
- the peak position 20a of the first n-type layer 10a to the portion 22 on the collector side is the portion of the first n-type layer 10a from the peak position 20a to the boundary 12a with the p + -type collector layer 9.
- the gradient of the carrier concentration distribution of the portion 22 on the collector side from the peak position 20a of the first n-type layer 10a is steeper than that of the tail portions of the second to fourth n-type layers 10b to 10d.
- the gradient of the carrier concentration distribution of the portion 22 on the collector side from the peak position 20a of the first n-type layer 10a is steeper than the gradient of the carrier concentration distribution of the tail portion 33 of the first n-type layer 10a without laser annealing. It has become.
- the tail portion 33 of the first n-type layer 10a refers to the p + -type collector layer 9 from the inflection point 31 which is separated from the peak position 20a of the first n-type layer 10a by a predetermined width on the collector side. Is the portion up to the boundary 12a.
- the carrier concentration C n1a of the boundary 12a of the first n-type layer 10a with the p + -type collector layer 9 is less than the carrier concentration C n2 of the boundary 12b of the first n-type layer 10a and the tail of the second n-type layer 10b.
- the degree is preferably (C n1 a ⁇ C n2 ).
- the carrier peak concentration C ppk of the p + -type collector layer 9 in the case of high-speed switching is, for example, 10 15 / cm 3 or more and 10 17 / cm 3 or less (preferably 10 17 / cm 3 or less in the first half) It is an extent.
- the carrier peak concentration C ppk of p + -type collector layer 9, of the 1n-type layer 10a by setting the density difference C pn 2 the carrier concentration C n1a boundary 12a between the p + -type collector layer 9 As shown in FIG.
- the variation ⁇ Von of the on voltage can be suppressed to, for example, about 5% or less.
- a carrier peak concentration C ppk of p + -type collector layer 9, of the 1n-type layer 10a, the upper limit of the density difference C pn 2 the carrier concentration C n1a boundary 12a between the p + -type collector layer 9 is, for example, above It may be determined in consideration of the switching speed as described above.
- the carrier concentration C n1a of the boundary 12 a of the first n-type layer 10 a with the p + -type collector layer 9 can be reduced to about the impurity concentration of the bulk substrate (ie, the carrier concentration C n5 of the n ⁇ -type drift layer 1) is there.
- the bulk substrate is a bulk single crystal silicon substrate grown by a general crystal growth method such as Czochralski method or float zone method. That is, the carrier concentration C n1a of the boundary 12a of the first n-type layer 10a with the p + -type collector layer 9 is the carrier concentration C n2 of the boundary 12b of the first n-type layer 10a and the tail portion of the second n-type layer 10b.
- the carrier concentration C n3 of the boundary 12c between the second n-type layer 10b and the tail of the third n-type layer 10c, and the carrier concentration C n4 of the boundary 12d between the tail of the third n-type layer 10c and the tail of the fourth n-type layer 10d It may be low.
- FIG. 5 is a flowchart showing an outline of a method of manufacturing a semiconductor device according to the embodiment.
- a MOS gate structure on the front surface side of the n ⁇ type semiconductor substrate (semiconductor wafer) to be the n ⁇ type drift layer 1, a MOS gate structure, an interlayer insulating film 7, an emitter electrode 8, a termination breakdown voltage structure (not A front surface element structure is formed (step S1), which is composed of a passivation film (not shown) and the like.
- step S1 A front surface element structure
- the n ⁇ -type semiconductor substrate is ground from the back surface side to a position of a product thickness used as a semiconductor device (step S 2).
- step S3 the process of step S3 implements the first injection process according to the present invention.
- hydrogen ions are implanted a plurality of times at different acceleration voltages, and the positions of the implantation depths of each hydrogen ion implantation (that is, the range Rp of hydrogen ion implantation) are peaks of carrier peak concentrations Cnpk1 to Cnpk4 .
- First to fourth n-type layers 10a to 10d are formed at positions 20a to 20d.
- the implantation depth of hydrogen ion implantation is deeper than the penetration depth of the laser irradiated from the back surface of the substrate in the laser annealing step for activating the p + -type collector layer 9 described later.
- the hydrogen ion implantation in step S3 may be, for example, proton implantation (proton irradiation).
- proton irradiation a layer of defects (vacancy (V)) is formed at a predetermined depth from the back surface of the n ⁇ type semiconductor substrate to be the n ⁇ type drift layer 1.
- the hydrogen atom irradiated to the defect and the oxygen (O) atom in the n -- type semiconductor substrate are combined to generate a complex defect (VOH defect).
- the layer of VOH defects functions as the n-type field stop layer 10 because the VOH defects act as donors (hydrogen donors) that supply electrons.
- furnace annealing is performed to increase the hydrogen donor concentration (VOH defect concentration) by increasing the VOH defect density (step S4).
- the first heat treatment process according to the present invention is realized by the process of step S4.
- the furnace annealing in step S4 promotes hydrogen donor generation to form a donor layer having a carrier peak concentration C npk1 to C npk4 higher than the carrier concentration C n5 of the n ⁇ type semiconductor substrate inside the n ⁇ type drift layer 1 Ru.
- This donor layer is the first to fourth n-type layers 10a to 10d.
- n - type semiconductor before hydrogen ion implantation ie, before introduction of manufacturing process, from the back surface of the substrate to a region (collector side) shallower than n-type field stop layer 10
- a hydrogen permeable region (not shown) having a hydrogen concentration equal to or higher than the hydrogen concentration of the substrate (bulk substrate) is formed.
- This hydrogen permeation region may be donorized.
- the carrier concentration distributions of the first to fourth n-type layers 10a to 10d become carrier concentration distributions in the state without laser annealing in FIGS. That is, the tail portion 33 is formed in all of the first to fourth n-type layers 10a to 10d.
- the carrier concentration C n1 b of the boundary 12 f of the tail portion 33 of the first n-type layer 10 a with the p + -type collector layer 9 is adjacent to the tail portions of the second to fourth n-type layers 10 b to 10 d and their collectors.
- the carrier concentration C n2 to C n4 at the boundaries 12b to 12d with the first to third n-type layers 10a to 10c is higher (C n1 b > C n2 > C n3 > C n4 ).
- the surface layer of the back surface of the n -- type semiconductor substrate is formed by ion implanting p-type impurities such as boron from the back side after grinding of the n -- type semiconductor substrate (hereinafter referred to as p-type impurity ion implantation).
- the p + -type collector layer 9 is formed at a position shallower than the n-type field stop layer 10 (step S5). Specifically, the p + -type collector layer 9 is formed in the hydrogen permeable region on the back surface of the substrate.
- the process of step S5 implements the second injection process according to the present invention.
- step S6 laser is irradiated from a back surface of the n ⁇ -type semiconductor substrate with a predetermined penetration depth to perform laser annealing (second heat treatment) (step S6).
- the p + -type collector layer 9 is activated, and the carrier concentration C n1 b in the vicinity of the boundary 12 f of the tail portion 33 of the first n-type layer 10 a with the p + -type collector layer 9 is reduced.
- the step of step S6 implements the second heat treatment step according to the present invention.
- a portion from a laser irradiation surface (substrate back surface) to a relatively shallow depth of, for example, 2 ⁇ m to 3 ⁇ m is heated to about 1000 ° C. or more (eg, about 1416 ° C. of silicon (Si) melting point) To melt away hydrogen donors (VOH defects) and reduce the carrier concentration in the heated portion.
- Si silicon
- a carrier peak concentration C ppk of p + -type collector layer 9, of the 1n-type layer 10a after the laser annealing, the concentration difference C pn 2 between the boundary of the carrier concentration C n1a of the p + -type collector layer 9 is above
- the carrier concentration in the vicinity of the boundary 12 a of the first n-type layer 10 a with the p + -type collector layer 9 is reduced so as to be within the range.
- the gradient of the carrier concentration distribution of the portion 22 on the collector side from the peak position 20a of the first n-type layer 10a is steeper than that before the laser annealing (without the laser annealing).
- the gradient of the carrier concentration distribution of the portion of the first n-type layer 10a with the tail portion 33 eliminated by making the tail portion 33 of the first n-type layer 10a disappear is steeper than before the laser annealing.
- Gradient of the carrier concentration distribution of the portion abolished tails 33 of the 1n-type layer 10a is, a carrier peak concentration C ppk of p + -type collector layer 9, after the laser annealing of the 1n-type layer 10a, the p + -type
- the concentration difference C pn2 with the carrier concentration C n1a at the boundary with the collector layer 9 may be within the above range, and can be set appropriately.
- the gradient of the carrier concentration distribution of the portion of the first n-type layer 10a where the tail portion 33 is eliminated is substantially the same as the gradient of the carrier concentration distribution of the portion 32 from the peak position 20a to the inflection point 31 in the state before laser annealing. It may be the same level.
- step S6 laser annealing may be performed under conditions that allow heating of a portion relatively shallow from the laser irradiation surface to about 500 ° C. or higher at which hydrogen donors can be eliminated.
- laser annealing is performed in a short time of, for example, about 100 ns so that the hydrogen donor does not disappear in the deep part of the first n-type layer 10a or more from the laser irradiation surface.
- the carrier concentration distribution of the first n-type layer 10a becomes the carrier concentration distribution in the state with laser annealing in FIGS.
- the carrier concentration distributions of the second to fourth n-type layers 10b to 10d hardly change before and after the laser annealing.
- a collector electrode 11 in contact with the p + -type collector layer 9 is formed as a back surface electrode (step S7). Thereafter, the semiconductor wafer is diced into chips, whereby the IGBT shown in FIG. 1 is completed.
- the n-type field stop layer is formed by hydrogen ion implantation, the hydrogen atoms in the relatively shallow portion of the back surface of the substrate are eliminated by the subsequent laser annealing to form the n-type field.
- the carrier concentration of the stop layer can be reduced.
- the carrier concentration of the n-type field stop layer is reduced by laser annealing after the p + -type collector layer is formed. It can be done.
- the concentration difference between the carrier concentration of the boundary between the p + -type collector layer A predetermined value or more can be secured. Therefore, the variation of the on voltage can be reduced.
- the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention.
- the n-type field stop layer including four n-type layers is provided as an example, but two or three n-type layers constituting the n-type field stop layer are described. Even if it is five or more, the same effect is produced.
- the present invention is applicable to reducing the carrier concentration in a relatively shallow portion.
- the trench gate type IGBT is described as an example, but the present invention is also applicable to a planar gate type IGBT.
- the semiconductor device and the method for manufacturing the semiconductor device according to the present invention are useful for a semiconductor device provided with an n-type field stop layer, and in particular, an IGBT having an n-type field stop layer disposed deep from the back surface of the substrate. Suitable for
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Abstract
Description
実施の形態にかかる半導体装置の構造について説明する。図1は、実施の形態にかかる半導体装置の構造を示す断面図である。図1には、電流駆動を担う活性領域(オン状態のときに電流が流れる領域)の1つの単位セル(素子の機能単位)を示し、この単位セルに隣接するように繰り返し配置された他の単位セルや、活性領域の周囲を囲む終端耐圧構造を図示省略する。終端耐圧構造は、n-型ドリフト層1の基板おもて面側の電界を緩和し耐圧を保持する領域であり、例えばガードリング、フィールドプレートおよびリサーフ等やこれらを組み合わせた耐圧構造を有する。
次に、実施の形態にかかる半導体装置の製造方法について説明する。図5は、実施の形態にかかる半導体装置の製造方法の概要を示すフローチャートである。まず、n-型ドリフト層1となるn-型半導体基板(半導体ウエハ)のおもて面側に、一般的な方法によりMOSゲート構造、層間絶縁膜7、エミッタ電極8、終端耐圧構造(不図示)およびパッシベーション膜(不図示)などからなるおもて面素子構造を形成する(ステップS1)。次に、n-型半導体基板を裏面側から研削していき、半導体装置として用いる製品厚さの位置まで研削する(ステップS2)。
2 p型ベース領域
3 トレンチ
4 ゲート絶縁膜
5 ゲート電極
6 n+型エミッタ領域
7 層間絶縁膜
8 エミッタ電極
9 p+型コレクタ層
10 n型フィールドストップ層
10a 第1n型層
10b 第2n型層
10c 第3n型層
10d 第4n型層
11 コレクタ電極
12a レーザーアニール後の第1n型層の、p+型コレクタ層との境界
12b 第1n型層と第2n型層のテール部との境界
12c 第2n型層と第3n型層のテール部との境界
12d 第3n型層と第4n型層のテール部との境界
12e 第4n型層とn-型ドリフト層との境界
12f レーザーアニール前の第1n型層のテール部の、p+型コレクタ層との境界
20a 第1n型層のピーク位置
20b 第2n型層のピーク位置
20c 第3n型層のピーク位置
20d 第4n型層のピーク位置
22 レーザーアニール後の第1n型層の、ピーク位置からコレクタ側の部分
31 レーザーアニール前の第1n型層の変曲点
32 レーザーアニール前の第1n型層の、ピーク位置から変曲点までの部分
33 レーザーアニール前の第1n型層のテール部
Cn1a レーザーアニール後の第1n型層の、p+型コレクタ層との境界のキャリア濃度
Cn1b レーザーアニール前の第1n型層のテール部の、p+型コレクタ層との境界のキャリア濃度
Cn2 第1n型層と第2n型層のテール部との境界のキャリア濃度
Cn3 第2n型層と第3n型層のテール部との境界のキャリア濃度
Cn4 第3n型層と第4n型層のテール部との境界のキャリア濃度
Cn5 n-型ドリフト層のキャリア濃度
Cnpk1 第1n型層のキャリアピーク濃度
Cnpk2 第2n型層のキャリアピーク濃度
Cnpk3 第3n型層のキャリアピーク濃度
Cnpk4 第4n型層のキャリアピーク濃度
Cpn1 p+型コレクタ層のキャリアピーク濃度と、第1n型層のキャリアピーク濃度との濃度差(=Cppk/Cnpk1)
Cpn2 p+型コレクタ層のキャリアピーク濃度と、第1n型層の、p+型コレクタ層との境界のキャリア濃度との濃度差(=Cppk/Cn1a)
Cppk p+型コレクタ層のキャリアピーク濃度
Claims (13)
- 第1導電型の第1半導体層の一方の主面側に設けられたおもて面素子構造と、前記第1半導体層の他方の主面の表面層に設けられた、前記第1半導体層よりもキャリア濃度の高い第1導電型の第2半導体層と、前記第1半導体層の他方の主面の表面層の、前記第2半導体層よりも浅い位置に設けられた第2導電型の第3半導体層と、を備えた半導体装置の製造方法であって、
前記第1半導体層となる第1導電型の半導体基板の他方の主面側から水素原子を注入し、前記半導体基板の他方の主面の表面層に、それぞれ前記半導体基板の他方の主面から異なる深さにキャリア濃度のピークを有する第1導電型の複数の前記第2半導体層を形成する第1注入工程と、
第1熱処理により前記水素原子のドナー化を促進させる第1熱処理工程と、
前記第1熱処理工程の後、前記半導体基板の他方の主面側から第2導電型不純物を注入し、前記半導体基板の他方の主面の表面層の、前記第2半導体層よりも浅い位置に第2導電型の前記第3半導体層を形成する第2注入工程と、
第2熱処理により前記半導体基板を局所的に加熱し、前記第3半導体層を活性化させるとともに、最も前記第3半導体層側に配置された前記第2半導体層の、前記第3半導体層との境界のキャリア濃度を低下させる第2熱処理工程と、
を含み、
前記第2熱処理工程では、前記第3半導体層のキャリア濃度のピーク値との濃度差が、最も前記第3半導体層側に配置された前記第2半導体層の、前記第3半導体層との境界のキャリア濃度に対して所定値以上となるようにキャリア濃度を低下させることを特徴とする半導体装置の製造方法。 - 前記第2熱処理工程では、前記半導体基板の他方の主面側を加熱して前記水素原子を消失させることにより、最も前記第3半導体層側に配置された前記第2半導体層の、前記第3半導体層との境界のキャリア濃度を低下させることを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記第2熱処理工程では、最も前記第3半導体層側に配置された前記第2半導体層の、キャリア濃度の前記ピークの位置よりも前記第3半導体層側の部分のキャリア濃度を低下させることを特徴とする請求項1または2に記載の半導体装置の製造方法。
- 前記第1熱処理工程では、前記ピークの位置から前記第3半導体層に向って減少するキャリア濃度分布を有し、かつ前記ピークの位置から前記第3半導体層側に離れた所定位置までの第1部分のキャリア濃度分布の勾配よりも、前記所定位置から前記第3半導体層側の第2部分のキャリア濃度分布の勾配が緩やかな複数の前記第2半導体層を形成し、
前記第2熱処理工程では、最も前記第3半導体層側に配置された前記第2半導体層の前記第2部分のキャリア濃度を低下させることを特徴とする請求項3に記載の半導体装置の製造方法。 - 前記第2熱処理工程では、最も前記第3半導体層側に配置された前記第2半導体層の前記第2部分のキャリア濃度分布の勾配を、前記第2熱処理前の状態よりも急峻にすることを特徴とする請求項4に記載の半導体装置の製造方法。
- 前記第2熱処理工程では、最も前記第3半導体層側に配置された前記第2半導体層の、前記第3半導体層との境界のキャリア濃度を、当該第2半導体層に隣接する他の前記第2半導体層との境界のキャリア濃度以下に低下させることを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記第2熱処理工程では、前記第3半導体層のキャリア濃度のピーク値との濃度差を、最も前記第3半導体層側に配置された前記第2半導体層の、前記第3半導体層との境界のキャリア濃度に対して5倍以上となるようにキャリア濃度を低下させることを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記第2注入工程では、最も前記第3半導体層側に配置された前記第2半導体層のキャリア濃度のピーク値以上のキャリア濃度のピーク値を有する前記第3半導体層を形成することを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記第2熱処理工程では、最も前記第3半導体層側に配置された前記第2半導体層の、前記第3半導体層との境界のキャリア濃度を、前記第1半導体層のキャリア濃度程度まで低下させることを特徴とする請求項1に記載の半導体装置の製造方法。
- 第1導電型の第1半導体層の一方の主面側に設けられたおもて面素子構造と、
前記第1半導体層の他方の主面の表面層に設けられた、前記第1半導体層よりもキャリア濃度が高く、かつそれぞれ前記第1半導体層の他方の主面から異なる深さにキャリア濃度のピークを有する第1導電型の複数の第2半導体層と、
前記第1半導体層の他方の主面の表面層の、前記第2半導体層よりも浅い位置に設けられた第2導電型の第3半導体層と、
を備え、
前記第2半導体層は、前記ピークの位置から前記第3半導体層に向って減少するキャリア濃度分布を有し、
最も前記第3半導体層側に配置された前記第2半導体層以外の前記第2半導体層は、前記ピークの位置から前記第3半導体層側に離れた所定位置までの第1部分のキャリア濃度分布の勾配よりも、前記所定位置から前記第3半導体層側の第2部分のキャリア濃度分布の勾配が緩やかであり、
最も前記第3半導体層側に配置された前記第2半導体層のキャリア濃度分布の勾配は、前記第2部分のキャリア濃度分布の勾配よりも急峻であることを特徴とする半導体装置。 - 最も前記第3半導体層側に配置された前記第2半導体層の、前記第3半導体層との境界のキャリア濃度は、当該第2半導体層に隣接する他の前記第2半導体層との境界のキャリア濃度以下であることを特徴とする請求項10に記載の半導体装置。
- 前記第3半導体層のキャリア濃度のピーク値は、最も前記第3半導体層側に配置された前記第2半導体層の、前記第3半導体層との境界のキャリア濃度の5倍以上であることを特徴とする請求項10に記載の半導体装置。
- 前記おもて面素子構造は、
前記第1半導体層の一方の主面の表面層に設けられた第2導電型の第1半導体領域と、
前記第1半導体領域の内部に設けられた第1導電型の第2半導体領域と、
前記第1半導体領域の、前記第1半導体層と前記第2半導体領域との間の領域に接して設けられたゲート絶縁膜と、
前記ゲート絶縁膜を挟んで前記第1半導体領域の反対側に設けられたゲート電極と、からなり、
前記第1半導体領域および前記第2半導体領域に接する第1電極と、
前記第1半導体層の他方の主面に接する第2電極と、
をさらに備えることを特徴とする請求項10~12のいずれか一つに記載の半導体装置。
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