JP4571099B2 - 阻止ゾーンを半導体基板に製造する方法、および、阻止ゾーンを有する半導体部品 - Google Patents
阻止ゾーンを半導体基板に製造する方法、および、阻止ゾーンを有する半導体部品 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 121
- 239000000758 substrate Substances 0.000 title claims description 70
- 230000000903 blocking effect Effects 0.000 title claims description 60
- 238000000034 method Methods 0.000 title claims description 39
- 238000004519 manufacturing process Methods 0.000 title description 7
- 238000010438 heat treatment Methods 0.000 claims description 12
- 229910052739 hydrogen Inorganic materials 0.000 claims description 10
- 239000001257 hydrogen Substances 0.000 claims description 10
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 9
- 230000000295 complement effect Effects 0.000 claims 1
- 150000002431 hydrogen Chemical class 0.000 claims 1
- 238000000137 annealing Methods 0.000 description 15
- 238000001465 metallisation Methods 0.000 description 12
- 230000007547 defect Effects 0.000 description 11
- 238000010586 diagram Methods 0.000 description 7
- 230000005684 electric field Effects 0.000 description 7
- 230000035515 penetration Effects 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 230000003321 amplification Effects 0.000 description 3
- 239000002800 charge carrier Substances 0.000 description 3
- 238000003199 nucleic acid amplification method Methods 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- 230000002441 reversible effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 230000002045 lasting effect Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
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Description
12 第2半導体ゾーン、第2ストップゾーンセクション
13 基本ドーピングを有する半導体ゾーン、ベースゾーン
14 n型エミッタ
15 p型エミッタ
21,22 電極
31 p型エミッタ
32 p型ベース
33 n型エミッタ
34 ゲート電極
35 絶縁層、ゲート絶縁
36,37 電極
41 p型エミッタ
42 p型ベース
43 n型エミッタ
44 補助エミッタ
45 BOD構造の領域におけるp型ベースのセクション
46,47 電極
48 ゲート電極
100 半導体基板
101 第1面、正面
102 第2面、背面
111 半導体基板の第1領域
112 半導体基板の第2領域
113 半導体基板の第1領域の陽子
114 半導体基板の第2領域の欠陥
A アノード
A−A 軸
E エミッタ
G ゲート
K カソード
X0 垂直位
Nref 基本ドーピング濃度
ND 第1または第2の阻止ゾーンのドーピング濃度
Claims (16)
- 半導体基板(100)に、埋設された阻止ゾーンを形成する方法であって、
第1及び第2の面(101,102)を有し、第1伝導型の基本ドーピングがなされた半導体基板(100)を準備する工程と、
半導体基板(100)における第1及び第2の面(101,102)の一方に、陽子を照射し、陽子が、照射面(101)と離間して配された、半導体基板(100)の第1の領域(111)に導入されるようにする工程と、
半導体基板(100)を所定時間、所定温度に加熱する加熱処理を行い、第1の領域(111)、及び該第1の領域(111)と照射面(101)で隣接する第2の領域の両方で、水素によって誘発されたドナーが生成されるようにする工程と、を含み、
第2の領域(112)におけるドーピング濃度を、第1の領域(111)における最大ドーピング濃度の5%よりも大きく、かつ50%よりも小さくする、方法。 - 上記温度が200℃と550℃との間であり、上記時間が2時間と20時間との間である、請求項1に記載の方法。
- 上記時間が2.5時間と12時間との間である、請求項2に記載の方法。
- 上記温度が400℃と500℃との間である、請求項2または3に記載の方法。
- 第1の領域(111)と上記照射面との距離が1μmと250μmとの間になるように、上記陽子の照射エネルギーを選択する、請求項1〜4の何れか1項に記載の方法。
- 第1の領域(111)と上記照射面との距離が半導体基板(100)の厚さの5%と40%との間になるように、半導体基板(100)の厚さに応じて上記陽子の照射エネルギーを選択する、請求項1〜5の何れか1項に記載の方法。
- 第1の領域(111)と上記照射面との距離が半導体基板(100)の厚さの10%と15%との間になるように、上記陽子の照射エネルギーを選択する、請求項6に記載の方法。
- 第1及び第2の面(101,102)を有する半導体基板(100)を備え、
第1及び第2の面の一方の領域にエミッタゾーン(14,31,41)が配され、
エミッタゾーン(14,31,41)から、半導体基板に対し垂直方向に離間して、第1伝導型の阻止ゾーン(11)が配され、
阻止ゾーン(11)とエミッタゾーン(14,31,41)との間に第1伝導型の中間ゾーン(12)が配され、
阻止ゾーン(11)に隣接してベースゾーン(13)が配され、このベースゾーンが阻止ゾーン(11)及び中間ゾーン(12)よりも弱くドープされた、半導体部品であって、
中間ゾーン(12)におけるドーピング濃度が、阻止ゾーン(11)における最大ドーピング濃度の5%よりも大きく、かつ50%よりも小さくなっている、半導体部品。 - 中間ゾーン(12)におけるドーピング濃度が、ベースゾーン(13)におけるドーピング濃度の2倍以上になっている、請求項8に記載の半導体部品。
- 阻止ゾーン(11)から第1及び第2の面の一方の面までの距離が、半導体基板(100)の厚さの5%と40%との間になっている、請求項8または9に記載の半導体部品。
- 阻止ゾーン(11)から第1及び第2の面の一方の面までの距離が、半導体基板(100)の厚さの10%と15%との間になっている、請求項10に記載の半導体部品。
- 半導体基板(100)に対し垂直方向の中間ゾーン(12)の寸法が、半導体基板(100)の厚さの4%と35%との間になっている、請求項8〜11の何れか1項に記載の半導体部品。
- 半導体基板(100)に対し上記垂直方向の中間ゾーン(12)の寸法が、半導体基板(100)の厚さの8%と14%との間になっている、請求項12に記載の半導体部品。
- 阻止ゾーン(11)及び中間ゾーン(12)が、水素によって誘発されたドナーを有している、請求項8〜13の何れか1項に記載の半導体部品。
- エミッタゾーン(14)が、阻止ゾーン(11)及び中間ゾーン(12)と同一の伝導型になっている、請求項8〜14の何れか1項に記載の半導体部品。
- エミッタゾーン(31,41)は、阻止ゾーン(11)及び中間ゾーン(12)と相補して、ドープされている、請求項8〜14の何れか1項に記載の半導体部品。
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DE200510026408 DE102005026408B3 (de) | 2005-06-08 | 2005-06-08 | Verfahren zur Herstellung einer Stoppzone in einem Halbleiterkörper und Halbleiterbauelement mit einer Stoppzone |
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US8178411B2 (en) | 2012-05-15 |
US20060286753A1 (en) | 2006-12-21 |
DE102005026408B3 (de) | 2007-02-01 |
US7667297B2 (en) | 2010-02-23 |
JP2006344977A (ja) | 2006-12-21 |
US20100015818A1 (en) | 2010-01-21 |
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