JP2019121797A - ワイドバンドギャップ半導体デバイスおよびワイドバンドギャップ半導体デバイスの形成方法 - Google Patents
ワイドバンドギャップ半導体デバイスおよびワイドバンドギャップ半導体デバイスの形成方法 Download PDFInfo
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Abstract
Description
Claims (20)
- ワイドバンドギャップ半導体デバイス(100)において、
第1の導電型の第1のドーピング領域(102)と、
第2の導電型の第2のドーピング領域と、
を含んでおり、
前記第2のドーピング領域のドリフト部分(104)は、1e17cm-3未満の第1の平均正味ドーピング濃度を有しており、
前記第2のドーピング領域の高ドープ部分(108)は、5e18cm-3超の第2の平均正味ドーピング濃度を有しており、
前記第2のドーピング領域の補償部分(106)は、前記ドリフト部分と前記高ドープ部分との間に設けられており、
前記補償部分(106)は、1e16cm-3超かつ1e17cm-3未満の正味ドーピング濃度を有している前記補償部分(106)の第1の区域(206)から、5e18cm-3超の正味ドーピング濃度を有している前記補償部分(106)の第2の区域(208)まで延在しており、
前記第2の区域から前記第1の区域へと少なくとも100nmにわたり延在している前記補償部分(106)の少なくとも一部のその内部における前記正味ドーピング濃度の最大勾配は、5e22cm-4未満である、
ワイドバンドギャップ半導体デバイス(100)。 - 前記ドリフト部分(104)の垂直方向の寸法は、前記補償部分(106)の前記第1の区域と前記補償部分(106)の前記第2の区域との間の垂直方向の距離の8倍未満である、
請求項1記載のワイドバンドギャップ半導体デバイス(100)。 - 前記ドリフト部分(104)の垂直方向の寸法は、前記補償部分(106)の前記第1の区域と前記補償部分(106)の前記第2の区域との間の垂直方向の距離の3倍超である、
請求項1または2記載のワイドバンドギャップ半導体デバイス(100)。 - 前記補償部分(106)の垂直方向の寸法は、1μm超かつ5μm未満である、
請求項1から3までのいずれか1項記載のワイドバンドギャップ半導体デバイス(100)。 - 前記補償部分(106)の垂直方向のドーピングプロファイルは、ドーピングプラトー(304)を有しており、前記ドーピングプラトー(304)は、1e21cm-4未満の正味ドーピング濃度の平均勾配を有しており、前記ドーピングプラトー(304)は、50nm超の垂直方向の寸法を有している、
請求項1から4までのいずれか1項記載のワイドバンドギャップ半導体デバイス(100)。 - 前記垂直方向のドーピングプロファイルは、複数のドーピングプラトー(304、306)を有しており、前記複数のドーピングプラトーのうちの少なくとも1つの前記正味ドーピング濃度の平均勾配は、5e20cm-4未満である、
請求項5記載のワイドバンドギャップ半導体デバイス(100)。 - 前記複数のドーピングプラトーは、前記補償部分(106)の垂直方向の寸法の50%超を占める、かつ/または、
前記複数のドーピングプラトーの各プラトー間の移行領域は、前記補償部分(106)の前記垂直方向の寸法の50%未満を占める、
請求項6記載のワイドバンドギャップ半導体デバイス(100)。 - 前記ドーピングプロファイルは、1e18cm-3超の平均ドーピング濃度の最も高いドーピングプラトー(310)を有しており、前記最も高いドーピングプラトー(310)は、前記高ドープ部分(108)の最も近くに設けられている、前記複数のドーピングプラトー(304、306)のうちのドーピングプラトーである、
請求項6または7記載のワイドバンドギャップ半導体デバイス(100)。 - 前記補償部分(106)内の前記正味ドーピング濃度の勾配の、前記補償部分(106)内の前記正味ドーピング濃度の平均勾配からの変化は、30%未満である、
請求項1から8までのいずれか1項記載のワイドバンドギャップ半導体デバイス(100)。 - 前記補償部分(106)内の前記第1の導電型のドーパントの最大ドーピング濃度は、1e17cm-3超である、
請求項1から9までのいずれか1項記載のワイドバンドギャップ半導体デバイス(100)。 - 前記補償部分(106)内のすべてのドーピング原子の80%超は、窒素原子である、
請求項1から10までのいずれか1項記載のワイドバンドギャップ半導体デバイス(100)。 - 前記ワイドバンドギャップ半導体デバイスの電気的な素子構造の降伏電圧は、100V超である、
請求項1から11までのいずれか1項記載のワイドバンドギャップ半導体デバイス(100)。 - 前記第1のドーピング領域(102)は、ダイオードのアノード領域、ダイオードのカソード領域、電界効果トランジスタのボディ領域およびバイポーラトランジスタのベース領域のうちの1つである、
請求項1から12までのいずれか1項記載のワイドバンドギャップ半導体デバイス(100)。 - 前記第1のドーピング領域(102)は、前記第2のドーピング領域に隣接して設けられており、それによって前記第1のドーピング領域(102)と前記第2のドーピング領域との間にpn接合部が存在している、
請求項1から13までのいずれか1項記載のワイドバンドギャップ半導体デバイス(100)。 - ワイドバンドギャップ半導体基板は、炭化ケイ素基板である、
請求項1から14までのいずれか1項記載のワイドバンドギャップ半導体デバイス(100)。 - ワイドバンドギャップ半導体デバイス(100)を形成するための方法(700)において、前記方法(700)は、
第1の導電型の第1のドーピング領域(102)を形成するステップ(710)と、
第2の導電型の第2のドーピング領域を形成するステップ(720)と、
を備えており、
前記第2のドーピング領域のドリフト部分(104)は、1e17cm-3未満の第1の平均正味ドーピング濃度を有しており、
前記の第2のドーピング領域の高ドープ部分(108)は、5e18cm-3超の第2の平均正味ドーピング濃度を有しており、
前記第2のドーピング領域の補償部分(106)は、前記ドリフト部分と高ドープ部分との間に設けられており、
前記補償部分(106)は、1e16cm-3超かつ1e17cm-3未満の正味ドーピング濃度を有している第1の区域から、5e18cm-3超の正味ドーピング濃度を有している第2の区域まで延在しており、
前記第2の区域から前記第1の区域へと少なくとも100nmにわたり延在している前記補償部分(106)の少なくとも一部のその内部における前記正味ドーピング濃度の最大勾配は、5e22cm-4未満である、
方法(700)。 - 前記第2のドーピング領域を形成するステップは、ワイドバンドギャップ半導体ベース基板上での、エピタキシャルワイドバンドギャップ半導体層のエピタキシャル成長を含み、前記ドリフト部分および前記補償部分は、前記エピタキシャルワイドバンドギャップ半導体層内に設けられている、
請求項16記載の方法。 - 前記補償部分(106)における所望のドーピングプロファイルの少なくとも一部を形成するために、前記エピタキシャルワイドバンドギャップ半導体層の前記エピタキシャル成長後に、前記ドリフト部分(104)を介して前記第2の導電型のドーパントを注入するステップをさらに含む、
請求項17記載の方法。 - 前記補償部分(106)における所望のドーパントプロファイルの少なくとも一部を形成するために、前記ドリフト部分(104)を含んでいる前記エピタキシャルワイドバンドギャップ半導体層の一部を形成する前に、前記第2の導電型のドーパントを注入するステップをさらに含む、
請求項17または18記載の方法。 - 前記補償部分(106)における所望のドーピングプロファイルの少なくとも一部を形成するために、前記補償部分(106)に前記第1の導電型のドーパントを注入するステップをさらに含む、
請求項16から19までのいずれか1項記載の方法。
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