WO2015118713A1 - 半導体装置及び半導体装置の製造方法 - Google Patents

半導体装置及び半導体装置の製造方法 Download PDF

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WO2015118713A1
WO2015118713A1 PCT/JP2014/073641 JP2014073641W WO2015118713A1 WO 2015118713 A1 WO2015118713 A1 WO 2015118713A1 JP 2014073641 W JP2014073641 W JP 2014073641W WO 2015118713 A1 WO2015118713 A1 WO 2015118713A1
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region
depth
concentration
semiconductor substrate
type impurity
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PCT/JP2014/073641
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English (en)
French (fr)
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亀山　悟
真也 岩崎
佑樹 堀内
大木　周平
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トヨタ自動車株式会社
亀山　悟
真也 岩崎
佑樹 堀内
大木　周平
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Application filed by トヨタ自動車株式会社, 亀山　悟, 真也 岩崎, 佑樹 堀内, 大木　周平 filed Critical トヨタ自動車株式会社
Priority to KR1020167023028A priority Critical patent/KR101897380B1/ko
Priority to US15/114,201 priority patent/US9633997B2/en
Priority to CN201480075198.8A priority patent/CN105981143B/zh
Priority to EP14882050.9A priority patent/EP3107117B1/en
Publication of WO2015118713A1 publication Critical patent/WO2015118713A1/ja

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Definitions

  • the technology disclosed in this specification relates to a semiconductor device.
  • Patent Document 1 discloses an RC-IGBT in which a diode and an IGBT are formed on one semiconductor substrate.
  • An n-type cathode layer is formed in a range exposed on the lower surface of the diode.
  • An n-type buffer layer is formed on the upper side of the cathode layer.
  • An n-type drift layer is formed on the upper side of the buffer layer.
  • the n-type impurity concentration of the drift layer is lower than that of the buffer layer and the cathode layer.
  • the buffer layer has an n-type impurity concentration lower than that of the cathode layer.
  • Patent Document 1 a structure in which a high-concentration impurity region, a medium-concentration impurity region, and a low-concentration impurity region are arranged in this order from the surface side of the substrate is used in various semiconductor devices such as diodes and MOSFETs.
  • the present specification provides a technique capable of further stabilizing characteristics in such a semiconductor device.
  • the inventors of the present application are researching a technique for further increasing the impurity concentration of the high-concentration impurity region described above.
  • this technique after a high concentration of impurities is implanted in the vicinity of the surface of the semiconductor substrate, the region in the vicinity of the surface is melted and then solidified again. Since the impurities diffuse throughout the melted region, the region solidified again becomes a region containing impurities at a high concentration.
  • crystal defects formed by high-concentration impurity implantation can be efficiently eliminated. Therefore, it is possible to form a high concentration impurity region having a high impurity concentration and a low crystal defect density.
  • impurities adhering to the surface of the semiconductor substrate before melting diffuse into the melted region.
  • p-type impurities attached to the surface of the semiconductor substrate may diffuse into the melted region.
  • the p-type impurity diffuses into the region where the n-type impurity concentration is low, and the region is p-type. It may become.
  • the n-type impurity concentration at the boundary between the high concentration impurity region and the medium concentration impurity region is high.
  • the n-type impurity concentration at the boundary is high, the high concentration impurity region and the medium concentration impurity region are not sufficiently separated. Then, under the influence of both the high concentration impurity region and the medium concentration impurity region, the efficiency of electron injection into the high concentration impurity region changes. This makes it difficult to control the characteristics of the semiconductor device.
  • This semiconductor device has a first conductivity type region exposed on the surface of the semiconductor substrate.
  • a maximum value N1, a minimum value N2, and a maximum value N3 are formed.
  • the depth having the maximum value N1 is located closer to the surface than the depth having the minimum value N2.
  • the depth having the maximum value N3 is located on the opposite side of the surface from the depth having the minimum value N2.
  • a region having a first conductivity type impurity concentration N4 is present in the first conductivity type region located on the opposite side of the surface from the depth having the maximum value N3.
  • the relationship of N1> N3> N2> N4 is satisfied, and the relationship of N3 / 10> N2 is satisfied.
  • the distance a from the surface to the depth having the maximum value N1 is larger than twice the distance b from the depth having the maximum value N1 to the depth having the minimum value N2.
  • said 1st conductivity type impurity means either an n-type or a p-type.
  • concentration of the region having the concentration N4 does not have to be constant, and the concentration N4 of the region may change depending on the position within a range where the relationship of N2> N4 is satisfied.
  • the distance a from the surface of the semiconductor substrate to the depth having the maximum value N1 is larger than twice the distance b from the depth having the maximum value N1 to the depth having the minimum value N2.
  • Such an impurity distribution is called a box profile, and is a characteristic distribution obtained by a method of activating impurities by melting the semiconductor substrate described above.
  • the region having the maximum value N1 corresponds to the high concentration region
  • the region having the maximum value N3 corresponds to the medium concentration region
  • the region having the concentration N4 corresponds to the low concentration region.
  • the depth having the minimum value N2 corresponds to the boundary between the high concentration region and the medium concentration region.
  • the minimum value N2 is higher than the concentration N4.
  • the second conductivity type impurities of a conductivity type different from the first conductivity type (hereinafter referred to as the second conductivity type) are diffused in the depth of the minimum value N2 in the manufacturing process of the semiconductor device (that is, the melting process of the semiconductor substrate).
  • this depth region is unlikely to be the second conductivity type. That is, in this semiconductor device, it is difficult to form the second conductivity type region at the boundary between the high concentration region and the medium concentration region.
  • the relationship of N3 / 10> N2 is satisfied.
  • the efficiency of electron injection into the high-concentration impurity region is determined by the impurity concentration of the high-concentration impurity region with little influence from the medium-concentration impurity region.
  • this semiconductor device it is possible to suppress the formation of the second conductivity type region at the boundary and to suppress the influence of the medium concentration impurity region on the electron injection efficiency of the high concentration impurity region. can do. Therefore, the characteristics of this semiconductor device are stable during mass production.
  • the present specification also provides a method of manufacturing a semiconductor device.
  • the heat treatment step is performed after the first injection step
  • the melting and solidifying step is performed after the second injection step
  • the first injection step, the heat treatment step, the second injection step, and The steps of melting and solidifying may be performed in any order.
  • the first conductivity type impurity is implanted at a relatively deep position in the first implantation step, and the first conductivity type impurity implanted in the first implantation step is activated in the heat treatment step. Thereby, an intermediate concentration region is formed.
  • the first conductivity type impurity is implanted at a relatively shallow position in the second implantation step, and the first conductivity type impurity implanted in the second implantation step is activated in the melting and solidifying step. Thereby, a high concentration region is formed. A region where the first conductivity type impurity is not diffused is a low concentration region. According to this manufacturing method, a semiconductor device having a high concentration region, a medium concentration region, and a low concentration region can be manufactured.
  • FIG. 1 is a longitudinal sectional view of a semiconductor device 10 of Example 1.
  • FIG. 2 is a graph showing the n-type impurity concentration along the line AA in FIG.
  • FIG. 6 is an explanatory diagram of a manufacturing process of the semiconductor device 10.
  • FIG. 6 is an explanatory diagram of a manufacturing process of the semiconductor device 10.
  • FIG. 6 is an explanatory diagram of a manufacturing process of the semiconductor device 10.
  • FIG. 6 is an explanatory diagram of a manufacturing process of the semiconductor device 10.
  • FIG. 6 is an explanatory diagram of a manufacturing process of the semiconductor device 10.
  • FIG. 3 is a graph corresponding to FIG. 2 of the semiconductor device of Example 2.
  • FIG. 3 is a graph corresponding to FIG. 2 of the semiconductor device of Comparative Example 1;
  • the graph corresponding to FIG. 2 of the semiconductor device of the comparative example 3. 1 is a longitudinal sectional view of an RC-IGBT to which
  • a depth having a concentration N5 of the first conductivity type impurity of 1/10 of the maximum value N1 may exist on the surface side of the depth having the maximum value N1. In this case, the distance c from the depth having the concentration N5 to the depth having the maximum value N1 may be greater than twice the distance b.
  • a diode and an IGBT may be formed on a semiconductor substrate, and the first conductivity type region may be a cathode region of the diode.
  • the depth having the maximum value N1 may exist within the range of 0.3 to 0.7 ⁇ m from the surface.
  • the depth having the maximum value N3 may exist within the range of 0.5 to 3.0 ⁇ m from the surface.
  • Example 1 A semiconductor device 10 of Example 1 shown in FIG. 1 includes a semiconductor substrate 12, an anode electrode 20 formed on the upper surface 12a of the semiconductor substrate 12, and a cathode electrode 22 formed on the lower surface 12b of the semiconductor substrate 12. Yes.
  • a p-type anode region 30 and an n-type cathode region 38 are formed in the semiconductor substrate 12.
  • the anode region 30 is formed in a range exposed on the upper surface 12 a of the semiconductor substrate 12 and is connected to the anode electrode 20.
  • the cathode region 38 is formed in a range exposed on the lower surface 12 b of the semiconductor substrate 12 and is connected to the cathode electrode 22. That is, a diode is formed in the semiconductor substrate 12.
  • FIG. 2 shows the concentration distribution of the n-type impurity along the line AA in FIG. 2 indicates the depth from the lower surface 12b of the semiconductor substrate 12, and the vertical axis designates the n-type impurity concentration by logarithm.
  • the n-type impurity concentration gradually increases from the lower surface 12b of the semiconductor substrate 12 toward the deep side, and reaches a maximum value N1.
  • the n-type impurity concentration rapidly decreases from the depth D1 of the maximum value N1 toward the deep side, and becomes a minimum value N2.
  • the n-type impurity concentration increases from the depth D2 of the minimum value N2 toward the deep side, and reaches a maximum value N3.
  • the n-type impurity concentration decreases from the depth D3 of the maximum value N3 toward the deep side, and becomes a concentration N4 at the depth D4. In a region deeper than the depth D4, the n-type impurity concentration is substantially constant at the concentration N4.
  • the concentrations N1 to N4 satisfy the relationship of N1> N3> N2> N4.
  • the minimum value N2 is a value smaller than one tenth of the maximum value N3. That is, N3 / 10> N2 is satisfied.
  • the n-type impurity concentration Ns on the lower surface 12b of the semiconductor substrate 12 is a value larger than one tenth of the maximum value N1.
  • the cathode region 38 located on the side shallower than the depth D2 (the lower surface 12b side) is referred to as a contact region 36, and the cathode region 38 between the depth D2 and the depth D4 is referred to as a buffer region 34.
  • the cathode region 38 on the side deeper than D4 (upper surface 12a side) is referred to as a drift region 32.
  • the n-type impurity concentration is gradually changed as compared with the above-described range of the distance b (the range between the depth D1 and the depth D2).
  • n-type impurities are distributed in a Gaussian distribution.
  • the buffer region 34 is a region formed by injecting an n-type impurity at a depth D3 and then diffusing and activating the n-type impurity by heat treatment.
  • the diode When the diode is turned on (that is, when a forward voltage is applied to the diode), holes flow from the anode electrode 20 toward the cathode electrode 22 and electrons flow from the cathode electrode 22 toward the anode electrode 20.
  • the contact region 36 has a high n-type impurity concentration, the contact resistance between the contact region 36 and the cathode electrode 22 is extremely low. For this reason, electrons are injected from the cathode electrode 22 into the contact region 36 with high injection efficiency. Further, since the crystal defect density of the contact region 36 is low, it is difficult for loss to occur in the contact region 36 when electrons and holes pass through the contact region 36. For this reason, the diode can operate with low loss.
  • a depletion layer extends from the pn junction at the boundary between the anode region 30 and the drift region 32 toward the cathode electrode 22. Since the buffer region 34 has a relatively high n-type impurity concentration, the depletion layer stops in the buffer region 34. As a result, the depletion layer is prevented from reaching the contact region 36, and the breakdown voltage of the diode is ensured.
  • the buffer region 34 is formed at a relatively deep position. More specifically, the depth D3 is formed to be 0.5 to 3.0 ⁇ m. For this reason, even if a scratch is generated on the lower surface 12 b, the scratch is difficult to reach the buffer region 34. This makes it difficult for the breakdown voltage of the diode to be reduced due to scratches.
  • an n-type semiconductor substrate 12 shown in FIG. 3 is prepared.
  • the entire semiconductor substrate 12 has an n-type impurity concentration equal to the above-described concentration N4.
  • n-type impurities are implanted into the back surface of the semiconductor substrate 12.
  • the implantation energy is adjusted so that the average stop position of the n-type impurity is located at a depth D3 from the lower surface 12b of the semiconductor substrate 12.
  • the semiconductor substrate 12 is annealed by using a furnace or a laser annealing apparatus.
  • annealing is performed so that the position of the depth D3 into which the n-type impurity is implanted in the buffer implantation process is sufficiently heated.
  • the annealing is performed at a temperature at which the surface of the semiconductor substrate 12 does not melt.
  • the n-type impurity implanted in the buffer implantation process is diffused and activated.
  • a buffer region 34 is formed in the semiconductor substrate 12 as shown in FIG. That is, by performing the buffer annealing step, a buffer region 34 in which n-type impurities are distributed in a Gaussian distribution as shown in FIG.
  • the maximum value N3 of the n-type impurity concentration is formed at the depth D3 after the buffer annealing step, as shown in FIG.
  • a region having a lower n-type impurity concentration on the upper surface 12 a side than the buffer region 34 is a drift region 32.
  • n-type impurities are implanted into the lower surface 12 b of the semiconductor substrate 12.
  • the implantation energy is adjusted so that the n-type impurity average stop position is shallower than the buffer region 34.
  • n-type impurities are implanted at a higher concentration than in the buffer implantation process. For this reason, high-density crystal defects are formed in the region that has received the n-type impurity implantation in the contact implantation step (that is, the region in the vicinity of the lower surface 12b).
  • the semiconductor substrate 12 is annealed by laser annealing.
  • the vicinity of the lower surface 12b is locally annealed by irradiating the lower surface 12b of the semiconductor substrate 12 with a laser.
  • the laser annealing is performed in a short time so that a large amount of heat is not transferred to the buffer region 34.
  • the laser annealing is performed so that the temperature is raised to a temperature at which the semiconductor layer near the lower surface 12b is melted.
  • laser annealing is performed so that the region on the side deeper than the depth D2 (the upper surface 12a side) does not melt.
  • the region 36 melted by laser annealing is then solidified and recrystallized.
  • the n-type impurity implanted in the contact implantation process diffuses almost uniformly into the melted region 36. Therefore, when the region 36 is recrystallized, the region 36 becomes a contact region 36 containing an n-type impurity at a high concentration. That is, as shown in FIG. 7, the contact region 36 is formed in a range exposed on the lower surface 12 b of the semiconductor substrate 12.
  • the n-type impurity diffuses substantially uniformly in the region 36.
  • the n-type impurity hardly diffuses into the region that has not melted.
  • the n-type impurity concentration does not change so much in the region between the lower surface 12b and the depth D1, and the n-type impurity concentration rapidly decreases from the depth D1 to the depth D2. Distribution is obtained. Accordingly, the distances a and b in the figure satisfy the relationship of a> 2b.
  • the contact region 36 having a box distribution is formed by performing the contact annealing step.
  • the contact region 36 Since the region to be melted is limited to a very shallow region, the thickness of the contact region 36 is reduced (depth D1 is 0.3 to 0.7 ⁇ m), and the peak concentration N1 of the contact region 36 is increased. In the process of melting and then solidifying the region 36, most of the crystal defects existing in the region 36 at a high density disappear. For this reason, the contact region 36 after recrystallization has few crystal defects. That is, by performing the contact annealing step, the contact region 36 having a high n-type impurity concentration (more specifically, a peak n-type impurity concentration N1) and a low crystal defect density is formed. The contact annealing process is performed so that an n-type impurity concentration N2 (see FIG. 2) satisfying the relationship of N3 / 10> N2> N4 is obtained after the contact annealing process.
  • the anode region 30 is formed by implanting and activating p-type impurities into the upper surface 12a of the semiconductor substrate 12.
  • the anode electrode 20 is formed on the upper surface 12 a of the semiconductor substrate 12.
  • the cathode electrode 22 is formed on the lower surface 12 b of the semiconductor substrate 12.
  • the contact region 36 having a high n-type impurity concentration and a low crystal defect density can be formed. Therefore, a low-loss diode can be formed.
  • the n-type impurity in the buffer region 34 is activated by an annealing process (buffer annealing process) different from the contact annealing process for melting the surface. For this reason, the buffer region 34 can be formed at a deep position. Therefore, it is possible to suppress a decrease in breakdown voltage due to scratches on the lower surface 12b.
  • the contact annealing step is performed so that the relationship of N2> N4 is satisfied.
  • the region 36 is melted in the contact annealing step, p-type impurities diffuse into the 36. Therefore, if the n-type impurity concentration is extremely low at the depth D2, the p-type impurity concentration may exceed the n-type impurity concentration near the depth D2, and a p-type region may be formed near the depth D2.
  • the contact annealing is performed so that the relationship of N2> N4 is satisfied (that is, the n-type impurity concentration N2 at the depth D2 is higher than the n-type impurity concentration N4 of the raw semiconductor substrate 12).
  • a process is performed. For this reason, even if a very small amount of p-type impurity diffuses in the vicinity of the depth D2, the region in the vicinity of the depth D2 is difficult to become p-type. Therefore, the p-type region is prevented from being formed at the depth D2. For this reason, when the semiconductor device 10 is mass-produced by the method of the embodiment, the characteristics (particularly, VF) of the diode are stabilized.
  • the diode is formed so that the relationship of N3 / 10> N2 is satisfied. This stabilizes the characteristics of the diode. That is, if the n-type impurity concentration N2 at the depth D1 is too high, the contact region 36 and the buffer region 34 function as a single region, and the n-type impurity concentration of the contact region 36 and the n-type impurity concentration of the buffer region 34 Impurity concentration affects each other's characteristics.
  • the efficiency of electron injection from the cathode electrode 22 to the contact region 36 varies depending not only on the n-type impurity concentration of the contact region 36 but also on the n-type impurity concentration of the buffer region 34. It becomes like this. For this reason, it is difficult to accurately control the electron injection efficiency, and a large variation occurs in the electron injection efficiency during mass production of semiconductor devices.
  • the method of the embodiment since the relationship of N3 / 10> N2 is satisfied, the electron injection efficiency is hardly affected by the buffer region 34. Therefore, according to the method of the embodiment, variations in electron injection efficiency into the contact region 36 of each semiconductor device hardly occur during mass production.
  • the semiconductor device of Example 2 is manufactured by the same method as that of Example 1.
  • the n-type impurity concentration Ns on the lower surface 12b may be lowered as in the second embodiment. Even in this case, the relationship of c> 2b is satisfied in a typical box profile.
  • the box profile can be defined by the distance c and the distance b (when the n-type impurity concentration Ns on the lower surface 12b satisfies Ns> N1 / 10 as in the first embodiment). (As long as the distance a between the lower surface 12b and the depth D1 satisfies the relationship of a> 2b as in the first embodiment).
  • the semiconductor device according to the second embodiment and the manufacturing method thereof can obtain substantially the same advantages as the semiconductor device according to the first embodiment.
  • the semiconductor device of the comparative example also has a contact region, a buffer region, a drift region, an anode region, a cathode electrode, and an anode electrode as in the first and second embodiments.
  • the impurity concentrations and dimensions of these regions are different, the basic functions of these regions are the same as those of the first and second embodiments. Therefore, below, the part which has commonality with Example 1, 2 is demonstrated using the same number as Example 1,2.
  • all of the following comparative examples were carried out in experiments by the inventors of the present application and are not publicly known.
  • FIG. 9 shows n-type impurity concentration distributions in the contact region 36, the buffer region 34, and the drift region 32 of the semiconductor device of Comparative Example 1.
  • an n-type impurity is implanted to the depth D3 of the semiconductor substrate.
  • an n-type impurity is implanted near the lower surface 12b of the semiconductor substrate 12 (for example, depth D1).
  • the lower surface 12b of the semiconductor substrate 12 is melted by laser annealing.
  • the region up to the depth D2 shown in FIG. 9 is melted.
  • a contact region 36 is formed.
  • the region near the depth D3 is heated by laser annealing although it does not melt.
  • the n-type impurity is activated in the vicinity of the depth D3, and the buffer region 34 is formed in the vicinity of the depth D3.
  • a semiconductor device in which n-type impurities are distributed as shown in FIG. 9 is obtained.
  • the buffer region 34 is formed by the heat of laser annealing, it is necessary to form the buffer region 34 at a position close to the lower surface 12b (that is, the depth D3 needs to be shallow). For this reason, the buffer region 34 cannot be formed at a deep position. Therefore, the breakdown voltage of the semiconductor device of Comparative Example 1 tends to decrease when the lower surface 12b is scratched.
  • the contact region 36 and the buffer region 34 are not sufficiently separated. For this reason, when the semiconductor device is mass-produced by this method, variations in the efficiency of electron injection into the contact region 36 tend to occur.
  • FIG. 10 shows n-type impurity concentration distributions in the contact region 36, the buffer region 34, and the drift region 32 of the semiconductor device of Comparative Example 2.
  • the manufacturing method of the semiconductor device of Comparative Example 2 is the same as that of Comparative Example 1.
  • the n-type impurity implantation depth D3 for the buffer region 34 is deeper than that of the first comparative example.
  • the semiconductor substrate 12 is melted to a position deeper than the comparative example 1 in order to activate the n-type impurity implanted at a depth D3 deeper than the comparative example 1. For this reason, as shown in FIG.
  • the buffer region 34 is formed at a deeper position than Comparative Example 1, while the contact region 36 becomes wider, and the n-type of the contact region 36 is formed. Impurity concentration is low. For this reason, the semiconductor device of Comparative Example 2 has a problem that the contact resistance of the contact region 36 to the cathode electrode 22 is high. Also in the semiconductor device of Comparative Example 2, the minimum value N2 is high, and the contact region 36 and the buffer region 34 are not sufficiently separated.
  • FIG. 11 shows n-type impurity concentration distributions in the contact region 36, the buffer region 34, and the drift region 32 of the semiconductor device of Comparative Example 3.
  • an n-type impurity is implanted to a depth D3.
  • the depth D3 of Comparative Example 3 is equivalent to the depth D3 of Example 1.
  • the lower surface 12b of the semiconductor substrate 12 is melted by laser annealing.
  • the depth D1 is heated by melting up to a depth close to the depth D1 (depth Da in FIG. 11).
  • the impurity implanted to the depth D1 is diffused to form the buffer region 34.
  • an n-type impurity is implanted to a depth near the lower surface 12 b of the semiconductor substrate 12.
  • the lower surface 12b of the semiconductor substrate 12 is melted by laser annealing. That is, only a region shallower than the depth Da is melted, and n-type impurities are diffused into the melted region. Thereby, the contact region 36 is formed.
  • a contact region 36 having a high n-type impurity concentration and a buffer region 34 formed at a deep position can be realized.
  • the first laser annealing laser annealing that melts to the depth Da
  • the first laser annealing laser annealing that melts to the depth Da
  • the p-type impurity may diffuse into the region from the lower surface 12b to the depth Da.
  • the p-type impurity concentration may exceed the n-type impurity concentration at the depth D2 having the minimum value N2 of the n-type impurity. That is, a p-type region may be formed between the contact region 36 and the buffer region 34.
  • a p-type region is formed between the contact region 36 and the buffer region 34, and the characteristics of the diode are not stable during mass production.
  • these steps are performed in the order of the buffer injection step, the buffer annealing step, the contact injection step, and the contact annealing step.
  • the execution order of these steps may be changed. The order may be changed as long as the buffer annealing process is performed after the buffer process and the contact annealing process is performed after the contact implantation process.
  • the semiconductor device in which only the diode is formed has been described.
  • the above-described technique is applied to the diode portion of the RC-IGBT in which the diode and the IGBT are formed on a single semiconductor substrate.
  • An example of the RC-IGBT is the configuration shown in FIG. In FIG. 12, reference numerals 20 to 22 and 30 to 36 correspond to the first embodiment.
  • Reference number 51 is an emitter region
  • reference number 52 is a body region
  • reference number 53 is a collector region
  • reference number 55 is a gate insulating film
  • reference number 56 is a gate electrode.
  • These constituent elements 51 to 56 and regions 32 and 34 form an IGBT.
  • the anode electrode 20 also serves as an IGBT emitter electrode
  • the cathode electrode 22 also serves as an IGBT collector electrode.
  • the diode has been described.
  • the above-described technique may be applied to the contact region between the source region and the source electrode of the FET (eg, MOSFET) and the contact region between the drain region and the drain electrode.

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Abstract

　半導体基板１２の表面に露出している第１導電型領域３８における第１導電型不純物の濃度分布を半導体基板の厚み方向に沿って見たときに、表面側から極大値Ｎ１、極小値Ｎ２、極大値Ｎ３、濃度Ｎ４が形成されており、Ｎ１＞Ｎ３＞Ｎ２＞Ｎ４の関係が満たされており、Ｎ３／１０＞Ｎ２の関係が満たされており、表面から極大値Ｎ１を有する深さＤ１までの距離ａが、極大値Ｎ１を有する深さＤ１から極小値Ｎ２を有する深さまＤ２での距離ｂの２倍より大きい半導体装置。

Description

半導体装置及び半導体装置の製造方法
（関連出願の相互参照）
　本出願は、２０１４年２月１０日に出願された日本特許出願特願２０１４－０２３８７３の関連出願であり、この日本特許出願に基づく優先権を主張するものであり、この日本特許出願に記載された全ての内容を、本明細書を構成するものとして援用する。
　本明細書が開示する技術は、半導体装置に関する。
　日本国特許公開第２０１１－８２２２０号公報（以下、特許文献１という）には、１つの半導体基板にダイオードとＩＧＢＴが形成されたＲＣ－ＩＧＢＴが開示されている。ダイオードの下面に露出する範囲には、ｎ型のカソード層が形成されている。カソード層の上側には、ｎ型のバッファ層が形成されている。バッファ層の上側には、ｎ型のドリフト層が形成されている。ドリフト層のｎ型不純物濃度は、バッファ層及びカソード層よりも低い。バッファ層のｎ型不純物濃度は、カソード層よりも低い。
　特許文献１のように、基板の表面側から、高濃度不純物領域、中濃度不純物領域及び低濃度不純物領域がこの順に配置されている構造は、ダイオードやＭＯＳＦＥＴ等の種々の半導体装置で用いられる。本明細書では、このような半導体装置において、特性をより安定させることが可能な技術を提供する。
　本願発明者らは、上述した高濃度不純物領域の不純物濃度をより高める技術を研究している。この技術では、半導体基板の表面近傍に高濃度に不純物を注入した後に、その表面近傍の領域を溶融させ、その後、再度固化させる。不純物は溶融した領域全体に拡散するため、再度固化した領域は高濃度に不純物を含有する領域となる。また、このように半導体基板を溶融させると、高濃度の不純物注入によって形成された結晶欠陥を効率的に消滅させることができる。したがって、不純物濃度が高く、かつ、結晶欠陥密度が低い高濃度不純物領域を形成することが可能である。しかしながら、このように半導体基板の表面を溶融させる技術においては、溶融前に半導体基板の表面に付着していた不純物が、溶融した領域内に拡散することが分かってきた。例えば、ｎ型の高濃度不純物領域を形成する際に、半導体基板の表面に付着しているｐ型不純物が、溶融した領域内に拡散する場合がある。このような場合において、高濃度不純物領域と中濃度不純物領域の境界でｎ型不純物濃度が低くなっていると、そのｎ型不純物濃度が低い領域にｐ型不純物が拡散し、その領域がｐ型化してしまう場合がある。このような問題を解消するためには、高濃度不純物領域と中濃度不純物領域の境界のｎ型不純物濃度が高いことが求められる。しかしながら、当該境界のｎ型不純物濃度が高いと、高濃度不純物領域と中濃度不純物領域が十分に分離されない。すると、高濃度不純物領域と中濃度不純物領域の両方の影響を受けて、高濃度不純物領域への電子の注入効率が変化する。このため、半導体装置の特性の制御が困難となる。
　したがって、本明細書では、以下の半導体装置を提供する。この半導体装置は、半導体基板の表面に露出している第１導電型領域を有している。前記第１導電型領域における第１導電型不純物の濃度分布を前記半導体基板の厚み方向に沿って見たときに、極大値Ｎ１、極小値Ｎ２、極大値Ｎ３が形成されている。前記極大値Ｎ１を有する深さが、前記極小値Ｎ２を有する深さよりも前記表面側に位置している。前記極大値Ｎ３を有する深さが、前記極小値Ｎ２を有する前記深さよりも前記表面の反対側に位置している。前記極大値Ｎ３を有する前記深さよりも前記表面の反対側に位置する前記第１導電型領域内に、第１導電型不純物の濃度Ｎ４を有する領域が存在している。Ｎ１＞Ｎ３＞Ｎ２＞Ｎ４の関係が満たされており、Ｎ３／１０＞Ｎ２の関係が満たされている。前記表面から前記極大値Ｎ１を有する深さまでの距離ａが、前記極大値Ｎ１を有する深さから前記極小値Ｎ２を有する深さまでの距離ｂの２倍より大きい。
　なお、上記の第１導電型不純物は、ｎ型またはｐ型のいずれか一方を意味する。また、濃度Ｎ４を有する領域の濃度は一定である必要はなく、Ｎ２＞Ｎ４の関係が満たされる範囲内で当該領域の濃度Ｎ４が位置によって変化していてもよい。
　この半導体装置では、半導体基板の表面から極大値Ｎ１を有する深さまでの距離ａが、極大値Ｎ１を有する深さから極小値Ｎ２を有する深さまでの距離ｂの２倍より大きい。このような不純物分布は、ボックスプロファイルと呼ばれ、上述した半導体基板を溶融させることで不純物を活性化させる方法によって得られる特徴的な分布である。この半導体装置では、極大値Ｎ１を有する領域が高濃度領域に相当し、極大値Ｎ３を有する領域が中濃度領域に相当し、濃度Ｎ４を有する領域が低濃度領域に相当する。また、極小値Ｎ２を有する深さは、高濃度領域と中濃度領域の境界に相当する。この半導体装置では、極小値Ｎ２が濃度Ｎ４より高い。このため、この半導体装置の製造工程（すなわち、半導体基板の溶融工程）において極小値Ｎ２の深さに第１導電型とは異なる導電型（以下、第２導電型という）の不純物が拡散した場合でも、この深さの領域が第２導電型になり難い。すなわち、この半導体装置では、高濃度領域と中濃度領域の境界に第２導電型領域が形成され難い。また、この半導体装置では、Ｎ３／１０＞Ｎ２の関係が満たされている。極小値Ｎ２がこの程度に低い濃度であると、高濃度領域と中濃度領域とが十分に分離され、これらの領域が互いに影響を及ぼすことを抑制することができる。このため、高濃度不純物領域への電子の注入効率が、中濃度不純物領域の影響をほとんど受けることなく高濃度不純物領域の不純物濃度によって定まるようになる。このように、この半導体装置によれば、前記境界に第２導電型領域が形成されることを抑制することができるとともに、中濃度不純物領域による高濃度不純物領域の電子の注入効率に対する影響を抑制することができる。したがって、この半導体装置は、量産時に特性が安定する。
　また、本明細書は、半導体装置を製造する方法を提供する。この方法は、第１導電型の半導体基板の表面に、第１導電型不純物を注入する第１注入工程と、前記第１注入工程後に、前記半導体基板が溶融しない温度で前記半導体基板を熱処理する工程と、前記半導体基板の前記表面に、前記第１注入工程よりも低いエネルギーで前記第１注入工程よりも高濃度に第１導電型不純物を注入する第２注入工程と、第２注入工程後に、前記第１注入工程における第１導電型不純物の平均停止位置よりも前記表面側の領域を溶融させ、その後、固化させる工程を有する。
　なお、上記熱処理する工程が第１注入工程の後に行われ、上記溶融・固化させる工程が第２注入工程よりも後に行われる限りは、第１注入工程、上記熱処理する工程、第２注入工程及び上記溶融・固化させる工程は、どのような順序で行われてもよい。
　この方法では、第１注入工程で比較的深い位置に第１導電型不純物が注入され、上記熱処理する工程において第１注入工程で注入された第１導電型不純物が活性化する。これによって、中濃度領域が形成される。また、この方法では、第２注入工程で比較的浅い位置に第１導電型不純物が注入され、上記溶融・固化する工程において第２注入工程で注入された第１導電型不純物が活性化する。これによって、高濃度領域が形成される。第１導電型不純物が拡散しなかった領域は、低濃度領域となる。この製造方法によれば、高濃度領域、中濃度領域及び低濃度領域を有する半導体装置を製造することができる。
実施例１の半導体装置１０の縦断面図。 図１のＡ－Ａ線におけるｎ型不純物濃度を示すグラフ。 半導体装置１０の製造工程の説明図。 半導体装置１０の製造工程の説明図。 半導体装置１０の製造工程の説明図。 半導体装置１０の製造工程の説明図。 半導体装置１０の製造工程の説明図。 実施例２の半導体装置の図２に対応するグラフ。 比較例１の半導体装置の図２に対応するグラフ。 比較例２の半導体装置の図２に対応するグラフ。 比較例３の半導体装置の図２に対応するグラフ。 本明細書に開示の技術を適用したＲＣ－ＩＧＢＴの縦断面図。
　以下に説明する実施例の特徴について、以下に説明する。なお、以下の特徴は、何れも独立して有用なものである。
（特徴１）極大値Ｎ１を有する深さよりも表面側に、極大値Ｎ１の１／１０の第１導電型不純物の濃度Ｎ５を有する深さが存在していてもよい。この場合、濃度Ｎ５を有する深さから極大値Ｎ１を有する深さまでの距離ｃが、距離ｂの２倍より大きくてもよい。
（特徴２）半導体基板にダイオードとＩＧＢＴが形成されており、第１導電型領域がダイオードのカソード領域であってもよい。
（特徴３）極大値Ｎ１を有する深さが表面から０．３～０．７μｍの範囲内に存在してもよい。
（特徴４）極大値Ｎ３を有する深さが表面から０．５～３．０μｍの範囲内に存在してもよい。
（実施例１）
　図１に示す実施例１の半導体装置１０は、半導体基板１２と、半導体基板１２の上面１２ａに形成されたアノード電極２０と、半導体基板１２の下面１２ｂに形成されたカソード電極２２を有している。
　半導体基板１２内には、ｐ型のアノード領域３０とｎ型のカソード領域３８が形成されている。アノード領域３０は、半導体基板１２の上面１２ａに露出する範囲に形成されており、アノード電極２０に対して接続されている。カソード領域３８は、半導体基板１２の下面１２ｂに露出する範囲に形成されており、カソード電極２２に対して接続されている。すなわち、半導体基板１２内には、ダイオードが形成されている。
　図２は、図１のＡ－Ａ線におけるｎ型不純物の濃度分布を示している。なお、図２の横軸は半導体基板１２の下面１２ｂからの深さを示しており、縦軸はｎ型不純物濃度を対数により指名している。ｎ型不純物濃度は、半導体基板１２の下面１２ｂから深い側に向かうにしたがって緩やかに上昇し、極大値Ｎ１となる。ｎ型不純物濃度は、極大値Ｎ１の深さＤ１から深い側に向かうにしたがって急激に減少し、極小値Ｎ２となる。ｎ型不純物濃度は、極小値Ｎ２の深さＤ２から深い側に向かうにしたがって上昇し、極大値Ｎ３となる。ｎ型不純物濃度は、極大値Ｎ３の深さＤ３から深い側に向かうにしたがって減少し、深さＤ４で濃度Ｎ４となる。深さＤ４よりも深い領域では、ｎ型不純物濃度は濃度Ｎ４で略一定となっている。濃度Ｎ１～Ｎ４は、Ｎ１＞Ｎ３＞Ｎ２＞Ｎ４の関係を満たす。また、極小値Ｎ２は、極大値Ｎ３の十分の一よりも小さい値である。すなわち、Ｎ３／１０＞Ｎ２が満たされる。また、半導体基板１２の下面１２ｂにおけるｎ型不純物濃度Ｎｓは、極大値Ｎ１の十分の一よりも大きい値である。以下では、深さＤ２よりも浅い側（下面１２ｂ側）に位置するカソード領域３８をコンタクト領域３６といい、深さＤ２と深さＤ４の間のカソード領域３８をバッファ領域３４といい、深さＤ４よりも深い側（上面１２ａ側）のカソード領域３８をドリフト領域３２という。本実施例では、深さＤ１＝０．３～０．７μｍであり、深さＤ３＝０．５～３．０μｍである。
　下面１２ｂと深さＤ１の間の距離ａ（＝Ｄ１）は、深さＤ１と深さＤ２の間の距離ｂ（＝Ｄ２－Ｄ１）の２倍よりも大きい。すなわち、ａ＞２ｂが満たされる。すなわち、コンタクト領域３６内のｎ型不純物濃度分布は、ボックスプロファイルとなっている。すなわち、コンタクト領域３６は、ｎ型不純物を注入した半導体領域を一旦溶融させた後に固化（再結晶化）させて形成されたものである。このため、コンタクト領域３６では、ｎ型不純物濃度が高いにも係らず、結晶欠陥密度が低い。
　バッファ領域３４内では、上述した距離ｂの範囲（深さＤ１と深さＤ２の間の範囲）内に比べて緩やかにｎ型不純物濃度が変化している。バッファ領域３４内では、ガウス分布状にｎ型不純物が分布している。バッファ領域３４は、深さＤ３にｎ型不純物を注入した後に、熱処理によってｎ型不純物を拡散及び活性化させることで形成された領域である。
　ダイオードがオンすると（すなわち、ダイオードに順電圧が印加されると）、アノード電極２０からカソード電極２２に向かってホールが流れるとともに、カソード電極２２からアノード電極２０に向かって電子が流れる。上記の通り、コンタクト領域３６が高いｎ型不純物濃度を有するため、コンタクト領域３６とカソード電極２２の間のコンタクト抵抗は極めて低くなっている。このため、カソード電極２２からコンタクト領域３６に高い注入効率で電子が注入される。また、コンタクト領域３６の結晶欠陥密度が低いため、電子及びホールがコンタクト領域３６を通過する際に、コンタクト領域３６で損失が生じ難くなっている。このため、このダイオードは低損失で動作することができる。
　ダイオードをオフすると（すなわち、ダイオードに逆電圧が印加されると）、アノード領域３０とドリフト領域３２の境界のｐｎ接合から、カソード電極２２に向かって空乏層が伸びる。バッファ領域３４のｎ型不純物濃度が比較的高いため、空乏層はバッファ領域３４内で停止する。これによって、空乏層がコンタクト領域３６に達することが防止され、ダイオードの耐圧が確保される。
　また、製造工程において半導体基板１２の下面１２ｂにキズが生じ、そのキズがバッファ領域３４に達すると、ダイオードの耐圧が低下する。しかしながら、この半導体装置１０では、バッファ領域３４が比較的深い位置に形成されている。より具体的には、深さＤ３が０．５～３．０μｍとなるように形成されている。このため、下面１２ｂにキズが生じても、キズがバッファ領域３４に達し難い。これによって、キズによるダイオードの耐圧低下が生じ難くなっている。
　次に、半導体装置１０の製造方法について説明する。まず、図３に示すｎ型の半導体基板１２を準備する。この段階では、半導体基板１２の全体が、上述した濃度Ｎ４と等しいｎ型不純物濃度を有している。
（バッファ注入工程）
　次に、図４に示すように、半導体基板１２の裏面に、ｎ型不純物を注入する。ここでは、ｎ型不純物の平均停止位置が、半導体基板１２の下面１２ｂから深さＤ３の位置となるように、注入エネルギーを調節する。
（バッファアニール工程）
　次に、炉またはレーザアニール装置を用いることによって、半導体基板１２をアニールする。ここでは、バッファ注入工程でｎ型不純物が注入された深さＤ３の位置が十分に加熱されるようにアニールを行う。また、アニールは、半導体基板１２の表面が溶融しない温度で行う。これによって、バッファ注入工程で注入されたｎ型不純物を拡散、活性化させる。これによって、図５に示すように、半導体基板１２中にバッファ領域３４が形成される。すなわち、バッファアニール工程を実施することで、図２に示すようにガウス分布状にｎ型不純物が分布するバッファ領域３４が形成される。バッファ注入工程におけるｎ型不純物の平均停止深さが深さＤ３であるので、バッファアニール工程後に、図２に示すように深さＤ３にｎ型不純物濃度の極大値Ｎ３が形成される。また、バッファ領域３４よりも上面１２ａ側のｎ型不純物濃度が低い領域は、ドリフト領域３２となる。
（コンタクト注入工程）
　次に、図６に示すように、半導体基板１２の下面１２ｂに、ｎ型不純物を注入する。ここでは、ｎ型不純物の平均停止位置が、バッファ領域３４よりも浅い位置となるように注入エネルギーを調節する。また、コンタクト注入工程では、バッファ注入工程よりも高い濃度でｎ型不純物を注入する。このため、コンタクト注入工程でｎ型不純物の注入を受けた領域（すなわち、下面１２ｂ近傍の領域）には、高密度の結晶欠陥が形成される。
（コンタクトアニール工程）
　次に、レーザアニールによって、半導体基板１２をアニールする。ここでは、半導体基板１２の下面１２ｂにレーザを照射することによって、下面１２ｂ近傍を局所的にアニールする。より詳細には、レーザアニールは、バッファ領域３４に多くの熱が伝わらないように、短時間で行われる。また、レーザアニールは、下面１２ｂ近傍の半導体層が溶融する温度まで昇温するように実施される。具体的には、深さＤ２よりも深い側（上面１２ａ側）の領域が溶融しないように、レーザアニールが実施される。レーザアニールによって溶融した領域３６は、その後、固化して再結晶化する。コンタクト注入工程で注入されたｎ型不純物は、溶融した領域３６内に略均等に拡散する。このため、領域３６が再結晶化すると、領域３６は高濃度にｎ型不純物を含有するコンタクト領域３６となる。すなわち、図７に示すように、半導体基板１２の下面１２ｂに露出する範囲に、コンタクト領域３６が形成される。
　上記の通り、コンタクトアニール工程で領域３６が溶融すると、ｎ型不純物が領域３６内に略均等に拡散する。他方、ｎ型不純物は、溶融しなかった領域にはほとんど拡散しない。その結果、図２に示すように、下面１２ｂと深さＤ１の間の領域ではｎ型不純物濃度があまり大きく変化せず、深さＤ１から深さＤ２に向かってｎ型不純物濃度が急激に減少する分布が得られる。したがって、図の距離ａ、ｂが、ａ＞２ｂの関係を満たすようになる。このように、コンタクトアニール工程を実施することで、ボックス分布を有するコンタクト領域３６が形成される。溶融させる領域が極めて浅い領域に限定されているので、コンタクト領域３６の厚みは薄くなり（深さＤ１が０．３～０．７μｍ）、コンタクト領域３６のピーク濃度Ｎ１が高くなる。また、領域３６を溶融し、その後、固化させる過程において、領域３６内に高密度に存在していた結晶欠陥の大部分が消滅する。このため、再結晶化後のコンタクト領域３６には、結晶欠陥が少ない。すなわち、コンタクトアニール工程を実施することで、ｎ型不純物濃度（より詳細には、ピークｎ型不純物濃度Ｎ１）が高く、かつ、結晶欠陥密度が低いコンタクト領域３６が形成される。なお、コンタクトアニール工程は、コンタクトアニール工程後にＮ３／１０＞Ｎ２＞Ｎ４の関係を満たすｎ型不純物濃度Ｎ２（図２参照）が得られるように実施する。
　次に、半導体基板１２の上面１２ａにｐ型不純物を注入し、活性化させることで、アノード領域３０を形成する。次に、半導体基板１２の上面１２ａにアノード電極２０を形成する。次に、半導体基板１２の下面１２ｂにカソード電極２２を形成する。以上の工程によって、図１に示す半導体装置１０が完成する。
　以上に説明したように、実施例の方法によれば、ｎ型不純物濃度が高く、かつ、結晶欠陥密度が低いコンタクト領域３６を形成することができる。したがって、低損失のダイオードを形成することができる。
　また、実施例の方法では、表面を溶融させるコンタクトアニール工程とは別のアニール工程（バッファアニール工程）によりバッファ領域３４内のｎ型不純物を活性化させる。このため、深い位置にバッファ領域３４を形成することができる。したがって、下面１２ｂへのキズ等による耐圧低下を抑制することができる。
　また、実施例の方法では、Ｎ２＞Ｎ４の関係が満たされるようにコンタクトアニール工程が実施される。これによって、深さＤ２近傍にｐ型領域が形成されることが防止される。すなわち、コンタクトアニール工程前の半導体基板１２の下面１２ｂには、意図せず、ｐ型不純物が付着している場合がある。このような場合に、コンタクトアニール工程において領域３６を溶融させると、ｐ型不純物が３６中に拡散する。従って、深さＤ２においてｎ型不純物濃度が極端に低いと、深さＤ２近傍においてｐ型不純物濃度がｎ型不純物濃度を上回り、深さＤ２近傍にｐ型領域が形成されるおそれがある。しかしながら、本実施例の方法では、Ｎ２＞Ｎ４の関係が満たされる（すなわち、深さＤ２におけるｎ型不純物濃度Ｎ２が原料の半導体基板１２のｎ型不純物濃度Ｎ４よりも高くなる）ようにコンタクトアニール工程が実施される。このため、深さＤ２近傍に微量のｐ型不純物が拡散しても、深さＤ２近傍の領域がｐ型化し難い。したがって、深さＤ２にｐ型領域が形成されることが防止される。このため、実施例の方法により半導体装置１０を量産したときには、ダイオードの特性（特に、ＶＦ）が安定する。
　また、実施例の方法では、Ｎ３／１０＞Ｎ２の関係が満たされるようにダイオードを形成する。これによって、ダイオードの特性の安定化が図られる。すなわち、深さＤ１におけるｎ型不純物濃度Ｎ２が高すぎると、コンタクト領域３６とバッファ領域３４が単一の領域として機能するようになり、コンタクト領域３６のｎ型不純物濃度とバッファ領域３４のｎ型不純物濃度が、互いの特性に影響を及ぼし合うようになる。例えば、ｎ型不純物濃度Ｎ２が高いと、カソード電極２２からコンタクト領域３６への電子の注入効率が、コンタクト領域３６のｎ型不純物濃度だけでなく、バッファ領域３４のｎ型不純物濃度によっても変化するようになる。このため、この電子の注入効率を正確に制御することが困難となり、半導体装置の量産時に電子の注入効率に大きいばらつきが生じるようになる。これに対し、実施例の方法では、Ｎ３／１０＞Ｎ２の関係が満たされるため、電子の注入効率が、バッファ領域３４の影響を受け難い。したがって、実施例の方法によれば、量産時に、各半導体装置のコンタクト領域３６への電子の注入効率にばらつきが生じ難い。
（実施例２）
　実施例２の半導体装置では、図８に示すように、下面１２ｂにおけるｎ型不純物濃度Ｎｓが、実施例１に比べて低い。実施例２では、Ｎ１／１０＞Ｎｓとなっている。このため、深さＤ１よりも浅い領域内に、Ｎ５＝Ｎ１／１０となるｎ型不純物濃度Ｎ５を有する深さＤ５が存在する。実施例２では、深さＤ５から深さＤ１までの距離ｃが、ｃ＞２ｂの関係を満たす。実施例２の半導体装置は、実施例１と同様の方法により製造される。半導体基板の表面を溶融させる方法によって比較的厚みが厚いコンタクト領域３６を形成する際には、実施例２のように、下面１２ｂにおけるｎ型不純物濃度Ｎｓが低くなる場合がある。この場合でも、典型的なボックスプロファイルにおいては、ｃ＞２ｂの関係が満たされる。このように濃度Ｎｓが低い場合には、距離ｃと距離ｂによってボックスプロファイルを定義することもできる（実施例１のように下面１２ｂにおけるｎ型不純物濃度ＮｓがＮｓ＞Ｎ１／１０を満たす場合には、実施例１のように下面１２ｂと深さＤ１の間の距離ａがａ＞２ｂの関係を満たせばよい）。実施例２の半導体装置及びその製造方法でも、実施例１の半導体装置と略同じ利点が得られる。
　次に、比較例の半導体装置と、その製造方法について説明する。なお、比較例の半導体装置も、実施例１、２と同様に、コンタクト領域、バッファ領域、ドリフト領域、アノード領域、カソード電極及びアノード電極を有している。比較例の半導体装置において、これらの領域の不純物濃度及び寸法は異なるものの、これらの領域の基本的な機能は実施例１、２と同じである。したがって、以下では、実施例１、２と共通性を有する部分を、実施例１、２と同じ番号を用いて説明する。また、以下の比較例は、何れも、本願発明者らが実験において実施したものであり、公然知られたものではない。
（比較例１）
　図９は、比較例１の半導体装置のコンタクト領域３６、バッファ領域３４、ドリフト領域３２のｎ型不純物濃度分布を示している。比較例１の半導体装置の製造方法では、まず、半導体基板の深さＤ３にｎ型不純物を注入する。次に、半導体基板１２の下面１２ｂ近傍（例えば、深さＤ１）にｎ型不純物を注入する。次に、レーザアニールによって、半導体基板１２の下面１２ｂを溶融させる。このとき、図９に示す深さＤ２までの領域を溶融させる。これによって、コンタクト領域３６が形成される。また、深さＤ３近傍の領域は、溶融しないものの、レーザアニールにより加熱される。このため、深さＤ３近傍においてｎ型不純物が活性化し、深さＤ３近傍にバッファ領域３４が形成される。これによって、図９に示すようにｎ型不純物が分布する半導体装置が得られる。比較例１の方法では、レーザアニールの熱によってバッファ領域３４を形成するため、バッファ領域３４を下面１２ｂに近い位置に形成する必要がある（すなわち、深さＤ３を浅くする必要がある）。このため、バッファ領域３４を深い位置に形成することができない。したがって、比較例１の半導体装置は、下面１２ｂにキズが生じたときに、耐圧が低下しやすい。また、深さＤ２におけるｎ型不純物濃度が高いため、コンタクト領域３６とバッファ領域３４が十分に分離されない。このため、この方法で半導体装置を量産した場合には、コンタクト領域３６への電子の注入効率にばらつきが生じやすい。
（比較例２）
　図１０は、比較例２の半導体装置のコンタクト領域３６、バッファ領域３４、ドリフト領域３２のｎ型不純物濃度分布を示している。比較例２の半導体装置の製造方法は、比較例１と同様である。但し、バッファ領域３４に対するｎ型不純物の注入深さＤ３が、比較例１よりも深い。また、レーザアニールでは、比較例１よりも深い深さＤ３に注入されたｎ型不純物を活性化させるために、比較例１よりも深い位置まで半導体基板１２を溶融させる。このため、図１０に示すように、比較例２の半導体装置では、バッファ領域３４が比較例１よりも深い位置に形成されている一方で、コンタクト領域３６が幅広となり、コンタクト領域３６のｎ型不純物濃度が低くなっている。このため、比較例２の半導体装置では、コンタクト領域３６のカソード電極２２に対するコンタクト抵抗が高いという問題がある。また、比較例２の半導体装置でも、極小値Ｎ２が高く、コンタクト領域３６とバッファ領域３４が十分に分離されない。
（比較例３）
　図１１は、比較例３の半導体装置のコンタクト領域３６、バッファ領域３４、ドリフト領域３２のｎ型不純物濃度分布を示している。比較例３の半導体装置の製造方法では、まず、深さＤ３にｎ型不純物を注入する。比較例３の深さＤ３は、実施例１の深さＤ３と同等である。次に、半導体基板１２の下面１２ｂをレーザアニールによって溶融させる。ここでは、深さＤ３の領域は溶融させないものの、深さＤ１に近い深さ（図１１の深さＤａ）までを溶融させることで、深さＤ１を加熱する。これによって、深さＤ１に注入された不純物を拡散させ、バッファ領域３４を形成する。次に、半導体基板１２の下面１２ｂ近傍の深さにｎ型不純物を注入する。次に、半導体基板１２の下面１２ｂをレーザアニールによって溶融させる。すなわち、深さＤａよりも浅い領域のみを溶融させ、その溶融させた領域にｎ型不純物を拡散させる。これによって、コンタクト領域３６を形成する。比較例３の方法によれば、図１１に示すように、ｎ型不純物濃度が高いコンタクト領域３６と、深い位置に形成されたバッファ領域３４を実現することができる。しかしながら、比較例３の方法では、半導体基板１２の下面１２ｂにｐ型不純物が意図せず付着している場合に、最初のレーザアニール（深さＤａまで溶融させるレーザアニール）において溶融領域内にｐ型不純物が拡散する。これによって、図１１に示すように、下面１２ｂから深さＤａまでの領域にｐ型不純物が拡散する場合がある。すると、ｎ型不純物の極小値Ｎ２を有する深さＤ２において、ｐ型不純物濃度がｎ型不純物濃度を上回る場合がある。すなわち、コンタクト領域３６とバッファ領域３４の間にｐ型領域が形成される場合がある。このように、比較例３の方法では、コンタクト領域３６とバッファ領域３４の間にｐ型領域が形成されるおそれがあり、量産時にダイオードの特性が安定しない。
　実施例１、２の方法では、上述した比較例１～３のいずれの問題も生じず、高い特性を有する半導体装置を安定的に製造することができる。
　なお、上述した実施例１、２では、バッファ注入工程、バッファアニール工程、コンタクト注入工程、コンタクトアニール工程の順にこれらの工程を実施したが、これらの工程の実施順序を変更してもよい。バッファアニール工程がバッファ工程よりも後に行われ、コンタクトアニール工程がコンタクト注入工程よりも後に行われれば、どのように順序を変更してもよい。
　また、上述した実施例では、ダイオードのみが形成されている半導体装置について説明したが、ダイオードとＩＧＢＴが単一の半導体基板に形成されているＲＣ－ＩＧＢＴのダイオード部分に上述した技術を適用してもよい。なお、ＲＣ－ＩＧＢＴとしては、例として、図１２に示す構成を挙げることができる。図１２において、参照番号２０～２２及び３０～３６は、実施例１に対応する。また、参照番号５１はエミッタ領域であり、参照番号５２はボディ領域であり、参照番号５３はコレクタ領域であり、参照番号５５はゲート絶縁膜であり、参照番号５６はゲート電極である。これらの構成要素５１～５６及び領域３２、３４によって、ＩＧＢＴが形成されている。また、アノード電極２０はＩＧＢＴのエミッタ電極を兼ねており、カソード電極２２はＩＧＢＴのコレクタ電極を兼ねている。
　また、上述した実施例では、ダイオードについて説明したが、上述した技術をＦＥＴ（例えば、ＭＯＳＦＥＴ）のソース領域とソース電極のコンタクト部分やドレイン領域とドレイン電極のコンタクト部分に適用してもよい。
　以上、本発明の具体例を詳細に説明したが、これらは例示にすぎず、特許請求の範囲を限定するものではない。特許請求の範囲に記載の技術には、以上に例示した具体例をさまざまに変形、変更したものが含まれる。
　本明細書または図面に説明した技術要素は、単独であるいは各種の組み合わせによって技術的有用性を発揮するものであり、出願時請求項記載の組み合わせに限定されるものではない。また、本明細書または図面に例示した技術は複数目的を同時に達成するものであり、そのうちの一つの目的を達成すること自体で技術的有用性を持つものである。

Claims (6)

  1. 　半導体基板の表面に露出している第１導電型領域を有しており、
    　前記第１導電型領域における第１導電型不純物の濃度分布を前記半導体基板の厚み方向に沿って見たときに、極大値Ｎ１、極小値Ｎ２、極大値Ｎ３が形成されており、
    　前記極大値Ｎ１を有する深さが、前記極小値Ｎ２を有する深さよりも前記表面側に位置しており、
    　前記極大値Ｎ３を有する深さが、前記極小値Ｎ２を有する前記深さよりも前記表面の反対側に位置しており、
    　前記極大値Ｎ３を有する前記深さよりも前記表面の反対側に位置する前記第１導電型領域内に、第１導電型不純物の濃度Ｎ４を有する領域が存在し、
    　Ｎ１＞Ｎ３＞Ｎ２＞Ｎ４の関係が満たされており、
    　Ｎ３／１０＞Ｎ２の関係が満たされており、
    　前記表面から前記極大値Ｎ１を有する深さまでの距離ａが、前記極大値Ｎ１を有する深さから前記極小値Ｎ２を有する深さまでの距離ｂの２倍より大きい、
    　半導体装置。
  2. 　前記極大値Ｎ１を有する前記深さよりも前記表面側に、前記極大値Ｎ１の１／１０の第１導電型不純物の濃度Ｎ５を有する深さが存在しており、
    　前記濃度Ｎ５を有する深さから前記極大値Ｎ１を有する深さまでの距離ｃが、前記距離ｂの２倍より大きい、
    　請求項１の半導体装置。
  3. 　前記半導体基板に、ダイオードが形成されており、
    　前記第１導電型領域がダイオードのカソード領域である請求項１または２の半導体装置。
  4. 　前記半導体基板に、ＩＧＢＴがさらに形成されている請求項３の半導体装置。
  5. 　前記半導体基板に、ＭＯＳＦＥＴが形成されており、
    　前記第１導電型領域がＭＯＳＦＥＴのソース領域またはドレイン領域である請求項１または２の半導体装置。
  6. 　半導体装置を製造する方法であって、
    　第１導電型の半導体基板の表面に、第１導電型不純物を注入する第１注入工程と、
    　前記第１注入工程後に、前記半導体基板が溶融しない温度で前記半導体基板を熱処理する工程と、
    　前記半導体基板の前記表面に、前記第１注入工程よりも低いエネルギーで前記第１注入工程よりも高濃度に第１導電型不純物を注入する第２注入工程と、
    　第２注入工程後に、前記第１注入工程における第１導電型不純物の平均停止位置よりも前記表面側の領域を溶融させ、その後、固化させる工程、
    　を有する方法。
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