TWI543369B - 具有抑制穿通效應之先進電晶體 - Google Patents

具有抑制穿通效應之先進電晶體 Download PDF

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TWI543369B
TWI543369B TW100121611A TW100121611A TWI543369B TW I543369 B TWI543369 B TW I543369B TW 100121611 A TW100121611 A TW 100121611A TW 100121611 A TW100121611 A TW 100121611A TW I543369 B TWI543369 B TW I543369B
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region
dopant
concentration
field effect
effect transistor
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TW100121611A
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TW201205811A (en
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露西安 席弗倫
普西卡 蘭納德
保羅Ｅ 格列高里
史考特Ｅ 湯普森
沙琴Ｒ 桑庫沙爾
鄭偉銘
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三重富士通半導體股份有限公司
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Description

具有抑制穿通效應之先進電晶體 相關申請案
本申請案主張2009年9月30申請之美國臨時申請案第61/247,300號之權益，該案之揭示內容以引用之方式併入本文。本申請案亦主張2009年11月17日申請之美國臨時申請案第61/262,122號之權益，該案之揭示內容以引用之方式併入本文，且主張2010年2月18日申請之標題名稱為「電子裝置與系統及其製造與使用方法」之美國專利申請案第12/708,497號之權益，該案之揭示內容以引用之方式併入本文。本申請案亦主張2010年6月22日申請之美國臨時申請案第61/357,492號之權益，該案之揭示內容以引用之方式併入本文。
發明領域
本揭示案係關於用於形成具有改良操作特性之先進電晶體的結構及製程，該等改良操作特性包括增強的抑制穿通效應。
 發明背景
需要將更多電晶體裝配至單個晶粒上，以降低電子設備之成本並改良電子設備之功能能力。半導體製造商使用之共同策略為簡單地減小場效電晶體(FET)之閘極大小，且成比例地縮小電晶體源極、汲極及電晶體之間所需互連之區域。然而，簡單成比例縮小由於被稱為「短通道效應」之效應而致並非總是可行。當電晶體閘極下方之通道長度在量值上操作電晶體之空乏深度相當時，短通道效應尤其嚴重，且該等短通道效應包括臨界電壓之減少、嚴重表面散射、汲極引致位障降低(DIBL)、源極-汲極穿通及電子遷移率問題。
減緩一些短通道效應之習知解決方案可能涉及圍繞源極及汲極植入口袋植入物及暈輪植入物。暈輪植入物可為相對於電晶體源極及汲極對稱或非對稱，且該等暈輪植入物通常在電晶體井與源極及汲極之間提供較平滑之摻雜梯度。遺憾地是，儘管此等植入物改善諸如臨界電壓下降及汲極引致位障降低之一些電氣特性，但是所得增加的通道摻雜卻不利地影響電子遷移率，主要因為通道中增加的摻雜劑散射。
許多半導體製造商已試圖藉由使用新電晶體類型來減少短通道效應，該等新電晶體類型包括完全或部分空乏絕緣體上矽(SOI)電晶體。將SOI電晶體建置於覆在絕緣體層上面之矽之薄層上，該等SOI電晶體具有使短通道效應最小化之無摻雜或低摻雜的通道，且該等SOI電晶體不需要用於操作之深井植入物或暈輪植入物。遺憾地，建立適合絕緣體層為昂貴的且難以實現。早期SOI裝置係建置於絕緣藍寶石晶圓上而非矽晶圓上，且由於高成本，通常僅用在專業應用(例如軍用航空電子設備或衛星)中。現代SOI技術可使用矽晶圓，但是需要昂貴且費時的額外晶圓處理步驟，以製作絕緣氧化矽層，該絕緣氧化矽層在裝置品質單晶矽之表面層下方延伸跨越整個晶圓。
在矽晶圓上製作此氧化矽層之一個普通方法需要高劑量離子植入氧及高溫退火，以在塊體矽晶圓中形成埋藏氧化物(BOX)層。或者，可藉由將矽晶圓接合至另一矽晶圓(「操作」晶圓)來製造SOI晶圓，該另一矽晶圓在其表面上具有氧化物層。使用將BOX層之上的單晶矽之薄電晶體品質層留在操作晶圓上之製程，將該對晶圓分裂開。此稱為「層轉移」技術，因為該技術將矽之薄層轉移至操作晶圓之熱生長氧化物層上。
如將預期到者，BOX形成及層轉移二者皆為具有相當高失敗率之昂貴製造技術。因此，SOI電晶體之製造對於許多領先製造商並非為經濟上吸引人的解決方案。當將克服「浮體」效應、需要開發新SOI特定電晶體製程及其他電路變化的電晶體重新設計之成本添加至SOI晶圓成本時，顯然需要其他解決方案。
已研究之另一可能先進電晶體使用多閘極電晶體，如同SOI電晶體，該等多閘極電晶體藉由在通道中具有極少或沒有摻雜來最小化短通道效應。通常被稱為finFET(由於部分遭閘極圍繞的鰭狀形狀之通道)，對於具有28奈米或更小電晶體閘極大小之電晶體而言，已提出finFET電晶體之使用。但是再次，如同SOI電晶體，儘管發展至完全新的電晶體架構解決了一些短通道效應問題，但是該架構造成其他問題，從而需要比SOI更顯著的電晶體佈局重新設計。慮及可能需要複雜非平面電晶體製造技術來製作finFET，及建立用於finFET之新製程流程中之未知困難，製造商已不願投資於能夠製作finFET之半導體製造設備。
 發明概要
依據本發明之一實施例，係特地提出一種場效電晶體結構，包含：一井，該井經摻雜為具有一摻雜劑之一第一濃度；一屏蔽層，該屏蔽層植入至該井中，且具有大於每立方公分5×1018個摻雜劑原子之摻雜劑之一第二濃度；以及至少一個穿通抑制區域，該至少一個穿通抑制區域具有介於摻雜劑之該第一濃度與該第二濃度之間的一摻雜劑之一第三濃度，其中該穿通抑制區域定置在該閘極下方且在該屏蔽區域與該井之間。
依據本發明之另一實施例，係特地提出一種用於形成一場效電晶體結構之方法，該場效電晶體結構減少不利的穿通效應，該方法包含以下步驟：形成一井，該井經摻雜為具有一摻雜劑之一第一濃度；植入一屏蔽區域，該屏蔽區域具有大於每立方公分5×1018個摻雜劑原子之一摻雜劑濃度；以及在該井中形成一穿通抑制區域。
圖式簡單說明
第1圖圖示具有抑制穿通效應之DDC電晶體；第2圖圖示具有增強的抑制穿通效應之DDC電晶體之摻雜劑分佈輪廓；第3圖-第7圖圖示替代性有用摻雜劑分佈輪廓；以及第8圖為圖示用於形成具有抑制穿通效應之DDC電晶體之一個示例性製程的流程圖。
 較佳實施例之詳細說明
不同於絕緣體上矽(SOI)電晶體，奈米級塊體CMOS電晶體(通常具有小於100奈米之閘極長度之電晶體)經受顯著不利的短通道效應，包括經由汲極引致位障降低(DIBL)與源極-汲極穿通之主體洩漏。穿通與源極及汲極空乏層之合併相關聯，從而使汲極空乏層延伸越過摻雜基體並到達源極空乏層，進而建立源極與汲極之間的傳導路徑或漏電流。此舉導致所需電晶體電功率之顯著增長，以及電晶體熱輸出之必然增加及使用此等電晶體之攜帶型或電池供電裝置之操作壽命之減少。
可製造於塊體CMOS基體上之改良電晶體參見於第1圖中。場效電晶體(FET) 100根據某些描述之實施例經組配以具有大幅減少之短通道效應及增強的抑制穿通效應。FET 100包括閘極電極102、源極104、汲極106及定置在通道110上方之閘極介電質108。在操作中，使通道110深空乏，從而形成與習知電晶體相比可被描述為深空乏通道(DDC)之通道，其中空乏深度部分由高摻雜屏蔽區域112設定。儘管通道110為大體上無摻雜的，且如圖所示通道110定置在高摻雜屏蔽區域112上方，但是通道110可包括具有不同摻雜劑濃度之簡單或複雜的分層。此摻雜分層可包括具有小於屏蔽區域112之摻雜劑濃度的臨界電壓設定區域111，臨界電壓設定區域111選擇性地於通道110中定置在閘極介電質108與屏蔽區域112之間。臨界電壓設定區域111容許FET 100之操作臨界電壓之小幅調整，同時使通道110之塊體大體上無摻雜。特定言之，鄰接於閘極介電質108之通道110之部分應保持無摻雜。另外，在屏蔽區域112之下形成穿通抑制區域113。如臨界電壓設定區域111，穿通抑制區域113具有之摻雜劑濃度小於屏蔽區域112而高於輕摻雜井基體114之整體摻雜劑濃度。
在操作中，可將偏壓122 VBS施加至源極104，以進一步修改操作臨界電壓，且可將P+端子126在連接124處連接至P型井114，以閉合電路。閘極堆疊包括閘極電極102、閘極接點118及閘極介電質108。包括閘極間隔物130，以使閘極與源極及汲極分離，且選擇性的源極/汲極延伸(SDE) 132或「尖端」使源極及汲極在閘極間隔物及閘極介電質108之下延伸，從而稍微減少閘極長度並改善FET 100之電氣特性。
在此示例性實施例中，FET 100係圖示為具有由N型摻雜劑材料製成之源極及汲極之N型通道電晶體，FET 100係形成於作為P型摻雜矽基體之基體之上，從而提供形成於基體116上之P型井114。然而，將理解，在適當改變基體或摻雜劑材料的情況下，可取代由諸如基於砷化鎵之材料之其他適合基體形成的非矽P型半導體電晶體。可使用習知摻雜劑植入製程及材料來形成源極104及汲極106，且源極104及汲極106可例如包括以下修改：諸如應力引致源極/汲極結構、凸起及/或凹入源極/汲極、非對稱摻雜、反摻雜或晶體結構修改的源極/汲極、或根據低摻雜汲極(LDD)技術之源極/汲極延伸區域之植入摻雜。亦可使用修改源極/汲極操作特性之各種其他技術，該等技術在某些實施例中包括使用異質摻雜劑材料作為補償摻雜劑來修改電氣特性。
閘極電極102可由習知材料形成，該等材料較佳包括但不限於金屬、金屬合金、金屬氮化物及金屬矽化物，以及該等材料之疊層及複合物。在某些實施例中，閘極電極102亦可由多晶矽形成，該多晶矽包括例如高摻雜多晶矽及多晶矽-鍺合金。金屬或金屬合金可包括含有鋁、鈦、鉭或其氮化物之彼等金屬或金屬合金，該等氮化物包括含有諸如氮化鈦之化合物之鈦。閘極電極102之形成可包括矽化方法、化學氣相沈積方法及物理氣相沈積方法，諸如但不限於蒸發方法及濺鍍方法。通常，閘極電極102具有約1奈米至約500奈米之整體厚度。
閘極介電質108可包括習知介電材料，諸如，氧化物、氮化物及氮氧化物。或者，閘極介電質108可包括通常較高介電常數之介電材料、基於金屬之介電材料及具有介電性質之其他材料，該等通常較高介電常數之介電材料包括但不限於氧化鉿、矽酸鉿、氧化鋯、氧化鑭、氧化鈦、鈦酸鍶鋇及鋯鈦酸鉛。較佳含鉿氧化物包括HfO2、HfZrOx、HfSiOx、HfTiOx、HfAlOx及其類似物。取決於組合物及可用的沈積處理設備，可藉由諸如熱氧化或電漿氧化、氮化方法、化學氣相沈積方法(包括原子層沈積方法)及物理氣相沈積方法之方法來形成閘極介電質108。在一些實施例中，可使用多個或複合層、疊層及介電材料之成分混合物。舉例而言，閘極介電質可由具有介於約0.3 nm與1 nm之間的厚度之基於SiO2之絕緣體及具有介於0.5 nm與4 nm之間的厚度之基於氧化鉿之絕緣體形成。通常，閘極介電質具有約0.5奈米至約5奈米之整體厚度。
在閘極介電質108下方且在高摻雜屏蔽區域112上方形成通道區域110。通道區域110亦接觸源極104及汲極106，且在源極104與汲極106之間延伸。較佳地，通道區域包括大體上無摻雜的矽，該大體上無摻雜的矽鄰接或接近閘極介電質108具有小於每立方公分5×1017個摻雜劑原子之摻雜劑濃度。通道厚度可通常在5奈米至50奈米之範圍。在某些實施例中，藉由在屏蔽區域上磊晶生長純的或大體上純的矽來形成通道區域110。
如所揭示的，將臨界電壓設定區域111定置在屏蔽區域112上方，且通常將臨界電壓設定區域111形成為薄摻雜層。適當地改變摻雜劑濃度、厚度及使閘極介電質與屏蔽區域分離，在操作FET 100中允許臨界電壓之受控輕微調整。在某些實施例中，摻雜臨界電壓設定區域111，以具有介於約每立方公分1×1018個摻雜劑原子與約每立方公分1×1019個摻雜劑原子之間的濃度。可藉由若干不同製程來形成臨界電壓設定區域111，該等製程包括：1)原位磊晶摻雜，2)矽之薄層之磊晶生長繼之以緊密受控摻雜劑植入，3)矽之薄層之磊晶生長繼之以摻雜劑原子自屏蔽區域112之擴散，或4)藉由此等製程之任何組合(例如矽之磊晶生長繼之以摻雜劑植入與摻雜劑自屏蔽層112擴散)。
高摻雜屏蔽區域112之位置通常設定操作FET 100之空乏區之深度。有利地，以相當於閘極長度之深度(Lg/1)至閘極長度之較大分數之深度(Lg/5)之範圍的深度來設定屏蔽區域112(及相關聯空乏深度)。在較佳實施例中，典型範圍在Lg/3至Lg/1.5之間。具有Lg/2或更大之深度的裝置對於極低功率的操作較佳，而時常可使以較高電壓操作之數位或類比裝置形成有介於Lg/5與Lg/2之間的屏蔽區域。舉例而言，可形成具有32奈米之閘極長度之電晶體，以具有在閘極介電質下方約16奈米之深度(Lg/2)處具有峰值摻雜劑密度的屏蔽區域，且在8奈米之深度(Lg/4)處具有峰值摻雜劑密度之臨界電壓設定區域。
在某些實施例中，摻雜屏蔽區域112，以具有介於約每立方公分5×1018個摻雜劑原子與約每立方公分1×1020個摻雜劑原子之間的濃度，該濃度顯著大於無摻雜通道之摻雜劑濃度，且至少稍微大於選擇性臨界電壓設定區域111之摻雜劑濃度。如將瞭解到，可修改精確摻雜劑濃度及屏蔽區域深度，以改良FET 100之所要的操作特性，或慮及可用的電晶體製造程序及製程條件。
為幫助控制洩漏，在屏蔽區域112之下形成穿通抑制區域113。通常，藉由直接植入至輕摻雜井中來形成穿通抑制區域113，但是穿通抑制區域113係藉由自屏蔽區域向外擴散、原位生長或其他已知製程形成。如臨界電壓設定區域111，穿通抑制區域113具有小於屏蔽區域122之摻雜劑濃度，通常設定在約每立方公分1×1018個摻雜劑原子與約每立方公分1×1019個摻雜劑原子之間。另外，將穿通抑制區域113摻雜劑濃度設定為高於井基體之整體摻雜劑濃度。如將瞭解，可修改精確摻雜劑濃度及深度，以改良FET 100之所要的操作特性，或慮及可用的電晶體製造程序及製程條件。
與SOI或finFET電晶體相比，形成此FET 100相對簡單，因為可容易地調適良好發展且長期使用之平坦化CMOS處理技術。
同時，此等結構及製作該等結構之方法允許具有與習知奈米級裝置相比偏低之操作電壓與低臨界電壓之FET電晶體。此外，可組配DDC電晶體，以允許藉助於電壓主體偏壓產生器使臨界電壓得以靜態地設定。在一些實施例中，甚至可動態控制臨界電壓，從而允許電晶體漏電流得以大幅降低(藉由設定電壓偏壓，以向上調整用於低洩漏、低速操作之VT)或增加(藉由向下調整用於高洩漏、高速操作之VT)。最終，此等結構及製作結構之方法提供設計具有FET裝置之積體電路，當電路處於操作中時可動態調整該等FET裝置。因此，可將積體電路中之電晶體設計為具有標稱相同結構，且該等電晶體可經控制、調變或規劃，來回應於不同偏壓而以不同操作電壓操作，或回應於不同偏壓及操作電壓而以不同操作模式操作。另外，可在製造後組配此等電晶體以用於電路內之不同應用。
如將瞭解，依據實體及功能區域或層來描述植入或以其他方式存在於半導體之基體或結晶層中以修改半導體之實體及電氣特性的原子之濃度。熟習此項技術者可將此等區域或層理解為具有特定之濃度平均值的材料之三維塊體。或者，可將此等區域或層理解為具有不同或隨空間變化之濃度的子區域或子層。此等區域或層亦可作為摻雜劑原子之小群組、大體上類似的摻雜劑原子或其類似物之區域或其他實體實施例而存在。基於此等性質之區域之描述不意欲限制形狀、精確位置或方位。該等描述亦不意欲將此等區域或層限制於任何特定類型或數量之製程步驟、任何特定類型或數量之層(例如複合或單一的)、半導體沈積、蝕刻技術或使用之生長技術。此等製程可包括磊晶形成區域或原子層沈積、摻雜劑植入方法或特定豎直或橫向摻雜劑分佈輪廓，包括線性、單調增加、逆行或其他適合的空間變化摻雜劑濃度。為確保所要的摻雜劑濃度得以維持，涵蓋各種摻雜劑抗遷移技術，包括低溫處理、碳摻雜、原位摻雜劑沈積及先進快閃或其他退火技術。所得摻雜劑分佈輪廓可具有含不同摻雜劑濃度之一或更多區域或層，且濃度之變化及區域或層如何與製程無關地被界定，可能為或可能不為可經由技術來檢測，該等技術包括紅外光譜術、拉塞福背向散射(Rutherford Back Scattering；RBS)、二次離子質譜法(SIMS)或使用不同定性或定量摻雜劑濃度測定方法之其他摻雜劑分析工具。
為更好地瞭解一個可能的電晶體結構，第2圖圖示在源極與汲極之間且自閘極介電質至井向下延伸的中線處取得之深空乏電晶體之摻雜劑分佈輪廓202。以每立方公分摻雜劑原子之數量來量測濃度，且根據閘極長度Lg之比率來量測向下的深度。根據比率而非以奈米為單位之絕對深度來量測，更好地允許在不同節點(例如45 nm、32 nm、22 nm或15 nm)處製造之電晶體之間的交叉比較，其中通常依據最小閘極長度來界定節點。
如第2圖中所見，鄰接於閘極介電質之通道區域210為大體上無摻雜劑的，到達幾乎Lg/4之深度，具有少於每立方公分5×1017個摻雜劑原子。臨界電壓設定區域211使摻雜劑濃度增加至約每立方公分3×1018個摻雜劑原子，且使濃度增加另一數量級，至約每立方公分3×1019個摻雜劑原子，以形成屏蔽區域212，屏蔽區域212設定操作電晶體中之空乏區之基極。在約Lg/1之深度處具有約每立方公分1×1019個摻雜劑原子之摻雜劑濃度的穿通抑制區域213之區域為屏蔽區域與輕摻雜井214之間的中間區域。在沒有穿通抑制區域的情況下，經建構以具有例如30 nm閘極長度及1.0伏特之操作電壓之電晶體，將預期具有顯著更大的洩漏。當植入所揭示的穿通抑制區域213時，穿通洩漏減少，從而使得電晶體更為在功率上有效，且更好地能夠容忍電晶體結構中之製程變化而不發生穿通故障。
參閱以下表1可更好地看出此狀況，表1指示穿通劑量及臨界電壓之範圍之預期效能改良：
涵蓋替代性摻雜劑分佈輪廓。如第3圖中所見，圖示替代性摻雜劑分佈輪廓，該替代性摻雜劑分佈輪廓包括用於低摻雜通道之稍微增加的深度。與第3圖之實施例不同，臨界電壓設定區域211為主要藉由自屏蔽區域212外擴散至矽之磊晶沈積層中形成之淺缺口。屏蔽區域212本身經設定以具有大於每立方公分3×1019個摻雜劑原子之摻雜劑濃度。穿通抑制區域213具有約每立方公分8×1018個摻雜劑原子之摻雜劑濃度，該摻雜劑濃度由來自屏蔽區域212之外擴散與單獨低能植入之組合提供。
如第4圖中所見，圖示替代性摻雜劑分佈輪廓，該替代性摻雜劑分佈輪廓包括用於低摻雜通道之大為增加的深度。與第2圖及第3圖之實施例不同，不存在幫助臨界電壓設定之獨異缺口、平面或層。將屏蔽區域212設定為大於每立方公分3×1019個摻雜劑原子，且穿通抑制區域213具有約每立方公分8×1018個摻雜劑原子之類似高的但狹窄界定之摻雜劑濃度，該摻雜劑濃度由單獨低能植入提供。
摻雜劑分佈輪廓之另一變化參見於第5圖中，第5圖圖示用於包括極低摻雜通道210之電晶體結構之電晶體摻雜劑分佈輪廓205。藉由生長於屏蔽區域上之薄磊晶層之原位或良好受控植入摻雜來精確地形成臨界電壓設定區域211。將屏蔽區域212設定為約每立方公分1×1019個摻雜劑原子，且穿通抑制區域213亦具有約每立方公分8×1018個摻雜劑原子之狹窄界定之摻雜劑濃度，該摻雜劑濃度由單獨低能植入提供。將井植入214濃度逐漸減少至約每立方公分5×1017個摻雜劑原子。
如第6圖中所見，摻雜劑分佈輪廓206包括鄰接於閘極介電質之低摻雜通道210，及狹窄界定之臨界電壓設定區域211。屏蔽區域212增加至被設定為約每立方公分1×1019個摻雜劑原子之窄峰值，且穿通抑制區域213亦具有約每立方公分5×1018個摻雜劑原子之寬峰值摻雜劑濃度，該寬峰值摻雜劑濃度由單獨低能植入提供。井植入214濃度高，以改善電晶體之偏壓係數，其中濃度為約每立方公分8×1017個摻雜劑原子。
與第6圖之窄屏蔽區域峰值摻雜劑濃度不同，第7圖之摻雜劑分佈輪廓207具有寬峰值212。除狹窄無摻雜通道210之外，此電晶體結構包括良好界定之部分逆行臨界設定211及獨特單獨穿通抑制峰值213。井214摻雜濃度相對低，小於約每立方公分5×1017個摻雜劑原子。
第8圖為示意性製程流程圖300，製程流程圖300圖示用於形成具有穿通抑制區域及屏蔽區域之電晶體之一個示例性製程，該電晶體適合於不同類型之FET結構，該等FET結構包括類比電晶體與數位電晶體。在此所示之製程在描述上意欲為一般且廣泛的，以便不使本發明概念難以理解，且下文闡述更詳細實施例及實例。此等及其他製程步驟允許處理及製造包括DDC結構裝置及舊有裝置之積體電路，從而允許設計涵蓋具有改良的效能及降低的功率之全範圍之類比裝置及數位裝置。
在步驟302中，製程自井形成開始，該井形成可為根據不同實施例及實例之許多不同製程中之一個製程。如步驟303中所指示，井形成可在淺溝槽隔離(STI)形成304之前或之後，此取決於應用及所要的結果。硼(B)、銦(I)或其他P型材料可用於P型植入，且砷(As)或磷(P)及其他N型材料可用於N型植入。對於PMOS井植入而言，可在10 keV至80 keV之範圍內植入P+植入物，而對於NMOS井植入而言，可在0.5 keV至5 keV之範圍內且在1×1013/cm2至8×1013/cm2之濃度範圍內植入硼植入物B+。可在10 keV至60 keV之範圍內且以1×1014/cm2至5×1014/cm2之濃度來執行鍺植入物Ge+。為減少摻雜劑遷移，可在0.5 keV至5 keV範圍且以1×1013/cm2至8×1013/cm2之濃度來執行碳植入物C+。井植入可包括穿通抑制區域、具有比穿通抑制區域高的摻雜劑密度之屏蔽區域及臨界電壓設定區域之順序植入及/或磊晶生長及植入，先前所述之臨界電壓設定區域通常係藉由將摻雜劑植入或擴散至屏蔽區域上之生長磊晶層中而形成。
在一些實施例中，井形成302可包括Ge/B(N)、As(P)之射束線植入，繼之以磊晶(EPI)預清潔製程，且最終繼之以非選擇性的毯覆性EPI沈積，如302A中所示。或者，可使用B(N)、As(P)之電漿植入來形成井，該電漿植入繼之以EPI預清潔，此後最終繼之以非選擇性(毯覆性)EPI沈積，即302B。或者，井形成可包括B(N)、As(P)之固態源擴散，繼之以EPI預清潔，且最終繼之以非選擇性(毯覆性)EPI沈積，即302C。或者，井形成可包括B(N)、As(P)之固態源擴散，繼之以EPI預清潔，且最終繼之以非選擇性(毯覆性)EPI沈積，即302D。作為另一替代方法，井形成可簡單地包括井植入，繼之以B(N)、P(P)之原位摻雜選擇性EPI。本文描述之實施例允許數個裝置中之任一裝置，該等裝置係使用不同井結構且根據不同參數組配在共用基體上。
再次可發生在井形成302之前或之後的淺溝槽隔離(STI)形成304可包括以低於900℃之溫度的低溫溝槽犧牲氧化物(TSOX)襯裡。可以數個不同方式、由不同材料或由不同功函數來形成或以其他方式建構閘極堆疊306。一個選擇為多晶矽/SiON閘極堆疊306A。另一選擇為先閘極製程306B，該先閘極製程306B包括SiON/金屬/多晶矽及/或SiON/多晶矽，繼之以高介電常數/金屬閘極。另一選擇，後閘極製程306C，包括高介電常數/金屬閘極堆疊，其中可使用「先高介電常數後金屬閘極」流程或「後高介電常數後金屬閘極」流程來形成該閘極堆疊。另一選擇306D為金屬閘極，該金屬閘極包括取決於裝置構造N(NMOS)/P(PMOS)/N(PMOS)/P(NMOS)/中間隙或在之間的任何地方之可調諧範圍之功函數。在一個實例中，N具有4.05 V±200 mV之功函數(WF)，而P具有5.01 V±200 mV之WF。
接著，在步驟308中，可取決於應用而植入源極/汲極尖端，或選擇性地可不植入該等尖端。可根據需要改變尖端之尺寸，且該等尖端之尺寸將部分取決於是否使用閘極間隔物(SPCR)。在一個選擇中，在308A中可不存在尖端植入。接著，在選擇性步驟310及選擇性步驟312中，可在源極及汲極區域中將PMOS或NMOS EPI層形成為用於建立應變通道之效能增強器。對於後閘極之閘極堆疊選擇而言，在步驟314中，形成後閘極模組。此舉可能僅用於後閘極製程314A。
本發明涵蓋支援多個電晶體類型之晶粒，該多個電晶體類型包括有及沒有抑制穿通效應之電晶體類型、具有不同臨界電壓之電晶體類型以及有及沒有靜態或動態偏壓之電晶體類型。使用本文描述之方法可將單晶片系統(SoC)、先進微處理器、射頻、記憶體及具有一或更多數位電晶體及類比電晶體組態之其他晶粒併入一裝置中。根據本文論述之方法及製程，可使用塊體CMOS在矽上生產具有含或不含穿通抑制效應之DDC及/或電晶體裝置及結構之各種組合的系統。在不同實施例中，可將晶粒分為一或更多區域，其中動態偏壓結構、靜態偏壓結構或無偏壓結構單獨存在或以一些組合存在。在動態偏壓區段中，例如，動態可調整裝置可與高VT裝置及低VT裝置一起存在，且可能與DDC邏輯裝置一起存在。
儘管已描述且在隨附圖式中圖示某些示例性實施例，但是應理解，此等實施例僅說明廣義發明而非加以限制，且本發明不限於所示並描述之特定構造及佈置，因為一般熟於此技術者可想到各種其他修改。因此，本說明書及圖式將以說明性意義而非限制性意義視之。
100．．．場效電晶體(FET)
102．．．閘極電極
104．．．源極
106．．．汲極
108．．．閘極介電質
110．．．通道/通道區域
111．．．臨界電壓設定區域
112．．．高摻雜屏蔽區域/屏蔽區域/屏蔽層
113．．．穿通抑制區域
114．．．輕摻雜井基體/P型井
116．．．基體
118．．．閘極接點
122、VBS．．．偏壓
124．．．連接
126．．．P+端子
130．．．閘極間隔物
132．．．源極/汲極延伸
202、206、207．．．摻雜劑分佈輪廓
205．．．電晶體摻雜劑分佈輪廓
210．．．窄無摻雜通道/通道區域/低摻雜通道
211．．．臨界電壓設定區域/良好界定之部分逆行臨界設定
212．．．屏蔽區域/寬峰值
213．．．穿通抑制區域/穿通抑制/穿通抑制峰值
214．．．輕摻雜井/井植入/井
300．．．製程流程圖
302．．．步驟/井形成
302A~D、303、306、308、308A、314‧‧‧步驟
304‧‧‧步驟/淺溝槽隔離形成
306A‧‧‧多晶矽/SiON閘極堆疊
306B‧‧‧先閘極製程
306C、314A‧‧‧後閘極製程
306D‧‧‧金屬閘極
310~312‧‧‧選擇性步驟
LG‧‧‧閘極長度
第1圖圖示具有抑制穿通效應之DDC電晶體；
第2圖圖示具有增強的抑制穿通效應之DDC電晶體之摻雜劑分佈輪廓；
第3圖-第7圖圖示替代性有用摻雜劑分佈輪廓；以及
第8圖為圖示用於形成具有抑制穿通效應之DDC電晶體之一個示例性製程的流程圖。
100．．．場效電晶體(FET)
102．．．閘極電極
104．．．源極
106．．．汲極
108．．．閘極介電質
110．．．通道/通道區域
111．．．臨界電壓設定區域
112．．．高摻雜屏蔽區域/屏蔽區域/屏蔽層
113．．．穿通抑制區域
114．．．輕摻雜井基體/P型井
116．．．基體
118．．．閘極接點
122、VBS．．．偏壓
124．．．連接
126．．．P+端子
130．．．閘極間隔物
132．．．源極/汲極延伸
LG．．．閘極長度

Claims (11)

  1. 一種場效電晶體結構，具有一位在一具有長度Lg之閘極下方的閘極介電質，而該場效電晶體結構包含：一基體；在該基體中之一井，其係經摻雜為具有一摻雜劑之一第一濃度；一無摻雜的通道，其位在該閘極介電質下方且延伸至一源極與一汲極；一屏蔽區域，其位在該井中並位在該閘極介電質下方，該屏蔽區域延伸至該源極與該汲極，且具有大於每立方公分5×1018個摻雜劑原子之摻雜劑之一第二濃度；至少一個穿通抑制區域，其具有介於摻雜劑之該第一濃度與該第二濃度之間的一摻雜劑之一第三濃度，其中該穿通抑制區域定置在該井中並位在該閘極介電質下方且在該屏蔽區域之下；以及一臨界電壓設定區域，其具有介於該第二濃度與每立方公分5×1017個摻雜劑原子之間的一第四摻雜劑濃度，其中該臨界電壓設定區域定置在該閘極介電質下方且與之相間隔開並定置在該屏蔽區域上方，該臨界電壓設定區域延伸至該源極與該汲極。
  2. 如申請專利範圍第1項之場效電晶體結構，其中該屏蔽區域層定置在該閘極介電質下方且在介於Lg/5與Lg/1之間的深度。
  3. 如申請專利範圍第1項之場效電晶體結構，其中該屏蔽區 域層定置在該閘極介電質下方且在大於Lg/2的深度。
  4. 如申請專利範圍第1項之場效電晶體結構，其中該通道包含一磊晶成長層。
  5. 如申請專利範圍第1項之場效電晶體結構，其中該通道係被形成為一毯覆性磊晶層。
  6. 如申請專利範圍第1項之場效電晶體結構，其中該屏蔽區域係設定該場效電晶體結構的空乏深度。
  7. 如申請專利範圍第1項之場效電晶體結構，其中該臨界電壓設定區域係被形成為一磊晶層。
  8. 如申請專利範圍第1項之場效電晶體結構，進一步包含一淺溝槽隔離區域。
  9. 一種用於形成場效電晶體結構之方法，係用於形成如請求項1之場效電晶體結構之方法，該方法包含以下步驟：形成一井，該井經摻雜為具有一摻雜劑之一第一濃度；植入一屏蔽區域，該屏蔽區域具有大於每立方公分5×1018個摻雜劑原子之一摻雜劑濃度；在該井中形成一穿通抑制區域；在該屏蔽區域之上生長一毯覆性磊晶層，此步驟包括以下步驟：藉由摻雜劑之直接植入、自該屏蔽區域擴散或原位沈積中之一或更多方法來摻雜鄰接於該屏蔽區域之該毯覆性磊晶層之一部分，以形成一臨界電壓設定層。
  10. 如申請專利範圍第9項之方法，進一步包含以下步驟：在 於該屏蔽區域之上生長一磊晶毯覆性層之步驟之後，使用淺溝槽隔離來將該場效電晶體隔離。
  11. 如申請專利範圍第9項之方法，其中形成一穿通抑制區域之步驟進一步包含以下步驟：藉由直接植入及/或自該屏蔽區域擴散來摻雜鄰接於該屏蔽區域之層體之一部分。
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US8421162B2 (en) 2013-04-16
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US9508800B2 (en) 2016-11-29
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