CN103981568A - 形成含碳外延硅层的方法 - Google Patents

形成含碳外延硅层的方法 Download PDF

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CN103981568A
CN103981568A CN201410226203.2A CN201410226203A CN103981568A CN 103981568 A CN103981568 A CN 103981568A CN 201410226203 A CN201410226203 A CN 201410226203A CN 103981568 A CN103981568 A CN 103981568A
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carbon
carbon containing
containing silicon
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Y·金
Z·叶
A·佐嘉吉
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Applied Materials Inc
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    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02Epitaxial-layer growth
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
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    • C30B29/06Silicon
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/34Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/4763Deposition of non-insulating, e.g. conductive -, resistive -, layers on insulating layers; After-treatment of these layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type

Abstract

在第一方面中,提供一种在基材上形成外延层叠层的方法。此方法包含:(1)选择所述外延层叠层的目标碳浓度;(2)在所述基材上形成含碳硅层,所述含碳硅层所具有的初始碳浓度、厚度以及沉积时间中的至少之一依据所选择的目标碳浓度进行选择;以及(3)在蚀刻前,在所述含碳硅层上形成非含碳硅层。亦提供多种其它方面。

Description

形成含碳外延硅层的方法
本申请是申请号为“200780028487.2”、申请日为2009年2月1日、题为“形成含碳外延硅层的方法”的专利申请的分案申请。
本申请要求2006年7月31日提交的题为“形成含碳外延硅层的方法”(Method of Forming Carbon-containing Silicon Epitaxial Layers)的美国临时专利申请S/N.60/834/773(律师案号No.10595/L)的优先权,该申请通用地通过引用全部结合于此。
相关申请的交叉引用
本申请涉及以下共同待审的申请,这些申请通过引用全部结合于此:
2004年12月1日提交的美国专利申请S/N.11/001,774(律师案号No.9618);以及
2005年9月14日提交的美国专利申请S/N.11/227,974(律师案号No.9618/P01)。
技术领域
本发明涉及半导体器件制造,更具体地涉及形成含碳外延硅层的方法。
背景技术
随着小型晶体管的生产,超浅源/漏极结的制造变得更具挑战性。一般而言,次100纳米的CMOS器件(互补金属氧化物半导体)要求结深度小于30nm。选择性的外延沉积常用来将含硅材料(例如硅、硅锗或碳化硅)的外延层形成于结中。一般而言,选择性外延沉积允许外延层在硅槽(siliconmoat)而非介电区上生长。选择性外延可用于半导体器件,例如抬高源/漏极、源/漏极延展、接触插塞或双极性器件的基极层沉积。
一般而言,选择性外延工艺牵涉到沉积反应与蚀刻反应。沉积反应与蚀刻反应同时发生,但对于外延层与多晶层则具有不同的反应速率。在沉积过程中,外延层被形成于单晶表面,而多晶层则沉积于至少第二层上,例如现有的多晶层和/或非晶层。然而,所沉积的多晶层通常以比外延层快的速率蚀刻。因此,通过改变蚀刻气体的浓度,净选择工艺导致外延材料沉积,以及多晶材料有限沉积或不沉积。举例而言,选择性外延工艺会导致在单晶硅表面上形成含硅材料的外延层,而于间隙壁上无任何沉积。
在形成抬高源/漏极与源/漏极延展的特征期间,例如在形成含硅MOSFET(金属氧化物半导体场效应晶体管)器件期间,含硅材料的选择性外延沉积已变成有用的技术。源/漏极延展特征通过以下步骤制造:蚀刻硅表面以制造出凹入的源/漏极,随后用选择性成长的外延层(例如硅锗材料)填充经蚀刻表面。选择性外延能以原位掺杂允许近乎完全的掺杂剂活化,进而省略后退火工艺。因此,可通过硅蚀刻与选择性外延准确地定义结深度。另一方面,超浅源/漏结无可避免地会导致串联电阻的增加。此外,在形成硅化物过程中的结消耗会进一步地增大串联电阻。为了弥补结消耗,在结上外延地且选择性地生长抬高的源/漏极。一般而言,抬高的源/漏极层为未掺杂硅。
然而,现有选择性外延工艺具有某些缺点。为了在现今的外延工艺中维持选择性,前体的化学浓度以及反应温度必须在沉积过程中全程控管与调整。若未提供足够的硅前体,蚀刻反应则会占主导,并延滞整个工艺。此外,亦可能产生对基材有害的过度蚀刻。若未提供足够的蚀刻前体,沉积反应则会占主导,从而降低在基材表面形成单晶与多晶材料的选择性。另外,现今选择性外延工艺通常需要高反应温度,例如约800℃、1000℃或更高。但由于热预算的考量,且对基材表面可能有难以控制的氮化反应,在制造工艺中,此高温反应是不利的。另外,部分外延膜和/或工艺易于产生形态缺陷,例如在膜中产生坑洞或表面粗糙。
因此,仍需开发一种用于选择性且外延地沉积硅与含硅化合物的工艺。此外,在快速沉积速率且工艺温度维持于例如约800℃或更低的同时,此工艺应当是通用的,用来形成具有变化元素浓度的含硅化合物。最后,此工艺应产生低缺陷的膜或膜叠层(例如几乎没有坑洞、断层、粗糙、点缺陷等)。
发明内容
在本发明的第一方面中,提供一种在基材上形成外延层叠层的方法。此方法包含:(1)选择所述外延层叠层的目标碳浓度;(2)在所述基材上形成含碳硅层,所述含碳硅层所具有的初始碳浓度、厚度以及沉积时间的至少之一依据所选择的所述目标碳浓度来选择;以及(3)在蚀刻前,在所述含碳硅层上形成非含碳硅层。
在本发明的第二方面中,提供一种用于形成外延层叠层的方法。此方法包含:(1)选择所述外延层叠层的目标碳浓度;(2)通过交替沉积含碳硅层与非含碳硅层,形成所述外延层叠层。依据所述含碳硅层的总厚度、初始碳浓度以及沉积时间的至少之一,达到所述目标碳浓度。
在本发明的第三方面中,提供一种用以控制形成在基材上的外延层叠层中的碳浓度的方法。此方法包含:(1)确定所述外延层叠层的所需碳浓度;(2)通过(a)在所述基材上形成含碳外延层,以及(b)在所述含碳外延层上形成非含碳覆盖层,形成所述外延层叠层。依据所述外延层叠层的所需碳浓度,选择所述含碳外延层的厚度。亦提供多种其它方面。
依据下述的实施方式、权利要求与附图,可使本发明其它特征与方面更为清楚。
附图说明
图1A-1D是绘示依照本发明的在形成外延层叠层过程中的基材的剖面图。
图2是绘示依照本发明形成的贯穿非含碳籽晶外延层、含碳外延层以及非含碳覆盖外延层的叠层的碳浓度的曲线图。
图3是绘示依照本发明的针对籽晶外延层与覆盖外延层的固定沉积时间取代碳浓度(SC)对含碳外延层的沉积时间的相关性的曲线图。
图4是绘示依照本发明的用于形成具有目标碳浓度的外延层叠层的方法的流程图。
具体实施方式
在以介电质膜图案化的硅基材上的选择性外延生长工艺期间,仅于暴露的硅表面上形成(例如而不在介电质表面)单晶半导体。选择性外延生长工艺可包含同时进行的蚀刻-沉积工艺,以及交替供气工艺。在同时进行的蚀刻-沉积工艺中,蚀刻剂与沉积物两者同时流动。据此,在形成外延层的过程中,该外延层同时沉积与蚀刻。
相反地,在所附的美国专利申请案S/N.11/001,774(申请日2004年12月1日,代理人案号9618)中,则描述了用于在基材上形成外延层的交替供气工艺。在AGS工艺中,则是先在基材上进行外延沉积工艺,然后在基材上进行蚀刻工艺。此籽晶外延沉积工艺继以蚀刻工艺的循环则不断重复,直至形成所需的外延层厚度为止。
沉积过程可包含将基材表面暴露在含有至少硅源与载气的沉积气体中。沉积气体亦可包含锗源和/或碳源、以及掺杂剂源。常见的掺杂剂可包含砷、硼、磷、锑、镓、铝以及其它元素。
在沉积过程中,当多晶层形成于副表面(例如非晶和/或多晶表面)上时,外延层形成于基材的单晶表面。接着,将基材暴露在蚀刻气体中。此蚀刻气体包含载气与蚀刻剂。蚀刻气体移除在沉积过程中沉积的含硅材料。在蚀刻过程中,多晶层的移除速率比外延层快。因此,沉积与蚀刻工艺的净结果会在单晶表面上形成外延生长含硅材料,同时最小化副表面上多晶含硅材料的生长(如果有的话)。用来沉积含硅材料的示例包含硅、硅锗、碳化硅、硅锗碳、掺杂剂变体与类似物。
常规的硅外延膜的形成工艺利用氢气、氯化氢与硅源,例如二氯甲硅烷,在基材温度高于约700℃下反应(例如以解离氯化氢和/或硅源)。降低外延膜的形成温度的一种方法采用氯气取代氯化氢(氯化氢),这是由于氯气在较低温度下(例如约600℃或以下)可更有效地解离。由于氢气与氯气不兼容,因此可采用除了氢气以外的载气与氯气一同使用,例如氮气。同样地,亦可使用具有较低解离温度的硅源(例如硅烷(SiH4)、二硅乙烷(Si2H6)等)。
使用氯气作为硅外延膜形成过程的蚀刻气体,可能会导致较差的所得硅外延膜的表面形态。尽管不希望受限于任何特定的理论,但氯气被认为会激烈地侵害硅外延膜表面,从而产生坑洞或类似物。且已发现当硅外延膜含有碳时,使用氯气会造成特定的问题。
本发明是提供用于在硅外延膜形成过程中使用氯气作为蚀刻气体的方法,所述方法可改善外延膜的表面形态。举例而言,本发明方法可与美国专利申请S/N.11/001,774(2004年12月1日提交,代理人案号9618)中所述的交替供气工艺一并使用。
在部分实施例中,在蚀刻相中,在暴露于氯气之前可先将任何含碳硅外延膜封装。举例而言,可通过不用碳源所形成的硅外延膜(即,不含碳硅外延膜)来封装含碳硅外延膜。
作为示例,在下文中将参照图1A-1D描述根据本发明的含碳硅外延层叠层的形成以及所采用的AGS工艺。参照图1A,绘示了基材100的剖面图,其中籽晶外延层102(例如,硅(Si)外延层)形成于基材100上。在部分实施例中,可将籽晶外延层102移除。
为了形成籽晶外延层102,可将基材100置于处理室中,并加热至所需基材和/或工艺温度。虽然亦可使用其它外延膜处理室和/或系统,但示例性的外延膜处理室可由位于美国加州Santa Clara的Applied Materials,Inc.所提供的Episystem与Polysystem获得。在至少一个实施例中,可采用低于约700℃的基材和/或工艺温度,以改善处理室内所形成的硅外延层中的碳含量。在特定实施例中,可使用介于约550-650℃间的基材和/或工艺温度范围,然而,在另一实施例中,可使用低于约600℃的基材和/或工艺温度。亦可使用其它基材和/或工艺温度,包含高于700℃的基材和/或工艺温度。
在达到所需基材和/或工艺温度后,基材100暴露在至少硅源(无碳源)下,以便形成籽晶外延层102。举例而言,基材100可暴露于硅源(例如硅烷或二硅乙烷)以及载气(例如氮气)下。亦可使用掺杂源,例如磷或硼、锗源或类似物(其它任何合适的源和/或气体亦可)。在外延膜形成的过程中,外延层102可形成在基材100的任一单晶表面上,而多晶层可形成在基材100上的任一多晶层和/或非晶层上(如前所述)。
举例而言,可通过流入硅烷流速约50-150sccm的硅源(或流速约10-40sccm的二硅乙烷)形成籽晶外延层102,以及流速约20-25slm的氮气载气(尽管可使用其它较大或较小流速的硅源和/或载气)。可按需流入氯化氢。
在至少一个实施例中,虽然亦可采用其它厚度,籽晶外延层102所具有的厚度可约为举例而言,沉积时间可约为1秒至100秒,而在一个或更多个实施例中,则约采用5秒。
在形成籽晶外延层102之后(若有采用的话),将基材100暴露在至少硅源以及碳源中,以在基材100的籽晶外延层102上形成含碳硅外延层104(图1B)。举例而言,基材100可暴露于硅源(例如硅烷或二硅乙烷),碳源(例如甲烷),以及载气(例如氮气)下。亦可使用掺杂剂源,例如磷或硼、锗源或类似物(其它任何合适的源和/或气体亦可)。在外延膜形成的过程中,可在基材100的任一单晶表面上形成含碳外延层,而在基材100上的任一多晶层和/或非晶层上(如前所述)可形成多晶层。
在至少一个实施例中,甲烷流速约1-5sccm的碳源可与硅烷流速约50-150sccm的硅源(或流速约10-40sccm的二硅乙烷),以及流速约20-25slm的氮气载气一并使用(尽管可使用其它较大或较小流速的硅源和/或载气)。可按需流入氯化氢。
虽然亦可采用其它厚度,含碳外延层104所具有的厚度约为例如,沉积时间可约为1秒至50秒,而在一个或更多个实施例中,则约采用10秒。
在形成含碳外延层104之后,将基材100暴露在至少硅源中(而无碳源),以在基材100上的含碳硅外延层104上形成第二硅外延层106(如图1C中所示的覆盖层)。举例而言,基材100可暴露于硅源(例如硅烷或二硅乙烷),以及载气(例如氮气)中。亦可使用掺杂剂源,例如磷或硼、锗源或类似物(其它任何合适的源和/或气体亦可)。含碳硅外延层104上所覆盖的第二硅外延层106,可减少氯气与含碳硅外延层104中的碳(和/或氢气)之间的作用。可按需如前所述流入氯化氢。
举例而言,第二硅外延层106可通过流入硅烷流速约50-150sccm的硅源形成(或流速约10-40sccm的二硅乙烷),以及流速约20-25slm的氮气载气(尽管可使用其它较大或较小流速的硅源和/或载气)。可按需流入氯化氢。
在至少一个实施例中,虽然亦可使用其它厚度,第二硅外延层106所具有的厚度可约为举例而言,沉积时间可约为1秒至100秒,而在一个或更多个实施例中,则约采用5秒。
据此,可形成外延层叠层108,其中含碳外延层104被封装于非含碳外延层102、106之间(例如不以碳源形成的外延层)。
在形成第二硅外延层106之后,基材100暴露在氯气和/或另一蚀刻剂中,以蚀刻至少第二硅外延层106和/或其它任何形成在基材100上的膜(例如在多晶上所形成的多晶硅,和/或基材100上的非晶层,和/或在含碳硅外延层104上所形成的单晶硅)。举例而言,在至少一个实施例中,基材100被暴露于流速约30-50sccm的氯气,以及流速约20slm的氮气载气中(虽然可使用其它较大或较小流速的氯气和/或载气)。可按需流入氯化氢。
在蚀刻后,可清洁所使用的处理室(例如用氮气和/或另一惰性气体清洁约20秒,或其它合适的时长),以从室中移除氯气和/或其它多余的物质/副产物。
覆盖外延层106和/或籽晶外延层102可防止蚀刻剂与含碳外延层104中的碳发生反应。据此,由于蚀刻时位于下方的含碳层并不会暴露在氯气中,因此可采用氯气作为蚀刻剂。据此,含碳外延层104可具有平坦表面形态,而非坑洞表面形态。
可持续重复沉积与蚀刻的过程,直至达到所需总外延层叠层厚度,如图1D所示。举例而言,可重复非含碳硅层沉积/含碳硅层沉积/非含碳硅层沉积/蚀刻的次序约80次,以使总外延层叠层厚度达到约。在其它实施例中,可省略下方籽晶外延层沉积的步骤,因此所重复的形成次序为含碳硅层沉积/非含碳硅层沉积/蚀刻,以达到所需的总外延层叠层厚度。
尽管上述实施例举出了特定的实施方法,一般而言,外延层叠层(具有含碳外延层与非含碳外延层)的厚度范围约为到约较佳地约从到约为更佳地从约到约在特定一实施例中,可采用约的叠层厚度
通过控制(1)封装的含碳外延层相对于非含碳外延材料的膜厚;及(2)含碳外延层中的碳浓度,可控制和/或确定最后外延层叠层中的平均碳浓度。举例而言,在部分实施例中,尽管只在含碳外延层形成的步骤中进行碳沉积,含碳外延层中的碳会快速且均匀地沿着叠层(例如籽晶层、含碳层、以及覆盖层)的深度扩散。
图2中的曲线200绘示了依据本发明所形成的叠层(例如图1C所示)中贯穿非含碳籽晶外延层、含碳晶层以及非含碳覆盖外延层的碳浓度。如图2所示,由线条202所一般标示的碳浓度,贯穿叠层的深度均匀分布(其中X轴代表叠层的深度,Y代表贯穿叠层的碳分布)。依据本发明的部分实施例,可通过控制含碳层和/或籽晶外延层和/或覆盖层的相对厚度,以及控制含碳层中的初始碳浓度,进而控制叠层中的碳浓度。
在部分实施例中,可从含碳外延层相对于非含碳外延层的厚度,估计最后的碳浓度。举例而言,图3中的曲线300绘示了针对籽晶外延层与覆盖外延层的固定沉积时间(例如图1C所示),取代碳浓度(SC)对含碳外延层的沉积时间的相关性。如图3中的线条302所示,叠层中的碳浓度与含碳外延层的沉积时间成正比。因此,依据本发明的部分实施例,通过控制含碳外延层的沉积时间,可进而控制在籽晶外延层/含碳层/覆盖层叠层或“夹层”中的碳浓度。
在一个或多个实施例中,外延层中的目标碳浓度的范围可为从约200ppm到5原子百分率(at%),较佳地为从约0.5at%到2at%,例如约1.5at%。亦可使用其它目标浓度。在部分实施例中,外延层中(例如图1A-1D中的层104)的碳浓度可呈渐次变化。
含碳硅层中所含的碳一般都位于紧接在含硅层沉积之后的晶格裂缝中。初始碳浓度,即含碳层中所沉积的碳含量可约为10at%或更少,较佳地少于约5at%,更佳地约0.5at%-约3at%,例如2at%。若裂缝碳并未全部进入晶格的取代位置的话,利用退火(如下述)或(后续)工艺步骤中的自然扩散,可使外延层包含至少一部分碳。无论是位于叠层中的裂缝或取代碳,外延层叠层中的总碳浓度包含所有的碳。高分辨率X光衍射(XRD)可用来确定取代碳的浓度与厚度。二次离子质谱仪(SIMS)可用来测定外延叠层中的总碳浓度(取代碳与裂缝碳)。取代碳浓度可小于或等于总碳浓度。合适的退火过程可包含尖峰退火,例如快速热处理系统(RTP),激光退火或用大气气体(例如氧气、氮气、氢气、氩气,氦气或上述的任意组合)进行的热退火处理。在部分实施例中,退火过程在温度约800℃-1200℃下进行,较佳地约为1050℃-约1100℃。可在非含碳覆盖层106沉积后,或在其它各工艺步骤后(例如在整个膜叠层沉积之后),进行此退火过程。
图4的流程图绘示根据本发明的用以形成具有目标碳浓度的外延层叠层的示例性方法400。请参照图4,在步骤401,将基材放入处理室中,并以低于或约为800℃的温度加热。在部分实施例中,在外延膜的形成过程中可采用较低温度范围,例如低于750℃、低于700℃或低于650℃。
在步骤402,含碳外延层形成于基材之上。可依据外延层叠层的目标碳浓度,选择含碳外延层的初始碳浓度、厚度和/或沉积时间。接着,在步骤403,在含碳外延层上形成非含碳外延层。在部分实施例中,非含碳外延层具有足够的厚度,以保护下方的含碳层免于后续蚀刻。
在步骤404,利用蚀刻剂(例如氯化氢和/或氯气)对基材进行蚀刻。如所述地,非含碳外延层可保护下方的含碳外延层,免于被蚀刻气体蚀刻。在蚀刻步骤后,亦可采取清洁步骤(未绘示),以移除处理室中任何蚀刻气体和/或其它多余的气体。
在步骤405,判断是否达到所需的外延层叠层厚度。若达到的话,则步骤406为结束工艺。否则,工艺则再返回到步骤402,以在基材上沉积额外的外延材料。
在另一示例性实施例中,工艺循环可包含(1)非含碳硅(Si)层沉积步骤;(2)含碳硅(Si:C)层沉积步骤;(3)非含碳硅(Si)层沉积步骤;(4)蚀刻步骤;以及(5)清洁步骤。可重复数次工艺循环以达到总外延层叠层厚度。在一个特定实施例中,重复约80次的工艺循环,可获得外延材料约为的外延层叠层。在此实施例中,每次Si或Si:C的沉积可产生约的外延材料,而其中一部分被后续的蚀刻步骤蚀刻(例如约在重复约80次后,剩下的外延材料(例如在硅槽上)则约为(而在基材的介电质区上则几乎没有或没有沉积)。在另一实施例中,可采用约30-100纳米的外延层叠层厚度范围。
在部分实施例中,外延层叠层和/或所沉积的含碳硅层中的取代碳浓度范围约为0.5-2.0at%。当Si:C层夹在硅(Si)层中间时,整体叠层碳浓度则取决于与Si:C层厚度相较的Si层厚度而降低。依据工艺条件,取代碳浓度可小于或等于总碳浓度。
示例的气体流速范围包含:针对二氯硅烷、硅烷、二硅乙烷或其它高级硅烷的硅源,流速约5-500sccm;针对单甲基硅烷的碳源,流速约1-30sccm;针对氢气或氮气的载气,流速约3-30slm。在蚀刻过程中,示例性的氯化氢流速约为20-1000sccm,而氯气流速约为10-500sccm。
在一个特定的实施例中,在每一蚀刻工艺步骤中(除了清洁步骤外),可以约相同的流速(例如以约300sccm流速或另一合适的流速)流入氯化氢,而仅在蚀刻步骤中流入氯气(例如以约30sccm流速或另一合适的流速)。可在每一沉积步骤中,流入二硅乙烷(例如以约7sccm流速或另一合适的流速),可在Si:C沉积步骤中流入甲基硅甲烷(例如以约2.2sccm流速或另一合适的流速)。在每一工艺循环步骤中,可以约20slm流速或另一合适的流速流入氮气载气,并在每一清洁步骤中,增加至约30slm或另一合适的流速。在部分实施例中,在第一硅沉积步骤中(例如沉积约4秒),沉积约的硅,在Si:C硅沉积步骤中(例如沉积约7秒),沉积约的Si:C,在第二硅沉积步骤中(例如沉积约10秒),沉积约的硅,而在蚀刻步骤中(例如蚀刻约13秒),移除约的外延材料。可采用合适的清洁时间(例如约10秒)。在沉积与清洁过程中,工艺温度约600℃而处理室压力约10Torr(托),而在蚀刻过程中,压力约13Torr。如所述地,亦可采用其它工艺条件。
前面的描述仅揭示了本发明的示例性实施例。以上所揭示的落入本发明范围内的装置和方法的变体对本领域普通技术人员是显而易见的。因此,尽管已结合示例性实施例揭示了本发明,但应当理解,其它实施例可落入所附权利要求所限定的本发明的精神和范围内。

Claims (20)

1.一种在基材上形成外延层叠层的方法,包含:
(a)在所述基材上形成含碳硅层;
(b)在蚀刻之前在所述含碳硅层上形成非含碳硅层;
(c)使来自所述含碳硅层的碳分布至所述非含碳硅层;
(d)蚀刻所述外延层叠层以移除所述非含碳硅层的一部分;
(e)重复步骤(a)至(d),直至所述经蚀刻的外延层叠层具有期望的厚度;以及
(f)控制所述含碳硅层的以下一个或多个:(i)初始碳浓度,(ii)厚度,以及(iii)沉积时间,以获得所述经蚀刻的外延层叠层的目标碳浓度。
2.如权利要求1所述的方法,其中所述目标碳浓度是介于约200ppm与5at%之间。
3.如权利要求1所述的方法,其中所述初始碳浓度是介于约0.5at%至10at%之间。
4.如权利要求1所述的方法,更包含于所述含碳硅层与所述基材之间,形成非含碳外延层。
5.如权利要求1所述的方法,其中所述外延层叠层具有厚度介于约之间。
6.如权利要求1所述的方法,其中所述初始碳浓度是大于或等于所述目标碳浓度。
7.如权利要求1所述的方法,其中蚀刻所述外延层叠层包含以含有氯气的蚀刻气体蚀刻所述外延层叠层。
8.如权利要求7所述的方法,其中所述非含碳硅层具有厚度,以避免所述蚀刻气体与所述含碳硅层之间发生反应。
9.如权利要求1所述的方法,其中形成所述含碳硅层与所述非含碳硅层中的至少之一,是在低于或约700℃的温度下进行。
10.一种形成外延层叠层的方法,包含:
选择所述外延层叠层的目标碳浓度;
以沉积交替的含碳硅层与非含碳硅层,形成所述外延层叠层;
使来自各含碳硅层的碳分布至邻近的非含碳硅层;以及
在形成各对交替的含碳硅层和非含碳硅层之后蚀刻所述外延层叠层,以移除所述非含碳硅层的一部分;
其中依据所述含碳硅层的总厚度、初始碳浓度以及沉积时间中的至少之一,达到所述目标碳浓度。
11.如权利要求10所述的方法,其中所述目标碳浓度介于约200ppm与5at%之间。
12.如权利要求10所述的方法,其中每含碳硅层的所述初始碳浓度是介于约0.5at%至10at%之间。
13.如权利要求10所述的方法,更包含于第一含碳硅层与所述基材之间,形成非含碳外延层。
14.如权利要求10所述的方法,其中所述外延层叠层的厚度介于约之间。
15.一种用以控制形成于基材上的外延层叠层中的碳浓度的方法,包含:
确定所述外延层叠层的所需碳浓度;以及
形成所述外延层叠层,通过:
(a)在所述基材上形成含碳外延层;
(b)于所述含碳外延层上形成非含碳覆盖层;
(c)使来自所述含碳硅层的碳分布至所述非含碳覆盖层;
(d)蚀刻以移除所述非含碳覆盖层的一部分;
(e)重复步骤(a)至(d),直至所述经蚀刻的外延层叠层具有期望的厚度;以及
(f)控制所述含碳硅层的以下一个或多个:(i)初始碳浓度,(ii)厚度,以及(iii)沉积时间,以获得所述经蚀刻的外延层叠层的所述所需碳浓度。
16.如权利要求15所述的方法,更包含于所述含碳外延层与所述基材之间,形成一种外延层(seed epitaxial layer)。
17.如权利要求15所述的方法,其中所述目标碳浓度介于约200ppm与5at%之间。
18.如权利要求15所述的方法,其中所述含碳外延层的厚度介于约之间。
19.如权利要求15所述的方法,更包含以氯气蚀刻所述外延层叠层。
20.如权利要求15所述的方法,更包含形成所述外延层叠层的额外的交替的含碳层与非含碳层。
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