CN105070716A - 具有穿通抑制的先进晶体管 - Google Patents

具有穿通抑制的先进晶体管 Download PDF

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CN105070716A
CN105070716A CN201510494596.XA CN201510494596A CN105070716A CN 105070716 A CN105070716 A CN 105070716A CN 201510494596 A CN201510494596 A CN 201510494596A CN 105070716 A CN105070716 A CN 105070716A
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dopant
concentration
depth
transistor
grid
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CN105070716B (zh
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L·希弗伦
P·拉纳德
P·E·格雷戈里
S·R·松库沙莱
W·张
S·E·汤普森
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Triple Fujitsu Semiconductor Co Ltd
Suvolta Inc
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Abstract

本发明提供一种具有穿通抑制的先进晶体管和管芯，所述管芯包括：衬底，衬底为单个半导体材料的单晶；多个场效应晶体管结构，由衬底支撑；其中至少一个晶体管结构具有在栅极下方且在所述源极与漏极之间延伸的多个不同的掺杂区域，注入多个掺杂区域来为所述晶体管结构中的至少一个限定p型或n型材料的掺杂剂分布，掺杂剂分布在距离栅极的第一深度处具有峰掺杂剂浓度并且在距离栅极的第二深度处具有第一中间掺杂剂浓度，第一中间掺杂剂浓度低于峰掺杂剂浓度；多个晶体管结构中的每个包括通常由无掺杂的均厚外延生长形成的沟道区域，沟道区域直接位于在单半导体材料的单晶中形成的阈值电压控制区域之上，阈值电压控制区域与第一中间掺杂剂浓度相关。

Description

具有穿通抑制的先进晶体管
本申请是申请号为201180035830.2、发明名称为“具有穿通抑制的先进晶体管”、申请日为2011年06月21日的发明专利申请的分案申请。
相关申请
本申请要求2009年9月30日提交的美国临时申请No.61/247300的优先权，将该临时申请的公开内容通过引用并入于此。本申请还要求其公开内容通过引用并入于此的2009年11月17日提交的美国临时申请No.61/262122以及其公开内容通过引用并入于此的2010年2月18日提交的、发明名称为“ElectronicDevicesandSystems,andMethodsforMakingandUsingtheSame”的美国专利申请No.12/708497的优先权。本申请还要求其公开内容通过引用并入于此的2010年6月22日提交的美国临时申请No.61/357492的优先权。
技术领域
本公开内容涉及形成具有包括增强的穿通(punchthrough)抑制的改进的工作特性的先进晶体管的结构和工艺。
背景技术
期望将多个晶体管适配到单个管芯，以减小电子设备的成本并改进其功能能力。半导体制造商所采用的常见策略是简单地减小场效应晶体管(FET)的栅极尺寸，并且按比例缩小晶体管源极、漏极以及晶体管之间的所需互连的面积。然而，由于称为“短沟道效应”的效应，所以简单地按比例缩小并不总是可能的。短沟道效应在晶体管栅极下的沟道长度与工作晶体管的耗尽深度的大小可比较时特别严重，短沟道效应包括阈值电压减小、严重的表面散射、漏极感应势垒降低(DIBL)、源极-漏极穿通以及电子迁移率问题。
减轻某些短沟道效应的常规解决方案可以涉及袋状物(pocket)注入或源极和漏极周围的晕环(halo)注入。晕环注入可以关于晶体管的源极和漏极对称或不对称，并且通常在晶体管阱与源极和漏极之间提供平滑的掺杂剂梯度。不幸的是，虽然这样的注入改善了诸如阈值电压滚降(rolloff)和漏极感应势垒降低等某些电气特性，但是所得到的增大的沟道掺杂对电子迁移率产生不利的影响，这主要是因为沟道中的掺杂剂散射增大。
许多半导体制造商都试图通过采用新的晶体管类型(包括全部或部分耗尽的绝缘体上硅(SOI)晶体管)来减小短沟道效应。SOI晶体管构建在绝缘体层之上的薄硅层上，具有使短沟道效应最小化的未掺杂的或低掺杂沟道，并且不需要深阱注入或晕环注入来工作。不幸的是，形成合适的绝缘体层十分昂贵且难以完成。早期的SOI器件构建在绝缘蓝宝石晶片上而非硅晶片上，并且因为成本高，通常仅用于特殊应用(例如军用航空电子设备或卫星)。现代的SOI技术可以使用硅晶片，但需要昂贵且费时的额外的晶片处理步骤来制作延伸跨越器件质量单晶硅的表面层下的整个晶片的绝缘氧化硅层。
在硅晶片上制作这样的氧化硅层的一种常用方法需要高剂量氧离子注入和高温退火，以在体硅晶片中形成埋入氧化物(BOX)层。或者，可以通过将一个硅晶片键合到表面上具有氧化物层的另一硅晶片(“处理”晶片)来制造SOI。使用在处理晶片的BOX层的顶部上留下单晶硅的薄晶体管质量层的工艺来将这对晶片分开。这就是所谓的“层转移”技术，因为该技术将薄硅层转移到处理晶片的热生长氧化物层上。
如所预期的，BOX形成或层转移这两者都是具有相对较高故障率的昂贵制造技术。因此，对于许多领先的制造商而言，制造SOI晶体管不是经济上有吸引力的解决方案。当重新设计晶体管以应对“浮体(floatingbody)”效应、研发新的SOI特定晶体管工艺的需要和其它电路变化的成本被添加到SOI晶片的成本时，很显然需要其它解决方案。
正在研究的另一可能的先进晶体管采用多栅极晶体管，其类似于SOI晶体管，通过在沟道中少量掺杂或不掺杂来使短沟道效应最小化。通常称为finFET(由于由栅极部分地围绕的鳍形状的沟道)，对具有28纳米或更低晶体管栅极尺寸的晶体管提出使用finFET晶体管。但同样，类似于SOI晶体管，虽然换到全新的晶体管架构解决了某些短沟道效应问题，但是又产生了需要比SOI更加显著的晶体管布局重新设计的其它问题。考虑到可能需要复杂的非平面晶体管制造技术来制作finFET以及创建finFET的新工艺流程的未知困难，制造商一直不愿在能制作finFET的半导体制造设施上投资。
发明内容
因此，为了克服现有技术的缺陷，本发明提供一种管芯，包括：衬底，所述衬底为单半导体材料的单晶；多个场效应晶体管结构，由所述衬底支撑，每个场效应晶体管结构具有栅极、源极和漏极；其中至少一个所述晶体管结构具有在所述栅极下方且在所述源极与漏极之间延伸的多个不同的(distinct)掺杂区域，注入所述多个掺杂区域来为至少一个所述晶体管结构限定p型或n型材料的掺杂剂分布，所述掺杂剂分布在距离所述栅极的第一深度处具有峰掺杂剂浓度并且在距离所述栅极的第二深度处具有第一中间掺杂剂浓度，所述第一中间掺杂剂浓度低于所述峰掺杂剂浓度；其中所述多个晶体管结构中的每个包括通常由无掺杂的均厚外延生长形成的沟道区域，所述沟道区域直接位于在单半导体材料的单晶中形成的阈值电压控制区域之上，所述阈值电压控制区域与所述第一中间掺杂剂浓度相关。
根据实施例的另一个方案，本发明提供一种管芯，包括：衬底；多个场效应晶体管结构，由所述衬底支撑，每个场效应晶体管结构具有栅极、源极和漏极；其中至少一个所述晶体管结构具有在所述栅极下方且在所述源极与漏极之间延伸的多个不同的掺杂区域，注入所述多个掺杂区域来为至少一个所述晶体管结构限定p型或n型材料的掺杂剂分布，所述掺杂剂分布在距离所述栅极的第一深度处具有峰掺杂剂浓度并且在距离所述栅极的第二深度处具有第一中间掺杂剂浓度，所述第一中间掺杂剂浓度建立第一凸峰；其中所述多个晶体管结构中的每个包括通常由无掺杂的均厚外延生长形成的沟道。
根据本发明的管芯，可以减小电子设备的成本并改进晶体管的功能。
附图说明
图1示出了具有穿通抑制的DDC晶体管；
图2示出了具有增强的穿通抑制的DDC晶体管的掺杂剂分布；
图3-7示出了替代的有用的掺杂剂分布；以及
图8是示出用于形成具有穿通抑制的DDC晶体管的一个示例性工艺的流程图。
具体实施方式
不同于绝缘体上硅(SOI)的晶体管，纳米级体CMOS晶体管(通常具有小于100纳米的栅极长度)受到短沟道效应的显著不利影响，包括通过漏极感应势垒降低(DIBL)和源极漏极穿通这两者的体泄漏。穿通与源极和漏极耗尽层的合并有关，导致漏极耗尽层延伸穿过掺杂衬底并到达源极耗尽层，在源极与漏极之间产生传导路径或漏电流。这导致所需的晶体管电功率大幅增大，并连同晶体管热输出随之增大，使用这样的晶体管的便携式或电池供电设备的工作寿命降低。
图1中示出了可在体CMOS衬底上制造的改进的晶体管。根据某些所描述的实施例，场效应晶体管(FET)100配置成具有大大减小的短沟道效应以及增强的穿通抑制。FET100包括栅极电极102、源极104、漏极106和定位在沟道110上的栅极电介质108。在工作时，沟道110被深耗尽，与常规晶体管相比，形成可以描述为深耗尽沟道(DDC)的沟道，且部分地通过高度掺杂的屏蔽区域112来设定耗尽深度。虽然沟道110基本上未掺杂，并且如图所示定位在高度掺杂的屏蔽区域112上，但是沟道110可以包括具有不同掺杂剂浓度的简单或复杂分层。这种掺杂的分层可以包括掺杂剂浓度小于屏蔽区域112的阈值电压设定区域111，其可选地定位在沟道110中的栅极电介质108与屏蔽区域112之间。阈值电压设定区域111允许小幅调整FET100的工作阈值电压，同时留下基本上未掺杂的沟道110的体。具体而言，邻近于栅极电介质108的沟道110的部分应当保持不掺杂。此外，穿通抑制区域113形成在屏蔽区域112的下方。类似于阈值电压设定区域111，穿通抑制区域113的掺杂剂浓度小于屏蔽区域112，同时高于轻掺杂阱衬底114的整体掺杂剂浓度。
在工作中，可以将偏置电压122VBS施加到源极104以进一步修改工作阈值电压，并且P+端子126可以在连接部124连接到P阱114以使电路闭合。栅极堆叠包括栅极电极102、栅极接触部118和栅极电介质108。包括栅极间隔部130以使源极和漏极与栅极分离，并且可选的源极/漏极延伸部(SDE)132或“尖端”在栅极间隔部和栅极电介质108下延伸源极和漏极，稍微减小了栅极长度并改进了FET100的电气特性。
在此示例性实施例中，FET100示出为N沟道晶体管，其具有由N型掺杂材料制成的源极和漏极，形成在作为P型掺杂的硅衬底的衬底上，且设置有形成在衬底116上的P阱114。然而，将会理解通过适当改变衬底或掺杂剂材料，可以替代由诸如砷化镓基材料等其它合适的衬底形成的非硅P型半导体晶体管。可以使用常规的掺杂剂注入工艺和材料形成源极104和漏极106，并且源极104和漏极106例如可以包括诸如应力感应的源极/漏极结构、升起和/或凹陷的源极/漏极、不对称掺杂、反掺杂(counter-doped)或晶体结构修改的源极/漏极、或根据LDD(低掺杂漏极)技术的源极/漏极延伸区域的注入掺杂等修改。也可以使用各种其它的技术来修改源极/漏极工作特性，在某些实施例中包括作为补偿掺杂剂的多相(heterogeneous)掺杂剂材料来修改电气特性。
栅极电极102可以由传统材料形成，优选包括但不限于金属、金属合金、金属氮化物、金属硅化物、以及其叠层和其组合物。在某些实施例中，栅极电极102也可以由多晶硅形成，例如包括高掺杂多晶硅和多晶硅锗合金。金属或金属合金可以包括含有铝、钛、钽的那些金属或金属合金、或其氮化物，该氮化物包括含有钛的化合物，诸如氮化钛等。栅极电极102的形成可以包括硅化物法、化学气相沉积法和物理气相沉积法，诸如但不限于蒸镀法和溅射法。通常，栅极电极102的总厚度为从约1至约500纳米。
栅极电介质108可以包括常规电介质材料，诸如氧化物、氮化物和氧氮化物等。或者，栅极电介质108通常可以包括较高介电常数的电介质材料，包括但不限于氧化铪、铪硅酸盐、氧化锆、氧化镧、氧化钛、钡锶钛酸盐和铅锆钛酸盐、金属类电介质材料和其它具有电介质性质的材料。优选的含有铪的氧化物包括HfO2、HfZrOx、HfSiOx、HfTiOx、HfAlOx等。取决于组合物和可用沉积处理设备，栅极电介质108可以由以下方法形成，诸如热或等离子氧化、氮化法、化学气相沉积法(包括原子层沉积法)和物理气相沉积法等。在某些实施例中，可以使用多层或复合层、叠层和电介质材料的组合混合物。例如，栅极电介质层可以由厚度约0.3与1nm之间的SiO2基绝缘体以及厚度约0.5与4nm之间的氧化铪基绝缘体形成。通常，栅极电介质层的总厚度从约0.5至约5纳米。
沟道区域110形成在栅极电介质108下方和高度掺杂的屏蔽区域112上方。沟道区域110还接触源极104和漏极106，并且在源极104和漏极106之间延伸。优选地，沟道区域包括邻近栅极电介质108或其附近的基本上未掺杂的硅，其掺杂剂浓度小于5×1017个掺杂剂原子/cm3。沟道厚度的范围通常可以从5至50纳米。在某些实施例中，沟道区域110由屏蔽区域上外延生长的纯的或基本上纯的硅形成。
如所公开的，阈值电压设定区域111定位在屏蔽区域112上方，并且通常形成为薄掺杂层。适当改变掺杂剂浓度、厚度以及与栅极电介质层和屏蔽区域的分离使得可以可控地略微调节工作FET100的阈值电压。在某些实施例中，阈值电压设定区域111掺杂为具有约1×1018个掺杂剂原子/cm3与约1×1019个掺杂剂原子/cm3之间的浓度。阈值电压设定区域111可以由若干不同工艺形成，包括：1)原位外延掺杂，2)外延生长薄硅层后严格可控的掺杂剂注入，3)外延生长薄硅层后原子从屏蔽区域112的掺杂剂扩散，或4)这些工艺的任何组合(例如，外延生长硅后进行掺杂剂注入和从屏蔽层112的掺杂剂扩散这两者)。
高度掺杂的屏蔽区域112的位置通常设定了工作FET100的耗尽区的深度。有利的是，屏蔽区域112(和相关耗尽深度)设定在从与栅极长度(Lg/1)可比较的深度至栅极长度的大的分数(Lg/5)的深度范围内的深度处。在优选实施例中，代表性范围在Lg/3至Lg/1.5之间。具有Lg/2或更大的器件对于极低的功率操作而言是优选的，而在高电压下工作的数字或模拟器件通常可以形成有在Lg/5与Lg/2之间的屏蔽区域。例如，可以形成具有32纳米的栅极长度的晶体管，以使得屏蔽区域在低于约16纳米(Lg/2)的栅极电介质的深度处具有峰值掺杂剂密度，并且阈值电压设定区域在8纳米(Lg/4)的深度处处于峰值掺杂剂密度。
在某些实施例中，屏蔽区域112掺杂为具有约5×1018个掺杂剂原子/cm3与约1×1020个掺杂剂原子/cm3之间的浓度，明显大于未掺杂沟道的掺杂剂浓度，且至少略微大于可选的阈值电压设定区域111的掺杂剂浓度。如将理解的，可以修改确切的掺杂剂浓度和屏蔽区域深度，以改进FET100的期望工作特性，或考虑可用的晶体管制造工艺和工艺条件。
为了帮助控制泄漏，穿通抑制区域113形成在屏蔽区域112的下方。通常，穿通抑制区域113通过直接注入到轻掺杂阱中而形成，但它还可以通过从屏蔽区域向外扩散、原位生长、或其它已知工艺形成。类似于阈值电压设定区域111，穿通抑制区域113的掺杂剂浓度小于屏蔽区域122，通常设定在约1×1018个掺杂剂原子/cm3与约1×1019个掺杂剂原子/cm3之间。此外，穿通抑制区域113的掺杂剂浓度设定为高于阱衬底的整体掺杂剂浓度。如将理解的，可以修改确切的掺杂剂浓度和深度，以改进FET100的期望工作特性，或考虑可用的晶体管制造工艺和工艺条件。
由于可以容易地适应良好研发且长期使用的平面CMOS工艺技术，所以与SOI或finFET晶体管相比，形成这样的FET100相对较为简单。
总体而言，与常规纳米级器件相比，制造上述结构的结构和方法可以使得FET晶体管同时具有低工作电压和低阈值电压。此外，DDC晶体管可以配置为使得阈值电压可以借助于电压体(voltagebody)偏置发生器而被静态地设定。在某些实施例中，甚至可以动态地控制阈值电压，这使得可以大幅减小晶体管的泄漏电流(通过设定电压偏置以向上调节VT，从而低泄漏、低速工作)，或大幅增大晶体管的泄漏电流(通过向下调节VT，从而高泄漏、高速工作)。最终，提供了制造上述结构的这些结构和方法，以设计具有可以在电路处于工作的同时动态调节的FET器件的集成电路。因此，可以用名义上相同的结构设计集成电路中的晶体管，并可以对其进行控制、调制或编程，使其在响应于不同偏置电压的不同工作电压下工作，或者在响应于不同偏置电压和工作电压的不同工作模式下工作。此外，可以为了电路内的不同应用而在制造后对这些进行配置。
如将理解的，按照物理和功能区域或层，描述了注入的或者存在于半导体的衬底或晶体层中的、用于修改半导体的物理和电气特性的原子的浓度。本领域技术人员可以将这些理解为具有特定浓度平均值的材料的三维体积(mass)。或者，它们可以被理解为具有不同的或空间上变化的浓度的子区域或子层。它们也可以存在为小的掺杂剂原子团、基本上类似的掺杂剂原子的区域等，或其它物理实施例。对基于这些性质的区域的描述并不旨在限制形状、确切位置或取向。它们也并不旨在将这些区域或层限制于所采用的任何特定类型或数量的工艺步骤、任何特定类型或数量的层(例如，组合的或整体的)、半导体沉积、蚀刻技术或生长技术。这些工艺可以包括外延形成的区域或原子层沉积、掺杂注入方法工艺、或特定的纵向或横向掺杂剂分布，其包括线性的、单调增大的、倒退的(retrograde)、或其它合适的空间变化的掺杂剂浓度。为了确保维持期望的掺杂剂浓度，预期了各种掺杂剂抗迁移技术，包括低温处理、碳掺杂、原位掺杂剂沉积，和提前闪蒸(advancedflash)或其它退火技术。所得到的掺杂剂分布可以具有不同掺杂剂浓度的一个或多个区域或层，并且无论工艺如何，通过包括红外光谱、卢瑟福背散射(RBS)、二次离子质谱法(SIMS)或使用不同定性或定量掺杂剂浓度确定方法工艺的其它掺杂剂分析工具的技术，浓度的变化和区域或层如何限定可以是或可以不是可检测的。
为了更好地理解一个可能的晶体管结构，图2示出了在源极与漏极之间的中线处获得的且从栅极电介质朝向阱向下延伸的深耗尽晶体管的掺杂剂分布202。以每立方厘米掺杂剂原子的数量为单位测量浓度，向下的深度测量为栅极长度Lg的比值。测量为比值而非以纳米为单位的绝对深度能够更好的在不同节点(例如，45nm、32nm、22nm、15nm)处制造的晶体管之间跨越比较，其中结点通常按照最小栅极长度来限定。
如图2中所示，邻近于栅极电介质层的沟道210的区域基本上没有掺杂剂，直到差不多Lg/4的深度浓度小于5×1017个掺杂剂原子/cm3。阈值电压设定区域211的掺杂剂浓度增大到约3×1018个掺杂剂原子/cm3，并且浓度增大另一数量级到约3×1019个掺杂剂原子/cm3，以形成设定工作晶体管中的耗尽区的底部的屏蔽区域212。在约Lg/1的深度处具有约1×1019个掺杂剂原子/cm3的掺杂剂浓度的穿通抑制区域213是屏蔽区域与轻掺杂阱214之间的中间值。在没有穿通抑制区域的情况下，例如构造为具有30nm栅极长度和1.0伏工作电压的晶体管预期具有明显更大的泄漏。当注入所公开的穿通抑制213时，减小了穿通泄漏，使晶体管功率效率更高，而且能够更好地容忍晶体管结构中的工艺变化而没有穿通失效。
关于下表1可以更好地看出，表1表示了针对穿通剂量和阈值电压范围的预期性能改善：
表1
Ioff(nA/μm) Idsat(mA/μm) Vt(V)
目标穿通层 2 0.89 0.31
没有穿通层 70 1 0.199
较高剂量穿通 0.9 0.54 0.488
非常深的穿通 15 1 0.237
预期了可替代的掺杂剂分布。如图3中所示，示出了包括针对低掺杂沟道的略微增大的深度的替代掺杂剂分布。与图3的实施例相反，阈值电压设定区域211是主要由从屏蔽区域212向外扩散到外延沉积的硅层中形成的浅凹口(notch)。屏蔽区域212自身设定为具有大于3×1019个掺杂剂原子/cm3的掺杂剂浓度。穿通抑制区域213具有约8×1018个掺杂剂原子/cm3的掺杂剂浓度，这是由从屏蔽区域212的向外扩散和单独的低能量注入的组合提供的。
如图4中所示，示出了包括针对低掺杂沟道的大大增大的深度的替代掺杂剂分布。与图2和3的实施例相反，不存在明显的切口、平面或层来帮助阈值电压设定。屏蔽区域212设定为大于3×1019个掺杂剂原子/cm3，穿通抑制区域213具有类似高但窄限定的(narrowlydefined)约8×1018个掺杂剂原子/cm3的掺杂剂浓度，这是由单独的低能量注入提供的。
图5中示出了掺杂剂分布的另一种变化，其示出了针对包括非常低掺杂沟道210的晶体管结构的晶体管掺杂剂分布205。阈值电压设定区域211通过原位或生长在屏蔽区域上的薄外延层的良好控制的注入掺杂而精确地形成。屏蔽区域212设定为约1×1019个掺杂剂原子/cm3，穿通抑制区域213也具有约8×1018个掺杂剂原子/cm3的窄限定的掺杂剂浓度，这是由单独的低能量注入提供的。阱注入214的浓度逐渐减小到约5×1017个掺杂剂原子/cm3。
如图6中所示，掺杂剂分布206包括邻近于栅极电介质层的低掺杂沟道210和窄限定的阈值电压设置区域211。屏蔽区域212增大到设定为约1×1019个掺杂剂原子/cm3的窄峰，穿通抑制区域213也具有约5×1018个掺杂剂原子/cm3的宽峰掺杂剂浓度，这是由单独的低能量注入提供的。阱注入214的浓度较高，以改善晶体管偏置系数，且具有约8×1017个掺杂剂原子/cm3的浓度。
与图6的窄屏蔽区域峰掺杂剂浓度相反，图7的掺杂剂分布207具有宽峰212。除了窄未掺杂的沟道210以外，晶体管结构还包括良好限定的部分倒退的阈值设定211和明显分离的穿通抑制峰213。阱214的掺杂剂浓度相对较低，小于约5×1017个掺杂剂原子/cm3。
图8是示出一个示例性工艺的示意性工艺流程图300，用于形成具有适合于不同类型的FET结构(包括模拟和数字晶体管这两者)的穿通抑制区域和屏蔽区域的晶体管。这里示出的工艺在其描述中旨在是一般性的和广泛的，以便不模糊本发明的概念，以下阐述更详细的实施例和示例。这些连同其它工艺步骤允许处理和制造包括DDC结构器件以及旧有器件的集成电路，允许覆盖整个范围的具有改进性能和较低功率的模拟和数字器件的设计。
在步骤302中，工艺开始于阱形成，其可以是根据不同实施例和示例的许多不同工艺中的一个。如303中所示，取决于期望的应用和结果，阱形成可以在STI(浅沟槽隔离)形成304之前或之后。硼(B)、铟(I)或其它P型材料可以用于P型注入，砷(As)或磷(P)和其它N型材料可以用于N型注入。对于PMOS阱注入，可以在从10至80keV的范围内注入P+注入，并且在NMOS阱注入时，可以在从0.5至5keV的范围内且在1×1013至8×1013/cm2的浓度范围内注入硼注入B+。可以在10至60keV的范围内且以1×1014至5×1014/cm2的浓度执行锗注入Ge+。为了减小掺杂剂迁移，可以在0.5至5keV的范围内且以1×1013至8×1013/cm2的浓度执行碳注入C+。阱注入可以包括穿通抑制区域、掺杂剂密度高于穿通抑制区域的屏蔽区域以及阈值电压设定区域的顺序注入和/或外延生长和注入(先前所讨论的这些通常由掺杂剂向屏蔽区域上生长的外延层中的注入或扩散形成)。
在某些实施例中，如302A中所示，阱形成302可以包括Ge/B(N)、As(P)的束线注入，随后是外延(EPI)预清洗工艺，最后是非选择性均厚(blanket)EPI沉积。或者，如302B中所示，阱可以使用B(N)、As(P)的等离子注入，随后是EPI预清洗，最后是非选择性(均厚)EPI沉积而形成。或者，如302C中所示，阱形成可以包括B(N)、As(P)的固体源扩散，随后是EPI预清洗，最后是非选择性(均厚)EPI沉积。或者，如302D中所示，阱形成可以包括B(N)、As(P)的固体源扩散，随后是EPI预清洗，最后是非选择性(均厚)EPI沉积。作为又一种选择，阱形成可以简单地包括阱注入，随后是B(N)、P(P)的原位掺杂选择性EPI。本文所描述的实施例允许具有不同阱结构且根据不同参数的、配置在共同衬底上的多个器件中的任一个。
同样可以在阱形成302之前或之后发生的浅沟槽隔离(STI)形成304可以包括在低于900℃的温度下的低温沟槽牺牲氧化物(TSOX)衬垫。栅极堆叠306可以按照多种不同的方法、由不同的材料形成或构建，并且具有不同的功函数。一个选择是多晶(poly)/SiON栅极堆叠306A。另一选择是先栅极(gate-first)工艺306B，其包括SiON/金属/多晶和/或SiON/多晶，随后是高K/金属栅极。另一选择，后栅极(gate-last)工艺306C包括高K/金属栅极堆叠，其中栅极堆叠可以由“先高K后金属栅极”的流程或“后高K后金属栅极”的流程形成。再一选择，306D是包括可调谐范围的功函数的金属栅极，其取决于器件构造，N(NMOS)/P(PMOS)/N(PMOS)/P(NMOS)/中间带隙(Mid-gap)或两者之间的任何地方。在一个示例中，N具有4.05V±200mV的功函数(WF)，P具有5.01V±200mV的WF。
接着，在步骤308中，可以注入源极/漏极尖端，或可选地可以取决于应用而不注入。尖端的尺寸可以根据需要而变化，并且将部分地取决于是否使用栅极间隔部(SPCR)。在一个选择中，在308A中可以没有尖端注入。接着，在可选步骤310和312中，PMOS或NMOSEPI层可以形成在源极和漏极区域中，作为用于创建应变沟道的性能增强部。对于后栅极的栅极堆叠选择而言，在步骤314中，形成后栅极模块。这仅可以针对后栅极工艺314A。
可以预期支持多种晶体管类型的管芯(包括具有和不具有穿通抑制的管芯、具有不同阈值电压的管芯、以及具有和不具有静态或动态偏置的管芯)。片上系统(SOC)、先进的微处理器、射频、存储器和其它具有一个或多个数字和模拟晶体管配置的管芯可以并入到使用本文所描述的方法的器件中。根据本文所讨论的方法和工艺，可以使用体CMOS在硅上生产出具有DDC和/或具有或不具有穿通抑制的晶体管器件和结构的多种组合的系统。在不同实施例中，管芯可以分割成动态偏置结构、静态偏置结构或无偏置结构单独地或以某种组合存在的一个或多个区域。在动态偏置部分中，例如，可动态调节的器件可以与高和低VT器件和可能的DDC逻辑器件一起存在。
虽然已经描述了特定示例性实施例并且在附图中示出了这些实施例，但是应当理解这些实施例仅仅是例示性的，而并非限制广泛的发明，还应当理解由于本领域技术人员可以做出各种其它修改，所以本发明并不限于所示和所述的特定结构和配置。因此，本说明书和附图应被视为说明性的而非限制性的意义。

Claims (20)

1.一种管芯，包括：
衬底，所述衬底为单个半导体材料的单晶；
多个场效应晶体管结构，由所述衬底支撑，每个场效应晶体管结构具有栅极、源极和漏极；
其中至少一个所述晶体管结构具有在所述栅极下方且在所述源极与漏极之间延伸的多个不同的掺杂区域，注入所述多个掺杂区域来为至少一个所述晶体管结构限定p型或n型材料的掺杂剂分布，所述掺杂剂分布在距离所述栅极的第一深度处具有峰掺杂剂浓度并且在距离所述栅极的第二深度处具有第一中间掺杂剂浓度，所述第一中间掺杂剂浓度低于所述峰掺杂剂浓度；
其中所述多个晶体管结构中的每个包括通常由无掺杂的均厚外延生长形成的沟道区域，所述沟道区域直接位于在单半导体材料的单晶中形成的阈值电压控制区域之上，所述阈值电压控制区域与所述第一中间掺杂剂浓度相关。
2.根据权利要求1所述的管芯，其中所述掺杂剂分布包括在距离所述栅极第三深度处的第二中间掺杂剂浓度，所述第二中间掺杂剂浓度高于所述第一中间掺杂剂浓度。
3.根据权利要求1所述的管芯，其中当电压被施加至所述栅极时，在所述第一深处的所述峰掺杂剂浓度为至少一个所述晶体管结构设置耗尽深度。
4.根据权利要求1所述的管芯，还包括：
偏置结构，被耦合至至少一个所述晶体管结构的源极，所述偏置结构能被操作以修改至少一个所述晶体管结构的工作阈值电压。
5.根据权利要求4所述的管芯，还包括：
固定电压源，被耦合至所述偏置结构以静态地设置至少一个所述晶体管结构的阈值电压。
6.根据权利要求4所述的管芯，还包括：
可变电压源，被耦合至所述偏置结构以动态地调整至少一个所述晶体管结构的阈值电压。
7.根据权利要求4所述的管芯，其中所述多个晶体管结构被分为不同的偏置部分，第一偏置部分不提供阈值电压调整，第二偏置部分能被操作以提供静态阈值电压调整，并且第三偏置部分能被操作以提供动态阈值电压调整。
8.根据权利要求7所述的管芯，其中所述不同的偏置部分具有带有调整或不带任何调整的不同的阈值电压。
9.根据权利要求1所述的管芯，其中所述第一深度在所述栅极以下比所述第二深度更深。
10.根据权利要求1所述的管芯，其中所述第一深度的范围在所述栅极的长度的一半到五分之一之间。
11.根据权利要求1所述的管芯，其中所述多个掺杂区域形成在所述衬底中。
12.根据权利要求1所述的管芯，其中所述多个掺杂区域形成在所述衬底上。
13.根据权利要求1所述的管芯，还包括：
源极和漏极延伸部，延伸至至少一个所述晶体管结构的所述沟道中。
14.根据权利要求1所述的管芯，其中所述多个掺杂区域与所述源极和所述漏极接触。
15.根据权利要求1所述的管芯，其中所述掺杂剂分布在所述第一深度与所述第二深度之间的第一点处具有第一掺杂剂浓度，所述第一掺杂剂浓度小于或等于所述第一中间掺杂剂浓度，以在所述掺杂剂分布中建立第一凹口。
16.根据权利要求2所述的管芯，其中所述掺杂剂分布在所述第一深度与所述第三深度之间的第二点处具有第二掺杂剂浓度，所述第二掺杂剂浓度小于或等于所述第二中间掺杂剂浓度，以在所述掺杂剂分布中建立第二凹口。
17.根据权利要求2所述的管芯，其中所述第二中间掺杂剂浓度与至少一个所述晶体管结构的穿通区域的抑制相关。
18.根据权利要求2所述的管芯，其中所述第三深度在所述栅极以下比所述第一深度更深。
19.一种管芯，包括：
衬底；
多个场效应晶体管结构，由所述衬底支撑，每个场效应晶体管结构具有栅极、源极和漏极；
其中至少一个所述晶体管结构具有在所述栅极下方且在所述源极与漏极之间延伸的多个不同的掺杂区域，注入所述多个掺杂区域来为至少一个所述晶体管结构限定p型或n型材料的掺杂剂分布，所述掺杂剂分布在距离所述栅极的第一深度处具有峰掺杂剂浓度并且在距离所述栅极的第二深度处具有第一中间掺杂剂浓度，所述第一中间掺杂剂浓度建立第一凸峰；
其中所述多个晶体管结构中的每个包括通常由无掺杂的均厚外延生长形成的沟道。
20.根据权利要求19所述的管芯，其中所述掺杂剂分布包括在距离所述栅极第三深度处的第二中间掺杂剂浓度，所述第二中间掺杂剂浓度建立第二凸峰。
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