TWI269358B - A bulk non-planar transistor having strained enhanced mobility and methods of fabrication - Google Patents

A bulk non-planar transistor having strained enhanced mobility and methods of fabrication Download PDF

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TWI269358B
TWI269358B TW094110070A TW94110070A TWI269358B TW I269358 B TWI269358 B TW I269358B TW 094110070 A TW094110070 A TW 094110070A TW 94110070 A TW94110070 A TW 94110070A TW I269358 B TWI269358 B TW I269358B
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semiconductor
cap layer
substrate
semiconductor body
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TW200535979A (en
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Nick Lindert
Stephen Cea
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Intel Corp
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
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Description

1269358 (1) 九、發明說明 【發明所屬之技術領域】 本發明係有關積體電路製造之領域，而更明確地係有 關一種應變增進遷移率整塊非平面電晶體之形成及其製造 方法。 【先前技術】 現代積體電路，諸如微處理器，係由耦合在一起的實 質上數億個電晶體所組成。爲了增進積體電路之性能及功 率，已提議了新的電晶體結構。一種非平面電晶體（諸如 三閘極電晶體）已被提議以增進裝置性能。一三閘極電晶 體100被顯示於圖1A及1B中。圖1A係三閘極電晶體 100之一上方/側視圖的圖示而圖1B係穿越三閘極電晶體 1 〇〇之閘極電極所取之一橫斷面視圖的圖示。三閘極電晶 體 1 00包含一矽本體 1 02，其具有一對橫向相對的側壁 103及一頂部表面104。矽本體102被形成於一包含氧化 物層1 06之絕緣基底上，其接著被形成於一單晶矽基底 1 0 8上。一閘極介電質1 1 〇被形成於矽本體1 02之頂部表 面104及側壁103上。一閘極電極120被形成於閘極介電 層1 10並圍繞矽本體102。一對源極/汲極區130被形成於 矽本體1 02中，沿著閘極電極1 20之橫向相對的側壁。電 晶體1 3 0可被稱爲一三閘極電晶體，因爲其基本上具有三 個基本上形成三個電晶體之閘極（Gl5G2，G3 )。三閘極電 晶體1 00具有一第一閘極/電晶體於於矽本體1 〇2之一側 -4- (2) 1269358 103上、一第二閘極/電晶體於矽本體102之一頂部表面 104上以及一第三閘極/電晶體於矽本體102之第二側103 上。各電晶體提供其正比於矽本體1 02之側邊的電流。三 閘極電晶體因爲其具有增進裝置性能之每區域的大電流而 爲引人注目的。 【發明內容及實施方式】 B 本發明之實施例爲具有應變增進遷移率之整塊非平面 電晶體及其製造方法。於下列描述中，已描述許多特定細 ' 節以提供本發明之一透徹瞭解。於其他例子中，眾所周知 的半導體處理及製造技術未被詳細地提供，以免不必要地 模糊了本發明。 本發明之實施例爲具有應變增進遷移率之整塊非平面 電晶體及其製造方法。本發明之實施例包含一半導體本 體，其係於應變下設置一形成在半導體本體上或其周圍之 # 蓋層。應變下之一蓋層增加了裝置中之載子的遷移率，其 增加裝置之電流，其可被使用以增進電路速度。 具有應變增進遷移率之一整塊非平面或三閘極電晶體 2 0 0的範例被顯示於圖2。電晶體2 0 0被形成於一整塊半 導體基底2 0 2上。於本發明之一實施例中，基底2 0 2係一 單晶矽基底。於半導體基底202中形成一對分開的絕緣區 2〇4 ’諸如淺溝槽絕緣（STI)區，其界定其間的基底主動 區206。然而，基底202無須爲一單晶矽基底而可爲其他 型式的基底，諸如但不限定於鍺（Ge )、矽鍺 -5- (3) 1269358 (SixGey)、石申化鎵（GaAs) 、InSb、GaP、及 GaSb。主 動區206通常被摻雜至一 n型裝置之介於lxl 〇16至 lxl〇19原子/公分3的Ρ型導電率位準，及被摻雜至一 Ρ 型裝置之介於lxl〇16至lxl〇19原子/公分3的η型導電率 位準。於本發明之其他實施例中，主動區2 0 6可爲一未摻 雜的半導體，諸如本質或未摻雜的單晶矽基底。 電晶體200具有一形成在整塊基底202之主動基底區 Β 206上的半導體本體208。半導體本體208具有一頂部表 _ 面209及一對橫向相對的側壁21 1。頂部表面209係以一 ' 段距離分離自其形成在半導體基底206上之底部表面，此 距離係界定本體高度。半導體本體208之橫向相對的側壁 211係分離以一段界定本體寬度之距離。半導體本體208 係一單晶或單一結晶半導體膜。於本發明之一實施例中， 半導體本體208係形成自一不同於用來形成整塊基底202 之半導體的半導體材料。於本發明之一實施例中，半導體 • 本體208係形成自一種具有不同於整塊半導體基底202之 晶格常數或尺寸的單一結晶半導體，以致其半導體本體 20 8被置於應變之下。於本發明之一實施例中，整塊半導 體基底係一單晶矽基底而半導體本體208係單一結晶矽鍺 合金。於本發明之一實施例中，矽鍺合金包含5-40%的 鍺及理想地約15-25%的鍺。 於本發明之一實施例中，整塊半導體基底202係一單 晶矽基底而半導體本體20 8係一矽碳合金。 於本發明之一實施例中，半導體本體208被形成至某 -6 - (4) 1269358 一厚度，此厚度係小於其半導體本體2〇8之外表面 成晶格鬆驰的量。於本發明之一實施例中，半導 208被形成至100-2000埃的厚度，而更明確地】 1 0 〇 〇埃的厚度。於本發明之一實施例中，半導體本 之厚度及高度係約略相同的。 於本發明之一實施例中，半導體本體2 0 8之寬 於半導體本體208高度的一半至半導體本體2〇8高 • 倍。於本發明之一實施例中，半導體本體2 0 8被摻 具有介於lxlO10至lxlO19原子/公分3之濃度的p ' 率（對於一 η型半導體裝置）及被摻雜至一具 lxlO16至lxlO19原子/公分3之濃度的η型導電率 一 ρ型半導體裝置）。於本發明之一實施例中，半 體2 0 8係本質半導體’諸如未摻雜的或本質的矽膜 電晶體200包含一半導體蓋層210，其係形成 體本體208之側壁211上以及半導體本體208之頂 • 209上。半導體蓋層210係單一結晶半導體膜。於 之一實施例中，半導體蓋層210係形成自一種具有 半導體本體2 0 8之晶格常數的半導體材料，以致其 被形成於蓋層中。於本發明之一實施例中，蓋層具 應變。拉伸應變被視爲會增進電子之遷移率。於本 一實施例中，蓋層具有壓縮應變。壓縮應變被視爲 電洞遷移率。於本發明之一實施例中，電流係流動 直於半導體蓋層2 1 0中之應變的方向。於本發明之 例中，半導體本體208之側壁211上的半導體蓋層 所將造 體本體 g 200-體208 度係介 度的兩 雜至一 型導電 有介於 (對於 導體本 〇 於半導 部表面 本發明 不同於 一應變 有拉伸 發明之 會增進 以一垂 一實施 2 1 0中 (5) 1269358 之應變係大於半導體本體208之頂部表面209 蓋層210中之應變。 於本發明之一實施例中，半導體蓋層2 1 0 矽膜。於本發明之一實施例中，半導體蓋層2 在矽鍺合金本體20 8上之單一結晶矽膜。一形 金本體2 0 8上之單一結晶砂膜將造成單一結晶 伸應變。於本發明之一實施例中，蓋層2 1 0係 碳合金半導體本體208上之單一結晶矽膜。一 合金半導體本體208上之單一結晶矽蓋層210 結晶矽膜2 1 0具有壓縮應變。
於本發明之一實施例中，半導體蓋層2 1 0 小於其使得單一結晶膜之晶格所將鬆弛之量的 發明之一實施例中，半導體蓋層2 1 0被形成至 之厚度。於本發明之一實施例中，半導體本體 211上的蓋層之厚度係相同於半導體本體208 209上的蓋層210之厚度，如圖2中所示。於 實施例中，半導體蓋層210在半導體本體208 上被形成爲較側壁2 1 1上更厚，諸如圖4C中戶J 電晶體200包含一閛極介電層212。聞極 被形成於其形成在半導體本體208之側壁21 210上，且被形成於其形成在半導體本體208 209上的半導體蓋層210上。閘極介電層212 所周知的閘極介電層。於本發明之一實施例中 層係二氧化矽（S i Ο 2 )、氧氮化矽（S i 0 XN y ) 上的半導體 係單一結晶 1 〇係一形成 成在矽鍺合 矽膜具有拉 一形成在石夕 形成在矽碳 將造成單一 被形成至一 厚度。於本 500-300 埃 208之側壁 之頂部表面 本發明之一 之頂部表面 ί1示。 介電層212 1上的蓋層 之頂部表面 可爲任何眾 ，閘極介電 、或氮化矽 (6) 1269358 (Si3N4 )介電層。於本發明之一實施例中，閘極介電層 2 1 2係一形成至厚度5 - 2 0埃的氧氮化矽膜。於本發明之 一實施例中，閘極介電層21 2係一高K閘極介電層，例 如一金屬氧化物介電質，諸如但不限定於氧化鉅 (Ta05 )、氧化鈦（Ti02 )、氧化給（HfO )及氧化鉻 (ZrO )。然而，閘極介電層212亦可爲其他型式的高K 介電質，諸如但不限定於PZT及BST。 B 電晶體2 0 0包含一閘極電極2 1 4。閘極電極2 1 4被形 ~ 成於閘極介電層2 1 2之上或其周圍，如圖2中所示。閘極 ， 電極2 1 4被形成於且鄰近於閘極介電層2 1 2 (其係形成於 其形成在半導體本體208之側壁21 1上的蓋層210上） 上；及被形成於閘極介電層2 1 2 (其係形成於其形成在半 導體本體208之頂部表面209上的蓋層210上）上；及被 形成於或鄰近於閘極介電層2 1 2 (其係形成於其形成在半 導體本體208之側壁21 1上的蓋層210上）上，如圖2中 φ 所示。閘極電極2 1 4具有一對橫向相對的側壁2 1 6，其係 分離以一界定電晶體200之閘極長度（Lg )的距離。於本 發明之一實施例中，閘極電極2 1 4之橫向相對側壁2 1 6具 有一垂直於半導體本體208之橫向相對側壁2 1 1的方向。 閘極電極2 1 4可由任何適當的閘極電極材料所形成。於本 發明之一實施例中，閘極電極2 1 4包含多晶矽膜，其被摻 雜至lxl 019至lxl 02G原子/公分3的濃度密度。閘極電極 2 1 4可被摻雜至n型導電率（對於η型裝置）以及p型導 電率（對於ρ型裝置）。於本發明之一實施例中，閘極電 -9 - (7) 1269358 極可爲一金屬閘極電極。於本發明之一實施例中，閘極電 極2 1 4係由一金屬膜所形成，此金屬膜具有一被修改以用 於η型裝置之工作函數，諸如一介於3.9 eV至4.2 eV之 工作函數。於本發明之一實施例中，閘極電極2丨4係由一 金屬膜所形成，此金屬膜具有一被修改以用於p型裝置之 工作函數，諸如一介於4.9 eV至5.2 eV之工作函數。於 本發明之一實施例中，閘極電極2 1 4被形成自一種具有 φ 4 · 6至4 · 8 eV之中間間隙工作函數的材料。中間間隙工作 函數極適用於當半導體本體208及蓋層210爲本質半導體 • 膜時。應理解其閘極電極2 1 4無需爲單一材料而可爲薄膜 之複合堆疊，諸如但不限定於多晶矽/金屬電極或金屬多 晶矽電極。 電晶體200具有一對源極/汲極區，其係形成於半導 體本體208中以及蓋層中，在閘極電極214之一橫向相對 側壁2 1 6的相對側上，如圖2中所示。源極/汲極區2 1 8 • 被摻雜至一 η型導電率（當形成一 η型裝置時）及被摻雜 至一 Ρ型導電率（當形成一 ρ型裝置時）。於本發明之一 實施例中，源極/汲極區具有介於lxl 〇19至lxl 021原子/ 公分3的摻雜濃度。源極/汲極區2 1 8可由均勻的濃度所 形成或者可包含不同濃度或摻雜輪廓之次區，諸如尖端區 (例如，源極/汲極延伸）。於本發明之一實施例中，當 電晶體200爲對稱電晶體時，源極及汲極區將具有相同的 摻雜濃度輪廓。於本發明之一實施例中，電晶體200爲一 非對稱電晶體，源極區及汲極區可改變以獲得特定的電特 -10- (8) 1269358 性。 位於源極/汲極區2 1 6間以及閘極電極2 1 4底下之半 導體本體208及蓋層210的部分係界定電晶體之一通道 區。通道區亦可被界定爲其由閘極電極2 1 4所圍繞之半導 體本體208及蓋層210的區域。源極/汲極區通常係透過 (例如）擴散而稍微地延伸於閘極電極底下，以界定通道 區爲稍小於閘極電極長度（Lg )。當電晶體3 00被”開” • 時，一反相層被形成於其形成一導電通道之裝置的通道區 中，此導電通道致能電流行進於源極/汲極區3 40之間。 ' 反相層或導電通道係形成於半導體本體20 8之側壁21 1上 的蓋層之表面中以及於半導體本體208之頂部表面209的 盖層210之表面中。 藉由提供一閘極介電層212及一閘極電極214 (其圍 繞半導體本體2 0 8及蓋層2 1 0 )於三側上，則非平面電晶 體之特徵爲具有三個通道及三個閘極；其一閘極（G 1 ) • 係延伸於半導體本體20 8之一側21 1上的源極/汲極區之 間、其第二閘極（G2 )係延伸於半導體本體20 8之頂部 表面209上的源極/汲極區之間、其第三閘極（G3 )係延 伸於半導體本體208之側21 1上的源極/汲極區之間。電 晶體2 0 0之閘極”寬度’’（G w )係三個通道區之寬度的總 和。亦即，電晶體200之閘極寬度係等於半導體本體208 之高度加上側壁2 1 1之頂部表面上的蓋層之厚度、加上半 導體本體208之寬度加上半導體本體之每一側211上的蓋 層之厚度加上半導體本體2 0 8之高度加上半導體本體20 8 -11 - 1269358 Ο) 之頂部表面209上的蓋層210之厚度。較大”寬f 體可被獲得，藉由使用其由單一閘極電極所圍繞 導體本體208及蓋層，諸如圖31中所示者。 雖然圖2係顯示一三閘極電晶體200，但本 可應用於其他的非平面電晶體。例如，本發明可 種”鰭式場效電晶體finfet”，或雙閘極電晶體， 兩個閘極被形成於半導體本體之相對側上。此外 • 可應用於’’omega”閘極或圍繞閘極裝置，其中閘 圍繞半導體本體以及位於半導體本體之一部分）| " 式場效電晶體 finfet"裝置及"omega"裝置之性 進，藉由包含一形成在半導體本體 208上之 2 1 〇，而藉此提升裝置中之載子的遷移率。應理 平面裝置係一種裝置’其（當被”開’’時）營幕一 或者導電通道之一部分於一垂直與基底202之 向。一非平面電晶體亦可被稱爲一種裝置，其中 Φ 區被形成於水平及垂直方向。 圖3 A - 3 I顯示一種形成一具有應變增進遷移 非平面電晶體的方法，依據本發明之一實施例。 供一半導體基底300，如圖3A中所示。於本發 施例中’半導體基底3 00係一單晶矽基底。基底 爲一矽基底而可爲其他型式的基底，諸如矽鍺基 底、砂鍺合金、砷化鎵、I n S b、及G a P。於本發 施例中’半導體基底3 0 0係一本質（亦即，未摻 底。於本發明之其他實施例中，半導體基底3〇〇 I ”的電晶 之多重半 發明同樣 應用於一 或者僅有 ，本發明 極電極係 3下。’’鰭 能可被增 應變蓋層 角军其一非 導電通道 •平面的方 導電通道 率之整塊 首先，提 明之一實 3 00無須 底、鍺基 明之一實 雜）矽基 被摻雜至 -12- 1269358 (ίο) 一具有介於1 X 1 〇16至1 X 1 〇 Η原子/公分3之濃度的p型或 η型導電率。接下來，一具有遮罩部3 02以供形成絕緣區 之遮罩被形成於基底3 00上，如圖Α中所示。於本發明 之一實施例中，遮罩係一抗氧化遮罩。於本發明之一實施 例中，遮罩部3 02包含一薄墊氧化物層304及一較厚的氮 化矽或抗氧化層306。遮罩部302界定基底300中之主動 區3 0 8，其中電晶體本體將形成於此。遮罩部3 0 2可藉由 • 全體沈積一墊氧化物層及接著一氮化矽層於基底3 00上而 被形成。接下來，使用眾所周知的光微影技術以遮蔽、曝 " 光、及顯影一光阻遮蔽層於其中將形成遮罩部3 0 2之位置 上。氮化物膜3 06及墊氧化物層3 04接著對齊與所形成之 光阻遮罩而被鈾刻，以形成遮罩部3 02，如圖3 Α中所 示。 於本發明之一實施例中，遮罩部3 02具有一寬度，其 爲最小寬度或最小特徵尺寸（亦即，關鍵尺寸（CD))，其 # 可使用光微影而被界定於電晶體之製造中。此外，於本發 明之一實施例中，遮罩部3 02被分離以一距離D 1，其爲 製造過程中可使用光微影術來界定之最小距離。亦即，遮 罩部302具有最小尺寸且被分開以一最小尺寸（亦即，關 鍵尺寸），其可利用電晶體製造所使用之光微影製程而被 可靠地達成。以此方式，遮罩部302被界定而具有其以電 晶體製造所使用之光微影製程所能夠達成的最小尺寸及最 大密度。 於本發明之一實施例中，遮罩部3 0 2具有一厚度 -13- (11) (11)
1269358 (T1)，其係等於或大於後續所形成之半導體本體 的厚度或高度。 接下來，如圖3Β中所示，半導體300之曝光 齊與遮罩部3 02之外部邊緣而被蝕刻以形成溝 3 1 0。溝槽開口被蝕刻至一足以將相鄰電晶體彼此 深度。 接下來，如圖3 C中所示，溝槽被塡充以一价 3 12來形成淺溝槽絕緣（STI)區312於基底300 4 本發明之一實施例中，介電層係藉由首先生長一薄纪 氧化物於溝槽3 1 0之側壁底部中而被形成。接下來， 3 1 2係藉著全體沈積一氧化物介電層於襯墊氧化物之 被塡充，藉由（例如）一種高密度電漿（H D Ρ )化學 沈積製程。塡充介電層亦將形成於遮罩部3 02之頂音丨 塡充介電層可接著被移除自遮罩部302之頂部，藉注 如）化學機械硏磨。化學機械硏磨製程被持續直到逛 302之頂部表面被暴露，且溝槽絕緣區312實質上岁 遮罩部3 0 2之頂部表面，如圖3 C中所示。 雖然淺溝槽絕緣區被理想地使用於本發明，但/力 用其他眾所周知的絕緣區及技術，諸如矽之局部 (LOCOS )或凹陷的 LOCOS。 接下來，如圖3D中所示，遮罩部3 02被移除 3〇〇以形成半導體本體開口 314。首先，一氮化矽 係利用一蝕刻劑而被移除，此蝕刻劑蝕刻掉抗氧化 化矽部3 0 6而不顯著地蝕刻絕緣區3〗2。在移除氮 希望 係對 開口 離之 電層 〇於 襯墊 溝槽 上而 氣相 上。 (例 罩部 面與 可使 氧化 基底 306 或氮 矽部 -14- (12) 1269358 3 06之後，墊氧化物部3 04被移除。墊氧化物部304可使 用（例如）一包含氫氟酸（HF )之濕式蝕刻劑而被移 除。遮罩部3 02之移除形成了 一具有實質上垂直之側壁的 半導體本體開口或溝槽314°垂直側壁致能半導體本體生 長於溝槽內且侷限於其中’以致能半導體本體被形成以幾 乎垂直的側壁。 接下來，如圖3 E中所示，一半導體本體膜3 1 6被形 ϋ 成於開口 3 1 4中，如圖3 E中所示。於本發明之一實施例 ^ 中，半導體本體膜3 1 6係一磊晶半導體膜。於本發明之一 ' 實施例中，當需要一應變增進半導體裝置時，半導體膜係 形成自單一結晶半導體膜，其具有與底下半導體基底不同 的晶格常數或不同的晶格尺寸，以致其半導體膜係於應變 之下。於本發明之一實施例中，單一結晶矽膜3 1 6具有較 底下半導體基底3 00更大的晶格常數或晶格尺寸。於本發 明之一實施例中，單一結晶矽膜3 1 6具有較底下半導體基 • 底3 00更大的晶格尺寸或常數。 於本發明之一實施例中，半導體膜3 1 6係一選擇性地 生長於一*單晶砂基底300上之嘉晶砂錯合金膜。砂錯合金 可利用一包含二氯矽烷（DCS ) 、Η2、鍺烷（GeH4 )、及 HC1之沈積氣體而被選擇性地生長於一磊晶反應器中。於 本發明之一實施例中，矽鍺合金包含 5 -40 %的鍺且理想 的是15-25%的鍺。於本發明之一實施例中，磊晶半導體 膜3 16係一形成於矽基底30〇上之單一結晶矽碳合金。單 一結晶半導體膜3 1 6被沈積至半導體本體之理想的厚度。 -15- (13) 1269358 於本發明之一實施例中，其被生長或沈積至小 3 1 2頂部表面之高度的厚度。以此方式，絕緣區 半導體膜3 1 6侷限於溝槽內以致其一具有幾乎垂 的半導體膜被形成。另一方面，半導體膜3 1 6可 積於基底3 00上（包含於溝槽314內以及於絕緣 頂部上）且接著被硏磨回以致其半導體膜3 1 6被 緣區之頂部且僅留存於溝槽3 1 4內，如圖3 E中戶 ® 於本發明之一實施例中，半導體膜3 1 6係一 本質的半導體膜。於本發明之一實施例中，當製 ' 裝置時，半導體膜3 1 6被摻雜至一具有介於 lxl〇19原子/公分3之濃度的η型導電率。於本 實施例中，當製造一 η型裝置時，半導體膜316 一具有介於lxlO16至lxl〇19原子/公分3之濃度 電率。半導體膜3 1 6可被摻雜於一 ”當地”製程中 間，藉由包含一摻雜氣體於沈積製程氣體混合中 # 面，半導體膜316可藉由（例如）離子植入或熱 後續地摻雜，以形成一摻雜的半導體膜3 1 6。 接下來，絕緣區3 1 2被蝕刻回或凹陷以曝光 3 16之側壁320並藉此形成半導體本體318，如Ϊ 示。半導體本體318具有幾乎垂直的側壁320, 體膜3 1 6係由絕緣區3 1 2所橫向地侷限於沈積期 區3 1 2係利用一蝕刻劑而被鈾刻回，此蝕刻劑不 蝕刻半導體膜3 1 6。當半導體膜3 1 6爲矽或矽合 緣區3 1 2可使用一包含HF之濕式蝕刻劑而被凹 於絕緣區 3 1 2係將 直之側壁 被全體沈 區312之 移除自絕 〒示。 未摻雜或 造一 P型 lxlO16 至 發明之一 被摻雜至 的P型導 之沈積期 〇另一方 擴散而被 半導體膜 S 3 F中所 因爲半導 間。絕緣 會顯著地 金時，絕 陷。於本 -16- (14) 1269358 發明之一實施例中，絕緣區被飽刻回至一 質上與半導體基底300中所形成之主動區 呈一平面的，如圖3 F中所示。 接下來’如圖3G中所示，一半導體 於半導體本體3 1 8之頂部表面3 1 9及側壁 蓋層3 22係單一結晶半導體膜。於本發明 半導體蓋層322係由一種具有與半導體本 φ 格常數或尺寸的材料所形成。於本發明之 導體蓋層322係單一結晶矽膜。於本發明 ^ 半導體蓋層322係一形成於矽鍺合金本體 晶矽膜。於本發明之一實施例中，半導體 成於矽碳合金半導體本體3 1 8上之單一結 晶矽蓋層3 2 2可利用一種包含D C S、H C 1 體而被選擇性地沈積於一磊晶沈積反應器 一實施例中，半導體蓋層3 22被形成至一 Φ 導體蓋層3 22中之實質上鬆弛之量的厚度 實施例中，半導體蓋層3 22被形成至一足 層被形成於蓋層中（當電晶體被”開”時） 明之一實施例中，半導體蓋層3 22被形成 厚度。於本發明之一實施例中，半導體蓋 雜或本質的半導體膜。於本發明之一實施 層322被摻雜至一介於lxl〇16至ΙχΙΟ19 型導電率（當形成一 P型裝置時），以及 lxlO16至1χ10ΐ9原子/公分3之p型導電 位準以致其係實 3 0 8的頂部表面 蓋層3 2 2被形成 3 20上。半導體 之一實施例中， 體3 1 8不同之晶 一實施例中，半 之一實施例中， 3 1 8上之單一結 蓋層3 22係一形 晶矽膜。單一結 及H2之製程氣 中。於本發明之 小於其將造成半 。於本發明之一 以致能整個反相 之厚度。於本發 :至5 0 - 3 0 〇埃的 層3 2 2係一未摻 例中’半導體蓋 原子/公分3之n 被摻雜至一介於 率（畠形成一 n -17- (15) 1269358 型裝置時）。於本發明之一實施例中，半導體蓋層3 2 2被 摻雜於一當地沈積製程中。另一方面，蓋層3 22可藉由其 他眾所周知的技術而被摻雜’諸如藉由離子植入或固體源 極擴散。 接下來，如圖3H中所示，一閘極介電膜324被形成 於蓋層322 (其被形成於半導體本體318之側壁320上） 上及被形成於蓋層3 22 (其被形成於半導體本體318之頂 B 部表面319上）上，圖3H中所示。閘極介電層324係一 生長的閘極介電層，諸如但不限定於二氧化矽層、氧氮化 ' 矽層或其組合。氧化矽或氧氮化矽可利用一種眾所周知的 乾式/濕式氧化製程而被生長於半導體蓋層上。當閘極介 電層324被生長時，其將僅形成於含半導體之區域上’諸 如於蓋層3 22上但非於絕緣區3 1 2上。另一方面，閘極介 電層3 24可爲一沈積的介電層。於本發明之一實施例中， 閘極介電層3 2 4係一高K的閘極介電層，諸如一金屬氧 # 化物介電層，諸如但不限定於氧化給、氧化锆、氧化鉅及 氧化鈦。高K的金屬氧化物介電層可藉由任何眾所周知 的技術而被沈積，諸如化學氣相沈積或濺射沈積。當閘極 介電層3 2 4被沈積，其亦將形成於絕緣區3 1 2上。 接，如圖3 Η中所示，一閘極電極材料3 2 6被全體沈 積於基底3 00上以致其係沈積於閘極介電層3 24上及其周 圍。亦即，閘極電極材料被沈積於閘極介電層3 2 4 (其被 形成於半導體本體318之頂部表面上的蓋層322上）上以 及被形成於或鄰近於蓋層3 22 (其被形成於半導體本體 -18- (16) 1269358 3 1 8之側壁3 2 0上）上。於本發明之一實施例中，閘極電 極材料3 26係一多晶矽。於本發明之一實施例中，閘極電 極材料3 26係一金屬膜。於本發明之一實施例中，閘極電 極材料3 2 6係一具有一被修改以用於η型裝置之工作函數 的金屬膜；以及於本發明之一實施例中，閘極電極材料係 一具有一被修改以用於ρ型裝置之工作函數的金屬膜。閘 極電極材料326被形成至一具有足以完全覆蓋或圍繞半導 • 體本體318、蓋層322、及閘極介電層324之厚度，如圖 3 Η中所示。 ' 接下來，如圖31中所示，閘極電極材料326及閘極 介電層324係藉由眾所周知的技術而被圖案化，以形成一 閘極電極3 3 0及一閘極介電層3 2 8。閘極電極材料3 26及 閘極介電層324可使用眾所周知的光微影術及鈾刻技術而 被圖案化。閘極電極3 3 0具有一對橫向相對的側壁3 3 2， 其界定裝置之閘極長度。於本發明之一實施例中，橫向相 # 對的側壁3 3 2係延伸於一垂直與半導體本體3 1 8之方向。 雖然係顯示一種減去製程以用於閘極電極3 3 0之形成’但 亦可利用其他眾所周知的技術（諸如取代閘極製程）以形 成閘極電極3 3 0。 接下來，如圖31中所示，一對源極/汲極區3 40被形 成於閘極電極3 3 0之相對側上的蓋層3 3 2以及半導體本體 3 1 8中。當形成一 η型裝置時，源極/汲極區可被形成至一 具有介於1X102G至lxlO21原子/公分3之濃度的η型導電 率。於本發明之一實施例中，當形成一 Ρ型裝置時’源極 19- (17) 1269358 /汲極區可被形成爲具有介於1X102G至lxio21原子/公分3 之濃度的P型導電率。可利用任何眾所周知的技術（諸如 離子植入或熱擴散），以形成源極/汲極區。當使用離子 植入時，閘極電極3 3 0可被使用以遮蔽電晶體之通道區自 一離子植入製程，而藉此自行對齊源極/汲極區3 40與閘 極電極3 3 0。此外，假如需要的話，源極/汲極區可包含次 區，諸如源極/汲極延伸及源極/汲極接觸區。可使用包含 φ 間隔物之形成等眾所周知的製程以形成次區。此外，假如 需要的話，可形成矽化物於源極/汲極區3 4 0上及於閘極 * 電極3 3 0之頂部上，以進一步減少電接觸阻抗。如此便完 成了具有應變增進遷移率之整塊非平面電晶體的製造。 可使用眾所周知的”後端”技術以形成金屬接觸、金屬 化層及層間介電質，以將各個電晶體互連在一起成爲功能 性積體電路，諸如微處理器。 本發明之一有價値的型態在於其蓋層增加了電晶體之 φ 閘極寬度。以此方式，最小特徵尺寸及間隔可被使用以形 成半導體本體，且接著蓋層可被形成於最小界定的半導體 本體上及其周圍，以增加裝置之閘極寬度。如此增加了裝 置之每區域的電流，其增進了裝置性能。於最小界定且分 離之特徵上形成一蓋層係減少了最小間隔本體間之距離至 一小於關鍵尺寸或小於用以界定裝置之光微影製程所能獲 得之尺寸的距離。以此方式，一蓋層之形成使各半導體本 體獲致較大的鬧極寬度’而仍以最小關鍵尺寸（CD )及 間隔界定本體。使用一蓋層以增加閘極寬度是極具價値 -20- (18) 1269358 的，即使於其不需要或不想要應變增進遷移率之應用中。 如此一來’本發明之實施例包含各種應用，其中（例如） 矽蓋層被形成於最小分隔的矽本體上以增加所製造之電晶 體的閘極寬度。此外，使用蓋層以增加每區域之閘極寬度 亦可用於非整塊裝置’諸如形成於絕緣基底（如絕緣體上 之矽（SOI)基底）上之三閘極或非平面裝置。 於本發明之實施例中，半導體膜之堆疊（整塊半導體 Φ 300、半導體本體318及蓋層322)被處理以產生高應變 於蓋層3 22中，其可顯著地增加載子遷移率。圖5顯示一 ' 整塊係單晶矽基底、一矽鍺合金半導體本體3 20及一矽蓋 層322如何可產生高拉伸應力於矽蓋層322中。當生長一 磊晶矽鍺合金膜3 1 6於一單晶基底3 00上時（圖3E )， 其平行於單晶矽基底3 0 0之表面的矽鍺膜3 1 8之平面5 0 2 的晶格常數係匹配整塊矽基底3 0 0之矽晶格。垂直與矽基 底表面之矽鍺合金3 1 6的平面5 04之晶格常數係大於其平 φ 行與矽基底3 00之平面5 02，由於矽鍺磊晶膜316之四角 形變形。一旦絕緣區3 1 2被凹陷（圖3 F )以形成矽鍺本 體3 1 8，則頂部3 1 9上之矽鍺晶格將擴張而側壁上之晶格 常數將收縮，由於自由表面之存在。通常’矽鍺合金3 1 8 之側壁3 20上的晶格常數將大於矽鍺合金之頂部表面3 1 9 上的晶格常數，其將大於單晶矽基底上之矽鍺合金的晶格 常數。當一矽蓋層3 2 2被生長於應變的砂鍺合金上時（圖 3G )，則砂鍺合金3 1 8會將其加長的垂直單元尺寸504 加諸於矽蓋層322之已經較小的單元尺寸上’其產生一斜 -21 - (19) 1269358 方晶矽蓋層3 22於矽鍺本體3 1 8之側壁上。因此，矽鍺合 金之蓋層3 22上所形成的矽蓋層將顯現一實質的拉伸應變 及一較低但顯著的拉伸應變於矽鍺合金之頂部表面3 1 9 上。矽蓋層322中所產生之應變係於一垂直與裝置中之電 流的方向。 圖4A-4C顯示一種形成一具有應變增進遷移率之整 塊非平面電晶體的方法，其中蓋層在半導體本體之頂部表 • 面被形成爲較側壁上更厚。如圖4A中所示，半導體本體 膜3 1 6被生長於絕緣區3 1 2之間，如參考圖3 E所述。然 ^ 而，於此實施例中，蓋層之一第一部4 1 0被生長於半導體 本體316之上，在凹陷絕緣區312以前。於本發明之一實 施例中，氮化矽層3 0 6被形成爲較半導體本體3 1 8所需者 更厚，以致其提供了額外的空間以致能半導體蓋層之第一 部4 1 0被生長於溝槽3 1 0內。以此方式，蓋層之第一部 4 1 0可被侷限於絕緣區3 1 2內。在形成蓋層之第一部4 1 0 # 以後，絕緣區3 1 2被凹陷回（如上所述）以形成一半導體 本體318，其具有一形成在其頂部表面上之蓋層410，如 圖4B中所示。接下來，如圖4C中所示，蓋層之一第二 部4 1 2被生長於半導體本體3 1 8之側壁3 2 0上以及半導體 本體318之頂部表面319所形成的蓋層之第一部410上。 於本發明之一實施例中，半導體蓋層410被形成至實質上 等於蓋層之第二部412的厚度。以此方式，當形成一實質 上方形的半導體本體3 1 8時，半導體本體3 1 8加上蓋層仍 將提供一實質上方形的蓋本體。接下來，可持續如圖3 Η -22- (20) 1269358 及3 I中所示之處理，以完成其具有應變增進遷移率之整 塊非平面電晶體的製造。 【圖式簡單說明】 圖1 A顯示一標準三閘極電晶體之上方視圖。 圖1 B顯示一標準三閘極電晶體之橫斷面視圖。
圖2係一具有應變感應遷移率之整塊三閘極電晶體的 圖示，依據本發明之一實施例。 圖3A-3I顯示一種形成一具有應變增進遷移率之整塊 三閘極電晶體的方法，依據本發明之一實施例。 圖 4A-4C顯示一種形成一具有應變增進遷移率之整 塊三閘極電晶體的方法，依據本發明之一實施例。 圖5顯示一整塊矽之晶格、一應變的矽鍺半導體本體 及一應變的砂蓋層。 【主要元件符號說明】 100 二 閘 極 電 晶體 1 02 矽 本 體 103 側 壁 104 頂 部 表 面 106 氧 化 物 層 108 單 晶 矽 基 底 110 閘 極 介 電 質 120 閘 極 電 極 -23- 1269358
(21) 130 源 極 /汲極區 200 電 晶 體 202 半 導 體 基 底 204 絕 緣 206 主 動 區 208 半 導 體 本 體 209 頂 部 表 面 2 10 半 導 體 蓋 層 2 11 側 壁 2 12 閘 極 介 電 層 2 14 閘 極 電 極 2 16 側 壁 300 電 晶 體 302 遮 罩 部 304 薄 墊 氧 化 物 層 306 較 厚 氮 化 矽 層 308 主 動 3 10 溝 槽 開 □ 3 12 介 電 層 3 14 開 □ 3 16 半 導 體 本 體 膜 3 18 半 導 體 本 體 3 19 頂 部 表 面 320 側 壁 -24- 1269358 (22) 3 2 2 半導體蓋層 324 閘極介電膜 326 閘極電極材料 328 閘極介電層 330 閘極電極 332 側壁 340 源極/汲極區 4 10 第一部 412 第二部 502 平面 504 平面
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Claims (1)

  1. (1) 1269358 十、申請專利範圍 1· 一種半導體裝置，包含： 一半導體基底上之一半導體本體，該半導體本體具有 一頂部表面及橫向相對的側壁； 一半導體蓋層，其係形成於該半導體本體之頂部表面 上及側壁上； 一閘極介電層，其係形成於該半導體本體之該頂部表 g 面上及該側壁上的該半導體蓋層上； 一閘極電極，其具有一對形成於該閘極介電層上及其 周圍之橫向相對的側壁；及 一對源極/汲極區，其係形成於該閘極電極之相對側 上的該半導體本體中。 2. 如申請專利範圍第1項之半導體裝置，其中該半 導體蓋層具有一拉伸應力。 3. 如申請專利範圍第2項之半導體裝置，其中該半 φ 導體蓋層具有較大的拉伸應力於該半導體本體之側壁上， 相較於該半導體本體之頂部表面上的拉伸應力。 4. 如申請專利範圍第2項之半導體裝置，其中該源 極/汲極區爲η型導電性。 5. 如申請專利範圍第1項之半導體裝置，其中該半 導體基底爲一矽基底’其中該半導體本體爲一矽鍺合金及 其中該半導體蓋層爲一矽膜。 6 ·如申請專利fe圍弟1項之半導體裝置，其中該半 導體蓋層具有一壓縮應力。 •26- (2) 1269358 7·如申請專利範圍第6項之半導體裝置，其中該半 導體蓋層具有較該半導體本體之頂部表面上更大的壓縮應 力於側壁上。 8 .如申請專利範圍第6項之半導體裝置，其中該半 導體基底爲一單晶矽基底，其中該半導體本體包含一矽碳 合金及其中該半導體蓋層爲一矽膜。 9 ·如申請專利範圍第1項之半導體裝置，其中該半 φ 導體基底爲一矽基底，其中該半導體本體爲一矽本體，及 其中該半導體蓋層爲一矽蓋層。 ” 10· —種半導體裝置，包含·· 一形成於單晶矽基底上之矽鍺本體，該矽鍺本體具有 一頂部表面及一對橫向相對的側壁； 一矽膜’其係形成於該矽鍺本體之該頂部表面上及該 側壁上； 一閘極介電層’其係形成於該半導體本體之該頂部表 φ 面上及該半導體本體之該側壁上的該砂膜上； 一閘極電極’其具有一對形成於該閘極介電層上及其 周圍之橫向相對的側壁；及 一對源極/汲極區’其係形成於該閘極電極之相對側 上的該半導體本體中。 11·如申請專利範圍第1 〇項之半導體裝置，其中該 砂膜被形成爲在該半導體本體之頂部表面上比在該半導體 本體之側壁上更厚。 1 2 ·如申請專利範圍第1 0項之半導體裝置，其中該 -27- (3) 1269358 矽膜具有介於50-300埃之厚度。 1 3 ·如申請專利範圍第1 0項之半導體裝置’其中該 矽鍺合金包含介於5-40%的鍺。 1 4 ·如申請專利範圔第1 3項之半導體裝置’其中該 矽鍺合金包含約1 5 - 2 5 %的鍺。 15.如申請專利範圔第1 0項之半導體裝置’其中該 源極/汲極區爲η型導電性。 H 16· —種半導體裝置，包含： 一形成於單晶矽基底上之矽碳合金，該矽碳合金具有 ’ 一頂部表面及一對橫向相對的側壁； 一矽膜，其係形成於該矽碳合金本體之該頂部表面上 及該側壁上； 一閘極介電層，其係形成於該矽碳合金本體之該頂部 表面上及該矽碳合金本體之該側壁上的該矽膜上； 一閘極電極’其具有一對形成於該閘極介電層上及其 Φ 周圍之橫向相對的側壁；及 一對源極/汲極區’其係形成於該閘極電極之相對側 上的該半導體本體中。 1 7 ·如申請專利範圍第1 6項之半導體裝置，其中該 矽膜被形成至5 0-3 00埃之厚度。 1 8 ·如申請專利範圍第1 7項之半導體裝置，其中該 矽膜具有介於5 0-3 00埃之厚度。 1 9.如申請專利範圍第1 6項之半導體裝置，其中該 源極/汲極區爲Ρ型導電性。 -28 - (4) 1269358 20. —種形成半導體裝置之方法，包含： 形成一對絕緣區於一半導體基底中，該對絕緣區係界 定介於其間之該半導體基底中的主動基底區，該絕緣區延 伸於該基底之上； 形成一半導體膜於該對絕緣區之間的該半導體基底之 該主動區上； 蝕刻回該絕緣區以從該半導體膜形成一半導體本體， φ 其中該半導體本體具有一頂部表面及一對橫向相對的側 壁； ^ 形成一半導體蓋層於該半導體本體之該頂部表面上及 該側壁上； 形成一閘極介電層於該半導體本體之該側壁及該頂部 表面上所形成的該蓋層上； 形成一閘極電極，其具有一對於該閘極介電層上及其 周圍之橫向相對的側壁；及 φ 形成一對源極/汲極區於該閘極電極之相對側上的該 半導體本體中。 21. 如申請專利範圍第2 0項之方法，其中該半導體 膜被選擇性地生長自該半導體基底之該主動區。 22. 如申請專利範圍第20項之方法，其中該蓋層被 選擇性地生長自該半導體本體。 2 3 .如申請專利範圍第2 0項之方法，其中該絕緣區 係以一濕式蝕刻劑而被蝕刻回。 24.如申請專利範圍第20項之方法，其中該半導體 -29- (5) 1269358 蓋層具有一拉伸應力。 25. 如申請專利範圍第24項之方法，其中該半導體 蓋層具有較大的拉伸應力於該半導體本體之側壁上，相較 於該半導體本體之頂部表面上的拉伸應力。 26. 如申請專利範圍第24項之方法，其中該源極/汲 極區爲η型導電性。 27. 如申請專利範圍第20項之方法，其中該半導體 φ 基底爲一矽基底，其中該半導體本體爲一矽鍺合金及其中 該半導體蓋層爲矽。 ~ 28.如申請專利範圍第20項之方法，其中該半導體 蓋層具有一壓縮應力。 29.如申請專利範圍第28項之方法，其中該半導體 蓋層具有較該半導體本體之頂部表面上更大的壓縮應力於 側壁上。 3〇·如申請專利範圍第28項之方法，其中該半導體 # 基底爲一單晶矽基底，其中該半導體本體包含一矽碳合金 及其中該半導體蓋層爲一磊晶矽。 3 1 .如申請專利範圍第2 8項之方法，其中該源極/汲 極區爲ρ型導電性。 32. —種形成半導體裝置之方法，包含： 形成一對分離的絕緣區於一半導體基底中，該分離的 絕緣區係界定該基底中之一主動基底區，其中該絕緣區延 伸於該主動基底區之上； 形成一半導體膜於該絕緣區之間的該基底之該主動區 -30- (6) 1269358 上； 形成一第一蓋層於該絕緣區之間的該半導體膜之該頂 部表面上； 蝕刻回該絕緣區以形成一半導體本體，該半導體本體 具有該第一蓋層之一頂部表面及一對橫向相對的側壁； 形成一第二蓋層於該半導體本體之該頂部表面上及該 半導體本體之該側壁上； •形成一閘極介電層於該半導體本體上之該第一蓋層上 的該第二蓋層上及該半導體本體之該側壁上的該第二蓋層 - 上； 形成一閘極電極，其具有一對於該閘極介電層上及其 周圍之橫向相對的側壁；及 形成一對源極/汲極區於該閘極電極之相對側上的該 半導體本體中。 3 3.如申請專利範圍第3 2項之方法，其中該第一及 φ 第二蓋層爲磊晶矽，其中該半導體本體爲一砂鍺合金’及 其中該半導體基底爲一單晶矽基。 3 4.如申請專利範圍第3 2項之方法，其中該第一及 第二蓋層爲磊晶矽，其中該半導體本體爲一矽碳合金’及 其中該半導體基底爲一單晶矽基。 35.如申請專利範圍第3 2項之方法，其中該第一及 第二半導體蓋層具有一拉伸應力。 3 6 .如申請專利範圍第3 2項之方法，其中該第一及 第二半導體蓋層具有一壓縮應力。 -31 - (7) 1269358 37·如申請專利範圍第32項之方法，其中該半導體 月吴具有與該半導體基底不同的晶格結構，以致其該半導體 膜具有一應力形成於其中。 38· —種形成半導體裝置之方法，包含： 形成一第一半導體本體及一第二半導體本體於一基底 上’該第一及該第二半導體本體各具有一頂部袠面及一對 橫向相對的側壁，該第一半導體本體與該第二半導體本體 _ 係分離以一段距離； 形成一半導體蓋層於該第一及第二半導體本體之該側 ' 壁上及該頂部表面上； 形成一閘極介電層於該第一及第二半導體本體之該頂 部表面上及該側壁上；及 开夕成一閘極電極於該桌一及第二半導體本體之該頂部 表面上’且係鄰近於該第一及第二半導體本體之該側壁上 的該閘極介電層。 • 39·如申請專利範圍第38項之方法，其中該半導體 本體係利用一光微影製程而被界定，及其中分離該第一與 第二本體之距離係該光微影製程所能達成之最小尺寸。 40·如申請專利範圍第39項之方法，其中該第一及 第二半導體本體具有一等於該光微影製程所能夠界定之最 小尺寸的寬度。 4 1 ·如申請專利範圍第3 8項之方法，其中該半導體 本體爲一磊晶砂fl吴及其中該半導體蓋層爲一嘉晶砂膜。 4 2 .如申請專利範圍第3 8項之方法，其中該半導體 -32- (8) 1269358 本體爲一磊晶矽鍺合金膜及其中該半導體蓋層爲一磊晶石夕 膜。
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI423443B (zh) * 2010-01-22 2014-01-11 Toshiba Kk 半導體裝置及其製造方法
US8816391B2 (en) 2009-04-01 2014-08-26 Taiwan Semiconductor Manufacturing Company, Ltd. Source/drain engineering of devices with high-mobility channels
US8927371B2 (en) 2009-04-01 2015-01-06 Taiwan Semiconductor Manufacturing Company, Ltd. High-mobility multiple-gate transistor with improved on-to-off current ratio
US9006788B2 (en) 2009-06-01 2015-04-14 Taiwan Semiconductor Manufacturing Company, Ltd. Source/drain re-growth for manufacturing III-V based transistors
US9536772B2 (en) 2013-06-11 2017-01-03 Taiwan Semiconductor Manufacturing Company, Ltd. Fin structure of semiconductor device
US9768305B2 (en) 2009-05-29 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Gradient ternary or quaternary multiple-gate transistor

Families Citing this family (263)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7358121B2 (en) * 2002-08-23 2008-04-15 Intel Corporation Tri-gate devices and methods of fabrication
US7074656B2 (en) * 2003-04-29 2006-07-11 Taiwan Semiconductor Manufacturing Company, Ltd. Doping of semiconductor fin devices
EP1643560A4 (en) * 2003-05-30 2007-04-11 Matsushita Electric Ind Co Ltd SEMICONDUCTOR COMPONENT AND METHOD FOR THE PRODUCTION THEREOF
US7598515B2 (en) * 2003-06-26 2009-10-06 Mears Technologies, Inc. Semiconductor device including a strained superlattice and overlying stress layer and related methods
US20070010040A1 (en) * 2003-06-26 2007-01-11 Rj Mears, Llc Method for Making a Semiconductor Device Including a Strained Superlattice Layer Above a Stress Layer
US20070015344A1 (en) * 2003-06-26 2007-01-18 Rj Mears, Llc Method for Making a Semiconductor Device Including a Strained Superlattice Between at Least One Pair of Spaced Apart Stress Regions
US20070020833A1 (en) * 2003-06-26 2007-01-25 Rj Mears, Llc Method for Making a Semiconductor Device Including a Channel with a Non-Semiconductor Layer Monolayer
US20070020860A1 (en) * 2003-06-26 2007-01-25 Rj Mears, Llc Method for Making Semiconductor Device Including a Strained Superlattice and Overlying Stress Layer and Related Methods
US7531828B2 (en) * 2003-06-26 2009-05-12 Mears Technologies, Inc. Semiconductor device including a strained superlattice between at least one pair of spaced apart stress regions
US7612366B2 (en) * 2003-06-26 2009-11-03 Mears Technologies, Inc. Semiconductor device including a strained superlattice layer above a stress layer
US7456476B2 (en) 2003-06-27 2008-11-25 Intel Corporation Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
US6909151B2 (en) 2003-06-27 2005-06-21 Intel Corporation Nonplanar device with stress incorporation layer and method of fabrication
US7105390B2 (en) 2003-12-30 2006-09-12 Intel Corporation Nonplanar transistors with metal gate electrodes
US7268058B2 (en) 2004-01-16 2007-09-11 Intel Corporation Tri-gate transistors and methods to fabricate same
US7154118B2 (en) 2004-03-31 2006-12-26 Intel Corporation Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
KR100541657B1 (ko) * 2004-06-29 2006-01-11 삼성전자주식회사 멀티 게이트 트랜지스터의 제조방법 및 이에 의해 제조된멀티 게이트 트랜지스터
US7042009B2 (en) 2004-06-30 2006-05-09 Intel Corporation High mobility tri-gate devices and methods of fabrication
US7598134B2 (en) * 2004-07-28 2009-10-06 Micron Technology, Inc. Memory device forming methods
US7348284B2 (en) 2004-08-10 2008-03-25 Intel Corporation Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
US7253493B2 (en) * 2004-08-24 2007-08-07 Micron Technology, Inc. High density access transistor having increased channel width and methods of fabricating such devices
US7679145B2 (en) * 2004-08-31 2010-03-16 Intel Corporation Transistor performance enhancement using engineered strains
US8673706B2 (en) * 2004-09-01 2014-03-18 Micron Technology, Inc. Methods of forming layers comprising epitaxial silicon
US7144779B2 (en) * 2004-09-01 2006-12-05 Micron Technology, Inc. Method of forming epitaxial silicon-comprising material
US7132355B2 (en) * 2004-09-01 2006-11-07 Micron Technology, Inc. Method of forming a layer comprising epitaxial silicon and a field effect transistor
US7531395B2 (en) * 2004-09-01 2009-05-12 Micron Technology, Inc. Methods of forming a layer comprising epitaxial silicon, and methods of forming field effect transistors
US7422946B2 (en) 2004-09-29 2008-09-09 Intel Corporation Independently accessed double-gate and tri-gate transistors in same process flow
US7332439B2 (en) 2004-09-29 2008-02-19 Intel Corporation Metal gate transistors with epitaxial source and drain regions
US7361958B2 (en) * 2004-09-30 2008-04-22 Intel Corporation Nonplanar transistors with metal gate electrodes
US20060086977A1 (en) 2004-10-25 2006-04-27 Uday Shah Nonplanar device with thinned lower body portion and method of fabrication
US7393733B2 (en) * 2004-12-01 2008-07-01 Amberwave Systems Corporation Methods of forming hybrid fin field-effect transistor structures
US7235501B2 (en) 2004-12-13 2007-06-26 Micron Technology, Inc. Lanthanum hafnium oxide dielectrics
US7193279B2 (en) * 2005-01-18 2007-03-20 Intel Corporation Non-planar MOS structure with a strained channel region
FR2881877B1 (fr) * 2005-02-04 2007-08-31 Soitec Silicon On Insulator Transistor a effet de champ multi-grille a canal multi-couche
US7518196B2 (en) 2005-02-23 2009-04-14 Intel Corporation Field effect transistor with narrow bandgap source and drain regions and method of fabrication
US20060202266A1 (en) 2005-03-14 2006-09-14 Marko Radosavljevic Field effect transistor with metal source/drain regions
US20060214233A1 (en) * 2005-03-22 2006-09-28 Ananthanarayanan Hari P FinFET semiconductor device
FR2885733B1 (fr) * 2005-05-16 2008-03-07 St Microelectronics Crolles 2 Structure de transistor a trois grilles
US8324660B2 (en) 2005-05-17 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US9153645B2 (en) 2005-05-17 2015-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US7858481B2 (en) 2005-06-15 2010-12-28 Intel Corporation Method for fabricating transistor with thinned channel
US20060286759A1 (en) * 2005-06-21 2006-12-21 Texas Instruments, Inc. Metal oxide semiconductor (MOS) device having both an accumulation and a enhancement mode transistor device on a similar substrate and a method of manufacture therefor
US7547637B2 (en) 2005-06-21 2009-06-16 Intel Corporation Methods for patterning a semiconductor film
US7279375B2 (en) 2005-06-30 2007-10-09 Intel Corporation Block contact architectures for nanoscale channel transistors
US7265008B2 (en) 2005-07-01 2007-09-04 Synopsys, Inc. Method of IC production using corrugated substrate
US7247887B2 (en) * 2005-07-01 2007-07-24 Synopsys, Inc. Segmented channel MOS transistor
US7190050B2 (en) * 2005-07-01 2007-03-13 Synopsys, Inc. Integrated circuit on corrugated substrate
US7288802B2 (en) * 2005-07-27 2007-10-30 International Business Machines Corporation Virtual body-contacted trigate
US7381649B2 (en) * 2005-07-29 2008-06-03 Taiwan Semiconductor Manufacturing Company, Ltd. Structure for a multiple-gate FET device and a method for its fabrication
US7348642B2 (en) 2005-08-03 2008-03-25 International Business Machines Corporation Fin-type field effect transistor
US7402875B2 (en) 2005-08-17 2008-07-22 Intel Corporation Lateral undercut of metal gate in SOI device
US7479421B2 (en) * 2005-09-28 2009-01-20 Intel Corporation Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby
US20070090416A1 (en) 2005-09-28 2007-04-26 Doyle Brian S CMOS devices with a single work function gate electrode and method of fabrication
US20070102756A1 (en) * 2005-11-10 2007-05-10 Bohumil Lojek FinFET transistor fabricated in bulk semiconducting material
DE102006027178A1 (de) * 2005-11-21 2007-07-05 Infineon Technologies Ag Multi-Fin-Bauelement-Anordnung und Verfahren zum Herstellen einer Multi-Fin-Bauelement-Anordnung
US7485503B2 (en) 2005-11-30 2009-02-03 Intel Corporation Dielectric interface for group III-V semiconductor device
US8183556B2 (en) 2005-12-15 2012-05-22 Intel Corporation Extreme high mobility CMOS logic
KR100713924B1 (ko) * 2005-12-23 2007-05-07 주식회사 하이닉스반도체 돌기형 트랜지스터 및 그의 형성방법
US7525160B2 (en) * 2005-12-27 2009-04-28 Intel Corporation Multigate device with recessed strain regions
US20070161214A1 (en) 2006-01-06 2007-07-12 International Business Machines Corporation High k gate stack on III-V compound semiconductors
DE102006001680B3 (de) * 2006-01-12 2007-08-09 Infineon Technologies Ag Herstellungsverfahren für eine FinFET-Transistoranordnung und entsprechende FinFET-Transistoranordnung
US7709402B2 (en) 2006-02-16 2010-05-04 Micron Technology, Inc. Conductive layers for hafnium silicon oxynitride films
US7777250B2 (en) 2006-03-24 2010-08-17 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures and related methods for device fabrication
JP2007299951A (ja) * 2006-04-28 2007-11-15 Toshiba Corp 半導体装置およびその製造方法
US20090321830A1 (en) * 2006-05-15 2009-12-31 Carnegie Mellon University Integrated circuit device, system, and method of fabrication
US7422960B2 (en) 2006-05-17 2008-09-09 Micron Technology, Inc. Method of forming gate arrays on a partial SOI substrate
JP2007329200A (ja) * 2006-06-06 2007-12-20 Toshiba Corp 半導体装置の製造方法
JP4552908B2 (ja) * 2006-07-26 2010-09-29 エルピーダメモリ株式会社 半導体装置の製造方法
US8143646B2 (en) 2006-08-02 2012-03-27 Intel Corporation Stacking fault and twin blocking barrier for integrating III-V on Si
US7727908B2 (en) 2006-08-03 2010-06-01 Micron Technology, Inc. Deposition of ZrA1ON films
US7537994B2 (en) 2006-08-28 2009-05-26 Micron Technology, Inc. Methods of forming semiconductor devices, assemblies and constructions
US7759747B2 (en) 2006-08-31 2010-07-20 Micron Technology, Inc. Tantalum aluminum oxynitride high-κ dielectric
US7776765B2 (en) 2006-08-31 2010-08-17 Micron Technology, Inc. Tantalum silicon oxynitride high-k dielectrics and metal gates
EP2062290B1 (en) 2006-09-07 2019-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Defect reduction using aspect ratio trapping
US7456471B2 (en) * 2006-09-15 2008-11-25 International Business Machines Corporation Field effect transistor with raised source/drain fin straps
US7799592B2 (en) 2006-09-27 2010-09-21 Taiwan Semiconductor Manufacturing Company, Ltd. Tri-gate field-effect transistors formed by aspect ratio trapping
US7875958B2 (en) 2006-09-27 2011-01-25 Taiwan Semiconductor Manufacturing Company, Ltd. Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures
US8502263B2 (en) 2006-10-19 2013-08-06 Taiwan Semiconductor Manufacturing Company, Ltd. Light-emitter-based devices with lattice-mismatched semiconductor structures
US7829407B2 (en) * 2006-11-20 2010-11-09 International Business Machines Corporation Method of fabricating a stressed MOSFET by bending SOI region
US7728364B2 (en) * 2007-01-19 2010-06-01 International Business Machines Corporation Enhanced mobility CMOS transistors with a V-shaped channel with self-alignment to shallow trench isolation
US8735990B2 (en) * 2007-02-28 2014-05-27 International Business Machines Corporation Radiation hardened FinFET
JP5003515B2 (ja) 2007-03-20 2012-08-15 ソニー株式会社 半導体装置
WO2008124154A2 (en) 2007-04-09 2008-10-16 Amberwave Systems Corporation Photovoltaics on silicon
US8304805B2 (en) 2009-01-09 2012-11-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor diodes fabricated by aspect ratio trapping with coalesced films
US8237151B2 (en) 2009-01-09 2012-08-07 Taiwan Semiconductor Manufacturing Company, Ltd. Diode-based devices and methods for making the same
US7825328B2 (en) 2007-04-09 2010-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Nitride-based multi-junction solar cell modules and methods for making the same
US8927353B2 (en) * 2007-05-07 2015-01-06 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor and method of forming the same
US8450165B2 (en) 2007-05-14 2013-05-28 Intel Corporation Semiconductor device having tipless epitaxial source/drain regions
US20080293192A1 (en) * 2007-05-22 2008-11-27 Stefan Zollner Semiconductor device with stressors and methods thereof
US8174073B2 (en) * 2007-05-30 2012-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit structures with multiple FinFETs
US8329541B2 (en) 2007-06-15 2012-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. InP-based transistor fabrication
US20090001415A1 (en) * 2007-06-30 2009-01-01 Nick Lindert Multi-gate transistor with strained body
US7692254B2 (en) * 2007-07-16 2010-04-06 International Business Machines Corporation Fin-type field effect transistor structure with merged source/drain silicide and method of forming the structure
US7969808B2 (en) * 2007-07-20 2011-06-28 Samsung Electronics Co., Ltd. Memory cell structures, memory arrays, memory devices, memory controllers, and memory systems, and methods of manufacturing and operating the same
KR20090116088A (ko) * 2008-05-06 2009-11-11 삼성전자주식회사 정보 유지 능력과 동작 특성이 향상된 커패시터리스 1ｔ반도체 메모리 소자
DE112008002387B4 (de) 2007-09-07 2022-04-07 Taiwan Semiconductor Manufacturing Co., Ltd. Struktur einer Mehrfachübergangs-Solarzelle, Verfahren zur Bildung einer photonischenVorrichtung, Photovoltaische Mehrfachübergangs-Zelle und Photovoltaische Mehrfachübergangs-Zellenvorrichtung,
KR101308048B1 (ko) * 2007-10-10 2013-09-12 삼성전자주식회사 반도체 메모리 장치
KR20090075063A (ko) * 2008-01-03 2009-07-08 삼성전자주식회사 플로팅 바디 트랜지스터를 이용한 동적 메모리 셀을 가지는메모리 셀 어레이를 구비하는 반도체 메모리 장치 및 이장치의 동작 방법
US7982269B2 (en) * 2008-04-17 2011-07-19 International Business Machines Corporation Transistors having asymmetric strained source/drain portions
JP5159413B2 (ja) * 2008-04-24 2013-03-06 株式会社東芝 半導体装置及びその製造方法
US8183667B2 (en) 2008-06-03 2012-05-22 Taiwan Semiconductor Manufacturing Co., Ltd. Epitaxial growth of crystalline material
US8362566B2 (en) 2008-06-23 2013-01-29 Intel Corporation Stress in trigate devices using complimentary gate fill materials
US8274097B2 (en) 2008-07-01 2012-09-25 Taiwan Semiconductor Manufacturing Company, Ltd. Reduction of edge effects from aspect ratio trapping
US8981427B2 (en) 2008-07-15 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Polishing of small composite semiconductor materials
US7833891B2 (en) * 2008-07-23 2010-11-16 International Business Machines Corporation Semiconductor device manufacturing method using oxygen diffusion barrier layer between buried oxide layer and high K dielectric layer
JP5416212B2 (ja) 2008-09-19 2014-02-12 台湾積體電路製造股▲ふん▼有限公司 エピタキシャル層の成長によるデバイス形成
US20100072515A1 (en) 2008-09-19 2010-03-25 Amberwave Systems Corporation Fabrication and structures of crystalline material
US8253211B2 (en) 2008-09-24 2012-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor sensor structures with reduced dislocation defect densities
KR20100070158A (ko) * 2008-12-17 2010-06-25 삼성전자주식회사 커패시터가 없는 동작 메모리 셀을 구비한 반도체 메모리 장치 및 이 장치의 동작 방법
KR101442177B1 (ko) * 2008-12-18 2014-09-18 삼성전자주식회사 커패시터 없는 1-트랜지스터 메모리 셀을 갖는 반도체소자의 제조방법들
US8058692B2 (en) 2008-12-29 2011-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Multiple-gate transistors with reverse T-shaped fins
US8305829B2 (en) * 2009-02-23 2012-11-06 Taiwan Semiconductor Manufacturing Company, Ltd. Memory power gating circuit for controlling internal voltage of a memory array, system and method for controlling the same
US8305790B2 (en) * 2009-03-16 2012-11-06 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical anti-fuse and related applications
US8957482B2 (en) * 2009-03-31 2015-02-17 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical fuse and related applications
CN102379046B (zh) 2009-04-02 2015-06-17 台湾积体电路制造股份有限公司 从晶体材料的非极性平面形成的器件及其制作方法
US8912602B2 (en) * 2009-04-14 2014-12-16 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs and methods for forming the same
US8455860B2 (en) 2009-04-30 2013-06-04 Taiwan Semiconductor Manufacturing Company, Ltd. Reducing source/drain resistance of III-V based transistors
US8461015B2 (en) * 2009-07-08 2013-06-11 Taiwan Semiconductor Manufacturing Company, Ltd. STI structure and method of forming bottom void in same
US8482073B2 (en) * 2010-03-25 2013-07-09 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit including FINFETs and methods for forming the same
US8629478B2 (en) * 2009-07-31 2014-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fin structure for high mobility multiple-gate transistor
US8440517B2 (en) 2010-10-13 2013-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET and method of fabricating the same
US8264021B2 (en) * 2009-10-01 2012-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Finfets and methods for forming the same
US9484462B2 (en) * 2009-09-24 2016-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Fin structure of fin field effect transistor
US8264032B2 (en) * 2009-09-01 2012-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Accumulation type FinFET, circuits and fabrication method thereof
US8759943B2 (en) 2010-10-08 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Transistor having notched fin structure and method of making the same
US8497528B2 (en) 2010-05-06 2013-07-30 Taiwan Semiconductor Manufacturing Company, Ltd. Method for fabricating a strained structure
US8980719B2 (en) 2010-04-28 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for doping fin field-effect transistors
US8623728B2 (en) 2009-07-28 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming high germanium concentration SiGe stressor
US8298925B2 (en) 2010-11-08 2012-10-30 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming ultra shallow junction
US8472227B2 (en) * 2010-01-27 2013-06-25 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuits and methods for forming the same
US20110097867A1 (en) * 2009-10-22 2011-04-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method of controlling gate thicknesses in forming fusi gates
EP2315239A1 (en) * 2009-10-23 2011-04-27 Imec A method of forming monocrystalline germanium or silicon germanium
US8269283B2 (en) 2009-12-21 2012-09-18 Intel Corporation Methods and apparatus to reduce layout based strain variations in non-planar transistor structures
US9040393B2 (en) 2010-01-14 2015-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor structure
US8609495B2 (en) * 2010-04-08 2013-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid gate process for fabricating finfet device
US8207038B2 (en) 2010-05-24 2012-06-26 International Business Machines Corporation Stressed Fin-FET devices with low contact resistance
DE102010038742B4 (de) * 2010-07-30 2016-01-21 Globalfoundries Dresden Module One Llc & Co. Kg Verfahren und Halbleiterbauelement basierend auf einer Verformungstechnologie in dreidimensionalen Transistoren auf der Grundlage eines verformten Kanalhalbleitermaterials
US8603924B2 (en) 2010-10-19 2013-12-10 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming gate dielectric material
US9048181B2 (en) 2010-11-08 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming ultra shallow junction
US8769446B2 (en) 2010-11-12 2014-07-01 Taiwan Semiconductor Manufacturing Company, Ltd. Method and device for increasing fin device density for unaligned fins
US8936978B2 (en) * 2010-11-29 2015-01-20 International Business Machines Corporation Multigate structure formed with electroless metal deposition
US8877602B2 (en) 2011-01-25 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms of doping oxide for forming shallow trench isolation
US8592915B2 (en) 2011-01-25 2013-11-26 Taiwan Semiconductor Manufacturing Company, Ltd. Doped oxide for shallow trench isolation (STI)
US8431453B2 (en) 2011-03-31 2013-04-30 Taiwan Semiconductor Manufacturing Company, Ltd. Plasma doping to reduce dielectric loss during removal of dummy layers in a gate structure
US9761666B2 (en) * 2011-06-16 2017-09-12 Taiwan Semiconductor Manufacturing Company, Ltd. Strained channel field effect transistor
US8841701B2 (en) * 2011-08-30 2014-09-23 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device having a channel defined in a diamond-like shape semiconductor structure
US9287385B2 (en) * 2011-09-01 2016-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-fin device and method of making same
US8441072B2 (en) * 2011-09-02 2013-05-14 United Microelectronics Corp. Non-planar semiconductor structure and fabrication method thereof
TWI499006B (zh) * 2011-10-07 2015-09-01 Etron Technology Inc 動態記憶體結構
US9368502B2 (en) * 2011-10-17 2016-06-14 GlogalFoundries, Inc. Replacement gate multigate transistor for embedded DRAM
US9893163B2 (en) * 2011-11-04 2018-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. 3D capacitor and method of manufacturing same
CN103117305A (zh) * 2011-11-16 2013-05-22 中芯国际集成电路制造(上海)有限公司 一种鳍式场效应管及其基体
US9461160B2 (en) 2011-12-19 2016-10-04 Intel Corporation Non-planar III-N transistor
CN104126228B (zh) * 2011-12-23 2016-12-07 英特尔公司 非平面栅极全包围器件及其制造方法
CN107195684B (zh) * 2011-12-30 2020-12-08 英特尔公司 环绕式沟槽接触部结构和制作方法
US8659097B2 (en) * 2012-01-16 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Control fin heights in FinFET structures
US9466696B2 (en) 2012-01-24 2016-10-11 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs and methods for forming the same
US9281378B2 (en) 2012-01-24 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Fin recess last process for FinFET fabrication
US9171925B2 (en) 2012-01-24 2015-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate devices with replaced-channels and methods for forming the same
US8742509B2 (en) 2012-03-01 2014-06-03 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for FinFETs
US9559099B2 (en) 2012-03-01 2017-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for FinFETs
KR101835655B1 (ko) 2012-03-06 2018-03-07 삼성전자주식회사 핀 전계 효과 트랜지스터 및 이의 제조 방법
US8836016B2 (en) * 2012-03-08 2014-09-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structures and methods with high mobility and high energy bandgap materials
US8994002B2 (en) * 2012-03-16 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET having superlattice stressor
US8872284B2 (en) 2012-03-20 2014-10-28 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET with metal gate stressor
CN103325833B (zh) * 2012-03-21 2018-08-07 三星电子株式会社 场效应晶体管以及包括其的半导体器件和集成电路器件
KR101894221B1 (ko) * 2012-03-21 2018-10-04 삼성전자주식회사 전계 효과 트랜지스터 및 이를 포함하는 반도체 장치
US8716765B2 (en) 2012-03-23 2014-05-06 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of semiconductor device
US8629512B2 (en) * 2012-03-28 2014-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Gate stack of fin field effect transistor with slanted sidewalls
US9368388B2 (en) * 2012-04-13 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus for FinFETs
US9559189B2 (en) 2012-04-16 2017-01-31 United Microelectronics Corp. Non-planar FET
US8709910B2 (en) 2012-04-30 2014-04-29 United Microelectronics Corp. Semiconductor process
US9059321B2 (en) * 2012-05-14 2015-06-16 International Business Machines Corporation Buried channel field-effect transistors
US8829610B2 (en) 2012-05-15 2014-09-09 United Microelectronics Corp. Method for forming semiconductor layout patterns, semiconductor layout patterns, and semiconductor structure
CN103426765B (zh) * 2012-05-24 2016-12-14 中芯国际集成电路制造(上海)有限公司 半导体器件的形成方法、鳍式场效应管的形成方法
US8729634B2 (en) 2012-06-15 2014-05-20 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET with high mobility and strain channel
CN103515430B (zh) * 2012-06-19 2016-08-10 中芯国际集成电路制造(上海)有限公司 鳍式场效应晶体管及其制造方法
KR101909204B1 (ko) * 2012-06-25 2018-10-17 삼성전자 주식회사 내장된 스트레인-유도 패턴을 갖는 반도체 소자 및 그 형성 방법
US8497171B1 (en) * 2012-07-05 2013-07-30 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET method and structure with embedded underlying anti-punch through layer
US9142400B1 (en) 2012-07-17 2015-09-22 Stc.Unm Method of making a heteroepitaxial layer on a seed area
US8847281B2 (en) 2012-07-27 2014-09-30 Intel Corporation High mobility strained channels for fin-based transistors
US9817928B2 (en) 2012-08-31 2017-11-14 Synopsys, Inc. Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3D integrated circuits
US9190346B2 (en) 2012-08-31 2015-11-17 Synopsys, Inc. Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3D integrated circuits
US8633516B1 (en) 2012-09-28 2014-01-21 Taiwan Semiconductor Manufacturing Company, Ltd. Source/drain stack stressor for semiconductor device
US20140091279A1 (en) * 2012-09-28 2014-04-03 Jessica S. Kachian Non-planar semiconductor device having germanium-based active region with release etch-passivation surface
CN103715087B (zh) * 2012-09-29 2016-12-21 中芯国际集成电路制造(上海)有限公司 鳍式场效应晶体管及其制造方法
US8716803B2 (en) * 2012-10-04 2014-05-06 Flashsilicon Incorporation 3-D single floating gate non-volatile memory device
US9443962B2 (en) 2012-11-09 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. Recessing STI to increase fin height in fin-first process
US9349837B2 (en) 2012-11-09 2016-05-24 Taiwan Semiconductor Manufacturing Company, Ltd. Recessing STI to increase Fin height in Fin-first process
CN103839810B (zh) * 2012-11-21 2017-02-22 中芯国际集成电路制造(上海)有限公司 鳍式场效应晶体管芯片及其制造方法
US8946063B2 (en) * 2012-11-30 2015-02-03 International Business Machines Corporation Semiconductor device having SSOI substrate with relaxed tensile stress
CN103855020B (zh) * 2012-12-04 2016-06-29 中芯国际集成电路制造(上海)有限公司 晶体管及其形成方法
US8772117B2 (en) * 2012-12-05 2014-07-08 Globalfoundries Inc. Combination FinFET and planar FET semiconductor device and methods of making such a device
EP2741337B1 (en) 2012-12-07 2018-04-11 IMEC vzw Semiconductor heterostructure field effect transistor and method for making thereof
US9379018B2 (en) 2012-12-17 2016-06-28 Synopsys, Inc. Increasing Ion/Ioff ratio in FinFETs and nano-wires
US8847324B2 (en) 2012-12-17 2014-09-30 Synopsys, Inc. Increasing ION /IOFF ratio in FinFETs and nano-wires
US8890119B2 (en) 2012-12-18 2014-11-18 Intel Corporation Vertical nanowire transistor with axially engineered semiconductor and gate metallization
US9054215B2 (en) 2012-12-18 2015-06-09 Intel Corporation Patterning of vertical nanowire transistor channel and gate with directed self assembly
US8768271B1 (en) 2012-12-19 2014-07-01 Intel Corporation Group III-N transistors on nanoscale template structures
US8957476B2 (en) * 2012-12-20 2015-02-17 Intel Corporation Conversion of thin transistor elements from silicon to silicon germanium
US8956942B2 (en) 2012-12-21 2015-02-17 Stmicroelectronics, Inc. Method of forming a fully substrate-isolated FinFET transistor
US9076813B1 (en) 2013-01-15 2015-07-07 Stc.Unm Gate-all-around metal-oxide-semiconductor transistors with gate oxides
US9123633B2 (en) 2013-02-01 2015-09-01 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for forming semiconductor regions in trenches
US9159824B2 (en) 2013-02-27 2015-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs with strained well regions
US9087902B2 (en) 2013-02-27 2015-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs with strained well regions
JP6309299B2 (ja) * 2013-02-27 2018-04-11 ルネサスエレクトロニクス株式会社 圧縮歪みチャネル領域を有する半導体装置及びその製造方法
US9385234B2 (en) 2013-02-27 2016-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs with strained well regions
US8963258B2 (en) * 2013-03-13 2015-02-24 Taiwan Semiconductor Manufacturing Company FinFET with bottom SiGe layer in source/drain
US9111801B2 (en) 2013-04-04 2015-08-18 Stmicroelectronics, Inc. Integrated circuit devices and fabrication techniques
US8796666B1 (en) * 2013-04-26 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. MOS devices with strain buffer layer and methods of forming the same
US9276087B2 (en) 2013-05-10 2016-03-01 Samsung Electronics Co., Ltd. Methods of manufacturing FINFET semiconductor devices using sacrificial gate patterns and selective oxidization of a fin
CN104217948B (zh) * 2013-05-31 2018-04-03 中国科学院微电子研究所 半导体制造方法
US9178043B2 (en) 2013-06-21 2015-11-03 Taiwan Semiconductor Manufacturing Company, Ltd. Non-planar transistors with replacement fins and methods of forming the same
US8957478B2 (en) 2013-06-24 2015-02-17 International Business Machines Corporation Semiconductor device including source/drain formed on bulk and gate channel formed on oxide layer
KR102098900B1 (ko) * 2013-06-28 2020-04-08 인텔 코포레이션 측방향 에피택시 과도성장 영역에서의 결함 없는 핀 기반 디바이스의 제조
US9263455B2 (en) 2013-07-23 2016-02-16 Micron Technology, Inc. Methods of forming an array of conductive lines and methods of forming an array of recessed access gate lines
US8952420B1 (en) 2013-07-29 2015-02-10 Stmicroelectronics, Inc. Method to induce strain in 3-D microfabricated structures
CN104347709B (zh) * 2013-08-09 2018-09-04 联华电子股份有限公司 半导体装置
US9105582B2 (en) 2013-08-15 2015-08-11 United Microelectronics Corporation Spatial semiconductor structure and method of fabricating the same
US9496397B2 (en) 2013-08-20 2016-11-15 Taiwan Semiconductor Manufacturing Co., Ltd. FinFet device with channel epitaxial region
US9099559B2 (en) 2013-09-16 2015-08-04 Stmicroelectronics, Inc. Method to induce strain in finFET channels from an adjacent region
CN105493251A (zh) * 2013-09-27 2016-04-13 英特尔公司 具有多层柔性衬底的非平面半导体器件
US9425042B2 (en) 2013-10-10 2016-08-23 Taiwan Semiconductor Manufacturing Company Limited Hybrid silicon germanium substrate for device fabrication
US9425257B2 (en) * 2013-11-20 2016-08-23 Taiwan Semiconductor Manufacturing Company Limited Non-planar SiGe channel PFET
US9508854B2 (en) * 2013-12-06 2016-11-29 Ecole Polytechnique Federale De Lausanne (Epfl) Single field effect transistor capacitor-less memory device and method of operating the same
US20150162435A1 (en) * 2013-12-09 2015-06-11 Globalfoundries Inc. Asymmetric channel growth of a cladding layer over fins of a field effect transistor (finfet) device
CN105723514B (zh) * 2013-12-16 2019-12-10 英特尔公司 用于半导体器件的双应变包覆层
CN105723500B (zh) * 2013-12-16 2019-11-12 英特尔公司 不具有弛豫衬底的nmos和pmos应变器件
KR102094535B1 (ko) 2014-03-21 2020-03-30 삼성전자주식회사 트랜지스터 및 그 제조 방법
US10153372B2 (en) * 2014-03-27 2018-12-11 Intel Corporation High mobility strained channels for fin-based NMOS transistors
US9490346B2 (en) 2014-06-12 2016-11-08 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of fin-like field effect transistor
US9502538B2 (en) 2014-06-12 2016-11-22 Taiwan Semiconductor Manufacturing Co., Ltd Structure and formation method of fin-like field effect transistor
US9490365B2 (en) * 2014-06-12 2016-11-08 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of fin-like field effect transistor
KR102218368B1 (ko) 2014-06-20 2021-02-22 인텔 코포레이션 고전압 트랜지스터들 및 저전압 비평면 트랜지스터들의 모놀리식 집적
KR102155327B1 (ko) * 2014-07-07 2020-09-11 삼성전자주식회사 전계 효과 트랜지스터 및 그 제조 방법
US9306067B2 (en) 2014-08-05 2016-04-05 Taiwan Semiconductor Manufacturing Company, Ltd. Nonplanar device and strain-generating channel dielectric
CN105355658B (zh) * 2014-08-18 2019-10-18 联华电子股份有限公司 鳍状场效晶体管元件及其制造方法
US9634125B2 (en) 2014-09-18 2017-04-25 United Microelectronics Corporation Fin field effect transistor device and fabrication method thereof
KR102255174B1 (ko) * 2014-10-10 2021-05-24 삼성전자주식회사 활성 영역을 갖는 반도체 소자 및 그 형성 방법
US9502567B2 (en) 2015-02-13 2016-11-22 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor fin structure with extending gate structure
US9929242B2 (en) 2015-01-12 2018-03-27 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
KR102235612B1 (ko) 2015-01-29 2021-04-02 삼성전자주식회사 일-함수 금속을 갖는 반도체 소자 및 그 형성 방법
CN105990240B (zh) * 2015-03-04 2019-06-28 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制备方法、电子装置
US10833175B2 (en) * 2015-06-04 2020-11-10 International Business Machines Corporation Formation of dislocation-free SiGe finFET using porous silicon
US10411135B2 (en) 2015-06-08 2019-09-10 Synopsys, Inc. Substrates and transistors with 2D material channels on 3D geometries
US9425313B1 (en) 2015-07-07 2016-08-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US9953881B2 (en) 2015-07-20 2018-04-24 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a FinFET device
US9548216B1 (en) 2015-07-26 2017-01-17 United Microelectronics Corp. Method of adjusting channel widths of semiconductive devices
CN107924944B (zh) 2015-09-11 2021-03-30 英特尔公司 磷化铝铟子鳍状物锗沟道晶体管
KR102465353B1 (ko) 2015-12-02 2022-11-10 삼성전자주식회사 전계 효과 트랜지스터 및 이를 포함하는 반도체 소자
US20170236841A1 (en) * 2016-02-11 2017-08-17 Qualcomm Incorporated Fin with an epitaxial cladding layer
EP3472867A4 (en) 2016-06-17 2020-12-02 INTEL Corporation SELF-ALIGNED GATE ELECTRODE FIELD-EFFECT TRANSISTORS ON A SEMICONDUCTOR FIN
KR101846991B1 (ko) 2016-08-11 2018-04-09 가천대학교 산학협력단 벌크 실리콘 기반의 실리콘 게르마늄 ｐ-채널 삼중 게이트 트랜지스터 및 그 제조방법
WO2018063192A1 (en) * 2016-09-28 2018-04-05 Intel Corporation Transistors with lattice matched gate structure
US11538905B2 (en) 2016-09-30 2022-12-27 Intel Corporation Nanowire transistors employing carbon-based layers
US11004954B2 (en) * 2016-09-30 2021-05-11 Intel Corporation Epitaxial buffer to reduce sub-channel leakage in MOS transistors
US9847392B1 (en) * 2016-10-11 2017-12-19 United Microelectronics Corp. Semiconductor device and method for fabricating the same
CN108063143B (zh) * 2016-11-09 2020-06-05 上海新昇半导体科技有限公司 一种互补晶体管器件结构及其制作方法
US10741560B2 (en) * 2017-10-26 2020-08-11 International Business Machines Corporation High resistance readout FET for cognitive device
US11171207B2 (en) * 2017-12-20 2021-11-09 Intel Corporation Transistor with isolation below source and drain
US10727352B2 (en) * 2018-01-26 2020-07-28 International Business Machines Corporation Long-channel fin field effect transistors
US11378750B2 (en) * 2020-01-17 2022-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. Germanium photodetector embedded in a multi-mode interferometer
US11257932B2 (en) * 2020-01-30 2022-02-22 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor device structure and method for forming the same
CN111509048A (zh) * 2020-04-28 2020-08-07 上海华力集成电路制造有限公司 N型鳍式晶体管及其制造方法

Family Cites Families (375)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4231149A (en) 1978-10-10 1980-11-04 Texas Instruments Incorporated Narrow band-gap semiconductor CCD imaging device and method of fabrication
GB2156149A (en) 1984-03-14 1985-10-02 Philips Electronic Associated Dielectrically-isolated integrated circuit manufacture
US4487652A (en) 1984-03-30 1984-12-11 Motorola, Inc. Slope etch of polyimide
US4711701A (en) 1986-09-16 1987-12-08 Texas Instruments Incorporated Self-aligned transistor method
US5514885A (en) 1986-10-09 1996-05-07 Myrick; James J. SOI methods and apparatus
US4818715A (en) 1987-07-09 1989-04-04 Industrial Technology Research Institute Method of fabricating a LDDFET with self-aligned silicide
US4907048A (en) 1987-11-23 1990-03-06 Xerox Corporation Double implanted LDD transistor self-aligned with gate
US4905063A (en) 1988-06-21 1990-02-27 American Telephone And Telegraph Company, At&T Bell Laboratories Floating gate memories
JPH0214578A (ja) 1988-07-01 1990-01-18 Fujitsu Ltd 半導体装置
KR910010043B1 (ko) 1988-07-28 1991-12-10 한국전기통신공사 스페이서를 이용한 미세선폭 형성방법
US4994873A (en) 1988-10-17 1991-02-19 Motorola, Inc. Local interconnect for stacked polysilicon device
US5346834A (en) 1988-11-21 1994-09-13 Hitachi, Ltd. Method for manufacturing a semiconductor device and a semiconductor memory device
US4906589A (en) 1989-02-06 1990-03-06 Industrial Technology Research Institute Inverse-T LDDFET with self-aligned silicide
JPH02302044A (ja) 1989-05-16 1990-12-14 Fujitsu Ltd 半導体装置の製造方法
US5328810A (en) 1990-05-07 1994-07-12 Micron Technology, Inc. Method for reducing, by a factor or 2-N, the minimum masking pitch of a photolithographic process
KR930003790B1 (ko) * 1990-07-02 1993-05-10 삼성전자 주식회사 반도체 장치의 캐패시터용 유전체
US5278102A (en) 1990-08-18 1994-01-11 Fujitsu Limited SOI device and a fabrication process thereof
JP3061406B2 (ja) 1990-09-28 2000-07-10 株式会社東芝 半導体装置
JP3202223B2 (ja) * 1990-11-27 2001-08-27 日本電気株式会社 トランジスタの製造方法
US5521859A (en) 1991-03-20 1996-05-28 Fujitsu Limited Semiconductor memory device having thin film transistor and method of producing the same
JPH05152293A (ja) 1991-04-30 1993-06-18 Sgs Thomson Microelectron Inc 段差付き壁相互接続体及びゲートの製造方法
US5346836A (en) 1991-06-06 1994-09-13 Micron Technology, Inc. Process for forming low resistance contacts between silicide areas and upper level polysilicon interconnects
US5292670A (en) * 1991-06-10 1994-03-08 Texas Instruments Incorporated Sidewall doping technique for SOI transistors
US5179037A (en) 1991-12-24 1993-01-12 Texas Instruments Incorporated Integration of lateral and vertical quantum well transistors in the same epitaxial stack
US5391506A (en) 1992-01-31 1995-02-21 Kawasaki Steel Corporation Manufacturing method for semiconductor devices with source/drain formed in substrate projection.
JPH05243572A (ja) 1992-02-27 1993-09-21 Fujitsu Ltd 半導体装置
US5405454A (en) 1992-03-19 1995-04-11 Matsushita Electric Industrial Co., Ltd. Electrically insulated silicon structure and producing method therefor
JP2572003B2 (ja) 1992-03-30 1997-01-16 三星電子株式会社 三次元マルチチャンネル構造を有する薄膜トランジスタの製造方法
JPH0793441B2 (ja) * 1992-04-24 1995-10-09 ヒュンダイ エレクトロニクス インダストリーズ カンパニー リミテッド 薄膜トランジスタ及びその製造方法
JPH06177089A (ja) 1992-12-04 1994-06-24 Fujitsu Ltd 半導体装置の製造方法
KR960002088B1 (ko) 1993-02-17 1996-02-10 삼성전자주식회사 에스오아이(SOI : silicon on insulator) 구조의 반도체 장치 제조방법
US5357119A (en) 1993-02-19 1994-10-18 Board Of Regents Of The University Of California Field effect devices having short period superlattice structures using Si and Ge
JPH06310547A (ja) 1993-02-25 1994-11-04 Mitsubishi Electric Corp 半導体装置及びその製造方法
JPH0750421A (ja) 1993-05-06 1995-02-21 Siemens Ag Ｍｏｓ形電界効果トランジスタ
US5739544A (en) 1993-05-26 1998-04-14 Matsushita Electric Industrial Co., Ltd. Quantization functional device utilizing a resonance tunneling effect and method for producing the same
US5475869A (en) 1993-05-28 1995-12-12 Nec Corporation Radio base station capable of distinguishing between interference due to collisions of outgoing call signals and an external interference noise
US6730549B1 (en) * 1993-06-25 2004-05-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for its preparation
JP3778581B2 (ja) 1993-07-05 2006-05-24 三菱電機株式会社 半導体装置およびその製造方法
JP3460863B2 (ja) * 1993-09-17 2003-10-27 三菱電機株式会社 半導体装置の製造方法
US5888304A (en) * 1996-04-02 1999-03-30 Applied Materials, Inc. Heater with shadow ring and purge above wafer surface
US5479033A (en) 1994-05-27 1995-12-26 Sandia Corporation Complementary junction heterostructure field-effect transistor
JP3361922B2 (ja) 1994-09-13 2003-01-07 株式会社東芝 半導体装置
JP3378414B2 (ja) 1994-09-14 2003-02-17 株式会社東芝 半導体装置
JPH08153880A (ja) 1994-09-29 1996-06-11 Toshiba Corp 半導体装置及びその製造方法
US5602049A (en) 1994-10-04 1997-02-11 United Microelectronics Corporation Method of fabricating a buried structure SRAM cell
JPH08125152A (ja) 1994-10-28 1996-05-17 Canon Inc 半導体装置、それを用いた相関演算装置、ａｄ変換器、ｄａ変換器、信号処理システム
US5576227A (en) 1994-11-02 1996-11-19 United Microelectronics Corp. Process for fabricating a recessed gate MOS device
JP3078720B2 (ja) 1994-11-02 2000-08-21 三菱電機株式会社 半導体装置およびその製造方法
GB2295488B (en) * 1994-11-24 1996-11-20 Toshiba Cambridge Res Center Semiconductor device
US5716879A (en) * 1994-12-15 1998-02-10 Goldstar Electron Company, Ltd. Method of making a thin film transistor
JPH08204191A (ja) 1995-01-20 1996-08-09 Sony Corp 電界効果トランジスタ及びその製造方法
US5665203A (en) 1995-04-28 1997-09-09 International Business Machines Corporation Silicon etching method
JP3303601B2 (ja) 1995-05-19 2002-07-22 日産自動車株式会社 溝型半導体装置
KR0165398B1 (ko) 1995-05-26 1998-12-15 윤종용 버티칼 트랜지스터의 제조방법
US5658806A (en) * 1995-10-26 1997-08-19 National Science Council Method for fabricating thin-film transistor with bottom-gate or dual-gate configuration
US5814895A (en) 1995-12-22 1998-09-29 Sony Corporation Static random access memory having transistor elements formed on side walls of a trench in a semiconductor substrate
KR100205442B1 (ko) 1995-12-26 1999-07-01 구본준 박막트랜지스터 및 그의 제조방법
US5595919A (en) 1996-02-20 1997-01-21 Chartered Semiconductor Manufacturing Pte Ltd. Method of making self-aligned halo process for reducing junction capacitance
DE19607209A1 (de) * 1996-02-26 1997-08-28 Gregor Kohlruss Reinigungsvorrichtung zum Reinigen von flächigen Gegenständen
JPH09293793A (ja) 1996-04-26 1997-11-11 Mitsubishi Electric Corp 薄膜トランジスタを有する半導体装置およびその製造方法
US5793088A (en) 1996-06-18 1998-08-11 Integrated Device Technology, Inc. Structure for controlling threshold voltage of MOSFET
JP3710880B2 (ja) 1996-06-28 2005-10-26 株式会社東芝 不揮発性半導体記憶装置
TW548686B (en) 1996-07-11 2003-08-21 Semiconductor Energy Lab CMOS semiconductor device and apparatus using the same
US5817560A (en) 1996-09-12 1998-10-06 Advanced Micro Devices, Inc. Ultra short trench transistors and process for making same
US6399970B2 (en) 1996-09-17 2002-06-04 Matsushita Electric Industrial Co., Ltd. FET having a Si/SiGeC heterojunction channel
US6063675A (en) 1996-10-28 2000-05-16 Texas Instruments Incorporated Method of forming a MOSFET using a disposable gate with a sidewall dielectric
US6163053A (en) 1996-11-06 2000-12-19 Ricoh Company, Ltd. Semiconductor device having opposite-polarity region under channel
JPH10150185A (ja) 1996-11-20 1998-06-02 Mitsubishi Electric Corp 半導体装置及びその製造方法
US5827769A (en) 1996-11-20 1998-10-27 Intel Corporation Method for fabricating a transistor with increased hot carrier resistance by nitridizing and annealing the sidewall oxide of the gate electrode
US5773331A (en) 1996-12-17 1998-06-30 International Business Machines Corporation Method for making single and double gate field effect transistors with sidewall source-drain contacts
US5908313A (en) 1996-12-31 1999-06-01 Intel Corporation Method of forming a transistor
JP4086926B2 (ja) 1997-01-29 2008-05-14 富士通株式会社 半導体装置及びその製造方法
JPH118390A (ja) 1997-06-18 1999-01-12 Mitsubishi Electric Corp 半導体装置及びその製造方法
US6251763B1 (en) 1997-06-30 2001-06-26 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing same
US6054355A (en) 1997-06-30 2000-04-25 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device which includes forming a dummy gate
JPH1140811A (ja) * 1997-07-22 1999-02-12 Hitachi Ltd 半導体装置およびその製造方法
US5952701A (en) 1997-08-18 1999-09-14 National Semiconductor Corporation Design and fabrication of semiconductor structure having complementary channel-junction insulated-gate field-effect transistors whose gate electrodes have work functions close to mid-gap semiconductor value
US5776821A (en) 1997-08-22 1998-07-07 Vlsi Technology, Inc. Method for forming a reduced width gate electrode
US6066869A (en) 1997-10-06 2000-05-23 Micron Technology, Inc. Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor
US5976767A (en) 1997-10-09 1999-11-02 Micron Technology, Inc. Ammonium hydroxide etch of photoresist masked silicon
US5856225A (en) 1997-11-24 1999-01-05 Chartered Semiconductor Manufacturing Ltd Creation of a self-aligned, ion implanted channel region, after source and drain formation
US6120846A (en) 1997-12-23 2000-09-19 Advanced Technology Materials, Inc. Method for the selective deposition of bismuth based ferroelectric thin films by chemical vapor deposition
US5888309A (en) 1997-12-29 1999-03-30 Taiwan Semiconductor Manufacturing Company, Ltd. Lateral etch inhibited multiple for forming a via through a microelectronics layer susceptible to etching within a fluorine containing plasma followed by an oxygen containing plasma
US6117741A (en) 1998-01-09 2000-09-12 Texas Instruments Incorporated Method of forming a transistor having an improved sidewall gate structure
US6294416B1 (en) 1998-01-23 2001-09-25 Texas Instruments-Acer Incorporated Method of fabricating CMOS transistors with self-aligned planarization twin-well by using fewer mask counts
US6097065A (en) * 1998-03-30 2000-08-01 Micron Technology, Inc. Circuits and methods for dual-gated transistors
US6307235B1 (en) 1998-03-30 2001-10-23 Micron Technology, Inc. Another technique for gated lateral bipolar transistors
US6087208A (en) 1998-03-31 2000-07-11 Advanced Micro Devices, Inc. Method for increasing gate capacitance by using both high and low dielectric gate material
US6215190B1 (en) 1998-05-12 2001-04-10 International Business Machines Corporation Borderless contact to diffusion with respect to gate conductor and methods for fabricating
US6232641B1 (en) 1998-05-29 2001-05-15 Kabushiki Kaisha Toshiba Semiconductor apparatus having elevated source and drain structure and manufacturing method therefor
US6114201A (en) 1998-06-01 2000-09-05 Texas Instruments-Acer Incorporated Method of manufacturing a multiple fin-shaped capacitor for high density DRAMs
US6317444B1 (en) 1998-06-12 2001-11-13 Agere System Optoelectronics Guardian Corp. Optical device including carbon-doped contact layers
US6165880A (en) 1998-06-15 2000-12-26 Taiwan Semiconductor Manufacturing Company Double spacer technology for making self-aligned contacts (SAC) on semiconductor integrated circuits
US6130123A (en) 1998-06-30 2000-10-10 Intel Corporation Method for making a complementary metal gate electrode technology
JP2000037842A (ja) 1998-07-27 2000-02-08 Dainippon Printing Co Ltd 電磁波吸収化粧材
US6696366B1 (en) 1998-08-17 2004-02-24 Lam Research Corporation Technique for etching a low capacitance dielectric layer
JP2000156502A (ja) 1998-09-21 2000-06-06 Texas Instr Inc <Ti> 集積回路及び方法
US5985726A (en) 1998-11-06 1999-11-16 Advanced Micro Devices, Inc. Damascene process for forming ultra-shallow source/drain extensions and pocket in ULSI MOSFET
US6114206A (en) 1998-11-06 2000-09-05 Advanced Micro Devices, Inc. Multiple threshold voltage transistor implemented by a damascene process
US6262456B1 (en) 1998-11-06 2001-07-17 Advanced Micro Devices, Inc. Integrated circuit having transistors with different threshold voltages
US6153485A (en) 1998-11-09 2000-11-28 Chartered Semiconductor Manufacturing Ltd. Salicide formation on narrow poly lines by pulling back of spacer
US6200865B1 (en) 1998-12-04 2001-03-13 Advanced Micro Devices, Inc. Use of sacrificial dielectric structure to form semiconductor device with a self-aligned threshold adjust and overlying low-resistance gate
US6362111B1 (en) 1998-12-09 2002-03-26 Texas Instruments Incorporated Tunable gate linewidth reduction process
TW449919B (en) 1998-12-18 2001-08-11 Koninkl Philips Electronics Nv A method of manufacturing a semiconductor device
TW406312B (en) 1998-12-18 2000-09-21 United Microelectronics Corp The method of etching doped poly-silicon
US6380558B1 (en) * 1998-12-29 2002-04-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of fabricating the same
US6150222A (en) 1999-01-07 2000-11-21 Advanced Micro Devices, Inc. Method of making a high performance transistor with elevated spacer formation and self-aligned channel regions
FR2788629B1 (fr) 1999-01-15 2003-06-20 Commissariat Energie Atomique Transistor mis et procede de fabrication d'un tel transistor sur un substrat semiconducteur
US6174820B1 (en) 1999-02-16 2001-01-16 Sandia Corporation Use of silicon oxynitride as a sacrificial material for microelectromechanical devices
JP2000243854A (ja) 1999-02-22 2000-09-08 Toshiba Corp 半導体装置及びその製造方法
US6093621A (en) 1999-04-05 2000-07-25 Vanguard International Semiconductor Corp. Method of forming shallow trench isolation
US7045468B2 (en) 1999-04-09 2006-05-16 Intel Corporation Isolated junction structure and method of manufacture
US6459123B1 (en) 1999-04-30 2002-10-01 Infineon Technologies Richmond, Lp Double gated transistor
EP1063697B1 (en) 1999-06-18 2003-03-12 Lucent Technologies Inc. A process for fabricating a CMOS integrated circuit having vertical transistors
JP2001015704A (ja) 1999-06-29 2001-01-19 Hitachi Ltd 半導体集積回路
US6218309B1 (en) 1999-06-30 2001-04-17 Lam Research Corporation Method of achieving top rounding and uniform etch depths while etching shallow trench isolation features
US6501131B1 (en) 1999-07-22 2002-12-31 International Business Machines Corporation Transistors having independently adjustable parameters
TW432594B (en) 1999-07-31 2001-05-01 Taiwan Semiconductor Mfg Manufacturing method for shallow trench isolation
US6259135B1 (en) 1999-09-24 2001-07-10 International Business Machines Corporation MOS transistors structure for reducing the size of pitch limited circuits
FR2799305B1 (fr) 1999-10-05 2004-06-18 St Microelectronics Sa Procede de fabrication d'un dispositif semi-conducteur a grille enveloppante et dispositif obtenu
EP1091413A3 (en) 1999-10-06 2005-01-12 Lsi Logic Corporation Fully-depleted, fully-inverted, short-length and vertical channel, dual-gate, cmos fet
US6541829B2 (en) 1999-12-03 2003-04-01 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US6252284B1 (en) 1999-12-09 2001-06-26 International Business Machines Corporation Planarized silicon fin device
KR100311049B1 (ko) 1999-12-13 2001-10-12 윤종용 불휘발성 반도체 메모리장치 및 그의 제조방법
US6303479B1 (en) 1999-12-16 2001-10-16 Spinnaker Semiconductor, Inc. Method of manufacturing a short-channel FET with Schottky-barrier source and drain contacts
JP4923318B2 (ja) 1999-12-17 2012-04-25 ソニー株式会社 不揮発性半導体記憶装置およびその動作方法
JP4194237B2 (ja) 1999-12-28 2008-12-10 株式会社リコー 電界効果トランジスタを用いた電圧発生回路及び基準電圧源回路
US7391087B2 (en) 1999-12-30 2008-06-24 Intel Corporation MOS transistor structure and method of fabrication
JP3613113B2 (ja) 2000-01-21 2005-01-26 日本電気株式会社 半導体装置およびその製造方法
US6319807B1 (en) 2000-02-07 2001-11-20 United Microelectronics Corp. Method for forming a semiconductor device by using reverse-offset spacer process
JP3846706B2 (ja) * 2000-02-23 2006-11-15 信越半導体株式会社 ウエーハ外周面取部の研磨方法及び研磨装置
US6483156B1 (en) * 2000-03-16 2002-11-19 International Business Machines Corporation Double planar gated SOI MOSFET structure
FR2806832B1 (fr) 2000-03-22 2002-10-25 Commissariat Energie Atomique Transistor mos a source et drain metalliques, et procede de fabrication d'un tel transistor
JP3906005B2 (ja) 2000-03-27 2007-04-18 株式会社東芝 半導体装置の製造方法
KR100332834B1 (ko) 2000-03-29 2002-04-15 윤덕용 비등방성 식각을 이용한 서브마이크론 게이트 제조 방법
TW466606B (en) 2000-04-20 2001-12-01 United Microelectronics Corp Manufacturing method for dual metal gate electrode
JP2001338987A (ja) 2000-05-26 2001-12-07 Nec Microsystems Ltd Ｍｏｓトランジスタのシャロートレンチ分離領域の形成方法
FR2810161B1 (fr) 2000-06-09 2005-03-11 Commissariat Energie Atomique Memoire electronique a architecture damascene et procede de realisation d'une telle memoire
US6526996B1 (en) 2000-06-12 2003-03-04 Promos Technologies, Inc. Dry clean method instead of traditional wet clean after metal etch
US6391782B1 (en) 2000-06-20 2002-05-21 Advanced Micro Devices, Inc. Process for forming multiple active lines and gate-all-around MOSFET
KR100545706B1 (ko) 2000-06-28 2006-01-24 주식회사 하이닉스반도체 반도체 소자 제조방법
WO2002003482A1 (de) 2000-07-04 2002-01-10 Infineon Technologies Ag Feldeffekttransistor
US20020011612A1 (en) * 2000-07-31 2002-01-31 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
JP2002047034A (ja) 2000-07-31 2002-02-12 Shinetsu Quartz Prod Co Ltd プラズマを利用したプロセス装置用の石英ガラス治具
US6403981B1 (en) 2000-08-07 2002-06-11 Advanced Micro Devices, Inc. Double gate transistor having a silicon/germanium channel region
KR100338778B1 (ko) 2000-08-21 2002-05-31 윤종용 선택적 실리사이드 공정을 이용한 모스 트랜지스터의제조방법
US6358800B1 (en) 2000-09-18 2002-03-19 Vanguard International Semiconductor Corporation Method of forming a MOSFET with a recessed-gate having a channel length beyond photolithography limit
US6387820B1 (en) 2000-09-19 2002-05-14 Advanced Micro Devices, Inc. BC13/AR chemistry for metal overetching on a high density plasma etcher
JP2002100762A (ja) 2000-09-22 2002-04-05 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP4044276B2 (ja) * 2000-09-28 2008-02-06 株式会社東芝 半導体装置及びその製造方法
US6562665B1 (en) * 2000-10-16 2003-05-13 Advanced Micro Devices, Inc. Fabrication of a field effect transistor with a recess in a semiconductor pillar in SOI technology
US7163864B1 (en) 2000-10-18 2007-01-16 International Business Machines Corporation Method of fabricating semiconductor side wall fin
US6645840B2 (en) 2000-10-19 2003-11-11 Texas Instruments Incorporated Multi-layered polysilicon process
US6413802B1 (en) * 2000-10-23 2002-07-02 The Regents Of The University Of California Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture
US6716684B1 (en) * 2000-11-13 2004-04-06 Advanced Micro Devices, Inc. Method of making a self-aligned triple gate silicon-on-insulator device
US6396108B1 (en) 2000-11-13 2002-05-28 Advanced Micro Devices, Inc. Self-aligned double gate silicon-on-insulator (SOI) device
US6472258B1 (en) 2000-11-13 2002-10-29 International Business Machines Corporation Double gate trench transistor
US6479866B1 (en) 2000-11-14 2002-11-12 Advanced Micro Devices, Inc. SOI device with self-aligned selective damage implant, and method
JP2002198441A (ja) 2000-11-16 2002-07-12 Hynix Semiconductor Inc 半導体素子のデュアル金属ゲート形成方法
WO2002043151A1 (en) 2000-11-22 2002-05-30 Hitachi, Ltd Semiconductor device and method for fabricating the same
US6552401B1 (en) 2000-11-27 2003-04-22 Micron Technology Use of gate electrode workfunction to improve DRAM refresh
US20020100942A1 (en) 2000-12-04 2002-08-01 Fitzgerald Eugene A. CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
US6921947B2 (en) 2000-12-15 2005-07-26 Renesas Technology Corp. Semiconductor device having recessed isolation insulation film
US6413877B1 (en) 2000-12-22 2002-07-02 Lam Research Corporation Method of preventing damage to organo-silicate-glass materials during resist stripping
JP2002198368A (ja) * 2000-12-26 2002-07-12 Nec Corp 半導体装置の製造方法
US6537901B2 (en) 2000-12-29 2003-03-25 Hynix Semiconductor Inc. Method of manufacturing a transistor in a semiconductor device
TW561530B (en) 2001-01-03 2003-11-11 Macronix Int Co Ltd Process for fabricating CMOS transistor of IC devices employing double spacers for preventing short-channel effect
US6975014B1 (en) 2001-01-09 2005-12-13 Advanced Micro Devices, Inc. Method for making an ultra thin FDSOI device with improved short-channel performance
US6359311B1 (en) 2001-01-17 2002-03-19 Taiwan Semiconductor Manufacturing Co., Ltd. Quasi-surrounding gate and a method of fabricating a silicon-on-insulator semiconductor device with the same
US6403434B1 (en) 2001-02-09 2002-06-11 Advanced Micro Devices, Inc. Process for manufacturing MOS transistors having elevated source and drain regions and a high-k gate dielectric
US6475890B1 (en) 2001-02-12 2002-11-05 Advanced Micro Devices, Inc. Fabrication of a field effect transistor with an upside down T-shaped semiconductor pillar in SOI technology
JP2002246310A (ja) 2001-02-14 2002-08-30 Sony Corp 半導体薄膜の形成方法及び半導体装置の製造方法、これらの方法の実施に使用する装置、並びに電気光学装置
US6475869B1 (en) * 2001-02-26 2002-11-05 Advanced Micro Devices, Inc. Method of forming a double gate transistor having an epitaxial silicon/germanium channel region
FR2822293B1 (fr) 2001-03-13 2007-03-23 Nat Inst Of Advanced Ind Scien Transistor a effet de champ et double grille, circuit integre comportant ce transistor, et procede de fabrication de ce dernier
TW582071B (en) 2001-03-20 2004-04-01 Macronix Int Co Ltd Method for etching metal in a semiconductor
JP3940565B2 (ja) 2001-03-29 2007-07-04 株式会社東芝 半導体装置及びその製造方法
JP2002298051A (ja) 2001-03-30 2002-10-11 Mizuho Bank Ltd ポイント交換サービス・システム
US6458662B1 (en) 2001-04-04 2002-10-01 Advanced Micro Devices, Inc. Method of fabricating a semiconductor device having an asymmetrical dual-gate silicon-germanium (SiGe) channel MOSFET and a device thereby formed
KR100414217B1 (ko) 2001-04-12 2004-01-07 삼성전자주식회사 게이트 올 어라운드형 트랜지스터를 가진 반도체 장치 및그 형성 방법
US6645861B2 (en) 2001-04-18 2003-11-11 International Business Machines Corporation Self-aligned silicide process for silicon sidewall source and drain contacts
US6787402B1 (en) 2001-04-27 2004-09-07 Advanced Micro Devices, Inc. Double-gate vertical MOSFET transistor and fabrication method
US6902947B2 (en) 2001-05-07 2005-06-07 Applied Materials, Inc. Integrated method for release and passivation of MEMS structures
SG112804A1 (en) 2001-05-10 2005-07-28 Inst Of Microelectronics Sloped trench etching process
KR100363332B1 (en) 2001-05-23 2002-12-05 Samsung Electronics Co Ltd Method for forming semiconductor device having gate all-around type transistor
US6635923B2 (en) 2001-05-24 2003-10-21 International Business Machines Corporation Damascene double-gate MOSFET with vertical channel regions
US6506692B2 (en) 2001-05-30 2003-01-14 Intel Corporation Method of making a semiconductor device using a silicon carbide hard mask
US6737333B2 (en) 2001-07-03 2004-05-18 Texas Instruments Incorporated Semiconductor device isolation structure and method of forming
JP2003017508A (ja) 2001-07-05 2003-01-17 Nec Corp 電界効果トランジスタ
US6501141B1 (en) 2001-08-13 2002-12-31 Taiwan Semiconductor Manufacturing Company, Ltd Self-aligned contact with improved isolation and method for forming
US6534807B2 (en) 2001-08-13 2003-03-18 International Business Machines Corporation Local interconnect junction on insulator (JOI) structure
JP2003100902A (ja) 2001-09-21 2003-04-04 Mitsubishi Electric Corp 半導体装置の製造方法
US6689650B2 (en) * 2001-09-27 2004-02-10 International Business Machines Corporation Fin field effect transistor with self-aligned gate
US6492212B1 (en) 2001-10-05 2002-12-10 International Business Machines Corporation Variable threshold voltage double gated transistors and method of fabrication
US20030085194A1 (en) * 2001-11-07 2003-05-08 Hopkins Dean A. Method for fabricating close spaced mirror arrays
US7385262B2 (en) 2001-11-27 2008-06-10 The Board Of Trustees Of The Leland Stanford Junior University Band-structure modulation of nano-structures in an electric field
US6967351B2 (en) 2001-12-04 2005-11-22 International Business Machines Corporation Finfet SRAM cell using low mobility plane for cell stability and method for forming
US6657259B2 (en) 2001-12-04 2003-12-02 International Business Machines Corporation Multiple-plane FinFET CMOS
US6610576B2 (en) 2001-12-13 2003-08-26 International Business Machines Corporation Method for forming asymmetric dual gate transistor
EP1321310A1 (de) * 2001-12-21 2003-06-25 Schächter, Friedrich Prüfverfahren für Schreibgeräte
US6555879B1 (en) 2002-01-11 2003-04-29 Advanced Micro Devices, Inc. SOI device with metal source/drain and method of fabrication
US6722946B2 (en) 2002-01-17 2004-04-20 Nutool, Inc. Advanced chemical mechanical polishing system with smart endpoint detection
US6583469B1 (en) 2002-01-28 2003-06-24 International Business Machines Corporation Self-aligned dog-bone structure for FinFET applications and methods to fabricate the same
KR100442089B1 (ko) 2002-01-29 2004-07-27 삼성전자주식회사 노치된 게이트 전극을 갖는 모스 트랜지스터의 제조방법
KR100458288B1 (ko) * 2002-01-30 2004-11-26 한국과학기술원 이중-게이트 ＦｉｎＦＥＴ 소자 및 그 제조방법
DE10203998A1 (de) 2002-02-01 2003-08-21 Infineon Technologies Ag Verfahren zum Herstellen einer zackenförmigen Struktur, Verfahren zum Herstellen eines Transistors, Verfahren zum Herstellen eines Floating Gate-Transistors, Transistor, Floating Gate-Transistor und Speicher-Anordnung
US6784071B2 (en) 2003-01-31 2004-08-31 Taiwan Semiconductor Manufacturing Company, Ltd. Bonded SOI wafer with <100> device layer and <110> substrate for performance improvement
US20030151077A1 (en) 2002-02-13 2003-08-14 Leo Mathew Method of forming a vertical double gate semiconductor device and structure thereof
JP3782021B2 (ja) * 2002-02-22 2006-06-07 株式会社東芝 半導体装置、半導体装置の製造方法、半導体基板の製造方法
US6660598B2 (en) 2002-02-26 2003-12-09 International Business Machines Corporation Method of forming a fully-depleted SOI ( silicon-on-insulator) MOSFET having a thinned channel region
JP4370104B2 (ja) 2002-03-05 2009-11-25 シャープ株式会社 半導体記憶装置
US6639827B2 (en) 2002-03-12 2003-10-28 Intel Corporation Low standby power using shadow storage
US6635909B2 (en) 2002-03-19 2003-10-21 International Business Machines Corporation Strained fin FETs structure and method
US6605498B1 (en) 2002-03-29 2003-08-12 Intel Corporation Semiconductor transistor having a backfilled channel material
FR2838238B1 (fr) 2002-04-08 2005-04-15 St Microelectronics Sa Dispositif semiconducteur a grille enveloppante encapsule dans un milieu isolant
US6784076B2 (en) 2002-04-08 2004-08-31 Micron Technology, Inc. Process for making a silicon-on-insulator ledge by implanting ions from silicon source
US6762469B2 (en) 2002-04-19 2004-07-13 International Business Machines Corporation High performance CMOS device structure with mid-gap metal gate
US6713396B2 (en) 2002-04-29 2004-03-30 Hewlett-Packard Development Company, L.P. Method of fabricating high density sub-lithographic features on a substrate
US6537885B1 (en) 2002-05-09 2003-03-25 Infineon Technologies Ag Transistor and method of manufacturing a transistor having a shallow junction formation using a two step EPI layer
US6642090B1 (en) 2002-06-03 2003-11-04 International Business Machines Corporation Fin FET devices from bulk semiconductor and method for forming
US7074623B2 (en) * 2002-06-07 2006-07-11 Amberwave Systems Corporation Methods of forming strained-semiconductor-on-insulator finFET device structures
US6680240B1 (en) * 2002-06-25 2004-01-20 Advanced Micro Devices, Inc. Silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide
CN1284216C (zh) * 2002-07-01 2006-11-08 台湾积体电路制造股份有限公司 具有伸张应变的沟道层的场效应晶体管结构及其制造方法
US7105891B2 (en) 2002-07-15 2006-09-12 Texas Instruments Incorporated Gate structure and method
US6974729B2 (en) 2002-07-16 2005-12-13 Interuniversitair Microelektronica Centrum (Imec) Integrated semiconductor fin device and a method for manufacturing such device
KR100477543B1 (ko) 2002-07-26 2005-03-18 동부아남반도체 주식회사 단채널 트랜지스터 형성방법
US6919238B2 (en) 2002-07-29 2005-07-19 Intel Corporation Silicon on insulator (SOI) transistor and methods of fabrication
US6921702B2 (en) 2002-07-30 2005-07-26 Micron Technology Inc. Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectrics
JP2004071996A (ja) 2002-08-09 2004-03-04 Hitachi Ltd 半導体集積回路装置の製造方法
US6833556B2 (en) 2002-08-12 2004-12-21 Acorn Technologies, Inc. Insulated gate field effect transistor having passivated schottky barriers to the channel
US6984585B2 (en) 2002-08-12 2006-01-10 Applied Materials Inc Method for removal of residue from a magneto-resistive random access memory (MRAM) film stack using a sacrificial mask layer
US6891234B1 (en) 2004-01-07 2005-05-10 Acorn Technologies, Inc. Transistor with workfunction-induced charge layer
JP3865233B2 (ja) 2002-08-19 2007-01-10 富士通株式会社 Ｃｍｏｓ集積回路装置
US7358121B2 (en) 2002-08-23 2008-04-15 Intel Corporation Tri-gate devices and methods of fabrication
US7163851B2 (en) 2002-08-26 2007-01-16 International Business Machines Corporation Concurrent Fin-FET and thick-body device fabrication
JP5179692B2 (ja) 2002-08-30 2013-04-10 富士通セミコンダクター株式会社 半導体記憶装置及びその製造方法
US6770516B2 (en) 2002-09-05 2004-08-03 Taiwan Semiconductor Manufacturing Company Method of forming an N channel and P channel FINFET device on the same semiconductor substrate
JP3651802B2 (ja) 2002-09-12 2005-05-25 株式会社東芝 半導体装置の製造方法
US6794313B1 (en) 2002-09-20 2004-09-21 Taiwan Semiconductor Manufacturing Company, Ltd. Oxidation process to improve polysilicon sidewall roughness
JP3556651B2 (ja) 2002-09-27 2004-08-18 沖電気工業株式会社 半導体装置の製造方法
US6800910B2 (en) 2002-09-30 2004-10-05 Advanced Micro Devices, Inc. FinFET device incorporating strained silicon in the channel region
KR100481209B1 (ko) 2002-10-01 2005-04-08 삼성전자주식회사 다중 채널을 갖는 모스 트랜지스터 및 그 제조방법
JP4294935B2 (ja) 2002-10-17 2009-07-15 株式会社ルネサステクノロジ 半導体装置
US6706571B1 (en) 2002-10-22 2004-03-16 Advanced Micro Devices, Inc. Method for forming multiple structures in a semiconductor device
US6833588B2 (en) 2002-10-22 2004-12-21 Advanced Micro Devices, Inc. Semiconductor device having a U-shaped gate structure
US6706581B1 (en) 2002-10-29 2004-03-16 Taiwan Semiconductor Manufacturing Company Dual gate dielectric scheme: SiON for high performance devices and high k for low power devices
US6787439B2 (en) 2002-11-08 2004-09-07 Advanced Micro Devices, Inc. Method using planarizing gate material to improve gate critical dimension in semiconductor devices
US6611029B1 (en) 2002-11-08 2003-08-26 Advanced Micro Devices, Inc. Double gate semiconductor device having separate gates
US6855990B2 (en) 2002-11-26 2005-02-15 Taiwan Semiconductor Manufacturing Co., Ltd Strained-channel multiple-gate transistor
US6709982B1 (en) * 2002-11-26 2004-03-23 Advanced Micro Devices, Inc. Double spacer FinFET formation
US6825506B2 (en) 2002-11-27 2004-11-30 Intel Corporation Field effect transistor and method of fabrication
US6821834B2 (en) 2002-12-04 2004-11-23 Yoshiyuki Ando Ion implantation methods and transistor cell layout for fin type transistors
US6645797B1 (en) * 2002-12-06 2003-11-11 Advanced Micro Devices, Inc. Method for forming fins in a FinFET device using sacrificial carbon layer
US7728360B2 (en) 2002-12-06 2010-06-01 Taiwan Semiconductor Manufacturing Co., Ltd. Multiple-gate transistor structure
US6686231B1 (en) 2002-12-06 2004-02-03 Advanced Micro Devices, Inc. Damascene gate process with sacrificial oxide in semiconductor devices
KR100487922B1 (ko) 2002-12-06 2005-05-06 주식회사 하이닉스반도체 반도체소자의 트랜지스터 및 그 형성방법
US6869868B2 (en) 2002-12-13 2005-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating a MOSFET device with metal containing gate structures
US6794718B2 (en) 2002-12-19 2004-09-21 International Business Machines Corporation High mobility crystalline planes in double-gate CMOS technology
ATE467905T1 (de) 2002-12-20 2010-05-15 Ibm Integrierte anitfuse-struktur für finfet- und cmos-vorrichtungen
US6780694B2 (en) 2003-01-08 2004-08-24 International Business Machines Corporation MOS transistor
US6803631B2 (en) 2003-01-23 2004-10-12 Advanced Micro Devices, Inc. Strained channel finfet
US7259425B2 (en) 2003-01-23 2007-08-21 Advanced Micro Devices, Inc. Tri-gate and gate around MOSFET devices and methods for making same
US6762483B1 (en) 2003-01-23 2004-07-13 Advanced Micro Devices, Inc. Narrow fin FinFET
US6885055B2 (en) 2003-02-04 2005-04-26 Lee Jong-Ho Double-gate FinFET device and fabricating method thereof
KR100543472B1 (ko) 2004-02-11 2006-01-20 삼성전자주식회사 소오스/드레인 영역에 디플리션 방지막을 구비하는 반도체소자 및 그 형성 방법
US7304336B2 (en) * 2003-02-13 2007-12-04 Massachusetts Institute Of Technology FinFET structure and method to make the same
US6855606B2 (en) 2003-02-20 2005-02-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor nano-rod devices
US7105894B2 (en) 2003-02-27 2006-09-12 Taiwan Semiconductor Manufacturing Co., Ltd. Contacts to semiconductor fin devices
KR100499159B1 (ko) 2003-02-28 2005-07-01 삼성전자주식회사 리세스 채널을 갖는 반도체장치 및 그 제조방법
US6800885B1 (en) 2003-03-12 2004-10-05 Advance Micro Devices, Inc. Asymmetrical double gate or all-around gate MOSFET devices and methods for making same
US6787854B1 (en) 2003-03-12 2004-09-07 Advanced Micro Devices, Inc. Method for forming a fin in a finFET device
US6716690B1 (en) 2003-03-12 2004-04-06 Advanced Micro Devices, Inc. Uniformly doped source/drain junction in a double-gate MOSFET
JP4563652B2 (ja) 2003-03-13 2010-10-13 シャープ株式会社 メモリ機能体および微粒子形成方法並びにメモリ素子、半導体装置および電子機器
TW582099B (en) 2003-03-13 2004-04-01 Ind Tech Res Inst Method of adhering material layer on transparent substrate and method of forming single crystal silicon on transparent substrate
US6844238B2 (en) 2003-03-26 2005-01-18 Taiwan Semiconductor Manufacturing Co., Ltd Multiple-gate transistors with improved gate control
US20040191980A1 (en) 2003-03-27 2004-09-30 Rafael Rios Multi-corner FET for better immunity from short channel effects
US6790733B1 (en) 2003-03-28 2004-09-14 International Business Machines Corporation Preserving TEOS hard mask using COR for raised source-drain including removable/disposable spacer
US6764884B1 (en) 2003-04-03 2004-07-20 Advanced Micro Devices, Inc. Method for forming a gate in a FinFET device and thinning a fin in a channel region of the FinFET device
TWI231994B (en) * 2003-04-04 2005-05-01 Univ Nat Taiwan Strained Si FinFET
US6902962B2 (en) 2003-04-04 2005-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Silicon-on-insulator chip with multiple crystal orientations
US7442415B2 (en) 2003-04-11 2008-10-28 Sharp Laboratories Of America, Inc. Modulated temperature method of atomic layer deposition (ALD) of high dielectric constant films
JP2004319704A (ja) 2003-04-15 2004-11-11 Seiko Instruments Inc 半導体装置
TW200506093A (en) 2003-04-21 2005-02-16 Aviza Tech Inc System and method for forming multi-component films
US20070108514A1 (en) 2003-04-28 2007-05-17 Akira Inoue Semiconductor device and method of fabricating the same
JP3976703B2 (ja) 2003-04-30 2007-09-19 エルピーダメモリ株式会社 半導体装置の製造方法
US6867433B2 (en) 2003-04-30 2005-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors
US6838322B2 (en) 2003-05-01 2005-01-04 Freescale Semiconductor, Inc. Method for forming a double-gated semiconductor device
JP4084843B2 (ja) 2003-06-12 2008-04-30 日本電産株式会社 動圧軸受装置およびその製造方法
US6830998B1 (en) 2003-06-17 2004-12-14 Advanced Micro Devices, Inc. Gate dielectric quality for replacement metal gate transistors
US7045401B2 (en) * 2003-06-23 2006-05-16 Sharp Laboratories Of America, Inc. Strained silicon finFET device
US6909151B2 (en) 2003-06-27 2005-06-21 Intel Corporation Nonplanar device with stress incorporation layer and method of fabrication
US20040262683A1 (en) * 2003-06-27 2004-12-30 Bohr Mark T. PMOS transistor strain optimization with raised junction regions
US6960517B2 (en) 2003-06-30 2005-11-01 Intel Corporation N-gate transistor
US6716686B1 (en) 2003-07-08 2004-04-06 Advanced Micro Devices, Inc. Method for forming channels in a finfet device
US6921982B2 (en) 2003-07-21 2005-07-26 International Business Machines Corporation FET channel having a strained lattice structure along multiple surfaces
KR100487566B1 (ko) 2003-07-23 2005-05-03 삼성전자주식회사 핀 전계 효과 트랜지스터 및 그 형성 방법
KR100487567B1 (ko) 2003-07-24 2005-05-03 삼성전자주식회사 핀 전계효과 트랜지스터 형성 방법
EP1519420A2 (en) 2003-09-25 2005-03-30 Interuniversitaire Microelectronica Centrum vzw ( IMEC) Multiple gate semiconductor device and method for forming same
US6835618B1 (en) 2003-08-05 2004-12-28 Advanced Micro Devices, Inc. Epitaxially grown fin for FinFET
US7172943B2 (en) * 2003-08-13 2007-02-06 Taiwan Semiconductor Manufacturing Company, Ltd. Multiple-gate transistors formed on bulk substrates
KR100496891B1 (ko) 2003-08-14 2005-06-23 삼성전자주식회사 핀 전계효과 트랜지스터를 위한 실리콘 핀 및 그 제조 방법
US7355253B2 (en) 2003-08-22 2008-04-08 International Business Machines Corporation Strained-channel Fin field effect transistor (FET) with a uniform channel thickness and separate gates
US6998301B1 (en) 2003-09-03 2006-02-14 Advanced Micro Devices, Inc. Method for forming a tri-gate MOSFET
US6877728B2 (en) 2003-09-04 2005-04-12 Lakin Manufacturing Corporation Suspension assembly having multiple torsion members which cooperatively provide suspension to a wheel
JP4439358B2 (ja) 2003-09-05 2010-03-24 株式会社東芝 電界効果トランジスタ及びその製造方法
US7170126B2 (en) 2003-09-16 2007-01-30 International Business Machines Corporation Structure of vertical strained silicon devices
US6970373B2 (en) 2003-10-02 2005-11-29 Intel Corporation Method and apparatus for improving stability of a 6T CMOS SRAM cell
JP4904815B2 (ja) 2003-10-09 2012-03-28 日本電気株式会社 半導体装置及びその製造方法
EP1683193A1 (en) 2003-10-22 2006-07-26 Spinnaker Semiconductor, Inc. Dynamic schottky barrier mosfet device and method of manufacture
US6946377B2 (en) 2003-10-29 2005-09-20 Texas Instruments Incorporated Multiple-gate MOSFET device with lithography independent silicon body thickness and methods for fabricating the same
KR100515061B1 (ko) 2003-10-31 2005-09-14 삼성전자주식회사 핀 전계 효과 트랜지스터를 갖는 반도체 소자 및 그 형성방법
US7138320B2 (en) 2003-10-31 2006-11-21 Advanced Micro Devices, Inc. Advanced technique for forming a transistor having raised drain and source regions
US6867460B1 (en) 2003-11-05 2005-03-15 International Business Machines Corporation FinFET SRAM cell with chevron FinFET logic
US6885072B1 (en) 2003-11-18 2005-04-26 Applied Intellectual Properties Co., Ltd. Nonvolatile memory with undercut trapping structure
US7545001B2 (en) 2003-11-25 2009-06-09 Taiwan Semiconductor Manufacturing Company Semiconductor device having high drive current and method of manufacture therefor
US7183137B2 (en) * 2003-12-01 2007-02-27 Taiwan Semiconductor Manufacturing Company Method for dicing semiconductor wafers
US7075150B2 (en) 2003-12-02 2006-07-11 International Business Machines Corporation Ultra-thin Si channel MOSFET using a self-aligned oxygen implant and damascene technique
US7018551B2 (en) 2003-12-09 2006-03-28 International Business Machines Corporation Pull-back method of forming fins in FinFets
US7388258B2 (en) 2003-12-10 2008-06-17 International Business Machines Corporation Sectional field effect devices
US7662689B2 (en) * 2003-12-23 2010-02-16 Intel Corporation Strained transistor integration for CMOS
US7223679B2 (en) 2003-12-24 2007-05-29 Intel Corporation Transistor gate electrode having conductor material layer
US7105390B2 (en) 2003-12-30 2006-09-12 Intel Corporation Nonplanar transistors with metal gate electrodes
US7045407B2 (en) 2003-12-30 2006-05-16 Intel Corporation Amorphous etch stop for the anisotropic etching of substrates
US7078282B2 (en) 2003-12-30 2006-07-18 Intel Corporation Replacement gate flow facilitating high yield and incorporation of etch stop layers and/or stressed films
US7247578B2 (en) 2003-12-30 2007-07-24 Intel Corporation Method of varying etch selectivities of a film
US6997415B2 (en) * 2003-12-31 2006-02-14 Gulfstream Aerospace Corporation Method and arrangement for aircraft fuel dispersion
US7705345B2 (en) 2004-01-07 2010-04-27 International Business Machines Corporation High performance strained silicon FinFETs device and method for forming same
US6974736B2 (en) 2004-01-09 2005-12-13 International Business Machines Corporation Method of forming FET silicide gate structures incorporating inner spacers
US7056794B2 (en) 2004-01-09 2006-06-06 International Business Machines Corporation FET gate structure with metal gate electrode and silicide contact
US7268058B2 (en) 2004-01-16 2007-09-11 Intel Corporation Tri-gate transistors and methods to fabricate same
US7385247B2 (en) 2004-01-17 2008-06-10 Samsung Electronics Co., Ltd. At least penta-sided-channel type of FinFET transistor
JP2005209782A (ja) 2004-01-21 2005-08-04 Toshiba Corp 半導体装置
US7250645B1 (en) 2004-01-22 2007-07-31 Advanced Micro Devices, Inc. Reversed T-shaped FinFET
US7224029B2 (en) 2004-01-28 2007-05-29 International Business Machines Corporation Method and structure to create multiple device widths in FinFET technology in both bulk and SOI
KR100587672B1 (ko) 2004-02-02 2006-06-08 삼성전자주식회사 다마신 공법을 이용한 핀 트랜지스터 형성방법
EP1566844A3 (en) 2004-02-20 2006-04-05 Samsung Electronics Co., Ltd. Multi-gate transistor and method for manufacturing the same
US7060539B2 (en) 2004-03-01 2006-06-13 International Business Machines Corporation Method of manufacture of FinFET devices with T-shaped fins and devices manufactured thereby
JP4852694B2 (ja) 2004-03-02 2012-01-11 独立行政法人産業技術総合研究所 半導体集積回路およびその製造方法
US6921691B1 (en) 2004-03-18 2005-07-26 Infineon Technologies Ag Transistor with dopant-bearing metal in source and drain
KR100576361B1 (ko) 2004-03-23 2006-05-03 삼성전자주식회사 3차원 시모스 전계효과 트랜지스터 및 그것을 제조하는 방법
US7141480B2 (en) 2004-03-26 2006-11-28 Texas Instruments Incorporated Tri-gate low power device and method for manufacturing the same
US8450806B2 (en) 2004-03-31 2013-05-28 International Business Machines Corporation Method for fabricating strained silicon-on-insulator structures and strained silicon-on insulator structures formed thereby
US7154118B2 (en) 2004-03-31 2006-12-26 Intel Corporation Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
US20050224797A1 (en) * 2004-04-01 2005-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. CMOS fabricated on different crystallographic orientation substrates
US20050230763A1 (en) 2004-04-15 2005-10-20 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing a microelectronic device with electrode perturbing sill
KR100642632B1 (ko) 2004-04-27 2006-11-10 삼성전자주식회사 반도체소자의 제조방법들 및 그에 의해 제조된 반도체소자들
US7084018B1 (en) 2004-05-05 2006-08-01 Advanced Micro Devices, Inc. Sacrificial oxide for minimizing box undercut in damascene FinFET
US20050255642A1 (en) 2004-05-11 2005-11-17 Chi-Wen Liu Method of fabricating inlaid structure
US6864540B1 (en) 2004-05-21 2005-03-08 International Business Machines Corp. High performance FET with elevated source/drain region
KR100625177B1 (ko) 2004-05-25 2006-09-20 삼성전자주식회사 멀티-브리지 채널형 모오스 트랜지스터의 제조 방법
KR100634372B1 (ko) 2004-06-04 2006-10-16 삼성전자주식회사 반도체 소자들 및 그 형성 방법들
US7132360B2 (en) 2004-06-10 2006-11-07 Freescale Semiconductor, Inc. Method for treating a semiconductor surface to form a metal-containing layer
WO2005122276A1 (ja) 2004-06-10 2005-12-22 Nec Corporation 半導体装置及びその製造方法
US7291886B2 (en) 2004-06-21 2007-11-06 International Business Machines Corporation Hybrid substrate technology for high-mobility planar and multiple-gate MOSFETs
US8669145B2 (en) 2004-06-30 2014-03-11 International Business Machines Corporation Method and structure for strained FinFET devices
US7348284B2 (en) 2004-08-10 2008-03-25 Intel Corporation Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
US20060040054A1 (en) 2004-08-18 2006-02-23 Pearlstein Ronald M Passivating ALD reactor chamber internal surfaces to prevent residue buildup
US7105934B2 (en) 2004-08-30 2006-09-12 International Business Machines Corporation FinFET with low gate capacitance and low extrinsic resistance
US7250367B2 (en) 2004-09-01 2007-07-31 Micron Technology, Inc. Deposition methods using heteroleptic precursors
US7071064B2 (en) 2004-09-23 2006-07-04 Intel Corporation U-gate transistors and methods of fabrication
US7332439B2 (en) 2004-09-29 2008-02-19 Intel Corporation Metal gate transistors with epitaxial source and drain regions
US7422946B2 (en) 2004-09-29 2008-09-09 Intel Corporation Independently accessed double-gate and tri-gate transistors in same process flow
US20060086977A1 (en) 2004-10-25 2006-04-27 Uday Shah Nonplanar device with thinned lower body portion and method of fabrication
US7247547B2 (en) 2005-01-05 2007-07-24 International Business Machines Corporation Method of fabricating a field effect transistor having improved junctions
US7875547B2 (en) 2005-01-12 2011-01-25 Taiwan Semiconductor Manufacturing Co., Ltd. Contact hole structures and contact structures and fabrication methods thereof
US20060172480A1 (en) 2005-02-03 2006-08-03 Taiwan Semiconductor Manufacturing Company, Ltd. Single metal gate CMOS device design
US7238564B2 (en) 2005-03-10 2007-07-03 Taiwan Semiconductor Manufacturing Company Method of forming a shallow trench isolation structure
US7177177B2 (en) 2005-04-07 2007-02-13 International Business Machines Corporation Back-gate controlled read SRAM cell
KR100699839B1 (ko) 2005-04-21 2007-03-27 삼성전자주식회사 다중채널을 갖는 반도체 장치 및 그의 제조방법.
US7429536B2 (en) 2005-05-23 2008-09-30 Micron Technology, Inc. Methods for forming arrays of small, closely spaced features
US7319074B2 (en) 2005-06-13 2008-01-15 United Microelectronics Corp. Method of defining polysilicon patterns
US7279375B2 (en) 2005-06-30 2007-10-09 Intel Corporation Block contact architectures for nanoscale channel transistors
US20070023795A1 (en) 2005-07-15 2007-02-01 Kabushiki Kaisha Toshiba Semiconductor device and method of fabricating the same
US7352034B2 (en) 2005-08-25 2008-04-01 International Business Machines Corporation Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures
US7416943B2 (en) 2005-09-01 2008-08-26 Micron Technology, Inc. Peripheral gate stacks and recessed array gates
US8513066B2 (en) 2005-10-25 2013-08-20 Freescale Semiconductor, Inc. Method of making an inverted-T channel transistor

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8816391B2 (en) 2009-04-01 2014-08-26 Taiwan Semiconductor Manufacturing Company, Ltd. Source/drain engineering of devices with high-mobility channels
US8927371B2 (en) 2009-04-01 2015-01-06 Taiwan Semiconductor Manufacturing Company, Ltd. High-mobility multiple-gate transistor with improved on-to-off current ratio
US9590068B2 (en) 2009-04-01 2017-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. High-mobility multiple-gate transistor with improved on-to-off current ratio
US10109748B2 (en) 2009-04-01 2018-10-23 Taiwan Semiconductor Manufacturing Company, Ltd. High-mobility multiple-gate transistor with improved on-to-off current ratio
US9768305B2 (en) 2009-05-29 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Gradient ternary or quaternary multiple-gate transistor
US10269970B2 (en) 2009-05-29 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Gradient ternary or quaternary multiple-gate transistor
US9006788B2 (en) 2009-06-01 2015-04-14 Taiwan Semiconductor Manufacturing Company, Ltd. Source/drain re-growth for manufacturing III-V based transistors
TWI423443B (zh) * 2010-01-22 2014-01-11 Toshiba Kk 半導體裝置及其製造方法
US9536772B2 (en) 2013-06-11 2017-01-03 Taiwan Semiconductor Manufacturing Company, Ltd. Fin structure of semiconductor device

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KR100845175B1 (ko) 2008-07-10
DE112005000704T5 (de) 2007-09-06
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US20050218438A1 (en) 2005-10-06
US7781771B2 (en) 2010-08-24
CN101189730B (zh) 2011-04-20
DE112005000704B4 (de) 2012-08-30
TW200535979A (en) 2005-11-01
US20050224800A1 (en) 2005-10-13
US20080142841A1 (en) 2008-06-19
KR20060130704A (ko) 2006-12-19
US7154118B2 (en) 2006-12-26
US7326634B2 (en) 2008-02-05

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