JP3651802B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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Description
Junko Tanaka,et al.,"A sub-0.1μm Grooved Gate MOSFET with High Immunity to Short Channel Effects"IEDM Tech.Digest,pp.537-540 1993
本発明では、ソース・ドレイン領域を構成するエクステンション領域の接合深さが30nm程度となる従来のイオン注入+活性化アニール技術を用いても、横方向の拡散を20nm以下(エクステンション領域の接合深さの2/3以下)にする技術を提供するものである。そのために、本発明は、少なくともゲート電極下のチャネル領域に、ソース・ドレイン領域形成が完遂する前に、窪みを形成しておくことを特徴としている。
以下、図6及び図7を参照して第2の実施形態を説明する。
上記従来技術での問題点を回避する製造方法を発明したので、以下に工程を追ってその内容を説明する。
上記実施形態1は、高速ロジック回路にポリシリコンまたはpoly−Si−Geからなるゲート電極材料50を埋め込んだが、メタルゲートを電極として使用しても、メリットが得られる。それを工程を追って説明する。
Claims (7)
- 半導体基板上にダミーゲート絶縁膜及びその上にダミーゲート電極を形成する工程と、
前記半導体基板の表面領域に前記ダミーゲート絶縁膜及びダミーゲート電極をマスクにして不純物をイオン注入しエクステンション領域を形成する工程と、
前記ダミーゲート絶縁膜及びダミーゲート電極の側面にゲート側壁絶縁膜を形成する工程と、
前記半導体基板の表面領域に前記ダミーゲート絶縁膜、前記ダミーゲート電極及びゲート側壁絶縁膜をマスクにして不純物を注入しコンタクトジャンクション領域を形成し、このコンタクトジャンクション領域と前記エクステンション領域とから構成されたソース領域及びドレイン領域を形成する工程と、
前記半導体基板上に前記ダミーゲート絶縁膜、前記ダミーゲート電極及びゲート側壁絶縁膜を被覆するように層間絶縁膜を形成する工程と、
前記層間絶縁膜を前記ダミーゲート電極の表面が露出するまで研磨して表面の平坦化を行う工程と、
前記ダミーゲート電極及び前記ダミーゲート絶縁膜を選択的に除去し、前記層間絶縁膜にゲート開口領域を形成する工程と、
前記ゲート開口領域の底部に露出する前記半導体基板表面をプラズマ酸素により600℃以下で酸化し、この酸化された部分を選択的に除去することにより前記半導体基板の表面領域に窪みを形成する工程と、
前記ゲート開口領域底面の前記窪み表面を絶縁化してゲート絶縁膜を形成する工程と、
前記ゲート開口領域内にゲート電極材料を埋め込んでゲート電極を形成する工程とを備えたことを特徴とする半導体装置の製造方法。 - 前記窪みの半導体基板表面からの深さは、前記エクステンション領域のイオン注入時における不純物濃度ピークの半導体基板表面からの深さより深いことを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記窪みの深さは、6nm以下であることを特徴とする請求項1又は2に記載の半導体装置の製造方法。
- 前記ゲート絶縁膜は、少なくともプラズマ酸化を用いて形成されることを特徴とする請求項1乃至3のいずれかに記載の半導体装置の製造方法。
- 前記ゲート電極がポリシリコンで形成されている場合において、前記ゲート電極に不純物をイオン注入し、その後1000℃以上で熱処理して前記不純物を活性化させる工程をさらに備えたことを特徴とする請求項1乃至4のいずれかに記載の半導体装置の製造方法。
- 前記ソース・ドレイン領域の不純物濃度が1E19/cm 3 以上の領域は、前記半導体基板表面から少なくとも10nm以下であることを特徴とする請求項1乃至5のいずれかに記載の半導体装置の製造方法。
- 前記ゲート電極がポリシリコンからなる場合において、前記層間絶縁膜を前記半導体基板から除去した後に、前記ゲート電極表面及び前記ソース・ドレイン領域表面にシリサイド層を形成することを特徴とする請求項1乃至6のいずれかに記載の半導体装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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JP2003318143A JP3651802B2 (ja) | 2002-09-12 | 2003-09-10 | 半導体装置の製造方法 |
US10/660,559 US6977415B2 (en) | 2002-09-12 | 2003-09-12 | Semiconductor device including a gate insulating film on a recess and source and drain extension regions |
US11/256,093 US7767535B2 (en) | 2002-09-12 | 2005-10-24 | Semiconductor device and method of manufacturing the same |
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JP2002266759 | 2002-09-12 | ||
JP2003318143A JP3651802B2 (ja) | 2002-09-12 | 2003-09-10 | 半導体装置の製造方法 |
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Cited By (1)
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US20060038241A1 (en) | 2006-02-23 |
US20040124492A1 (en) | 2004-07-01 |
US7767535B2 (en) | 2010-08-03 |
JP2004128491A (ja) | 2004-04-22 |
US6977415B2 (en) | 2005-12-20 |
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