J269412 • 九、發明說明： 【發明所屬之技術領域】 - 本發明係有關於一種半導體裝置及其製造方法，特別 . 是有關於一種具有磊晶矽通道層之垂直式電晶體及其製造 方法。 【先前技術】 金氧半導體（metal-oxide-semiconductor，MOS)電晶 • 體為半導體技術領域中一常見的電子裝置。典型的MOS 電晶體包括位於基底中的源極摻雜區及汲極掺雜區，兩摻 雜區經由位於基底中的一通道區而彼此分開。通道區上方 依序有一閘極介電層及一閘極電極。上述的電晶體因通道 區（或電流方向）平行基底平面’故稱之為水平式（planar ) 電晶體。 水平式電晶體具有易與電路整合之優點，因而被廣泛 地運用於積體電路之製造。然而，水平式電晶體會佔據較 φ 多的基底表面區域，使得積體電路的積集度無法提升。 在元件積集度要求越來越高的情況下，電晶體的尺寸 需要大幅縮小，才可能製造出高密度及高效能之半導體裝 置。另外，當積體電路進入次微米世代時，水平式電晶體 存在了其他的隱憂，諸如熱載子注入、漏電流、絕緣、短 通道效應及通道長度控制等問題。 為了改善上述問題，须發展出不同的電晶體的製程技 術，如立體化電晶體的製程技術，以大量地減少其於半導 體基底上所佔佈之面積。而相對於傳統水平式電晶體佔佈 〇548-*A5〇293TWf/9227i/spin 5 :1269412 半導體表面相當的面積而一 ^ ^ 田」叫償而5，垂直式電晶體可滿足目前高 度積集化的需求，而可忐炎口义：+十也丨山^ J珉為目則及未來製造半導體記憔 置的主要潮流。 ^ & 【發明内容】 有鑑於此，本發明之目的在於提供一種垂直式電晶體 及其製造方法，其藉由提供垂直式的主動區’而可輕易控 制電晶體通道長度，並改善水平式電晶體之缺點。J269412 • IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a vertical transistor having an epitaxial channel layer and a method of fabricating the same. [Prior Art] Metal-oxide-semiconductor (MOS) electro-crystals are a common electronic device in the field of semiconductor technology. A typical MOS transistor includes a source doped region and a drain doped region in a substrate, the two doped regions being separated from one another by a channel region located in the substrate. A gate dielectric layer and a gate electrode are sequentially arranged above the channel region. The above-mentioned transistor is referred to as a planar transistor because the channel region (or current direction) is parallel to the substrate plane. Horizontal transistors have the advantage of being easily integrated with circuits and are therefore widely used in the fabrication of integrated circuits. However, the horizontal transistor occupies more than φ of the surface area of the substrate, so that the integration of the integrated circuit cannot be improved. In the case where the component integration requirements are getting higher and higher, the size of the transistor needs to be greatly reduced, and it is possible to manufacture a high-density and high-performance semiconductor device. In addition, there are other concerns with horizontal transistors when the integrated circuit enters the sub-micron generation, such as hot carrier injection, leakage current, insulation, short channel effects, and channel length control. In order to improve the above problems, it is necessary to develop process technology of different transistors, such as a three-dimensional transistor process technology, to greatly reduce the area occupied by the semiconductor substrate. Compared with the traditional horizontal transistor, which covers the area equivalent to the surface of the 〇548-*A5〇293TWf/9227i/spin 5:1269412 semiconductor, the vertical transistor can meet the current height accumulation. The demand for chemical, but can be Yan Yanyi: + Ten is also the mountain ^ J珉 for the purpose and the future of manufacturing semiconductor records set the main trend. SUMMARY OF THE INVENTION In view of the above, it is an object of the present invention to provide a vertical transistor and a method of fabricating the same that can easily control the length of a transistor channel by providing a vertical active region and improve horizontal The shortcomings of the transistor.
，根據上述之目的，本發明提供一種垂直式電晶體之製 造方法。提供-基底’其上依序覆蓋有一第一介電層及— 罩幕層。在罩幕層及第_介電層中形成_開口，且在開口 下方的基底形成-凹陷區，以定義電晶體之主動區。在凹 陷區形成-具有第-導電性之第一石夕層並延伸至開口之下 =部。在開口上半部之兩側侧壁各形成一絕緣間隙壁。在 ^-石夕層上形成-具有相反於第—導電性之第二導電性之 第二石夕層。去除罩幕層，並在第—％層之兩側側壁各形成 —第二介電層。形成導電間隙壁以覆蓋每-第二介電層及 其上方之絕緣間隙壁，用以作為閘極電極。 又根據上述之目的，本發明提供一種垂直式電晶體。 :具有第-導電性之第-石夕層係位於一基底之一凹陷區並 突产出於基底表面。一具有相反於第一導電性之第二導電性 之第二石夕層係位於第一石夕層上。一對絕緣間隙壁係位於第 矽層上，且分別位於第二矽層兩側之側壁。一對導電間 隙，係位於基底上，且分別位於第一矽層兩侧之側壁二 對第一介電層係位於每一導電間隙壁與基底之間。一對第 二介電層係位於每一導電間隙壁與第一矽層之間。 6 〇548-A5〇293TWf/9227i/spin 1269412 為讓本發明之上述目的、特徵和優點能更明顯易懂， 下文特舉較佳實施例，並配合所附圖式，作詳細說明如下·· 【實施方式】 、第1H圖及第2圖係繪示出本發明不同實施例之垂直 式電晶體10’第2圖中與第1H圖相同的部件係使用相同 之標號並省略湘關之說明。 請參照第1H圖，垂直式電晶體1〇包括：一基底1〇〇、 ϋ層⑴、-第二石夕層116、—對絕緣間隙壁出、 對導電間隙壁123、一對第一介電層1〇3、以及一對第二 介電層120。在本實施例中’基底1〇〇包括矽基底、且應 變的石夕鍺基底、或是其組合。舉例而言，基底1〇〇為; 基底與位於上方之應變石夕層（石夕鍺層）（未繪示）所構成 之基底。此處’基底100具有一凹陷區跡，其深度在⑽ 至300埃（A)的範圍。 、，第一石夕層113,例如-蟲晶石夕層，係位於凹陷區職 亚突出於基底100表面。在本實施例中’第一石夕層⑴包 括位於凹陷區她的第-部u〇以及位於第一部;10上方 之第二部U2,其中第一石夕層113之第二部ιΐ2且有第一 導電性，例如N型或？型，用以作為電晶體H)之通道區。 而=石夕層113之第一部110為一具有相反於第-導電性 之弟一導電性之摻雜區，例如p别句 r 10夕、… 型或N型’用以作為電晶 體10之源極或汲極區。第二矽屑 ^ 116’例如—蟲晶石夕層或 一稷日日矽層，其位於第一矽層】 第一莫”……且同樣具有相反於 弟一V电性之第二導電性，例如 盔+曰触w型或Ρ型，同樣用以作 為包日日體10之沒極或源極區。 〇548-A5〇293TWf/9227i/spin ^ :1269412 系巴緣間隙壁115可由氧化石々所接 113 , 夕所構成。母一絕緣間隙壁 之側辟L i分別位於第二石夕層116兩側 土 ，上盍層118，例如氧化矽層，位於第二 石夕層116上方並覆蓋絕緣間隙壁丨丨5。 導電間隙壁123,可由摻雜的複晶矽、金屬 半導體技術習用之閘極材料所構 ^ y ^疋 柯抖所構成。母一導電間隙壁123 ⑽上方，且分別錄第1層⑴兩側之側壁 體切齊上蓋層U8之上^隙壁123之頂部大 表面。此處，導電間隙壁123係作 為電晶體1〇之閘極電極’其藉由絕緣間隙壁ιΐ5而與作為 源極或汲極的第二矽層116形成電性隔離。 … 一 電層1〇3可由氮化石夕層或氧化石夕層所構成。每 母¥電間隙壁U3與基底100之 間」吏得導電間隙壁123與摻雜區11〇形成電性隔離。第 二’丨，層120,可由氮化發層或氧化⑦層所構成。較佳地， 弟一介電層120為-熱氧化石夕層。每一第二介電層12〇位 於每一導電間隙壁123與第一石夕層ιΐ3之間，以作為—間 ^電層’而使得導電間隙壁123與通道區ιΐ2形成電性 隔肖隹。 在上述的實施例中，係以第一石夕層113之第一养 雜區）11 〇作為電日日日體i 〇其中之_源極或汲極區。然而: 在其他的實施例中，第—㈣⑴可僅具有第—導電性。 亦即，位於凹陷區施的第_梦層113並不存在呈 導電性的摻雜區。在此實施例中，電晶體1〇具有一 第二導電性之摻雜區124，分別位於每一導電間隙壁⑵ 〇548-A5〇293TWf/9227i/spin Λ269412 基底ιο〇ι如第⑼所示。此處，摻雜區124之 -源極=Γ中推雜區，作為電㈣ 番吉：下來卩下配合第1Α至1Η圖說明本發明實施例之 _ ^電晶體之製造方法。請參照第1Α目，提供一基底 1，例如魏底、具應變的梦錯基底、或是其組合。舉例 基底100為-發基底與位於上方之應變梦層（石夕錯 層）（未緣示）所構成之基底。基底100中可包含各種不 同的元件，例如電晶體、電阻、電容及其他習用的半導體 兀件。再者’基底100亦可包含其他導電層，其通常用於 半導體工業中連接基底上分離的半導體裝置。此處為了簡 化圖式’僅以一平整基底表示之。在本實施例中，基底⑽ 上依序覆蓋有-第-介電層1〇2及一罩幕層1〇7。第一介 電層102’例如-氣化石夕層或是氧化石夕層，且可藉由習知 沉積技術形成之。罩幕層1G7可為單—層或是多層結構， 如圖中所示，罩幕層107較佳是由一層墊氧化矽層1〇4與 一層較厚的氮化矽層106所組成。墊氧化矽層1〇4之形成 方法可為習知的常壓（atm〇spheric)或低壓化學氣相沉積 法（low pressure chemicaIvap〇rdep〇sid〇n，LpcvD)沉積 而成。氮化矽層106則可利用低壓化學氣相沉積法，以二 氯矽烷（SiCUH2)與氨氣（NH3)為反應原料沉積而成。 接著’在罩幕層1〇7表面上形成一層光阻層1〇8。之後， 藉由習知微影製程於光阻層108中形成至少一開口 i〇8a， 以供定義電晶體主動區之用。 接下來，請參照第1B圖，藉由具有開口 108a之光阻 〇548-A5〇293TWf/9227i/spin 9 :1269412 層108作為蝕刻罩幕，對罩幕層1〇7及其下方的第一介。 層102進行非等向性蝕刻製程，例如反應離子蝕刻（尺^)， - 以將光阻層1〇8的開口 l〇8a圖案轉移至其中並形成開口 107a接著，可利用適當餘刻溶液或灰化處理來去除光阻 層1〇8之後，藉由罩幕層107作為蝕刻罩幕，進行^等向 性蝕刻製程，例如RIE，以將罩幕層1〇7之開口 1〇乃下方 之基底200蝕刻至一預定深度而形成深度約為100至3〇〇 埃（A)之凹陷區100a’藉以完成電晶體之主動區。另外， • 亦可在形成凹陷區l〇〇a之後，再予以去除光阻層1〇8。’ 接下來，請參照第1C圖，在凹陷區100a中形成一第 -石夕層113並向上延伸至開口職之下半部。在本實施例 中，第一矽層113可藉由選擇性磊晶成長 epitaxial growth，SEG )形成之。如之前所述，第一矽層i u 包括位於凹陷區100a的第一部11〇以及位於第一部曰ιι〇 上方之第二部112，且第二部112與第一部ιι〇可具有相 同或相反的導電性。在具有相反導電性的情形中，為了使 • 第邛U〇及第二部Π2具有相反的導電性，可在磊晶成 長期間，使用離子植入或摻雜（d〇ping)不同雜質的方式 完，舉例而言，若第一部11〇為？^型，則在凹陷區i〇〇a 中蟲晶成長第-石夕層113期間，通入含礙、含石申、或類似 石的摻雜物之氣體。之後，在開口驗下半部蠢晶成長第一 矽層113期間，改通入含硼或類似的摻雜物之氣體。若第 -部110為P型，則先通入含硼或其他p型的摻雜物之氣 "再改通入含碟、含砷、或其他N型的摻雜物之氣體。 來可元成電晶體之源極/沒極摻雜區Π 〇及通道 〇548-A5〇293TWf/9227i/spin 10 .1269412 區AU2之衣作。在其他實施例中，在蟲晶成長第-石夕層U3 =部110期間，可藉由改變摻雜物氣體濃度，而形成 二产『度梯度源極/汲極摻雜區110’其中摻雜物 情形中，蟲晶成長第1== 電㈣ ^ 食弟矽層U3期間，並不改變通入的摻 音物，氣體7’使第一石夕層113僅具有單一導電性。但需注 、是/、、額外在基底丨〇〇形成源極/汲極接雜區。According to the above object, the present invention provides a method of manufacturing a vertical type transistor. The substrate-substrate is sequentially covered with a first dielectric layer and a mask layer. An opening is formed in the mask layer and the first dielectric layer, and a substrate below the opening forms a recessed region to define an active region of the transistor. A first layer having a first conductivity is formed in the recessed region and extends below the opening. An insulating spacer is formed on each of the side walls of the upper half of the opening. A second layer of a second conductivity having a conductivity opposite to the first conductivity is formed on the ^-shixi layer. The mask layer is removed, and a second dielectric layer is formed on each of the side walls of the first-% layer. A conductive spacer is formed to cover each of the second dielectric layer and the insulating spacer above it for use as a gate electrode. Still in accordance with the above objects, the present invention provides a vertical transistor. The first-conductive layer of the first-conductivity is located in a recessed area of a substrate and is produced on the surface of the substrate. A second layer having a second conductivity opposite to the first conductivity is located on the first layer. A pair of insulating spacers are located on the second layer and are respectively located on the side walls of the second layer. A pair of conductive gaps are disposed on the substrate, and sidewalls of the two sides of the first layer are respectively located between each of the conductive spacers and the substrate. A pair of second dielectric layers are between each of the conductive spacers and the first layer. 6 〇 - - - 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 694 694 694 694 694 694 694 694 694 694 694 694 694 694 694 694 694 694 694 694 694 694 694 694 694 694 694 694 694 694 694 694 694 694 [Embodiment] FIG. 1H and FIG. 2 are diagrams showing a vertical transistor 10' according to a different embodiment of the present invention. In FIG. 2, the same components as those in FIG. 1H are denoted by the same reference numerals and the description of the Xiangguan is omitted. . Referring to FIG. 1H, the vertical transistor 1A includes: a substrate 1 〇〇, a ϋ layer (1), a second 石 layer 116, a pair of insulating spacers, a pair of conductive spacers 123, and a pair of first dielectric layers. The electrical layer 1〇3 and a pair of second dielectric layers 120. In the present embodiment, the substrate 1 includes a ruthenium substrate, and the ruthenium substrate, or a combination thereof. For example, the substrate 1 is a substrate composed of a substrate and a strained stone layer (not shown) located above. Here, the substrate 100 has a depressed region having a depth in the range of (10) to 300 angstroms (A). The first stone layer 113, for example, the wormhole layer, is located in the depression area and protrudes from the surface of the substrate 100. In the present embodiment, the first layer (1) includes a first portion of the depression portion and a second portion U2 located above the first portion; 10, wherein the second portion of the first layer 113 is ιΐ2 and Is there a first conductivity, such as N-type or? Type, used as the channel area of the transistor H). And the first portion 110 of the shi-shi layer 113 is a doped region having a conductivity opposite to that of the first-conductivity, for example, p-type r 10, ... or N-type ' is used as the transistor 10 Source or bungee zone. The second chip ^ 116 'for example - a wormhole layer or a day 矽 layer, which is located in the first layer 】 first Mo" ... and also has a second conductivity opposite to the V-electricity For example, the helmet + 曰 type w or Ρ type is also used as the immersion or source region of the celestial body 10. 〇548-A5〇293TWf/9227i/spin ^ :1269412 The rim gap 115 can be oxidized The sarcophagus is connected to 113, and the side of the mother-insulated spacer L i is located on both sides of the second sap layer 116, and the upper slab layer 118, such as a yttrium oxide layer, is located above the second shoal layer 116. And covering the insulating gap wall 。 5. The conductive spacer wall 123 can be composed of a doped polysilicon and a gate material which is conventionally used in metal semiconductor technology, and is formed by a conductive spacer 123 (10). And respectively, the sidewalls on both sides of the first layer (1) are respectively cut to the top large surface of the upper gap layer 123 of the upper cap layer U8. Here, the conductive spacer 123 is used as the gate electrode of the transistor 1 其 by insulating The spacer ιΐ5 is electrically isolated from the second ruthenium layer 116 as a source or a drain. Each female electrical ¥ U3 spacer between the substrate 100 and the "Official spacer 123 and a conductive doped region formed 11〇 electrically isolated stone rock Xi Xi oxide layer or layers formed. The second layer, layer 120, may be composed of a nitride layer or a layer of oxide. Preferably, the dielectric layer 120 is a thermal oxidized stone layer. Each of the second dielectric layers 12 is located between each of the conductive spacers 123 and the first layer ΐ3 to serve as an electrical layer to electrically isolate the conductive spacers 123 from the channel regions ι2. . In the above embodiment, the first noisy zone of the first layer 113 is used as the source or the drain region of the electric day and day. However, in other embodiments, the first (-) (1) may have only the first conductivity. That is, the first layer 113 in the recessed region does not have a conductive doped region. In this embodiment, the transistor 1 has a second conductive doping region 124, which is located at each of the conductive spacers (2) 〇 548-A5 〇 293 TWf / 9227 i / spin Λ 269 412 ιο 〇 ι as shown in the (9) . Here, the source-doping region of the doping region 124 is used as the electric (four) singularity: the method of manufacturing the thyristor according to the embodiment of the present invention is described below. Please refer to the first item to provide a substrate 1, such as a Wei bottom, a strained dream base, or a combination thereof. For example, the substrate 100 is a substrate composed of a hair base and a strained dream layer (not shown). The substrate 100 can include various components such as transistors, resistors, capacitors, and other conventional semiconductor components. Further, substrate 100 can also include other conductive layers that are commonly used in semiconductor devices in the semiconductor industry to separate substrates. Here, for the sake of simplicity, the figure 'is represented only by a flat substrate. In this embodiment, the substrate (10) is sequentially covered with a -dielectric layer 1〇2 and a mask layer 1〇7. The first dielectric layer 102' is, for example, a gasified stone layer or a oxidized stone layer, and can be formed by conventional deposition techniques. The mask layer 1G7 may be a single layer or a multilayer structure. As shown in the figure, the mask layer 107 is preferably composed of a pad of ruthenium oxide layer 1〇4 and a thicker layer of tantalum nitride layer 106. The formation of the ruthenium oxide layer 1〇4 can be formed by conventional atmospheric pressure (atm〇spheric) or low pressure chemical vapor deposition (low pressure chemicaIvap〇rdep〇sid〇n, LpcvD). The tantalum nitride layer 106 can be deposited by low pressure chemical vapor deposition using dichlorosilane (SiCUH2) and ammonia (NH3) as reaction materials. Next, a photoresist layer 1〇8 is formed on the surface of the mask layer 1〇7. Thereafter, at least one opening i 〇 8a is formed in the photoresist layer 108 by a conventional lithography process for defining the active region of the transistor. Next, referring to FIG. 1B, the photoresist layer 548-A5〇293TWf/9227i/spin 9 : 1269412 layer 108 having the opening 108a is used as an etching mask, and the mask layer 1〇7 and the first layer below it are used. Introduction. The layer 102 is subjected to an anisotropic etching process, such as reactive ion etching, to transfer the pattern of the opening 10 8a of the photoresist layer 1 8 into it and form an opening 107a. Then, a suitable solution or After the ashing treatment is performed to remove the photoresist layer 1〇8, an isotropic etching process, such as RIE, is performed by using the mask layer 107 as an etching mask to open the opening of the mask layer 1〇7. The substrate 200 is etched to a predetermined depth to form a recessed region 100a' having a depth of about 100 to 3 angstroms (A) to complete the active region of the transistor. In addition, the photoresist layer 1〇8 may be removed after the recessed area l〇〇a is formed. Next, referring to Fig. 1C, a first-story layer 113 is formed in the recessed area 100a and extends upward to the lower half of the opening. In this embodiment, the first germanium layer 113 can be formed by epitaxial growth (SEG). As described earlier, the first layer iu includes a first portion 11〇 located in the recessed area 100a and a second portion 112 located above the first portion 曰ιι, and the second portion 112 and the first portion ιι can have the same Or the opposite conductivity. In the case of opposite conductivity, in order to make the second and second Π2 have opposite conductivity, ion implantation or doping may be used during epitaxial growth. End, for example, if the first part is 11? In the case of the type ^, during the growth of the sarcoplasmic crystal in the recessed area i〇〇a, a gas containing a dopant, a stone-containing, or a stone-like dopant is introduced. Thereafter, a gas containing boron or a similar dopant is introduced during the opening of the first amorphous layer 113. If the first portion 110 is of the P type, the gas containing boron or other p-type dopants is first introduced into the gas containing the dish, arsenic, or other N-type dopant. Source/polarization doping zone of 可元成成晶Π 通道 and channel 〇548-A5〇293TWf/9227i/spin 10 .1269412 District AU2 clothing. In other embodiments, during the growth of the smectic layer of the stellate layer U3 = portion 110, the second phase of the "gradient source/drain-doped region 110" may be formed by changing the concentration of the dopant gas. In the case of debris, the growth of the insect crystals is 1== electric (4) ^ During the period of U3, the gas-filled matter is not changed, and the gas 7' makes the first layer 113 have only a single conductivity. However, it is necessary to note that it is /, and additionally forms a source/drain junction in the substrate.
之後可藉由習知沉積技術，例如CVD，在罩幕層1们 上順應性形成一絕缓声1彳4，丨l斤 巴緣層114，例如氧化矽層，並形成於開 口广側壁及第一石夕層113之上表面。接著，對絕緣層 ⑴進行非等向性_，以在開口 _上半部之兩側側壁 各形成一絕緣間隙壁115，如第1D圖所示。 接下來，請參照第1E1，在第一石夕層113上形成_ =有弟一導電性之第二石夕層116。舉例而言，可藉由咖 技術並配合實施摻雜製程而形成之，以完成電晶體之源極 /汲極之製作。同樣地’可藉由改變摻雜物氣體濃度，而 形成具有摻雜物濃度梯度源極/汲極116，其中摻雜物濃 度朝通道區112方向遞減。另外，亦可藉由習知沉積技術， 例如CVD’在第-石夕層113沉積一複晶石夕層，再藉由離子 植入之方式，形成作為源極/純116之推雜的複晶矽 層。此處，第二石夕層116之高度係低於絕緣間隙壁出， 以利於在後續步驟中’藉由習知沉積技術，例如⑽或敎 乳化法三而在第二石夕層116上方形成一上蓋層ιΐ8。較佳 地，上盍層118之材質相同於絕緣間隙壁115，例如氧化 石夕層，且可藉由熱氧化法形成之。 〇548-A5〇293TWf/9227i/spin 11 .1269412 一人接下來’請參照第1F圖’去除罩幕層而而露 7電層1〇2以及第一矽層113之第二部ιΐ2之側壁。兴 例I言，剝除氮化石夕層106的方法為濕式侧法，例如; ，熱磷酸（h3P〇4)為餘刻液來浸泡而將其去除，剥^ =層的方法為濕式崎，其例如是以氫氣酸 F)為蝕刻液來浸泡。接著，在第 =Tr二介電層12〇;如氧 子（ALD)等方式所形成的介電層， 乍為電曰曰體之閘極介電層。在本實施例中，可 化法形成第二介電層120。 s…乳 如d下來，，參照第1G圖，可藉由習知沉積技術，例 122 ^圖中的結構表面順應性形成-導電層 ㈣之 複料層、金屬材料層、或是半導體技術 每施接;^請參照第1H圖，對第1G ”的導電層⑵ 向性蘭，以形成導電間隙壁123而覆蓋每— f…層12〇及其上方之絕緣間隙壁ιΐ5，其係 二體，電極。最後，可利用導電間隙壁123輪 ^罩幕1去除未被導電間隙壁123覆蓋之第_介以 ’而形成餘留部分的第-介電層103並完成垂首彳曰 —體:之製作。另外，需注意的是若第—二= 。電性，則可在形成導電層122之前，進行—離 表序，以在鄰近凹陷區跡的基底中形成具有第 =區124，使其在後續完成_ 123 :二 方的基底100中，如第2圖所示。 於/、下 ^48-A5〇293TW{/9227i/Spin 12 1269412 =據本發明之實施例之垂直式電晶體iq，其通道長度 ，，整第層113之厚度來控制，相較料 曰曰體叉限於微影及蝕刻技術而言，製程較為簡單且易：控 制，可改善熱载子注入及短通道效應等問題。再者，相^ 於白知水平式電晶體，所形成的上蓋I 118、絕緣間隙壁 U5以及餘留的第一介電層1〇3，可提升絕緣特性而改善漏 電流的問題。再者，根據本發明之具有雙閘極的垂直式電 曰日脰除了可縮小每一電晶體的佔佈面積之外，還可增加 電晶體之數量，進而提升積體電路之積集度及效能。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此項技藝者，在不脫離本發明之精 神和範圍内，當可作更動與潤飾，因此本發明之保護範圍 當視後附之申請專利範圍所界定者為準。Then, by a conventional deposition technique, such as CVD, a gradual sound can be formed on the mask layer 1 to form a gradual sound layer 彳4, 丨1 jin bambar layer 114, such as a yttrium oxide layer, and formed on the wide sidewall of the opening. The upper surface of the first stone layer 113. Next, the insulating layer (1) is anisotropically formed to form an insulating spacer 115 on both side walls of the upper half of the opening, as shown in Fig. 1D. Next, referring to FIG. 1E1, a second radiance layer 116 having a conductivity of _= is formed on the first slab layer 113. For example, it can be formed by the coffee technology and in conjunction with the doping process to complete the fabrication of the source/drain of the transistor. Similarly, a source/drain 116 having a dopant concentration gradient can be formed by varying the dopant gas concentration, wherein the dopant concentration decreases toward the channel region 112. In addition, a compounding technique, such as CVD, may be used to deposit a polycrystalline layer in the first layer, and then implanted as a source/pure 116 by means of ion implantation. Crystalline layer. Here, the height of the second layer 116 is lower than the insulating gap wall to facilitate formation in the subsequent step by the conventional deposition technique, such as (10) or hydrazine emulsification method A cover layer ιΐ8. Preferably, the upper germanium layer 118 is made of the same material as the insulating spacers 115, such as an oxidized layer, and can be formed by thermal oxidation. 〇548-A5〇293TWf/9227i/spin 11 .1269412 One person next 'please refer to FIG. 1F' to remove the mask layer and expose the side walls of the seventh electrical layer 1〇2 and the second portion ι2 of the first germanium layer 113. For example, the method of stripping the nitride layer 106 is a wet side method, for example; hot phosphoric acid (h3P〇4) is removed by immersion in a residual solution, and the method of stripping the layer is wet. Saki, which is immersed, for example, with hydrogen acid F) as an etchant. Next, in the dielectric layer formed by the =Tr dielectric layer 12; such as oxygen (ALD), the germanium is the gate dielectric layer of the electric germanium. In this embodiment, the second dielectric layer 120 is formed by a process. s...milk as d down, referring to Figure 1G, can be formed by conventional deposition techniques, such as the structural surface compliance of the conductive layer (4) of the conductive layer (4), the metal material layer, or the semiconductor technology Referring to FIG. 1H, the conductive layer (2) of the 1G" is directional blue to form a conductive spacer 123 to cover each of the -f... layers 12 and the insulating spacers ι 5 above it. Finally, the conductive spacers 123 can be used to remove the first dielectric layer 103 which is not covered by the conductive spacers 123 and which forms the remaining portion and completes the first dielectric layer 103. In addition, it should be noted that if the first and second = electrical properties, before the formation of the conductive layer 122, the surface sequence may be performed to form the region = 124 in the substrate adjacent to the recessed region trace, In the subsequent completion of the _ 123 : two-sided substrate 100, as shown in Figure 2. _ /, ^ 48-A5 〇 293TW {/9227i / Spin 12 1269412 = vertical type according to the embodiment of the present invention The crystal iq, its channel length, is controlled by the thickness of the entire layer 113, which is limited to lithography and etching. In terms of technology, the process is relatively simple and easy: control can improve the problems of hot carrier injection and short channel effect. Furthermore, the upper cover I 118 and the insulating spacer U5 are formed by the horizontally known transistor. The remaining first dielectric layer 1〇3 can improve the insulation characteristics and improve the leakage current. Furthermore, the vertical type electric eclipse with double gates according to the present invention can reduce the occupation of each transistor. In addition to the area of the cloth, the number of transistors can be increased, thereby increasing the integration and performance of the integrated circuit. Although the invention has been disclosed in the preferred embodiments as above, it is not intended to limit the invention, and any of the The scope of protection of the present invention is defined by the scope of the appended claims.
13 〇548-A5〇293TWf/9227i/spin /1269412 【圖式簡單說明】 體 本發明實施例之垂直式電晶 第1八至出圖料示出拫據 之製造方法剖面示意圖。 第2圖係1 會不出根據本發明另-實施例之垂直式電晶體剖 面示意圖。 【主要元件符號說明】 10〜垂直電晶體； 1〇〇〜基底； 100a〜凹陷區； 102〜第一介電層； 103〜餘留的第一介電層； 104〜墊氧化石夕層； 106〜氮化矽層； 107〜罩幕層； 107a、l〇8a 〜開口； 108〜光阻層； 110〜第一石夕層之第一部； 112〜第一石夕層之第二部； 113〜第一碎層； 114〜絕緣層； 115〜絕緣間隙壁； 116〜第二矽層； 118〜上蓋層； 120〜第二介電層； 122〜導電層； 123〜導電間隙壁； 124〜換雜區。 〇548-A5〇293TWf/9227i/spin 1413 〇 548-A5 〇 293 TWf / 9227 i / spin / 1269412 [Simplified description of the drawings] The vertical type of the electric crystal according to the embodiment of the present invention is shown in the first to eighth drawings. Fig. 2 is a schematic cross-sectional view of a vertical transistor according to another embodiment of the present invention. [Major component symbol description] 10~vertical transistor; 1〇〇~substrate; 100a~ recessed area; 102~first dielectric layer; 103~ remaining first dielectric layer; 104~pad oxide layer 106~layer of tantalum nitride; 107~mask layer; 107a, l8a~ opening; 108~ photoresist layer; 110~ first part of the first stone layer; 112~ second part of the first stone layer 113~first fragmented layer; 114~insulating layer; 115~insulating spacer; 116~second layer; 118~upper layer; 120~second dielectric layer; 122~conductive layer; 123~conductive spacer; 124 ~ change zone. 〇548-A5〇293TWf/9227i/spin 14