FR2810161B1 - Memoire electronique a architecture damascene et procede de realisation d'une telle memoire - Google Patents
Memoire electronique a architecture damascene et procede de realisation d'une telle memoireInfo
- Publication number
- FR2810161B1 FR2810161B1 FR0007416A FR0007416A FR2810161B1 FR 2810161 B1 FR2810161 B1 FR 2810161B1 FR 0007416 A FR0007416 A FR 0007416A FR 0007416 A FR0007416 A FR 0007416A FR 2810161 B1 FR2810161 B1 FR 2810161B1
- Authority
- FR
- France
- Prior art keywords
- memory
- making
- damascene architecture
- electronic
- electronic memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0007416A FR2810161B1 (fr) | 2000-06-09 | 2000-06-09 | Memoire electronique a architecture damascene et procede de realisation d'une telle memoire |
PCT/FR2001/001775 WO2001095392A1 (fr) | 2000-06-09 | 2001-06-08 | Memoire electronique a architecture damascene et procede de realisation d'une telle memoire |
US10/296,201 US6955963B2 (en) | 2000-06-09 | 2001-06-08 | Damascene architecture electronic storage and method for making same |
EP01943589A EP1292984A1 (fr) | 2000-06-09 | 2001-06-08 | Memoire electronique a architecture damascene et procede de realisation d'une telle memoire |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0007416A FR2810161B1 (fr) | 2000-06-09 | 2000-06-09 | Memoire electronique a architecture damascene et procede de realisation d'une telle memoire |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2810161A1 FR2810161A1 (fr) | 2001-12-14 |
FR2810161B1 true FR2810161B1 (fr) | 2005-03-11 |
Family
ID=8851145
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR0007416A Expired - Fee Related FR2810161B1 (fr) | 2000-06-09 | 2000-06-09 | Memoire electronique a architecture damascene et procede de realisation d'une telle memoire |
Country Status (4)
Country | Link |
---|---|
US (1) | US6955963B2 (fr) |
EP (1) | EP1292984A1 (fr) |
FR (1) | FR2810161B1 (fr) |
WO (1) | WO2001095392A1 (fr) |
Families Citing this family (37)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100469129B1 (ko) * | 2002-09-30 | 2005-01-29 | 삼성전자주식회사 | 불휘발성 메모리 장치 및 그 제조방법 |
US7456476B2 (en) * | 2003-06-27 | 2008-11-25 | Intel Corporation | Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication |
US6909151B2 (en) | 2003-06-27 | 2005-06-21 | Intel Corporation | Nonplanar device with stress incorporation layer and method of fabrication |
KR100518594B1 (ko) * | 2003-09-09 | 2005-10-04 | 삼성전자주식회사 | 로컬 sonos형 비휘발성 메모리 소자 및 그 제조방법 |
US7268058B2 (en) * | 2004-01-16 | 2007-09-11 | Intel Corporation | Tri-gate transistors and methods to fabricate same |
US7154118B2 (en) * | 2004-03-31 | 2006-12-26 | Intel Corporation | Bulk non-planar transistor having strained enhanced mobility and methods of fabrication |
US7042009B2 (en) | 2004-06-30 | 2006-05-09 | Intel Corporation | High mobility tri-gate devices and methods of fabrication |
US7348284B2 (en) * | 2004-08-10 | 2008-03-25 | Intel Corporation | Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow |
US7405116B2 (en) * | 2004-08-11 | 2008-07-29 | Lsi Corporation | Application of gate edge liner to maintain gate length CD in a replacement gate transistor flow |
KR100587396B1 (ko) * | 2004-08-13 | 2006-06-08 | 동부일렉트로닉스 주식회사 | 비휘발성 메모리 소자 및 그의 제조방법 |
US7422946B2 (en) * | 2004-09-29 | 2008-09-09 | Intel Corporation | Independently accessed double-gate and tri-gate transistors in same process flow |
US7332439B2 (en) * | 2004-09-29 | 2008-02-19 | Intel Corporation | Metal gate transistors with epitaxial source and drain regions |
US7361958B2 (en) * | 2004-09-30 | 2008-04-22 | Intel Corporation | Nonplanar transistors with metal gate electrodes |
US20060086977A1 (en) | 2004-10-25 | 2006-04-27 | Uday Shah | Nonplanar device with thinned lower body portion and method of fabrication |
US7518196B2 (en) | 2005-02-23 | 2009-04-14 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
US20060202266A1 (en) * | 2005-03-14 | 2006-09-14 | Marko Radosavljevic | Field effect transistor with metal source/drain regions |
US7858481B2 (en) | 2005-06-15 | 2010-12-28 | Intel Corporation | Method for fabricating transistor with thinned channel |
US7547637B2 (en) | 2005-06-21 | 2009-06-16 | Intel Corporation | Methods for patterning a semiconductor film |
JP4851740B2 (ja) * | 2005-06-30 | 2012-01-11 | 株式会社東芝 | 半導体装置およびその製造方法 |
US7279375B2 (en) * | 2005-06-30 | 2007-10-09 | Intel Corporation | Block contact architectures for nanoscale channel transistors |
KR100824400B1 (ko) * | 2005-07-08 | 2008-04-22 | 삼성전자주식회사 | 비휘발성 기억 소자 및 그 형성 방법 |
US7402875B2 (en) * | 2005-08-17 | 2008-07-22 | Intel Corporation | Lateral undercut of metal gate in SOI device |
US20070090416A1 (en) * | 2005-09-28 | 2007-04-26 | Doyle Brian S | CMOS devices with a single work function gate electrode and method of fabrication |
US20070090408A1 (en) * | 2005-09-29 | 2007-04-26 | Amlan Majumdar | Narrow-body multiple-gate FET with dominant body transistor for high performance |
US7485503B2 (en) | 2005-11-30 | 2009-02-03 | Intel Corporation | Dielectric interface for group III-V semiconductor device |
US20070152266A1 (en) * | 2005-12-29 | 2007-07-05 | Intel Corporation | Method and structure for reducing the external resistance of a three-dimensional transistor through use of epitaxial layers |
EP1840947A3 (fr) * | 2006-03-31 | 2008-08-13 | Semiconductor Energy Laboratory Co., Ltd. | Dispositif de mémoire à semi-conducteurs non volatile |
US8143646B2 (en) | 2006-08-02 | 2012-03-27 | Intel Corporation | Stacking fault and twin blocking barrier for integrating III-V on Si |
US8362566B2 (en) | 2008-06-23 | 2013-01-29 | Intel Corporation | Stress in trigate devices using complimentary gate fill materials |
US20100062593A1 (en) * | 2008-09-10 | 2010-03-11 | Promos Technologies Inc. | Method for preparing multi-level flash memory devices |
FR2943832B1 (fr) | 2009-03-27 | 2011-04-22 | Commissariat Energie Atomique | Procede de realisation d'un dispositif memoire a nanoparticules conductrices |
FR2943850B1 (fr) | 2009-03-27 | 2011-06-10 | Commissariat Energie Atomique | Procede de realisation d'interconnexions electriques a nanotubes de carbone |
CN102237365B (zh) * | 2010-04-28 | 2013-01-02 | 中国科学院微电子研究所 | 一种闪存器件及其制造方法 |
CN103811318B (zh) * | 2012-11-08 | 2016-08-31 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制备方法 |
CN103811423B (zh) * | 2012-11-13 | 2016-07-06 | 中芯国际集成电路制造(上海)有限公司 | 存储器件的形成方法 |
US10141417B2 (en) | 2015-10-20 | 2018-11-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Gate structure, semiconductor device and the method of forming semiconductor device |
JP2017139336A (ja) * | 2016-02-03 | 2017-08-10 | 渡辺 浩志 | フラッシュメモリの構造とその動作法 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08204032A (ja) * | 1995-01-20 | 1996-08-09 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
US5707897A (en) * | 1996-05-16 | 1998-01-13 | Taiwan Semiconductor Manufacturing Company Ltd. | Non-volatile-memory cell for electrically programmable read only memory having a trench-like coupling capacitors |
DE19639026C1 (de) * | 1996-09-23 | 1998-04-09 | Siemens Ag | Selbstjustierte nichtflüchtige Speicherzelle |
FR2757312B1 (fr) * | 1996-12-16 | 1999-01-08 | Commissariat Energie Atomique | Transistor mis a grille metallique auto-alignee et son procede de fabrication |
DE19732870C2 (de) * | 1997-07-30 | 1999-10-07 | Siemens Ag | Nichtflüchtige Speicherzelle mit hoher Koppelkapazität und Verfahren zu ihrer Herstellung |
US5960270A (en) * | 1997-08-11 | 1999-09-28 | Motorola, Inc. | Method for forming an MOS transistor having a metallic gate electrode that is formed after the formation of self-aligned source and drain regions |
US5856225A (en) * | 1997-11-24 | 1999-01-05 | Chartered Semiconductor Manufacturing Ltd | Creation of a self-aligned, ion implanted channel region, after source and drain formation |
US6002151A (en) * | 1997-12-18 | 1999-12-14 | Advanced Micro Devices, Inc. | Non-volatile trench semiconductor device |
JP4488565B2 (ja) * | 1999-12-03 | 2010-06-23 | 富士通株式会社 | 半導体記憶装置の製造方法 |
-
2000
- 2000-06-09 FR FR0007416A patent/FR2810161B1/fr not_active Expired - Fee Related
-
2001
- 2001-06-08 US US10/296,201 patent/US6955963B2/en not_active Expired - Lifetime
- 2001-06-08 WO PCT/FR2001/001775 patent/WO2001095392A1/fr active Application Filing
- 2001-06-08 EP EP01943589A patent/EP1292984A1/fr not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
FR2810161A1 (fr) | 2001-12-14 |
WO2001095392A1 (fr) | 2001-12-13 |
US6955963B2 (en) | 2005-10-18 |
EP1292984A1 (fr) | 2003-03-19 |
US20040029345A1 (en) | 2004-02-12 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
TP | Transmission of property | ||
PLFP | Fee payment |
Year of fee payment: 17 |
|
ST | Notification of lapse |
Effective date: 20180228 |