DE69924916D1 - Speicherschaltung - Google Patents

Speicherschaltung

Info

Publication number
DE69924916D1
DE69924916D1 DE69924916T DE69924916T DE69924916D1 DE 69924916 D1 DE69924916 D1 DE 69924916D1 DE 69924916 T DE69924916 T DE 69924916T DE 69924916 T DE69924916 T DE 69924916T DE 69924916 D1 DE69924916 D1 DE 69924916D1
Authority
DE
Germany
Prior art keywords
memory circuit
memory
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69924916T
Other languages
English (en)
Other versions
DE69924916T2 (de
Inventor
Kazuhiro Kitazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE69924916D1 publication Critical patent/DE69924916D1/de
Publication of DE69924916T2 publication Critical patent/DE69924916T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G11C7/1027—Static column decode serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled bit line addresses
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/103—Read-write modes for single port memories, i.e. having either a random port or a serial port using serially addressed read-write data registers
    • G11C7/1033—Read-write modes for single port memories, i.e. having either a random port or a serial port using serially addressed read-write data registers using data registers of which only one stage is addressed for sequentially outputting data from a predetermined number of stages, e.g. nibble read-write mode
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
DE69924916T 1998-05-28 1999-02-15 Speicherschaltung Expired - Lifetime DE69924916T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP14676598A JP4060442B2 (ja) 1998-05-28 1998-05-28 メモリデバイス
JP14676598 1998-05-28

Publications (2)

Publication Number Publication Date
DE69924916D1 true DE69924916D1 (de) 2005-06-02
DE69924916T2 DE69924916T2 (de) 2005-09-29

Family

ID=15415065

Family Applications (2)

Application Number Title Priority Date Filing Date
DE69939717T Expired - Lifetime DE69939717D1 (de) 1998-05-28 1999-02-15 Speicherschaltung
DE69924916T Expired - Lifetime DE69924916T2 (de) 1998-05-28 1999-02-15 Speicherschaltung

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE69939717T Expired - Lifetime DE69939717D1 (de) 1998-05-28 1999-02-15 Speicherschaltung

Country Status (6)

Country Link
US (1) US6172936B1 (de)
EP (2) EP1531480B1 (de)
JP (1) JP4060442B2 (de)
KR (1) KR100320266B1 (de)
DE (2) DE69939717D1 (de)
TW (1) TW487916B (de)

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US6601104B1 (en) * 1999-03-11 2003-07-29 Realtime Data Llc System and methods for accelerated data storage and retrieval
US6715067B1 (en) * 1999-09-21 2004-03-30 Intel Corporation Initializing a processor-based system from a non-volatile re-programmable semiconductor memory
US6539456B2 (en) * 1999-10-13 2003-03-25 Intel Corporation Hardware acceleration of boot-up utilizing a non-volatile disk cache
EP1103978B1 (de) * 1999-11-25 2009-01-28 STMicroelectronics S.r.l. Nichtflüchtiger Speicher mit Burstlesebetrieb sowie entsprechendes Leseverfahren
US6205084B1 (en) * 1999-12-20 2001-03-20 Fujitsu Limited Burst mode flash memory
EP1122737A1 (de) 2000-01-31 2001-08-08 STMicroelectronics S.r.l. Schaltung zur Steuerung von Datenströmenübertragung aus mehrerer Quellen eines Systems
EP1122735B1 (de) 2000-01-31 2010-09-01 STMicroelectronics Srl Verschachtelter Datenpfad und Ausgabesteuerungsarchitektur für einen verschachtelten Speicher sowie Impulsgeber zum Ausgeben von gelesenen Daten
US6452864B1 (en) 2000-01-31 2002-09-17 Stmicroelectonics S.R.L. Interleaved memory device for sequential access synchronous reading with simplified address counters
EP1122736B1 (de) 2000-01-31 2009-10-28 STMicroelectronics S.r.l. Erzeugung eines Addressenübergangssignals (ATD) für eine synchrone Speicheranordnung
EP1122739A3 (de) 2000-01-31 2003-12-17 STMicroelectronics S.r.l. Beschleunigte Ubertragungserzeugung
DE60019081D1 (de) 2000-01-31 2005-05-04 St Microelectronics Srl Verschachtelter Burst-Speicher mit Burst-Zugriff bei synchronen Lesezyklen, wobei die beiden untergeordneten Speicherfelder unabhängig lesbar sind mit wahlfreiem Zugriff während asynchroner Lesezyklen
EP1122887A1 (de) 2000-01-31 2001-08-08 STMicroelectronics S.r.l. Vorladeschaltung für einen Ausgangspuffer
EP1122733A1 (de) 2000-01-31 2001-08-08 STMicroelectronics S.r.l. Interne Regeneration eines Adressfreigabesignals (ALE) von einem Steuerprotokoll eines verschachtelten Burst-Speichers sowie entsprechende Schaltung
US6624679B2 (en) 2000-01-31 2003-09-23 Stmicroelectronics S.R.L. Stabilized delay circuit
US20010047473A1 (en) * 2000-02-03 2001-11-29 Realtime Data, Llc Systems and methods for computer initialization
US20030191876A1 (en) * 2000-02-03 2003-10-09 Fallon James J. Data storewidth accelerator
DE60011035T2 (de) 2000-03-02 2004-09-16 Stmicroelectronics S.R.L., Agrate Brianza Verfahren zur logischen Aufteilung einer nichtflüchtigen Speichermatrix
US6851026B1 (en) * 2000-07-28 2005-02-01 Micron Technology, Inc. Synchronous flash memory with concurrent write and read operation
US6621761B2 (en) * 2000-05-31 2003-09-16 Advanced Micro Devices, Inc. Burst architecture for a flash memory
DE10037004B4 (de) * 2000-07-29 2004-01-15 Sms Demag Ag Walzgerüst für bandkantenorientiertes Verschieben der Zwischenwalzen in einem 6-Walzen-Gerüst
US6691204B1 (en) * 2000-08-25 2004-02-10 Micron Technology, Inc. Burst write in a non-volatile memory device
US7417568B2 (en) * 2000-10-03 2008-08-26 Realtime Data Llc System and method for data feed acceleration and encryption
US9143546B2 (en) * 2000-10-03 2015-09-22 Realtime Data Llc System and method for data feed acceleration and encryption
US8692695B2 (en) 2000-10-03 2014-04-08 Realtime Data, Llc Methods for encoding and decoding data
DE10050604A1 (de) * 2000-10-12 2002-04-25 Siemens Ag Verfahren zum Starten einer Datenverarbeitungsanlage sowie zugehörige Komponenten
US7386046B2 (en) * 2001-02-13 2008-06-10 Realtime Data Llc Bandwidth sensitive data compression and decompression
JP2002337402A (ja) * 2001-03-15 2002-11-27 Ricoh Co Ltd 画像形成装置
US6400611B1 (en) * 2001-03-23 2002-06-04 Atmel Corporation Independent asynchronous boot block for synchronous non-volatile memory devices
AU2002331774A1 (en) * 2001-08-29 2003-03-18 Analog Devices, Inc. Methods and apparatus utilizing flash burst mode to improve processor performance
GB0122401D0 (en) * 2001-09-17 2001-11-07 Ttp Communications Ltd Interfacing processors with external memory
US6754132B2 (en) * 2001-10-19 2004-06-22 Samsung Electronics Co., Ltd. Devices and methods for controlling active termination resistors in a memory system
US6791898B1 (en) * 2002-10-11 2004-09-14 Cypress Semiconductor Corporation Memory device providing asynchronous and synchronous data transfer
JP4386706B2 (ja) * 2003-11-06 2009-12-16 富士通マイクロエレクトロニクス株式会社 半導体記憶装置
WO2006003693A1 (ja) * 2004-06-30 2006-01-12 Renesas Technology Corp. データプロセッサ
US8103805B2 (en) 2005-04-29 2012-01-24 Micron Technology, Inc. Configuration finalization on first valid NAND command
US7245552B2 (en) 2005-06-22 2007-07-17 Infineon Technologies Ag Parallel data path architecture
US8255108B2 (en) * 2005-08-31 2012-08-28 Spx Corporation Dynamic file system creation for scan tools
US7787324B2 (en) 2006-10-13 2010-08-31 Marvell World Trade Ltd. Processor instruction cache with dual-read modes
US8027218B2 (en) 2006-10-13 2011-09-27 Marvell World Trade Ltd. Processor instruction cache with dual-read modes
US8266405B2 (en) * 2006-12-13 2012-09-11 Cypress Semiconductor Corporation Memory interface configurable for asynchronous and synchronous operation and for accessing storage from any clock domain
TWI345788B (en) * 2007-11-02 2011-07-21 Inventec Corp Memory reset apparatus
US8291248B2 (en) 2007-12-21 2012-10-16 Mosaid Technologies Incorporated Non-volatile semiconductor memory device with power saving feature
CN101903953B (zh) * 2007-12-21 2013-12-18 莫塞德技术公司 具有功率节省特性的非易失性半导体存储器设备
US8386759B1 (en) * 2007-12-28 2013-02-26 Altera Corporation Integrated circuit boot method and apparatus for configuring memory device read mode using programmable circuitry boot code read from the memory device
JP4759717B2 (ja) * 2008-02-18 2011-08-31 スパンション エルエルシー 同期型不揮発性メモリおよびメモリシステム
JP2010044822A (ja) * 2008-08-12 2010-02-25 Toppan Printing Co Ltd 半導体メモリ
US7916575B2 (en) * 2008-12-23 2011-03-29 Emanuele Confalonieri Configurable latching for asynchronous memories

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KR960003526B1 (ko) * 1992-10-02 1996-03-14 삼성전자주식회사 반도체 메모리장치
EP0561370B1 (de) * 1992-03-19 1999-06-02 Kabushiki Kaisha Toshiba Taktsynchronisierter Halbleiterspeicheranordnung und Zugriffsverfahren
US6175901B1 (en) * 1994-04-15 2001-01-16 Micron Technology, Inc. Method for initializing and reprogramming a control operation feature of a memory device
US5696917A (en) * 1994-06-03 1997-12-09 Intel Corporation Method and apparatus for performing burst read operations in an asynchronous nonvolatile memory

Also Published As

Publication number Publication date
KR100320266B1 (ko) 2002-01-10
JP4060442B2 (ja) 2008-03-12
EP0961283A2 (de) 1999-12-01
JPH11339484A (ja) 1999-12-10
DE69924916T2 (de) 2005-09-29
DE69939717D1 (de) 2008-11-20
EP1531480B1 (de) 2008-10-08
EP0961283B1 (de) 2005-04-27
KR19990087864A (ko) 1999-12-27
US6172936B1 (en) 2001-01-09
EP1531480A3 (de) 2006-07-26
EP1531480A2 (de) 2005-05-18
EP0961283A3 (de) 2000-05-17
TW487916B (en) 2002-05-21

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU MICROELECTRONICS LTD., TOKYO, JP

8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU SEMICONDUCTOR LTD., YOKOHAMA, KANAGAWA, JP

8328 Change in the person/name/address of the agent

Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE