JP4852694B2 - 半導体集積回路およびその製造方法 - Google Patents
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Description
図1は、本発明の参考例1を示す図であって、図1(a)は、SOI基板上に形成されたシリコンフィン高さの異なる二重ゲートMOS電界効果トランジスタを有する半導体集積回路の平面図であり、図1(b)は、そのA−A′線での断面図である。図1において、1はシリコン基板、2は埋め込み酸化膜、3はゲート電極、4は絶縁膜、5はシリコン結晶層の一部に形成されたチャンネル領域で、図の左側のトランジスタのフィンチャネル高さは右側のトランジスタのフィンチャネル高さより高い。6はゲート絶縁膜、7はシリコン結晶層の一部に形成されたソース領域、8はシリコン結晶層の一部に形成されたドレイン領域、9aは選択酸化領域である。本参考例においては、各トランジスタのチャネル領域の両面に形成されたゲート絶縁膜はそれぞれ同じ膜厚に形成されている。すなわち、それぞれのゲート絶縁膜の膜厚をt1、t2として、t1=t2である。
図6に本発明の参考例2を示す。図6(a)は、本参考例に係わる、SOI基板上に形成した、シリコンフィン高さの異なる二重ゲートMOS電界効果トランジスタを有するCMOSインバータの平面図であり、図6(b)はそのA-A′線での断面図である。図6において、図1に示される参考例1の部分と同等の部分には同一の参照符号を付し、重複する説明は省略する。図6において、5p、7p、8pは、pMOSのチャネル領域とソース領域とドレイン領域であり、5n、7n、8nは、nMOSのチャネル領域とソース領域とドレイン領域である。本参考例においては、ゲート電極3が、pMOSとnMOSとに共通に形成され、pMOSのドレイン領域8pとnMOSのドレイン領域8nとがコンタクトメタル層12により接続されている。
図7に本発明の参考例3を示す。図7(a)は、本参考例に係わる、SOI基板上に形成した、シリコンフィン高さの異なる二重ゲートMOS電界効果トランジスタを有する半導体集積回路の平面図であり、図7(b)はそのA-A′線での断面図である。図7において、図1に示される参考例1の部分と同等の部分には同一の参照符号を付し、重複する説明は省略する。図7(b)において、13はトランジスタ間を分離するCVD酸化膜である。本参考例においては、フィンチャネル高さの高いトランジスタのゲート電極が、ゲート電極31とゲート電極32に2つに分離されている。
図8に本発明の参考例4を示す。図8(a)は、本参考例に係わる、SOI基板上に形成した、シリコンフィン高さの異なる二重ゲートMOS電界効果トランジスタを有する半導体集積回路の平面図であり、図8(b)はそのA-A′線での断面図である。図8において、図7に示される参考例3の部分と同等の部分には同一の参照符号を付し、重複する説明は省略する。本参考例においては、対となるゲート絶縁膜が異なる膜厚に形成されている。図8において、61は膜厚の薄い方のゲート絶縁膜であり、62は膜厚の厚い方のゲート絶縁膜である。すなわち、それぞれのゲート絶縁膜の膜厚をt1、t2として、t1<t2である。参考例4の作製工程は基本的に参考例3のそれと同様である。異なる点は、次の1点である。(1)シリコンフィンを作製する際に、まず片側のシリコンフィン側面を作製しておき、そのフィンの側面に厚いゲート酸化膜を作製する。その後に精密合わせ露光によりもう片側のフィン側面を作製し、薄いゲート酸化膜を形成する。
図9に本発明の参考例5を示す。図9(a)は、本発明の参考例に係わる、SOI基板上に形成した、シリコンフィン高さの異なる二重ゲートMOS電界効果トランジスタを有する半導体集積回路の平面図であり、図9(b)はそのA-A′線での断面図である。図9において、図7に示される参考例3の部分と同等の部分には同一の参照符号を付し、重複する説明は省略する。本参考例においては、シリコンフィン高さの高い方のトランジスタのみならず、シリコンフィン高さの低い方のトランジスタにおいてもゲート電極が、ゲート電極31とゲート電極32に分離されている。参考例5の作製工程は基本的に参考例3と同様である。異なる点は、次の1点である。(1)ゲート加工の際に(電極材料層3aのパターニング時に)、高さの低い方のシリコンフィン上に、スリットを入れる。
次に、図12(f)に示すように、シリコン基板1をロストウエハ(Lost Wafer)技術で取り除く。ロストウエハ技術としては、有機アルカリ水溶液でシリコンを溶かすウェットエッチング方法とdeep-RIE(deep Reactive Ion Etching)を用いるドライエッチング方法がある。この二つの方法とも、本工程に対して非常に有効である。ロストウエハした後注目すべき点は、図12(f)に示すように、シリコン結晶層5aは、高さは部分的に異なるがその最上面は平坦で同一平面になされていることである。ここに、段差を有するシリコン結晶層を有するSOI基板が新たに形成されたことになる。
2 埋め込み酸化膜
3、31、32、3n、3p ゲート電極
3a 電極材料層
4 絶縁膜
5、5n、5p チャネル領域
5a シリコン結晶層
6、61、62 ゲート絶縁膜
7、7n、7p ソース領域
8、8n、8p ドレイン領域
9 選択酸化膜
9a 選択酸化領域
10 酸化保護膜
11 レジスト膜
12 コンタクトメタル層
13、15、16 CVD酸化膜
14 シリコン支持基板
Claims (15)
- 埋め込み酸化膜上に形成され、起立した半導体よりなる起立薄膜横方向チャネル領域と、前記起立薄膜横方向チャネル領域の横方向の端部に隣接して形成されたソース領域およびドレイン領域と、前記起立薄膜横方向チャネル領域の両側面に形成されたゲート絶縁膜およびゲート電極と、を備えた二重ゲートMOS電界効果トランジスタを同一基板上に複数個有する半導体集積回路であって、2種類の異なる高さの起立薄膜横方向チャネル領域の二重ゲートMOS電界効果トランジスタは基板上の段差部にそれぞれ起立して配置されるとともに、該2種類の異なる高さの起立薄膜横方向チャネル領域の頂部が同じ平面上にあることを特徴とする半導体集積回路。
- 高さの高い方の起立薄膜横方向チャネル領域を有するトランジスタがpチャネルMOS電界効果トランジスタであり、高さの低い方の起立薄膜横方向チャネル領域を有するトランジスタがnチャネルMOS電界効果トランジスタであることを特徴とする請求項1に記載の半導体集積回路。
- 高さの高い方の起立薄膜横方向チャネル領域を有する二重ゲートMOS電界効果トランジスタの一対のゲート電極は互いに電気的に独立であり、高さの低い方の起立薄膜横方向チャネル領域を有する二重ゲートMOS電界効果トランジスタの一対のゲート電極は電気的に接続されていることを特徴とする請求項1または2に記載の半導体集積回路。
- 各二重ゲートMOS電界効果トランジスタの一対のゲート電極は互いに電気的に独立であることを特徴とする請求項1または2に記載の半導体集積回路。
- 各二重ゲートMOS電界効果トランジスタの一対のゲート絶縁膜の膜厚が異なることを特徴とする請求項1から4のいずれかに記載の半導体集積回路。
- 前記起立薄膜横方向チャネル領域、前記ソース領域および前記ドレイン領域が結晶シリコンにより形成されていることを特徴とする請求項1から5のいずれかに記載の半導体集積回路。
- 前記起立薄膜横方向チャネル領域、前記ソース領域および前記ドレイン領域がSOI基板のシリコン層により形成されていることを特徴とする請求項1から5のいずれかに記載の半導体集積回路。
- 前記起立薄膜横方向チャネル領域のゲート絶縁膜に接する面が(111)方位の面であることを特徴とする請求項6または7に記載の半導体集積回路。
- 請求項1から8のいずれかに記載された半導体集積回路を重ねて多層構造としたことを特徴とする半導体集積回路。
- 支持基板上に埋め込み酸化膜を介して形成された所定の層厚を有する半導体層を部分的に除去して層厚の薄い低高さ領域を部分的に形成する工程と、絶縁膜を堆積し、該絶縁膜を研磨して該絶縁膜の表面を平坦化する工程と、前記絶縁膜上に第2支持基板を貼り合わせる工程と、前記支持基板及び前記埋め込み酸化膜を除去する工程と、所定の層厚を有する半導体層領域と前記低高さ領域とにそれぞれ起立した半導体層よりなり、頂部が同じ平面上にある起立薄膜横方向チャネル領域と、前記起立薄膜横方向チャネル領域の横方向の端部に隣接して設けられたソース領域およびドレイン領域と、前記起立薄膜横方向チャネル両側面に設けられたゲート絶縁膜およびゲート電極と、を備えた二重ゲートMOS電界効果トランジスタを形成する工程と、を有することを特徴とする半導体集積回路の製造方法。
- 支持基板上に埋め込み酸化膜を介して形成された所定の層厚を有する半導体層を部分的に除去して層厚の薄い低高さ領域を部分的に形成する工程と、絶縁膜を堆積し、該絶縁膜を研磨して該絶縁膜の表面を平坦化する工程と、前記絶縁膜上に第2支持基板を貼り合わせる工程と、前記支持基板及び前記埋め込み酸化膜を除去する工程と、所定の層厚を有する半導体層領域と前記低高さ領域とにそれぞれ起立した半導体層よりなり、頂部が同じ平面上にある起立薄膜横方向チャネル領域と、前記起立薄膜横方向チャネル領域の横方向の端部に隣接して設けられたソース領域およびドレイン領域と、前記起立薄膜横方向チャネル両側面に設けられたゲート絶縁膜およびゲート電極と、を備えた二重ゲートMOS電界効果トランジスタを形成する工程と、該二重ゲートMOS電界効果トランジスタの表面に絶縁層を堆積し、該絶縁層を研磨して該絶縁層の表面を平坦化する工程と、同様な工程により形成された二重ゲートMOS電界効果トランジスタを別に用意し、前記絶縁層同士を貼り合わせることにより前記二重ゲートMOS電界効果トランジスタを多層化する工程と、を有することを特徴とする半導体集積回路の製造方法。
- 前記低高さ領域を部分的に形成する工程が、部分的に熱酸化膜を形成する工程と、該熱酸化膜を除去する工程とを含むことを特徴とする請求項10から11のいずれかに記載の半導体集積回路の製造方法。
- 前記二重ゲートMOS電界効果トランジスタを形成する工程が、起立薄膜横方向チャネル領域、ソース領域およびドレイン領域の形成予定領域上を覆うマスクを形成する工程と、該マスクにより保護されない領域をエッチング除去して起立薄膜横方向チャネル領域、ソース領域およびドレイン領域を形成する工程と、前記起立薄膜横方向チャネル領域の両側面にゲート絶縁膜を形成する工程と、前記起立薄膜横方向チャネル領域の両側面に形成されたゲート絶縁膜上にそれぞれゲート電極を形成する工程と、を含むことを特徴とする請求項10から12のいずれかに記載の半導体集積回路の製造方法。
- 所定の層厚を有する半導体層の領域に形成されるソース・ドレイン領域にp型の不純物を、低高さ領域に形成されるソース・ドレイン領域にn型の不純物を導入する工程が付加されることを特徴とする請求項13に記載の半導体集積回路の製造方法。
- 前記半導体層が(110)面を主面とする単結晶シリコン層であって、前記起立薄膜横方向チャネル領域のチャネル方向が<112>方向であることを特徴とする請求項10から14のいずれかに記載の半導体集積回路の製造方法。
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