WO2013190863A1 - 積層型半導体装置及びその製造方法 - Google Patents

積層型半導体装置及びその製造方法 Download PDF

Info

Publication number
WO2013190863A1
WO2013190863A1 PCT/JP2013/055527 JP2013055527W WO2013190863A1 WO 2013190863 A1 WO2013190863 A1 WO 2013190863A1 JP 2013055527 W JP2013055527 W JP 2013055527W WO 2013190863 A1 WO2013190863 A1 WO 2013190863A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor device
layer
forming
metal electrode
complementary
Prior art date
Application number
PCT/JP2013/055527
Other languages
English (en)
French (fr)
Inventor
池田　圭司
手塚　勉
雄一 上牟田
喜代恵 古瀬
Original Assignee
独立行政法人産業技術総合研究所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 独立行政法人産業技術総合研究所 filed Critical 独立行政法人産業技術総合研究所
Publication of WO2013190863A1 publication Critical patent/WO2013190863A1/ja
Priority to US14/577,209 priority Critical patent/US9721951B2/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02592—Microstructure amorphous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a stacked semiconductor device using a Ge channel and a manufacturing method thereof.
  • Non-Patent Document 3 a technique for laminating a CMOS with an a-Si-TFT on the intermediate wiring layer or the uppermost layer of the CMOS has been reported (for example, see Non-Patent Document 3).
  • the performance of the a-Si-TFT is extremely poor as compared with normal Si-CMOS, and it is difficult to set an appropriate threshold value. For this reason, there are various limitations such as an increase in driving voltage or an increase in leakage current. Therefore, at present, the advantages of high performance and low power consumption due to three-dimensional stacking are not fully enjoyed.
  • the problem to be solved by the invention is that an upper layer semiconductor device having a high-performance CMOS circuit can be stacked on a base semiconductor device having a CMOS structure, so that high performance and low power consumption of the 3D-CMOS structure can be achieved.
  • An object of the present invention is to provide a stacked semiconductor device that can be measured and a method for manufacturing the same.
  • the stacked semiconductor device includes a first complementary semiconductor device in which a CMOS circuit and a wiring layer are formed on a semiconductor substrate, and a metal formed together with the wiring layer on the first complementary semiconductor device.
  • a second complementary semiconductor device formed by forming a pMOSFET in the semiconductor layer of the pMOS region.
  • an upper semiconductor device having a high-performance CMOS circuit can be stacked on a base semiconductor device having a CMOS structure by a combination of selection of channel material / polarity and electrode structure. Therefore, high performance and low power consumption of the 3D-CMOS structure can be achieved.
  • 1 is a cross-sectional view showing an element structure of a stacked semiconductor device according to a first embodiment. It is an equivalent circuit diagram showing an example in which the stacked semiconductor device of the first embodiment is applied to a CMOS inverter. 1 is a layout diagram illustrating an example in which the stacked semiconductor device according to the first embodiment is applied to a CMOS inverter. 1 is an equivalent circuit diagram illustrating an example in which the stacked semiconductor device according to the first embodiment is applied to a NAND circuit. 1 is a layout diagram illustrating an example in which the stacked semiconductor device according to the first embodiment is applied to a NAND circuit. It is a figure which shows the threshold value characteristic of pMOSFET and GeMOSFET of Ge channel. It is sectional drawing which shows the manufacturing process of the laminated semiconductor device concerning 2nd Embodiment. It is sectional drawing which shows the manufacturing process of the laminated semiconductor device concerning 2nd Embodiment.
  • FIG. 1 is a cross-sectional view showing the element structure of the stacked semiconductor device according to the first embodiment.
  • a base CMOS circuit (first complementary semiconductor device) 100 is formed on the Si support substrate 110. Specifically, an nMOSFET and a pMOSFET comprising a gate insulating film 112, a gate electrode 113, and source / drain regions (not shown) are formed on the substrate 110, and multilayer wiring layers 131 to 134 are formed thereon. By forming this, a Si-CMOS circuit is manufactured. In the uppermost layer, metal electrodes 141 and 142 are formed by the same process as the wiring layers 131 to 134 and the vias 120 to 129.
  • a work function control layer 211 for pMOS is formed on the metal electrode 141, and a work function control layer 212 for nMOS is formed on the metal electrode 142.
  • a semiconductor layer 231 mainly composed of Ge is formed with an interlayer insulating film 220 interposed therebetween.
  • a pMOSFET composed of a gate insulating film 241, a gate electrode 251, and a metal S / D 261 is formed on the semiconductor layer 231.
  • a semiconductor layer 232 mainly composed of Ge is formed with an interlayer insulating film 220 interposed therebetween.
  • an nMOSFET composed of a gate insulating film 242, a gate electrode 252, and a metal S / D 262 is formed. That is, an upper layer CMOS circuit (second complementary semiconductor device) using Ge as a channel is formed.
  • 111 denotes an element isolation insulating film
  • 114 denotes a gate sidewall insulating film
  • 150 denotes an interlayer insulating film for a lower CMOS circuit.
  • reference numeral 270 denotes an interlayer insulating film for the upper layer CMOS circuit
  • 280 denotes a via for the upper layer CMOS circuit
  • 290 denotes a wiring layer for the upper layer CMOS circuit.
  • the lower layer is the Si-CMOS circuit 100
  • the upper layer Ge-CMOS circuit 200 made of pMOSFET and nMOSFET using Ge as a channel is formed above the Si-CMOS circuit via the interlayer film.
  • the lower-layer Si-CMOS circuit 100 and the upper-layer Ge-CMOS circuit 200 are integrated by being electrically connected via via wiring.
  • a so-called “BEOL Tr” Back End Of Line Transistor
  • BEOL Tr Back End Of Line Transistor
  • the mounting position of BEOL Tr. Is not limited to this layer, and the intermediate layer first layer (for example, the wiring 131) is used as a base electrode, and the case where it is mounted between the first layer and the second layer is used as the bottom layer. It can be mounted on any layer beyond this.
  • FIGS. 2 and 3 are diagrams for explaining a CMOS circuit in which an inverter is configured by “BEOL Tr” of this embodiment
  • FIG. 2 is an equivalent circuit diagram
  • FIG. 3 is a layout diagram.
  • metal electrodes 141 and 142 formed of a lower wiring layer are arranged. Then, Vbgp and Vbgn can be independently applied to the metal electrodes 141 and 142 by a back gate bias power source prepared independently from the signal line.
  • FIGS. 4 and 5 are diagrams for explaining a CMOS circuit in which a NAND circuit is configured by “BEOL Tr.”
  • FIG. 4 is an equivalent circuit diagram
  • FIG. 5 is a layout diagram. Similar to the examples of FIGS. 2 and 3, metal electrodes 141 and 142 formed of lower wiring layers are arranged in each circuit block constituting the pMOSFET and nMOSFET, and Vbgp and Vbgn can be applied by a back gate bias power source. It is possible. For this reason, the threshold voltage can be controlled independently in the nMOSFET and pMOSFET in both the boost and sleep directions. Therefore, it is possible to realize a configuration capable of adaptive threshold voltage setting in accordance with the calculation frequency and required speed of the circuit.
  • FIG. 6 is a diagram showing threshold characteristics of a p-channel MOSFET and an n-channel MOSFET using a Ge channel.
  • the solid line in FIG. 6 indicates no control, the broken line indicates a boost state by adjusting the back gate voltage (Vbgn> 0, Vbgp ⁇ 0), and the dotted line indicates a sleep state by adjusting the back gate voltage (Vbgn ⁇ 0, Vbgp ⁇ 0).
  • Vbgn> 0, Vbgp ⁇ 0 the back gate voltage
  • Vbgp ⁇ 0 the back gate voltage
  • the on-current increases and is suitable for high-speed operation.
  • the sleep state off-state current is reduced and low power consumption operation is possible.
  • the threshold values of the pMOSFET and nMOSFET using the Ge channel can be shifted, and the performance of the Ge-CMOS circuit can be adjusted to the characteristics required for the device. it can.
  • BEOL Tr. Formed in the wiring intermediate layer or uppermost layer has a higher mobility than a-Si in both nMOSFET and pMOSFET, and is composed of a poly-Ge channel that is expected to increase current driving capability. .
  • Each transistor is formed on metal electrodes (GP) 141 and 142 formed simultaneously with the wiring layer via work function control layers 211 and 212 and an interlayer insulating film 220. Then, for each of the nMOSFET and the pMOSFET in the GP, voltage control is performed by a power source line independent from the so-called “FEOL” Tr. (Front “End” Of “Line Transistor”) and “BEOL” Tr. By performing the above, dynamic threshold control can be performed.
  • BEOL Tr. May be either depletion type operation or inversion type operation for both nMOSFET and pMOSFET.
  • the work function control layers 211 and 212 deposited on the GP can set threshold values according to circuit requirements.
  • BEOL Tr. In the conventional structure, the performance and process cost of BEOL Tr. Formed in the wiring intermediate layer or the uppermost layer are contradictory and cannot satisfy both at the same time. In contrast, in the present embodiment, it is possible to form BEOL Tr. ⁇ ⁇ ⁇ ⁇ having an appropriate threshold value and current driving capability at a process temperature that does not degrade the underlying CMOS circuit (FEOL Tr.).
  • the Ge channel As described above, according to the present embodiment, by using the Ge channel as the upper CMOS circuit 200, it is possible to lower the process temperature and improve the performance (lower voltage) by the mobility higher than that of Si. In addition, since the wiring process and the back gate (Grand plane) forming process can be merged, the cost can be reduced. Further, the metal electrodes 141 and 142 can constitute a back gate, and can be formed in common with nMOSFETs and pMOSFETs. Thus, the problem of gate depletion, which is a problem in the conventional method of forming GP by ion implantation into a semiconductor, can also be avoided.
  • the threshold value can be appropriately set by the work function control layers 211 and 212 deposited on the GP, the power consumption can be reduced by reducing the off-current during standby. Furthermore, even under the above threshold setting, by biasing the back gate (GP) voltage to the boost side, adaptive power control can be realized such that the threshold setting is lowered only when high speed operation is required. This contributes to high performance, low power consumption and low cost of 3D-CMOS. Further, since the source / drain is made of NiGe alloy, there is an advantage that the resistance of the source / drain can be reduced.
  • the combination of the channel material, polarity, and electrode structure of this configuration comprehensively solves the problems of the background art, thereby improving the performance, power consumption, and cost of 3D CMOS. Can contribute.
  • a pMOSFET and an nMOSFET are formed on a Si support substrate 11 by a known process. These are connected by wiring layers 131 to 134 and vias 120 to 129, thereby forming a Si-CMOS circuit (first complementary semiconductor device) 100.
  • the pMOS metal electrode 141 and the nMOS metal electrode 142 are formed on the uppermost layer by the same process as the wiring layers 131 to 134.
  • a via 129 that is electrically connected to the transistor of the Si-CMOS circuit 100 is exposed on the uppermost surface of the Si-CMOS circuit 100.
  • a so-called damascene process can be used. For example, after providing grooves corresponding to the pattern of the back gate of “BEOL” Tr. “On the surface of the interlayer insulating film 150, a metal material is deposited on the entire surface. Then, the metal electrodes 141 and 142 are formed only in the grooves by planarizing the surface by CMP.
  • a barrier metal may be formed in the groove before forming the metal film.
  • a barrier metal may be formed in a portion in contact with the interlayer insulating film 150. Further, for the vias 120 to 129, a barrier metal may be formed at the interface with the base as necessary.
  • a pMOSFET work function control layer 211 is formed in the pMOS region by an n and p generation process using a normal lithography process, and the nMOS An nMOSFET work function control layer 212 is formed in the region.
  • a TiN film (work function control layer) 211 is formed on the metal electrode 141 by sputtering, and an HfO 2 / TiN film (work function control layer) 212 is formed on the metal electrode 142 by sputtering.
  • an a-Ge layer 230 having a thickness of 30 nm to be a channel of the upper CMOS circuit is formed by CVD or It is formed by sputtering.
  • the active pattern is separated into islands by mesa etching in accordance with the pMOS region and the nMOS region, and then a-Ge is polycrystallized by low-temperature annealing at 500 ° C. or lower.
  • Ge layers 231 and 232 are formed. That is, the polyGe layer 231 is formed on the metal electrode 141 serving as the back gate for the pMOSFET via the work function control layer 211 and the interlayer insulating film 220. Further, a poly Ge layer 232 is formed on the metal electrode 142 serving as a back gate for the nMOSFET via the work function control layer 212 and the interlayer insulating film 220.
  • the metal electrodes 141 and 142 exist on the base of the a-Ge layer 230, heat easily escapes when the a-Ge layer 230 is annealed. Thereby, crystallization is promoted and the crystal grains can be increased.
  • the annealed Ge layers 231 and 232 are polycrystalline. However, when the device is miniaturized and the channel length is close to the grain size, even if polycrystalline, it is regarded as substantially the same as a single crystal. Is possible.
  • an Al 2 O 3 film (4 nm) formed by ALD film formation at 250 ° C. or SiO 2 (5 nm) formed by PECVD is deposited on the Ge layers 231 and 232 as a gate insulating film.
  • a TaN film (30 nm) is deposited thereon by sputtering.
  • a gate electrode is formed by gate patterning and etching by a normal lithography process. That is, the gate electrode 251 is formed in the pMOS region through the gate insulating film 241, and the gate electrode 252 is formed in the nMOS region through the gate insulating film 242. At this time, both sides of the gate electrodes 251 and 252 may be oxidized to form a sidewall insulating film.
  • a metal S / D261 made of NiGe alloy formed by Ni deposition and low-temperature annealing ( ⁇ 350 ° C.) is formed on the source / drain of the pMOSFET.
  • a NiGe alloy is similarly formed in an nMOSFET, but in an nMOSFET, an S (sulfur) impurity is implanted before Ni deposition, and a metal S / D262 having a structure in which a high concentration sulfur segregation region is formed at the NiGe / Ge interface at the time of NiGe formation is formed. To do.
  • the Schottky barrier between the metal S / D layer (NiGe) 262 and the Ge layer 232 can be controlled, the parasitic resistance can be lowered, and the drive current can be increased. Thereafter, the unreacted Ni film is removed with dilute hydrochloric acid or the like.
  • the contact holes for connecting to the metal electrodes 141 and 142 serving as back gates and the source / drain regions 251 and 252 respectively. Form.
  • a conductive material such as Cu is embedded in the contact hole, and then planarized by CMP.
  • the Al wiring layer 290 and forming the CMOS circuit the structure shown in FIG. 1 is completed. Further, a passivation film is formed as necessary.
  • the wiring layer 290 may also be formed by a damascene process in the same manner as the metal electrodes 141 and 142 and the other wiring layers 131 to 134. That is, a wiring groove may be provided together with the contact hole in the step of FIG. 8G, and a metal material may be embedded in the wiring groove.
  • both the pMOS and nMOS use the poly Ge layer 230 having higher mobility than a-Si as a channel, so that a higher speed device can be manufactured. Moreover, since Ge can be formed at a lower temperature than Si, the influence on the lower Si-CMOS circuit 100 when the upper Ge-CMOS circuit 200 is formed can be reduced.
  • the formation substrate of the second complementary semiconductor device is not necessarily limited to the Ge layer, and any substrate having Ge as a main component may be used. Furthermore, the formation substrate of the first complementary semiconductor device is not necessarily limited to the Si substrate, and a Ge substrate can be used, and a compound semiconductor can also be used.
  • the source / drain is formed of NiGe as the Ge channel MOSFET structure of the second complementary semiconductor device.
  • the present invention is not limited to this, and other metals such as alloys of Co, Pd, Pt and Ge are used. Can do.
  • the source / drain is not necessarily limited to an alloy, and may be a diffusion layer formed by impurity doping.
  • the Ge channel MOSFET may have a so-called junctionless transistor structure having no pn junction between the source / drain (S / D) and the channel.
  • chalcogen elements such as Se and Te can also be used.
  • a combination of chalcogen elements S, Se, Te may be doped.
  • impurities suitable for n-type and p-type with respect to the Ge channel may be dope.
  • Si-CMOS circuit (first complementary semiconductor device) DESCRIPTION OF SYMBOLS 110 ... Si support substrate 111 ... Element isolation insulating film 112 ... Gate insulating film 113 ... Gate electrode 114 ... Gate side wall insulating film 120-129 ... Via 131-134 ... Wiring layer 141, 142 ... Metal electrode (back gate electrode) 150 ... interlayer insulating film 200 ... Ge-CMOS circuit (second complementary semiconductor device) 211, 212 ... work function control layer 220 ... interlayer insulating film 230 ... a-Ge layer 231, 232 ... poly Ge layer 241, 242 ... gate insulating film 251, 252 ... gate electrode 261, 262 ... metal S / D 270 ... Interlayer insulating film 280 ... Via 290 ... Wiring layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Engineering & Computer Science (AREA)
  • Composite Materials (AREA)
  • Materials Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

　積層型半導体装置であって、半導体基板（110）上にＣＭＯＳ回路及び配線層が形成された第１の相補型半導体装置（100）と、第１の相補型半導体装置（100）上に、配線層と共に形成された金属電極（141,142）と、金属電極（141,142）上に絶縁膜（220）を介して形成され、且つｎＭＯＳ領域とｐＭＯＳ領域で分離して形成された、Ｇｅを主成分とする半導体層（231,232）と、ｎＭＯＳ領域の半導体層にｎＭＯＳＦＥＴを形成し、ｐＭＯＳ領域の半導体層にｐＭＯＳＦＥＴを形成してなる第２の相補型半導体装置（200）と、を具備した。

Description

積層型半導体装置及びその製造方法
　本発明は、Ｇｅチャネルを用いた積層型半導体装置及びその製造方法に関する。
　半導体集積回路の高性能化、低消費電力化において、配線長短縮による寄生容量及び寄生抵抗の低減のために、トランジスタの３次元積層が有効である。３次元化は既に、Ｓｉチップを積み上げてＴＳＶ（Through Silicon Via）で接続する技術が開発中である。しかし、ＴＳＶサイズが通常のＣＭＯＳプロセスの配線間隔に比べ２ケタ以上大きいため、接続密度を上げて配線の効率化をはかるのは限界がある。また、ＴＳＶのためのエリアペナルティーが無視できない程度に大きいため、回路設計に支障を来たしたり、コストの増大を招いたりする。このため、より高密度に配線接続が可能な技術が求められる。
　ＴＳＶによるエリアペナルティの問題を解決する手法の一つとして、ＳＯＩ基板貼り合せによる３次元積層が提案され、下地ＣＭＯＳに匹敵する上部トランジスタ性能が得られることが報告されている（例えば、非特許文献１，２参照）。しかし、結晶Ｓｉ層を貼り合せることによるコスト増大の問題、上層トランジスタのプロセス温度、６００度による下地ＣＭＯＳへの影響は解決されていない。
　また、ＣＭＯＳの配線中間層若しくは最上層にａ－Ｓｉ－ＴＦＴによるＣＭＯＳを積層する技術が報告されている（例えば、非特許文献３参照）。しかし、ａ－Ｓｉ－ＴＦＴの性能は、通常のＳｉ－ＣＭＯＳに比べ極端に悪く、適切なしきい値設定が困難である。このため、駆動電圧が高くなる、或いはリーク電流が高くなる等種々の制限がある。従って、３次元積層化による高性能化、低消費電力化のメリットを十分享受できていないのが現状である。
P. Batude et al., VLSI Technical Digest, (2011) p.158 P. Batude et al., IEDM Technical Digest, (2011) p.151 T. Naito et al., 2010 Symposium on VLSI Technology, Technical Digest Papers, p.219
　発明が解決しようとする課題は、ＣＭＯＳ構造を有する下地半導体装置上に、高性能のＣＭＯＳ回路を有する上層半導体装置を積層することができ、３Ｄ－ＣＭＯＳ構造の高性能化及び低消費電力化をはかり得る積層型半導体装置及びその製造方法を提供することである。
　実施形態の積層型半導体装置は、半導体基板上にＣＭＯＳ回路及び配線層が形成された第１の相補型半導体装置と、前記第１の相補型半導体装置上に、前記配線層と共に形成された金属電極と、前記金属電極上に絶縁膜を介して形成され、且つｎＭＯＳ領域とｐＭＯＳ領域で分離して形成された、Ｇｅを主成分とする半導体層と、前記ｎＭＯＳ領域の前記半導体層にｎＭＯＳＦＥＴを形成し、前記ｐＭＯＳ領域の前記半導体層にｐＭＯＳＦＥＴを形成してなる第２の相補型半導体装置と、を具備したことを特徴とする。
　本発明の実施形態によれば、チャネル材料・極性、電極構の選択の組み合わせによって、ＣＭＯＳ構造を有する下地半導体装置上に、高性能のＣＭＯＳ回路を有する上層半導体装置を積層することができる。このため、３Ｄ－ＣＭＯＳ構造の高性能化及び低消費電力化をはかることができる。
第１の実施形態に係わる積層型半導体装置の素子構造を示す断面図である。 第１の実施形態の積層型半導体装置をＣＭＯＳインバータに適用した例を示す等価回路図である。 第１の実施形態の積層型半導体装置をＣＭＯＳインバータに適用した例を示すレイアウト図である。 第１の実施形態の積層型半導体装置をＮＡＮＤ回路に適用した例を示す等価回路図である。 第１の実施形態の積層型半導体装置をＮＡＮＤ回路に適用した例を示すレイアウト図である。 ＧｅチャネルのｐＭＯＳＦＥＴ及びｎＭＯＳＦＥＴのしきい値特性を示す図である。 第２の実施形態に係わる積層型半導体装置の製造工程を示す断面図である。 第２の実施形態に係わる積層型半導体装置の製造工程を示す断面図である。
　以下、本発明の実施形態を図面を参照して説明する。
　（第１の実施形態）
　図１は、第１の実施形態に係わる積層型半導体装置の素子構造を示す断面図である。
　Ｓｉ支持基板１１０上に下地ＣＭＯＳ回路（第１の相補型半導体装置）１００が形成されている。具体的には、基板１１０上に、ゲート絶縁膜１１２，ゲート電極１１３，及びソース／ドレイン領域（図示せず）からなるｎＭＯＳＦＥＴとｐＭＯＳＦＥＴを形成し、これらの上に多層の配線層１３１～１３４を形成することにより、Ｓｉ－ＣＭＯＳ回路が作製されている。また、最上層には、配線層１３１～１３４及びビア１２０～１２９と同一プロセスによる金属電極１４１，１４２が形成されている。
　金属電極１４１上には、ｐＭＯＳ用の仕事関数制御層２１１が形成され、金属電極１４２上には、ｎＭＯＳ用の仕事関数制御層２１２が形成されている。仕事関数制御層２１１上には、層間絶縁膜２２０を介してＧｅを主成分とする半導体層２３１が形成されている。この半導体層２３１に、ゲート絶縁膜２４１，ゲート電極２５１，及びメタルＳ／Ｄ２６１からなるｐＭＯＳＦＥＴが形成されている。仕事関数制御層２１２上には、層間絶縁膜２２０を介してＧｅを主成分とする半導体層２３２が形成されている。この半導体層２３２に、ゲート絶縁膜２４２，ゲート電極２５２，及びメタルＳ／Ｄ２６２からなるｎＭＯＳＦＥＴが形成されている。即ち、Ｇｅをチャネルとする上層ＣＭＯＳ回路（第２の相補型半導体装置）が形成されている。
　なお、図中の１１１は素子分離絶縁膜、１１４はゲート側壁絶縁膜、１５０は下層ＣＭＯＳ回路用の層間絶縁膜を示している。また、２７０は上層ＣＭＯＳ回路用の層間絶縁膜、２８０は上層ＣＭＯＳ回路用のビア、２９０は上層ＣＭＯＳ回路用の配線層を示している。
　このように本実施形態では、下層がＳｉ－ＣＭＯＳ回路１００で、その上部にＧｅをチャネルとするｐＭＯＳＦＥＴ及びｎＭＯＳＦＥＴからなる上層Ｇｅ－ＣＭＯＳ回路２００が、層間膜を介して形成されている。そして、下層Ｓｉ－ＣＭＯＳ回路１００と上層Ｇｅ－ＣＭＯＳ回路２００とは、ビア配線を介して電気的に接続することにより一体化されている。
　なお、本実施形態では、最上層とその一つ下の層との間にＧｅ－ＣＭＯＳ回路２００である、所謂 BEOL Tr.（Back End Of Line Transistor）を実装する構成を取っている。しかし、必ずしも BEOL Tr. の実装位置はこの層に限らず、中間層１層目（例えば、配線１３１）を下地電極とし、１層目と２層目の間に実装する場合を最下層として、これ以上の何れの層にも実装可能である。
　図２及び図３は、本実施形態の BEOL Tr. によりインバータを構成したＣＭＯＳ回路を説明するためのもので、図２は等価回路図、図３はレイアウト図である。ｐＭＯＳＦＥＴ，ｎＭＯＳＦＥＴを構成する各回路ブロックには、下層配線層で形成された金属電極１４１，１４２が配置されている。そして、信号線とは独立に用意したバックゲートバイアス電源によって、金属電極１４１，１４２にＶbgp 及びＶbgn を独立に印加することが可能となっている。
　図４及び図５は、本実施形態の BEOL Tr. によりＮＡＮＤ回路を構成したＣＭＯＳ回路を説明するためのもので、図４は等価回路図、図５はレイアウト図である。図２及び図３の例と同様に、ｐＭＯＳＦＥＴ，ｎＭＯＳＦＥＴを構成する各回路ブロックに下層配線層で形成された金属電極１４１，１４２が配置され、バックゲートバイアス電源によってＶbgp 及びＶbgn を印加することが可能となっている。このため、ブースト（Boost）、スリープ（Sleep）両方向にｎＭＯＳＦＥＴ，ｐＭＯＳＦＥＴ独立にしきい値電圧の制御が可能となる。従って、回路の演算頻度、要求速度に合わせたアダプティブなしきい値電圧設定が可能な構成を実現することができる。
　図６は、ＧｅチャネルによるｐＭＯＳＦＥＴ及びｎＭＯＳＦＥＴのしきい値特性を示す図である。図６中の実線は制御無しの場合、破線はバックゲート電圧の調整によるブースト状態（Ｖbgn＞０，Ｖbgp＜０）の場合、点線はバックゲート電圧の調整によるスリープ状態（Ｖbgn≦０，Ｖbgp≧０）の場合である。ブースト状態では、オン電流が増大し、高速動作に適している。また、スリープ状態では、オフ電流が低減し、低消費電力動作が可能となる。
　このようにバックゲート電圧を独立に制御することにより、Ｇｅチャネルを用いたｐＭＯＳＦＥＴ及びｎＭＯＳＦＥＴのしきい値をシフトさせることができ、Ｇｅ－ＣＭＯＳ回路の性能を装置に要求される特性に合わせることができる。
　本実施形態では、配線中間層若しくは最上層に形成する BEOL Tr. は、ｎＭＯＳＦＥＴ，ｐＭＯＳＦＥＴ共にａ－Ｓｉよりも高い移動度を持ち、電流駆動力の増大が期待されるポリＧｅチャネルにより構成される。各トランジスタは、配線層と同時形成される金属電極（Grand plane：ＧＰ）１４１，１４２上に、仕事関数制御層２１１，２１２及び層間絶縁膜２２０を介して形成される。そして、上記ＧＰにｎＭＯＳＦＥＴ，ｐＭＯＳＦＥＴの各々に対して、下地Ｓｉ－ＣＭＯＳ回路１００である、所謂 FEOL Tr.（Front End Of Line Transistor） 及び BEOL Tr. の信号線とは独立な電源線による電圧制御を行うことで、動的しきい値制御を行うことができる。BEOL Tr. は、ｎＭＯＳＦＥＴ，ｐＭＯＳＦＥＴ共に空乏型動作、反転型動作どちらでも構わない。ＧＰ上に堆積する仕事関数制御層２１１，２１２により、回路要求に合わせたしきい値設定を行うことができる。
　従来構造では、配線中間層若しくは最上層に形成する BEOL Tr. の性能とプロセスコストが二律背反で両者を同時に満たすことができない。これに対して本実施形態では、下地ＣＭＯＳ回路（FEOL Tr.）を劣化させないプロセス温度において、適切なしきい値、電流駆動力を有する BEOL Tr. を形成することができる。
　このように本実施形態によれば、上層ＣＭＯＳ回路２００としてＧｅチャネルを用いることで、プロセス温度の低温化と、Ｓｉより高い移動度による高性能化（低電圧化）が可能となる。また、配線工程とバックゲート（Grand plane）形成工程をマージできるため、コストの低減が可能となる。さらに、金属電極１４１，１４２でバックゲートを構成することができ、しかもｎＭＯＳＦＥＴ，ｐＭＯＳＦＥＴ共通で形成可能である。このことことから、ＧＰを半導体へのイオン注入によって形成する従来法で問題となるゲート空乏化の問題も回避できる。
　また、ＧＰ上に堆積する仕事関数制御層２１１，２１２により、適切なしきい値設定が可能なことから、スタンバイ時のオフ電流を低減することで低消費電力化が可能となる。さらに、上記のしきい値設定下においても、バックゲート（ＧＰ）電圧をブースト側にバイアスすることで、高速動作が必要な時のみ、しきい値設定を下げるといったアダプティブな電力制御を実現することが可能となり、３Ｄ－ＣＭＯＳの高性能化・低消費電力化・低コスト化に寄与する。また、ソース／ドレインをＮｉＧｅ合金としているので、ソース／ドレインの低抵抗化をはかり得ると云う利点もある。
　以上のように、本構成のチャネル材料・極性、電極構造の選択の組み合わせによって、背景技術の問題点が総合的に解決され、３次元ＣＭＯＳの高性能化・低消費電力化・低コスト化に寄与することができる。
　（第２の実施形態）
　次に、図１の積層型半導体装置の製造方法を、図７及び図８を参照して説明する。なお、図１と同一部分には同一符号を付して、その詳しい説明は省略する。
　まず、図７（ａ）に示すように、Ｓｉ支持基板１１上に周知のプロセスによりｐＭＯＳＦＥＴ及びｎＭＯＳＦＥＴを形成する。そして、これらを配線層１３１～１３４及びビア１２０～１２９で接続することにより、Ｓｉ－ＣＭＯＳ回路（第１の相補型半導体装置）１００を形成する。このとき、最上層にｐＭＯＳ用の金属電極１４１とｎＭＯＳ用の金属電極１４２を、配線層１３１～１３４と同じプロセスで形成する。また、金属電極１４１，１４２とは別に、Ｓｉ－ＣＭＯＳ回路１００の最上面に、Ｓｉ－ＣＭＯＳ回路１００のトランジスタと電気的に接続されるビア１２９を露出させる。
　金属電極１４１，１４２の具体的形成法としては、所謂ダマシンプロセスを用いることができる。例えば、層間絶縁膜１５０の表面に BEOL Tr. のバックゲートのパターンに対応する溝をそれぞれ設けた後に、全面に金属材料を堆積する。そして、ＣＭＰで表面を平坦化することにより、溝内のみに金属電極１４１，１４２を形成する。ここで、金属膜の形成前に溝内にバリアメタルを形成しても良い。他の配線層１３１～１３４に関しても、層間絶縁膜１５０と接する部分にバリアメタルを形成しても良い。さらに、ビア１２０～１２９に関しても、下地との界面に必要に応じてバリアメタルを形成しても良い。
　次いで、図７（ｂ）に示すように、通常のバリアメタルの替わりに、通常のリソグラフィ工程を用いたｎ，ｐ作り分けプロセスによって、ｐＭＯＳ領域にｐＭＯＳＦＥＴ用仕事関数制御層２１１を形成し、ｎＭＯＳ領域にｎＭＯＳＦＥＴ用仕事関数制御層２１２を形成する。具体的には、金属電極１４１上にＴｉＮ膜（仕事関数制御層）２１１をスパッタで形成し、金属電極１４２上にＨｆＯ2 ／ＴｉＮ膜（仕事関数制御層）２１２をスパッタで形成する。
　次いで、図７（ｃ）に示すように、仕事関数制御層２１１，２１２上に層間絶縁膜２２０を１０ｎｍ堆積した後に、上層ＣＭＯＳ回路のチャネルとなる厚さ３０ｎｍのａ－Ｇｅ層２３０をＣＶＤ若しくはスパッタにて形成する。
　次いで、図８（ｄ）に示すように、ｐＭＯＳ領域とｎＭＯＳ領域に合わせてアクティブパターンをメサエッチングによって島状に素子分離した後、５００℃以下の低温アニールによってａ－Ｇｅを多結晶化し、ポリＧｅ層２３１，２３２を形成する。即ち、ｐＭＯＳＦＥＴ用のバックゲートとなる金属電極１４１上に、仕事関数制御層２１１及び層間絶縁膜２２０を介してポリＧｅ層２３１を形成する。さらに、ｎＭＯＳＦＥＴ用のバックゲートとなる金属電極１４２上に、仕事関数制御層２１２及び層間絶縁膜２２０を介してポリＧｅ層２３２を形成する。
　ここで、ａ－Ｇｅ層２３０の下地に金属電極１４１，１４２が存在するため、ａ－Ｇｅ層２３０をアニールする際に熱が逃げ易くなる。これにより、結晶化が促進されて結晶粒の増大化をはかることができる。また、アニール後のＧｅ層２３１，２３２は多結晶であるが、素子が微細化されてチャネル長がグレインサイズに近くなると、多結晶であっても実質的に単結晶と同じにように見なすことが可能となる。
　次いで、図８（ｅ）に示すように、Ｇｅ層２３１，２３２上に、ゲート絶縁膜として２５０℃のＡＬＤ成膜によるＡｌ2Ｏ3 膜（４ｎｍ）若しくはＰＥＣＶＤによるＳｉＯ2 （５ｎｍ）を堆積し、その上にＴａＮ膜（３０ｎｍ）をスパッタ成膜によって堆積する。そして、通常リソグラフィ工程によるゲートパターニングとエッチングによって、ゲート電極を形成する。即ち、ｐＭＯＳ領域にゲート絶縁膜２４１を介してゲート電極２５１を形成し、ｎＭＯＳ領域にゲート絶縁膜２４２を介してゲート電極２５２を形成する。この際、ゲート電極２５１，２５２の両脇を酸化して側壁絶縁膜を形成しても良い。
　次いで、図８（ｆ）に示すように、ｐＭＯＳＦＥＴのソース／ドレインには、Ｎｉ堆積と低温アニール（＜３５０℃）により形成したＮｉＧｅ合金からなるメタルＳ／Ｄ２６１を形成する。ｎＭＯＳＦＥＴでも同様にＮｉＧｅ合金を形成するが、ｎＭＯＳＦＥＴではＮｉ堆積前にＳ（硫黄）不純物注入を行い、ＮｉＧｅ形成時にＮｉＧｅ／Ｇｅ界面に高濃度硫黄偏析領域を形成した構成のメタルＳ／Ｄ２６２を形成する。Ｓを偏析させることにより、メタルＳ／Ｄ層（ＮｉＧｅ）２６２とＧｅ層２３２とのショットキー障壁を制御し、寄生抵抗を下げて駆動電流を大きくすることができる。その後、未反応のＮｉ膜を希塩酸等で除去する。
　次いで、図８（ｇ）に示すように、全面に層間絶縁膜２７０を形成した後、バックゲートとなる金属電極１４１，１４２、及びソース／ドレイン領域２５１，２５２の各々に接続するためのコンタクトホールを形成する。続いて、コンタクトホール内にＣｕ等の導電材料を埋め込んだ後にＣＭＰで平坦化する。そして、Ａｌ配線層２９０を形成してＣＭＯＳ回路を形成することにより、前記図１に示す構造が完成することになる。さらに、必要に応じてパッシベーション膜を形成する。
　なお、配線層２９０に関しても、金属電極１４１，１４２や他の配線層１３１～１３４と同様に、ダマシンプロセスで形成しても良い。即ち、図８（ｇ）の工程でコンタクトホールと共に配線溝を設けておき、配線溝内に金属材料を埋め込むようにしても良い。
　このように本実施形態によれば、上層ＣＭＯＳ回路２００において、ｐＭＯＳ，ｎＭＯＳ共にａ－Ｓｉよりも移動度の高いポリＧｅ層２３０をチャネルとして用いるため、より高速なデバイスを作製することができる。しかも、ＧｅはＳｉによりも低温で形成可能であるため、上層Ｇｅ－ＣＭＯＳ回路２００を形成する際に下層Ｓｉ－ＣＭＯＳ回路１００に与える影響を少なくすることができる。
　また、配線工程とバックゲート（Grand plane）形成工程をマージできるため、コストの低減が可能となる。さらに、図７（ｃ）から図８（ｅ）に示す工程では、ａ－Ｇｅ層２３０の下地に金属電極１４１，１４２が存在するため、ａ－Ｇｅ層２３０をアニールする際に熱が逃げ易くなる。これにより、結晶化が促進されて結晶粒の増大をはかり得る利点もある。
　（変形例）
　なお、本発明は上述した各実施形態に限定されるものではない。
　第２の相補型半導体装置の形成基板は必ずしもＧｅ層に限るものではなく、Ｇｅを主成分とするものであればよい。さらに、第１の相補型半導体装置の形成基板は必ずしもＳｉ基板に限るものではなく、Ｇｅ基板を用いることもでき、更に化合物半導体を用いることも可能である。
　実施形態では、第２の相補型半導体装置のＧｅチャネルのＭＯＳＦＥＴ構造としてソース／ドレインをＮｉＧｅで形成したが、これに限らず他の金属、例えばＣｏ，Ｐｄ，ＰｔとＧｅとの合金を用いることができる。また、ソース／ドレインは必ずしも合金に限らず、不純物ドープによる拡散層としても良い。さらに、ＧｅチャネルのＭＯＳＦＥＴは、ソースドレイン（Ｓ／Ｄ）とチャネルの間にｐｎ接合のない、所謂ジャンクションレスのトランジスタ構造としても良い。
　また、ＧｅチャネルのｎＭＯＳＦＥＴでは、合金層とチャネルとの間に偏析される元素としてＳを用いたが、Ｓｅ，Ｔｅ等のカルコゲン元素を用いることも可能である。さらに、カルコゲン元素（Ｓ，Ｓｅ，Ｔｅ）の組み合わせをドープするようにしても良い。また、Ｇｅチャネルに関して、ｎ型及びｐ型に適した不純物をドープすることも可能である。
　本発明の幾つかの実施形態を説明したが、これらの実施形態は、例として提示したものであり、発明の範囲を限定することは意図していない。これら実施形態は、その他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で、種々の省略、置き換え、変更を行うことができる。これら実施形態やその変形は、発明の範囲や要旨に含まれると同様に、特許請求の範囲に記載された発明とその均等の範囲に含まれるものである。
　１００…Ｓｉ－ＣＭＯＳ回路（第１の相補型半導体装置）
　１１０…Ｓｉ支持基板
　１１１…素子分離絶縁膜
　１１２…ゲート絶縁膜
　１１３…ゲート電極
　１１４…ゲート側壁絶縁膜
　１２０～１２９…ビア
　１３１～１３４…配線層
　１４１，１４２…金属電極（バックゲート電極）
　１５０…層間絶縁膜
　２００…Ｇｅ－ＣＭＯＳ回路（第２の相補型半導体装置）
　２１１，２１２…仕事関数制御層
　２２０…層間絶縁膜
　２３０…ａ－Ｇｅ層
　２３１，２３２…ポリＧｅ層
　２４１，２４２…ゲート絶縁膜
　２５１，２５２…ゲート電極
　２６１，２６２…メタルＳ／Ｄ
　２７０…層間絶縁膜
　２８０…ビア
　２９０…配線層

Claims (16)

  1. 　半導体基板上にＣＭＯＳ回路及び配線層が形成された第１の相補型半導体装置と、
    　前記第１の相補型半導体装置上に、前記配線層と共に形成された金属電極と、
    　前記金属電極上に絶縁膜を介して形成され、且つｎＭＯＳ領域とｐＭＯＳ領域で分離して形成された、Ｇｅを主成分とする半導体層と、
    　前記ｎＭＯＳ領域の前記半導体層にｎＭＯＳＦＥＴを形成し、前記ｐＭＯＳ領域の前記半導体層にｐＭＯＳＦＥＴを形成してなる第２の相補型半導体装置と、
    　を具備したことを特徴とする積層型半導体装置。
  2. 　前記金属電極は、前記ｎＭＯＳ領域び前記ｐＭＯＳ領域で分離して形成されていることを特徴とする請求項１記載の積層型半導体装置。
  3. 　前記金属電極には、前記ｎＭＯＳＦＥＴ及び前記ｐＭＯＳＦＥＴで独立の信号線が接続されていることを特徴とする請求項２記載の積層型半導体装置。
  4. 　前記金属電極には、前記ｎＭＯＳＦＥＴ及び前記ｐＭＯＳＦＥＴで共通の信号線が接続されていることを特徴とする請求項２記載の積層型半導体装置。
  5. 　前記金属電極と前記絶縁膜との間に、前記ｐＭＯＳ領域と前記ｎＭＯＳ領域とで異なる仕事関数制御層が形成されていることを特徴とする請求項１記載の積層型半導体装置。
  6. 　前記仕事関数制御層はＴｉＮ又はＴａＮであり、前記絶縁膜は希土類酸化物を含むことを特徴とする請求項５記載の積層型半導体装置。
  7. 　前記仕事関数制御層はＴｉＮ又はＴａＮであり、前記絶縁膜はＨｆＯ2 ，Ａｌ2Ｏ3，ＨｆＡｌＯの何れかを含むことを特徴とする請求項５記載の積層型半導体装置。
  8. 　前記第２の相補型半導体装置は、前記第１の相補型半導体装置の最上層に形成された前記金属電極上に形成され、前記第１の相補型半導体装置と電気的に接続されていることを特徴とする請求項１～７の何れかに記載の積層型半導体装置。
  9. 　前記第２の相補型半導体装置は、前記第１の相補型半導体装置の複数の配線層のうちの中間層に形成された前記金属電極上に形成され、前記第１の相補型半導体装置と電気的に接続されていることを特徴とする請求項１～７の何れかに記載の積層型半導体装置。
  10. 　前記第１の相補型半導体装置はＳｉ基板上に形成されていることを特徴とする請求項１～７の何れかに記載の積層型半導体装置。
  11. 　半導体基板上に、ＣＭＯＳ回路及び配線層を有する第１の相補型半導体装置を形成すると共に、最上層に金属電極を形成する工程と、
    　前記金属電極上に絶縁膜を介してＧｅを主成分とする半導体層を形成する工程と、
    　前記半導体層をｎＭＯＳ領域とｐＭＯＳ領域で分離する工程と、
    　前記ｎＭＯＳ領域にｎＭＯＳＦＥＴを形成し、前記ｐＭＯＳ領域にｐＭＯＳＦＥＴを形成することにより、第２の相補型半導体装置を形成する工程と、
    　を含むことを特徴とする積層型半導体装置の製造方法。
  12. 　前記半導体層を形成する工程として、前記金属電極上に絶縁膜を介してアモルファスのＧｅ層を形成した後、前記Ｇｅ層をアニール処理することにより多結晶のＧｅ層を形成することを特徴とする請求項１１記載の積層型半導体装置の製造方法。
  13. 　前記金属電極をダマシンプロセスにより形成することを特徴とする請求項１１記載の積層型半導体装置の製造方法。
  14. 　半導体基板上に、ＣＭＯＳ回路及び配線層を有する第１の相補型半導体装置を形成すると共に、最上層にｎＭＯＳ領域とｐＭＯＳ領域で分離された金属電極を形成する工程と、
    　前記第１の相補型半導体装置上に絶縁膜を介してＧｅを主成分とする半導体層を形成する工程と、
    　前記半導体層を前記ｎＭＯＳ領域と前記ｐＭＯＳ領域で分離する工程と、
    　前記ｎＭＯＳ領域にｎＭＯＳＦＥＴを形成し、前記ｐＭＯＳ領域にｐＭＯＳＦＥＴを形成することにより、第２の相補型半導体装置を形成する工程と、
    　を含むことを特徴とする積層型半導体装置の製造方法。
  15. 　前記半導体層を形成する工程として、前記金属電極上に絶縁膜を介してアモルファスのＧｅ層を形成した後、前記Ｇｅ層をアニール処理することにより多結晶のＧｅ層を形成することを特徴とする請求項１４記載の積層型半導体装置の製造方法。
  16. 　前記金属電極をダマシンプロセスにより形成することを特徴とする請求項１４記載の積層型半導体装置の製造方法。
PCT/JP2013/055527 2012-06-19 2013-02-28 積層型半導体装置及びその製造方法 WO2013190863A1 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/577,209 US9721951B2 (en) 2012-06-19 2014-12-19 Semiconductor device using Ge channel and manufacturing method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2012-138103 2012-06-19
JP2012138103A JP5826716B2 (ja) 2012-06-19 2012-06-19 半導体装置及びその製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US14/577,209 Continuation US9721951B2 (en) 2012-06-19 2014-12-19 Semiconductor device using Ge channel and manufacturing method thereof

Publications (1)

Publication Number Publication Date
WO2013190863A1 true WO2013190863A1 (ja) 2013-12-27

Family

ID=49768473

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2013/055527 WO2013190863A1 (ja) 2012-06-19 2013-02-28 積層型半導体装置及びその製造方法

Country Status (4)

Country Link
US (1) US9721951B2 (ja)
JP (1) JP5826716B2 (ja)
TW (1) TWI525795B (ja)
WO (1) WO2013190863A1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150214256A1 (en) * 2014-01-30 2015-07-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, electronic device, and manufacturing method of semiconductor device

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10074576B2 (en) 2014-02-28 2018-09-11 Semiconductor Energy Laboratory Co., Ltd. Semiconductor memory device
US9330967B2 (en) 2014-05-16 2016-05-03 Taiwan Semiconductor Manufacturing Company Limited Method of fabricating a semiconductor device with reduced leak paths
US9287257B2 (en) 2014-05-30 2016-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Power gating for three dimensional integrated circuits (3DIC)
CN107924873A (zh) * 2015-09-01 2018-04-17 索尼公司 层叠体
FR3064396B1 (fr) * 2017-03-27 2019-04-19 Commissariat A L'energie Atomique Et Aux Energies Alternatives Cellule memoire sram
US11018134B2 (en) 2017-09-26 2021-05-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method for manufacturing the same
FR3073977B1 (fr) * 2017-11-22 2021-12-03 Commissariat Energie Atomique Transistors de circuit 3d a grille retournee
FR3076076B1 (fr) * 2017-12-22 2021-12-17 Commissariat Energie Atomique Assemblage ameliore pour circuit 3d a niveaux de transistors superposes
US20200058646A1 (en) * 2018-08-14 2020-02-20 Intel Corporation Structures and methods for large integrated circuit dies
WO2020055642A2 (en) * 2018-09-05 2020-03-19 Tokyo Electron Limited Power distribution network for 3d logic and memory
EP3660924A1 (en) * 2018-11-30 2020-06-03 IMEC vzw A pmos low thermal-budget gate stack

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0590517A (ja) * 1991-09-30 1993-04-09 Toshiba Corp 半導体装置及びその製造方法
JP2006210828A (ja) * 2005-01-31 2006-08-10 Fujitsu Ltd 半導体装置とその製造方法
JP2006344941A (ja) * 2005-06-10 2006-12-21 Sharp Corp Ｃｍｏｓ集積回路の製造に用いるゲルマニウム・エピタキシャル膜を絶縁体上で成長させる方法
JP2007251131A (ja) * 2006-03-15 2007-09-27 Sharp Corp シリコン−ゲルマニウム立体構造ｃｍｏｓ上の局所配線の製造方法
JP2010141230A (ja) * 2008-12-15 2010-06-24 Renesas Electronics Corp 半導体装置及び半導体装置の製造方法
JP2011142314A (ja) * 2009-12-11 2011-07-21 Semiconductor Energy Lab Co Ltd 半導体装置
JP2012028731A (ja) * 2010-06-22 2012-02-09 Renesas Electronics Corp 半導体装置、及び、半導体装置の製造方法
JP2012084851A (ja) * 2010-09-13 2012-04-26 Semiconductor Energy Lab Co Ltd 半導体装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6620665B1 (en) * 1998-09-14 2003-09-16 Matsushita Electric Industrial Co., Ltd. Method for fabricating semiconductor device
US20100190334A1 (en) * 2003-06-24 2010-07-29 Sang-Yun Lee Three-dimensional semiconductor structure and method of manufacturing the same
JP5007250B2 (ja) 2008-02-14 2012-08-22 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP2011151134A (ja) * 2010-01-20 2011-08-04 Renesas Electronics Corp 半導体装置、および、半導体装置の製造方法
FR2961016B1 (fr) * 2010-06-07 2013-06-07 Commissariat Energie Atomique Circuit integre a dispositif de type fet sans jonction et a depletion

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0590517A (ja) * 1991-09-30 1993-04-09 Toshiba Corp 半導体装置及びその製造方法
JP2006210828A (ja) * 2005-01-31 2006-08-10 Fujitsu Ltd 半導体装置とその製造方法
JP2006344941A (ja) * 2005-06-10 2006-12-21 Sharp Corp Ｃｍｏｓ集積回路の製造に用いるゲルマニウム・エピタキシャル膜を絶縁体上で成長させる方法
JP2007251131A (ja) * 2006-03-15 2007-09-27 Sharp Corp シリコン−ゲルマニウム立体構造ｃｍｏｓ上の局所配線の製造方法
JP2010141230A (ja) * 2008-12-15 2010-06-24 Renesas Electronics Corp 半導体装置及び半導体装置の製造方法
JP2011142314A (ja) * 2009-12-11 2011-07-21 Semiconductor Energy Lab Co Ltd 半導体装置
JP2012028731A (ja) * 2010-06-22 2012-02-09 Renesas Electronics Corp 半導体装置、及び、半導体装置の製造方法
JP2012084851A (ja) * 2010-09-13 2012-04-26 Semiconductor Energy Lab Co Ltd 半導体装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150214256A1 (en) * 2014-01-30 2015-07-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, electronic device, and manufacturing method of semiconductor device
TWI662653B (zh) * 2014-01-30 2019-06-11 日商半導體能源研究所股份有限公司 半導體裝置、電子裝置及半導體裝置的製造方法

Also Published As

Publication number Publication date
TW201401487A (zh) 2014-01-01
TWI525795B (zh) 2016-03-11
US20150102419A1 (en) 2015-04-16
US9721951B2 (en) 2017-08-01
JP5826716B2 (ja) 2015-12-02
JP2014003184A (ja) 2014-01-09

Similar Documents

Publication Publication Date Title
JP5826716B2 (ja) 半導体装置及びその製造方法
US10580709B2 (en) Flipped vertical field-effect-transistor
US11721701B2 (en) Semiconductor circuit with metal structure and manufacturing method
US9837534B2 (en) Semiconductor device and fabrication method therefor
US11257761B2 (en) Logic cell structure and method
JP2022529604A (ja) 積層型縦型輸送電界効果トランジスタのためのハイブリッド・ゲート・スタック集積
JP2005251873A (ja) 半導体集積回路およびその製造方法
JP2010056215A (ja) 縦型電界効果トランジスタを備える半導体装置及びその製造方法
JP6113500B2 (ja) 半導体装置及び半導体装置の製造方法
KR102344126B1 (ko) 후측면 전력 공급 회로를 포함한 반도체 디바이스
WO2013161331A1 (ja) 相補型半導体装置及びその製造方法
TW202201552A (zh) 半導體裝置結構
JP6162583B2 (ja) 半導体装置
JP6543392B2 (ja) 半導体装置
JP3176962B2 (ja) 半導体装置
JP6271982B2 (ja) 半導体装置及びその製造方法
JP6125802B2 (ja) 半導体装置
US20240332282A1 (en) Device having nanostructure electrostatic discharge structure and method
JP2010098205A (ja) Ｍｉｓ電界効果トランジスタ及び半導体基板の製造方法
JP6273406B2 (ja) 半導体装置及びその製造方法
JP2012142493A (ja) 半導体装置及びその製造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13807079

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 13807079

Country of ref document: EP

Kind code of ref document: A1