JP5826716B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP5826716B2 JP5826716B2 JP2012138103A JP2012138103A JP5826716B2 JP 5826716 B2 JP5826716 B2 JP 5826716B2 JP 2012138103 A JP2012138103 A JP 2012138103A JP 2012138103 A JP2012138103 A JP 2012138103A JP 5826716 B2 JP5826716 B2 JP 5826716B2
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Description
図1は、第1の実施形態に係わる積層型半導体装置の素子構造を示す断面図である。
次に、図1の積層型半導体装置の製造方法を、図7及び図8を参照して説明する。なお、図1と同一部分には同一符号を付して、その詳しい説明は省略する。
なお、本発明は上述した各実施形態に限定されるものではない。
110…Si支持基板
111…素子分離絶縁膜
112…ゲート絶縁膜
113…ゲート電極
114…ゲート側壁絶縁膜
120〜129…ビア
131〜134…配線層
141,142…金属電極(バックゲート電極)
150…層間絶縁膜
200…Ge−CMOS回路(第2の相補型半導体装置)
211,212…仕事関数制御層
220…層間絶縁膜
230…a−Ge層
231,232…ポリGe層
241,242…ゲート絶縁膜
251,252…ゲート電極
261,262…メタルS/D
270…層間絶縁膜
280…ビア
290…配線層
Claims (11)
- 半導体基板上に設けられ、且つCMOS回路を含む第1の相補型半導体装置と、
前記第1の相補型半導体装置上方に設けられた金属電極と、
前記金属電極上方に設けられ、互いに分離されたnMOS領域とpMOS領域とを有し、且つGeを含む半導体層と、
前記半導体層の前記nMOS領域に設けられたnMOSFETと、前記半導体層の前記pMOS領域に設けられたpMOSFETとを含む第2の相補型半導体装置と、
前記金属電極と前記pMOS領域および前記nMOS領域を含む前記半導体層との間に設けられた仕事関数制御層と、
前記半導体層と前記仕事関数制御層との間に設けられた絶縁膜と、
を具備したことを特徴とする半導体装置。 - 前記金属電極は、前記nMOS領域下方の第1部分と、前記第1部分と分離した前記pMOS領域下方の第2部分とを含むことを特徴とする請求項1記載の半導体装置。
- 前記金属電極の前記第1部分に接続された第1信号線と、
前記第1信号線とは独立して、前記金属電極の前記第2部分に接続された第2信号線と、
をさらに具備することを特徴とする請求項2記載の半導体装置。 - 前記金属電極の前記第1部分および前記金属電極の前記第2部分に接続された共通の信号線をさらに具備することを特徴とする請求項2記載の半導体装置。
- 前記仕事関数制御層はTiNを含むことを特徴とする請求項1記載の半導体装置。
- 前記金属電極は前記第1の相補型半導体装置上方の複数の配線層のうちの最上層に含まれ、前記第2の相補型半導体装置は前記第1の相補型半導体装置と電気的に接続されていることを特徴とする請求項1〜5の何れかに記載の半導体装置。
- 前記金属電極は前記第1の相補型半導体装置上方の複数の配線層のうちの中間層に含まれ、前記第2の相補型半導体装置は前記第1の相補型半導体装置と電気的に接続されていることを特徴とする請求項1〜5の何れかに記載の半導体装置。
- 前記第1の相補型半導体装置はSi基板上に設けられることを特徴とする請求項1〜5の何れかに記載の半導体装置。
- 半導体基板上に、CMOS回路及び配線層を有する第1の相補型半導体装置を形成すると共に、前記配線層の最上層に金属電極を形成する工程と、
前記金属電極上に仕事関数制御層を形成する工程と、
前記仕事関数制御層上に絶縁膜を形成する工程と、
前記絶縁膜上にGeを含む半導体層を形成する工程と、
前記半導体層をnMOS領域を含む第1部分とpMOS領域を含む第2部分に分離する工程と、
前記第1部分にnMOSFETを形成し、前記第2部分にpMOSFETを形成することにより、第2の相補型半導体装置を形成する工程と、
を含むことを特徴とする半導体装置の製造方法。 - 前記半導体層を形成する工程として、前記絶縁膜上にアモルファスのGe層を形成した後、前記Ge層をアニール処理することにより多結晶のGe層を形成することを特徴とする請求項9記載の半導体装置の製造方法。
- 半導体基板上に設けられ、且つCMOS回路を含む第1の相補型半導体装置と、
前記第1の相補型半導体装置上方に設けられた金属電極と、
前記金属電極上方に設けられ、互いに分離されたnMOS領域とpMOS領域とを有し、且つGeを含む半導体層と、
前記半導体層の前記nMOS領域に設けられたnMOSFETと、前記半導体層の前記pMOS領域に設けられたpMOSFETとを含む第2の相補型半導体装置と、
前記金属電極と前記pMOS領域および前記nMOS領域を含む前記半導体層との間に設けられ、TiNを含む第1の層と、
前記半導体層と前記第1の層との間に設けられた絶縁膜と、
を具備したことを特徴とする半導体装置。
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PCT/JP2013/055527 WO2013190863A1 (ja) | 2012-06-19 | 2013-02-28 | 積層型半導体装置及びその製造方法 |
TW102108627A TWI525795B (zh) | 2012-06-19 | 2013-03-12 | Laminated semiconductor device and manufacturing method thereof |
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