JP6113500B2 - 半導体装置及び半導体装置の製造方法 - Google Patents
半導体装置及び半導体装置の製造方法 Download PDFInfo
- Publication number
- JP6113500B2 JP6113500B2 JP2012286074A JP2012286074A JP6113500B2 JP 6113500 B2 JP6113500 B2 JP 6113500B2 JP 2012286074 A JP2012286074 A JP 2012286074A JP 2012286074 A JP2012286074 A JP 2012286074A JP 6113500 B2 JP6113500 B2 JP 6113500B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- insulating film
- semiconductor device
- layer
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 149
- 238000004519 manufacturing process Methods 0.000 title claims description 20
- 238000000034 method Methods 0.000 claims description 47
- 230000008569 process Effects 0.000 claims description 38
- 239000000758 substrate Substances 0.000 claims description 18
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 10
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 8
- 230000000295 complement effect Effects 0.000 claims description 2
- 229910044991 metal oxide Inorganic materials 0.000 claims description 2
- 150000004706 metal oxides Chemical class 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 claims 12
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims 2
- 229910052802 copper Inorganic materials 0.000 claims 2
- 239000010949 copper Substances 0.000 claims 2
- 238000000151 deposition Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 235
- 239000011229 interlayer Substances 0.000 description 33
- 239000000463 material Substances 0.000 description 30
- 238000010586 diagram Methods 0.000 description 29
- 238000009792 diffusion process Methods 0.000 description 29
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 22
- 230000004888 barrier function Effects 0.000 description 22
- 239000002184 metal Substances 0.000 description 19
- 229910052751 metal Inorganic materials 0.000 description 19
- 230000002265 prevention Effects 0.000 description 13
- 238000001312 dry etching Methods 0.000 description 7
- 102100036285 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Human genes 0.000 description 6
- 101000875403 Homo sapiens 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Proteins 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 230000006870 function Effects 0.000 description 6
- 238000000059 patterning Methods 0.000 description 6
- 238000004544 sputter deposition Methods 0.000 description 6
- 239000007769 metal material Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 230000009467 reduction Effects 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 3
- -1 SiCN Inorganic materials 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000012937 correction Methods 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 229910052731 fluorine Inorganic materials 0.000 description 3
- 239000011737 fluorine Substances 0.000 description 3
- 230000000873 masking effect Effects 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 108091006146 Channels Proteins 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 238000009832 plasma treatment Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 230000001629 suppression Effects 0.000 description 2
- 238000004347 surface barrier Methods 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 229910017090 AlO 2 Inorganic materials 0.000 description 1
- 229910016909 AlxOy Inorganic materials 0.000 description 1
- 229910021193 La 2 O 3 Inorganic materials 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- 229910006404 SnO 2 Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000002648 laminated material Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
- H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Description
図2及び図3を参照して、本発明による半導体装置10の第1の実施の形態における構成の詳細を説明する。図2は、第1の実施の形態における半導体装置の構成の一例を示す図である。図2を参照して、第1の実施の形態における半導体装置10は、基板100上に設けられた下地ロジック素子20と、複数の配線層200、300、400、500と、配線層400内に設けられたボトムゲート型トランジスタ11(配線層能動素子とも称す)を具備する。
第1の実施の形態で示されたボトムゲート型トランジスタ11は、配線層内に形成された他のボトムゲート型トランジスタとともに、論理回路を形成してもよい。例えば、図5に示すように、Pチャネル型のボトムゲート型トランジスタ11とNチャネル型のボトムゲート型トランジスタ12によってCMOS(Complementary Metal Oxide Semiconductor)回路30が形成され得る。図5を参照して、本発明による半導体装置10の第2の実施の形態における構成の詳細を説明する。図5を参照して、第2の実施の形態における半導体装置10は、基板100上に設けられた下地ロジック素子20と、複数の配線層200、300、400、500と、配線層400内に設けられたCMOS回路30(配線層能動素子とも称す)を具備する。
2、14、232、302、332、335、402、502 :配線
4、24 :ゲート絶縁膜
5、25 :半導体層
6、26 :ハードマスク絶縁膜
7、202、231、304、331、334、404 :バリアメタル
8、28、203 :コンタクトプラグ
9、29、210 :コンタクト
305、405 :ビアプラグ
310、410 :ビア
321、322、323、420、520 :層間絶縁膜
251、351 :拡散防止膜
10:半導体装置
11、12:配線層能動素子(ボトムゲート型トランジスタ)
16、230、330、333:埋込配線
20:下地ロジック素子
30:CMOS回路
41:ゲート配線
42:ソースコンタクト
43:ドレインコンタクト
44:ソース配線
45:ドレイン配線
100 :基板
200、250 :第1配線層
300、350 :第2配線層
400 :第3配線層
500 :第4配線層
600、601、602 :下地ロジック回路
700、701、702 :配線層回路
Claims (13)
- 基板上に形成された下地ロジック素子と、
アルミ配線上に形成された反射防止膜をゲート電極としたボトムゲート型トランジスタと
を具備し、
前記ボトムゲート型トランジスタは、前記下地ロジック素子の上層に形成された配線層内に形成される
半導体装置。 - 請求項1に記載の半導体装置において、
前記ボトムゲート型トランジスタは、前記反射防止膜上に形成されたゲート絶縁膜を備え、
前記ゲート絶縁膜は、Al2O3、SiO2のいずれかを含む
半導体装置。 - 請求項2に記載の半導体装置において、
前記ボトムゲート型トランジスタは、前記ゲート絶縁膜上に形成された酸化物半導体層を備え、
前記酸化物半導体層は、InGaZnO、InZnO、ZnO、ZnAlO、又はZnCuOのいずれかを含む
半導体装置。 - 請求項3に記載の半導体装置において、
前記酸化物半導体層上に形成されたハードマスク絶縁膜を更に具備する
半導体装置。 - 請求項1から4のいずれか1項に記載の半導体装置において、
他のアルミ配線上に形成された他の反射防止膜をゲート電極とした他のボトムゲート型トランジスタを更に具備し、
前記他のボトムゲート型トランジスタは、前記下地ロジック素子の上層に形成された配線層内に形成され、前記ボトムゲート型トランジスタともにCMOS(Complementary Metal Oxide Semiconductor)回路を構成する
半導体装置。 - 請求項1から5のいずれか1項に記載の半導体装置において、
前記下地ロジック素子は他の下地ロジック素子と銅配線を介して接続され、
前記アルミ配線は、前記銅配線に接続される
半導体装置。 - 請求項1から6のいずれか1項に記載の半導体装置において、
前記ボトムゲート型トランジスタは、第1電源電圧が供給される電源配線に接続され、
前記下地ロジック素子は、前記第1電源電圧よりも低い第2電源電圧が供給される電源配線に接続される
半導体装置。 - 請求項1から7のいずれか1項に記載の半導体装置において、
前記下地ロジック素子の出力電圧は前記ゲート電極に供給される
半導体装置。 - 請求項1から7のいずれか1項に記載の半導体装置において、
前記ボトムゲート型トランジスタを備えるロジック回路を具備し、
前記ロジック回路の出力電圧は前記下地ロジック素子の入力端子に供給される
半導体装置。 - 請求項1から7のいずれか1項に記載の半導体装置において、
前記ボトムゲート型トランジスタは、電源配線と前記下地ロジック素子との間に接続され、前記ゲート電極に供給される入力電圧に基づいて前記電源配線と前記下地ロジック素子との接続を制御する
半導体装置。 - 基板上に下地ロジック素子を形成するステップと、
前記下地ロジック素子上の配線層内にアルミ配線を形成するステップと、
前記アルミ配線上に反射防止膜を形成するステップと、
前記反射防止膜上にゲート絶縁膜、酸化物半導体層を下層から順に形成するステップと
前記酸化物半導体層に接続されたソースコンタクト及びドレインコンタクトを形成するステップと
を具備する
半導体装置の製造方法。 - 請求項11に記載の半導体装置の製造方法において、
前記アルミ配線を形成するステップは、同工程にて第1アルミ配線及び第2アルミ配線を形成するステップを備え、
前記反射防止膜を形成するステップは、同工程にて前記第1アルミ配線上に第1反射防止膜を形成するとともに前記第2アルミ配線上に第2反射防止膜を形成するステップを備え、
前記ゲート絶縁膜及び前記酸化物半導体層を形成するステップは、
前記第1反射防止膜上に第1ゲート絶縁膜、第1酸化物半導体層、第1ハードマスクを下層から順に成膜するステップと、
前記第1ハードマスク上及び前記第2反射防止膜上に、第2ゲート絶縁膜用の絶縁膜、第2酸化物半導体層用の酸化物半導体層、第2ハードマスクを下層から順に形成するステップと
エッチングにより、前記第2反射防止膜上に第2ゲート絶縁膜、第2酸化物半導体層を形成するステップと
を備え、
前記ソースコンタクト及び前記ドレインコンタクトを形成するステップは、同工程にて、前記第1酸化物半導体層に接続された第1ソースコンタクト及び第1ドレインコンタクトと、前記第2酸化物半導体層に接続された第2ソースコンタクト及び第2ドレインコンタクトを形成するステップを備え、
前記第1酸化物半導体層と前記第2酸化物半導体層の導電型は異なる
半導体装置の製造方法。 - 請求項12に記載の半導体装置の製造方法において、
前記第1アルミ配線と前記第2アルミ配線は接続され、
前記第1ドレインコンタクトと前記第2ドレインコンタクトは配線を介して接続される
半導体装置の製造方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012286074A JP6113500B2 (ja) | 2012-12-27 | 2012-12-27 | 半導体装置及び半導体装置の製造方法 |
US14/138,162 US9166057B2 (en) | 2012-12-27 | 2013-12-23 | Semiconductor device having the bottom gate type transistor formed in a wiring layer |
CN201310741171.5A CN103904109B (zh) | 2012-12-27 | 2013-12-27 | 半导体器件以及用于制造半导体器件的方法 |
US14/882,999 US20160043006A1 (en) | 2012-12-27 | 2015-10-14 | Method for manufacturing a semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012286074A JP6113500B2 (ja) | 2012-12-27 | 2012-12-27 | 半導体装置及び半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2014127703A JP2014127703A (ja) | 2014-07-07 |
JP6113500B2 true JP6113500B2 (ja) | 2017-04-12 |
Family
ID=50995350
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012286074A Expired - Fee Related JP6113500B2 (ja) | 2012-12-27 | 2012-12-27 | 半導体装置及び半導体装置の製造方法 |
Country Status (3)
Country | Link |
---|---|
US (2) | US9166057B2 (ja) |
JP (1) | JP6113500B2 (ja) |
CN (1) | CN103904109B (ja) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9985139B2 (en) | 2014-11-12 | 2018-05-29 | Qualcomm Incorporated | Hydrogenated p-channel metal oxide semiconductor thin film transistors |
US9685542B2 (en) * | 2014-12-30 | 2017-06-20 | Qualcomm Incorporated | Atomic layer deposition of P-type oxide semiconductor thin films |
US9647135B2 (en) | 2015-01-22 | 2017-05-09 | Snaptrack, Inc. | Tin based p-type oxide semiconductor and thin film transistor applications |
US10659046B2 (en) | 2015-09-25 | 2020-05-19 | Intel Corporation | Local cell-level power gating switch |
JP2017069513A (ja) * | 2015-10-02 | 2017-04-06 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
WO2018111247A1 (en) * | 2016-12-13 | 2018-06-21 | Intel Corporation | Passivation dielectrics for oxide semiconductor thin film transistors |
JP6997990B2 (ja) * | 2018-04-27 | 2022-01-18 | 株式会社タムラ製作所 | pチャンネル電界効果トランジスタ及び増幅回路用半導体素子 |
CN112956024A (zh) * | 2018-10-29 | 2021-06-11 | 东京毅力科创株式会社 | 用于半导体器件的单片3d集成的架构 |
US11616057B2 (en) | 2019-03-27 | 2023-03-28 | Intel Corporation | IC including back-end-of-line (BEOL) transistors with crystalline channel material |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3803631B2 (ja) * | 2002-11-07 | 2006-08-02 | 株式会社東芝 | 半導体装置及びその製造方法 |
JP2005038884A (ja) * | 2003-07-15 | 2005-02-10 | Toshiba Corp | 不揮発性半導体記憶装置及びその製造方法 |
CN100380629C (zh) * | 2006-02-24 | 2008-04-09 | 友达光电股份有限公司 | 像素结构的制作方法 |
JP2008140684A (ja) * | 2006-12-04 | 2008-06-19 | Toppan Printing Co Ltd | カラーelディスプレイおよびその製造方法 |
JP2009076879A (ja) * | 2007-08-24 | 2009-04-09 | Semiconductor Energy Lab Co Ltd | 半導体装置 |
JP5781720B2 (ja) * | 2008-12-15 | 2015-09-24 | ルネサスエレクトロニクス株式会社 | 半導体装置及び半導体装置の製造方法 |
KR101627728B1 (ko) * | 2008-12-30 | 2016-06-08 | 삼성디스플레이 주식회사 | 박막 트랜지스터 기판 및 그 제조 방법 |
EP2494597A4 (en) * | 2009-10-30 | 2015-03-18 | Semiconductor Energy Lab | SEMICONDUCTOR COMPONENT |
KR101752518B1 (ko) * | 2009-10-30 | 2017-06-29 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치 |
KR101436120B1 (ko) * | 2009-12-28 | 2014-09-01 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치의 제작 방법 |
JP2011238652A (ja) * | 2010-05-06 | 2011-11-24 | Renesas Electronics Corp | 半導体装置およびその製造方法 |
US8664658B2 (en) * | 2010-05-14 | 2014-03-04 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
FR2961016B1 (fr) * | 2010-06-07 | 2013-06-07 | Commissariat Energie Atomique | Circuit integre a dispositif de type fet sans jonction et a depletion |
JP5705559B2 (ja) * | 2010-06-22 | 2015-04-22 | ルネサスエレクトロニクス株式会社 | 半導体装置、及び、半導体装置の製造方法 |
WO2012020525A1 (ja) * | 2010-08-07 | 2012-02-16 | シャープ株式会社 | 薄膜トランジスタ基板及びそれを備えた液晶表示装置 |
TWI548057B (zh) * | 2011-04-22 | 2016-09-01 | 半導體能源研究所股份有限公司 | 半導體裝置 |
-
2012
- 2012-12-27 JP JP2012286074A patent/JP6113500B2/ja not_active Expired - Fee Related
-
2013
- 2013-12-23 US US14/138,162 patent/US9166057B2/en not_active Expired - Fee Related
- 2013-12-27 CN CN201310741171.5A patent/CN103904109B/zh not_active Expired - Fee Related
-
2015
- 2015-10-14 US US14/882,999 patent/US20160043006A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
US20140183525A1 (en) | 2014-07-03 |
CN103904109A (zh) | 2014-07-02 |
US20160043006A1 (en) | 2016-02-11 |
CN103904109B (zh) | 2018-11-09 |
JP2014127703A (ja) | 2014-07-07 |
US9166057B2 (en) | 2015-10-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6113500B2 (ja) | 半導体装置及び半導体装置の製造方法 | |
JP5981711B2 (ja) | 半導体装置および半導体装置の製造方法 | |
TWI540725B (zh) | 半導體裝置及半導體裝置之製造方法 | |
CN107256846B (zh) | 半导体装置及其制造方法 | |
JP5086797B2 (ja) | 半導体装置 | |
TWI503979B (zh) | 包含一場效電晶體於一覆矽的絕緣層構造的半導體裝置 | |
TWI566362B (zh) | 半導體裝置及半導體裝置之製造方法 | |
CN103632921B (zh) | 半导体器件及其制造方法 | |
JP5731904B2 (ja) | 半導体装置及び半導体装置の製造方法 | |
US9484271B2 (en) | Semiconductor device and method of manufacturing the same | |
JP2005197462A (ja) | 半導体装置及びその製造方法 | |
TWI738522B (zh) | 包含背面供電電路的半導體元件 | |
JP2008066715A (ja) | 半導体装置及びその製造方法 | |
JP6282505B2 (ja) | 半導体装置 | |
CN109755132A (zh) | 半导体装置以及其制作方法 | |
JP2020126915A (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20150821 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20160809 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20160818 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20161012 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20170215 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20170315 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6113500 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
LAPS | Cancellation because of no payment of annual fees |