WO2011013298A1 - Sramセル - Google Patents
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- WO2011013298A1 WO2011013298A1 PCT/JP2010/004354 JP2010004354W WO2011013298A1 WO 2011013298 A1 WO2011013298 A1 WO 2011013298A1 JP 2010004354 W JP2010004354 W JP 2010004354W WO 2011013298 A1 WO2011013298 A1 WO 2011013298A1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
- G11C11/4125—Cells incorporating circuit means for protecting against loss of information
Definitions
- the present invention relates to an SRAM (Static Random Access Memory) cell that performs a read operation and a write operation with one bit line.
- SRAM Static Random Access Memory
- a node of a circuit in an electric network is referred to as a node.
- a node can play two roles. That is, if a partial circuit network having a certain function in a certain circuit network is called a partial circuit, when an electric signal of a partial circuit at one node is output (output signal node), When viewed from other partial circuits connected to the node, the node may be a node to which an electric signal is input (input signal node).
- a wiring that supplies current to the circuit is referred to as a power supply line, and a wiring that feeds back a current passing through the circuit from the power supply line is referred to as a power supply feedback line.
- a terminal refers to an electrode provided for electrical connection of circuit elements such as transistors, resistors, and capacitors used in the circuit to the outside. Electrically, a terminal can also serve as a node.
- An electric circuit network that electrically performs a logical operation by associating a logical value with two representative values of different electric signals, for example, a high level and a low level of a signal amplitude is called a logic device.
- the electric signal in this case is referred to as a logic signal, and the logic value is 1 or 0, which corresponds to high level, H or low level, and L, respectively.
- the logic signal may be abbreviated as data.
- An electric signal for controlling the electric operation of the electric circuit and the active element used therein is referred to as a control signal.
- a logic signal may also serve as a control signal.
- the wiring related to the control signal is called a control signal line, and the wiring related to the logic signal is called a data line.
- a transistor is one embodiment of an electrical switch that has at least one control signal input terminal and at least two signal output terminals, and controls conduction and non-conduction between the two output terminals according to the control signal.
- the transistor is generally an insulated gate field effect transistor (MOST), a bipolar transistor (BPT) or the like.
- MOST insulated gate field effect transistor
- BPT bipolar transistor
- MOST its gate is used as a control signal input terminal
- BPT bipolar transistor
- the base is used as a control signal input terminal
- the collector and emitter are used as two signal output terminals.
- an inverter is an electrical circuit having a signal input terminal and a signal output terminal, and is a logic device capable of electrical logic operation, and a logic signal applied to the signal input terminal to the signal output terminal The inverted logic signal is output. Of course, it is connected to the power supply line and the power supply feedback line.
- the SRAM cell using the MOST is, for example, the dual bit line SRAM cell 10 of FIG.
- the “bit line” is a data line, and is a wiring through which a logic signal (data) related to stored contents is input / output (written or read) to / from the SRAM cell.
- “Dual” means that there are two of them and the logic signals passing through them simultaneously are inverted.
- bit lines for both write-only bit lines and read-only bit lines.
- the drains of the P-type MOST (PMOST) 20 and the N-type MOST (NMOST) 22 are connected to the output signal node Q1, and the gate electrodes are connected to the input signal node I1.
- the source of the PMOST20 is connected to the power supply line VDDL at the node VD1
- the source of the NMOST22 is connected to the power supply feedback line VSSL at the node VS1 to constitute the inverter 12, and the drains of the PMOST24 and NMOST26 are connected to the output signal.
- each gate is connected to input signal node I2
- the source of PMOS T24 is connected to power supply line VDDL at node VD2
- the source of NMOS T26 is connected to power supply feedback line VSSL at node VS2 to inverter 14 Is configured .
- An inverter composed of PMOST and NMOST as described above is called a CMOS inverter.
- the output signal node Q1 of the inverter 12 is connected to the input signal node I2 of the inverter 14, and the output signal node Q2 of the inverter 14 is connected to the input signal node I1 of the inverter 12 to be a positive feedback circuit (also called a latch circuit).
- a positive feedback circuit also called a latch circuit
- the output signal node Q2 of the inverter 14 is connected to the source (or drain) of the NMOS T16, which is an access transistor (a control transistor used for both reading and writing operations), and the drain (or The source) is connected to the bit line BL at the node D1, the output signal node Q1 of the inverter 12 is connected to the source (or drain) of the NMOST18 which is another access transistor, and the drain (or source) of the NMOST18 is connected to the bit at the node D2. It is connected to the bets line BLB, and is connected to the word line WL is one of the SRAM cells in NMOST16 and 18 respectively gates nodes P1 and P2 are configured.
- the bit lines BL and BLB are opposite to each other when the potentials are viewed as logic signals, that is, they are complementary.
- the logic signal levels of the output signal nodes Q1 and Q2 are also complementary in the steady state (if one is at the high level H, the other is at the low level L). For example, when the output signal node Q1 of the inverter 12 is at a low level and the output signal node Q2 of the inverter 14 is at a high level, the logic 1 is stored, and vice versa. The contents are decided.
- the NMOSTs 16 and 18 are used as read control transistors when reading the stored contents of the SRAM cells to the bit lines BL and BLB, or as write control transistors when writing the logic signals of the bit lines BL and BLB to the SRAM cells. Further, the logic signal level in the SRAM cell may be different from the logic signal level of the logic circuit outside the memory device using the SRAM cell.
- an SRAM device configured by arranging SRAM cells in an array is required to be capable of high-speed operation and to have a large storage capacity. For this reason, it is desirable to reduce the area of the SRAM cell, that is, to set the size of each transistor to the smallest possible size. However, when reading the stored contents of the SRAM cell, it is not possible to set all the transistors to the minimum size in order to prevent malfunctions that cause the stored contents to be reversed and to ensure that the stored contents are correctly written. .
- the channel length of the NMOSTs 22 and 26 of the inverter is the minimum dimension (the channel width is often larger than the minimum dimension in consideration of the area and operation speed), and the access transistors 16 and 18 are larger than these.
- the current driving capability is weakened (for example, the channel width is reduced, the channel length is increased, or both), and the current driving capability is stronger than the PMOST20 of the inverter 12 and the PMOST24 of the inverter 14 (for example, PMOST20 and 24).
- the channel length is set to be longer than that of the access transistors 16 and 18, and the channel width is set to be smaller or both.
- the channel width of each transistor must be set to be equal to or larger than the minimum dimension in consideration of this. Accordingly, the area of the SRAM cell is increased correspondingly, and the stray capacitance is increased, resulting in a decrease in the operation speed.
- FIG. 2 A circuit shown in FIG. 2 is disclosed in Patent Document 1 below as a conventional SRAM cell in which the dimensional constraint imposed on each transistor constituting the SRAM cell is removed.
- each drain of a P-type MOST (PMOST) 40 and an N-type MOST (NMOST) 42 is connected to an output signal node Q42, each gate electrode is connected to an input signal node I42, and the source of the PMOST40 is
- the node VD42 is connected to the power supply line VDDL, and the source of the NMOST42 is connected to the power supply feedback line VSSL at the node VS42 to form the first inverter 32.
- the drains of the PMOST44 and NMOST46 are connected to the output signal node Q44.
- Each gate electrode is connected to the input signal node I44, the source of the PMOST44 is connected to the power supply line VDDL at the node VD44, and the source of the NMOST46 is connected to the power supply feedback line VSSL at the node VS44.
- Inverter 34 It is configured. Further, the output signal node Q42 of the first inverter 32 is connected to the input signal node I44 of the second inverter 34, and the output signal node Q44 of the second inverter 34 is the drain (or source) of the PMOST50 which is a feedback control transistor.
- the source (or drain) of the PMOS T50 is connected to the input signal node I42 of the first inverter 32 so that a positive feedback circuit (or latch circuit) is configured when the PMOS T50 is in a conductive state.
- the gate of the PMOST 50 is connected to the word line CWL that supplies the feedback circuit control signal at the node P10
- the input signal node I42 of the first inverter 32 is connected to the source (or drain) of the NMOS T52 that is the write control transistor
- the drain (or source) of the NMOS T52 is connected to one bit line BL at a node D8, and the gate electrode is connected to a write control signal line WWL that supplies a write control signal at a node P8.
- the output signal node Q44 of the second inverter 34 is connected to the source (or drain) of the NMOS T54 which is a read control transistor, the drain (or source) of the NMOS T54 is connected to the bit line BL at the node D9, and the gate of the NMOS T54.
- the electrode is connected to a read control signal line RWL that supplies a read control signal at the node P9.
- the control circuit 60 appropriately controls the potentials of the decoding circuit for selecting this cell, the WWL line, the CWL line, and the RWL line, and generates respective control signals.
- the high level of the logic signal in the SRAM cell is set to the potential VDD of the power supply line VDDL, and the low level is set to the potential of the power supply feedback line VSSL (ground, GND, 0V).
- FIG. 3 is a configuration diagram of a conventional SRAM cell and shows a circuit used for the simulation, but the sense circuit is omitted for convenience of explanation.
- the value of VDD was 0.7V.
- a memory device using an SRAM cell that performs a write operation and a read operation with one bit line as shown in FIG. 2 needs countermeasures against a malfunction caused by a noise voltage induced in the bit line (especially a malfunction in a read operation).
- a so-called open bit line system can be adopted as a countermeasure.
- an inverter 86 (partial circuit surrounded by a dotted line) is composed of a PMOST 70 and an NMOST72
- an inverter 88 (partial circuit surrounded by a dotted line) is composed of a PMOST74 and an NMOST76, and an output signal node of the inverter 86.
- the input signal node of the inverter 88 is connected. This node is called Vcellhold.
- the input signal node of the inverter 86 is called Vcellwrite, and the output signal node of the inverter 88 is called Vcellread.
- the conduction / non-conduction state of the NMOS T84 is determined by the control signal Vfbcont applied to its gate.
- the nodes Vcellread and Vcellwrite are connected to one bit line BL by an NMOST80 which is a read control transistor and an NMOST82 which is a write control transistor, respectively.
- the conduction and non-conduction states of the NMOSTs 80 and 82 are determined by control signals Vwrl and Vwwl applied to the respective gate electrode terminals.
- a load capacitor Cbit was connected to the bit line BL on the assumption that many cells in other rows of the storage device array were connected.
- the potential is controlled by the NMOS T90 to the bit line potential control signal source Vbitsource.
- a control signal Vbitscont is applied to the gate electrode terminal of the NMOS T90, and the bit line BL can be brought into a high impedance state (a state in which charge discharge or charging is extremely restricted) by making the NMOS T90 non-conductive. Note that the symbol of the signal waveform of the node is also represented by the symbol of the node.
- a conventional double insulated gate field effect transistor shown in the schematic diagram of FIG. 4 was used in which two gate electrodes were connected in common and operated in three terminals.
- 91 is a substrate
- 92 is an insulating film
- 93 is a source region
- 94 is a drain region
- 95 is a channel region
- 96-1 is a first gate oxide film
- 96-2 is a second gate oxide film
- Reference numeral 97 denotes a first gate
- 98 denotes a second gate
- 99 denotes an insulating film.
- FIG. 5 shows a control signal waveform of the write operation
- FIG. 6 shows a signal waveform of each node of the SRAM cell at that time.
- Table 1 shows sampling values of control signal waveforms in the write operation of FIG.
- the horizontal axis of FIG. 5 represents Time (time) (s: second), and the vertical axis represents Signal Swing (signal amplitude) (V).
- ⁇ is the Vfbcont (feedback control signal line CWL signal, that is, feedback control signal) characteristic
- ⁇ indicates the characteristics of Vwwl (the signal of the write control signal line WWL, that is, the write control signal). From the characteristics of FIG. 5, Vfbcont and Vwwl take a constant value alternately in time.
- Table 2 shows sampling values of signal waveforms at the respective nodes of the SRAM cell during the write operation of FIG.
- the horizontal axis of FIG. 6 represents Time (time) (s: second), and the vertical axis represents Signal Swing (signal amplitude) (V).
- V Signal Swing (signal amplitude)
- the solid line shows the Vcellread (cell read voltage, ie, output node voltage of the second inverter) characteristic, * Indicates Vbitline (bit line voltage) characteristics.
- the amplitude of the control signal is larger than VDD, and is set to 1.4 V as an example. This is to avoid a threshold voltage drop of the signal level at the time of signal transfer of each control NMOST 80, 82 and NMOST84.
- the NMOS T90 that controls the potential of the bit line BL is in a conductive state. That is, the control signal Vbitscont is maintained at 1.4 V, the potential Vbitline of the bit line BL follows the potential of the control power supply Vbitsource, and the bit line BL is in a low impedance state (a state in which charge charge and discharge is extremely easy). ing.
- Vbitline is charged to a high level (0.7 V)
- the feedback control signal Vfbcont is changed from 1.4 V to 0.0 V to make the NMOS T84 nonconductive, and the nodes Vcellwrite and Vcellread Disconnect between.
- the write control signal Vwwl is changed from 0.0 V to 1.4 V to make the NMOS T82 conductive, and the potential of Vbitline is transferred to the node Vcellwrite. Then, as shown in FIG.
- Vcellwrite changes from the low level to the high level, so that the potential of Vcellhold changes to the low level and the potential of Vcellread changes sequentially to the high level.
- Vwwl is returned to 0.0 V
- NMOST 82 is returned to a non-conductive state
- Vfbcont is returned to 1.4 V
- NMOST 84 is returned to a conductive state
- a latch circuit is configured by inverters 86 and 88.
- the stored content is held.
- the period during which Vfbcont is maintained at 1.4 V is the holding state. In this way, the state when the nodes Vcellwrite and Vcellread are at the high level (0.7 V), and therefore Vcellhold is at the low level (0.0 V), the stored content is referred to as the high level.
- the high-level memory content is rewritten to the low-level memory content.
- the potential of Vbitline is changed from a high level to a low level.
- the feedback control signal Vfbcont is changed from 1.4 V to 0.0 V in the same manner as the write procedure described above to make the NMOS T84 non-conductive, and the node Vcellwrite and Vcellread are disconnected.
- the write control signal Vwwl is changed from 0.0 V to 1.4 V to make the NMOS T82 conductive, and the potential of Vbitline is transferred to the node Vcellwrite.
- the potential of each node of Vcellwrite, Vcellhold, and Vcellread is inverted and written to the low-level storage contents.
- FIG. 7 shows signal waveforms at each node when the contents of the conventional SRAM cell of FIG. 2 are read from the SRAM cell in which the stored contents are held at a low level.
- the horizontal axis of FIG. 7 represents Time (time) (s: second), and the vertical axis represents Signal Swing (signal amplitude) (V).
- ⁇ indicates Vcellhold (cell hold voltage) characteristics
- ⁇ is Vcellwrite (cell write voltage) characteristics
- ⁇ is the Vcellread (cell read voltage) characteristic
- X indicates Vfbcont (feedback control signal line CWL signal, that is, feedback control signal) characteristic
- -Solid line with Vbitsource voltage of pulse power supply to give bit line potential
- a chain line with ⁇ indicates Vbitscont (a pulse voltage for applying a potential of the bit line and a gate voltage applied to NMOST for controlling a connection state of the bit line).
- Table 3 shows sample values of signal waveforms at each node in FIG.
- the bit line BL is charged to VDD / 2.
- the control signal Vbitscont that controls the potential of the bit line BL is changed from 1.4 V to 0.0 V, so that the NMOS T90 is turned off and the bit line BL is put into a high impedance state.
- the feedback control signal Vfbcont is changed from 1.4V to 0.0V to make the NMOS T84 non-conductive, and the node Vcellwrite and Vcellread are disconnected.
- the read control signal Vwr1 is changed from 0.0 V to 1.4 V to make the NMOS T80 conductive, and the bit line BL and the node Vcellread are connected.
- the node Vcellread is in a low impedance state because the NMOS T76 of the inverter 88 is in a conductive state.
- the electric charge charged in the bit line BL is discharged through the NMOSTs 80 and 76, and the potential Vbitline decreases from VDD / 2. With this lowered potential, the sense amplifier can detect that the stored content is at a low level. Note that the potential of the node Vcellread was initially 0.0 V, but increases immediately after the read operation starts.
- the degree is determined by the ratio of the impedances of the NMOSTs 80 and 76, but is clearly lower than the potential VDD / 2 set at the beginning of the read operation of the bit line BL. However, even if the potential of the bit line BL further rises due to noise or the like not considered in the simulation, even if the potential of the node Vcellread exceeds the logic threshold value (about VDD / 2) of the inverter 86, Since the nodes Vcellwrite and Vcellread are disconnected, the stored contents are not reversed.
- the control signal is returned to 0.0 V, and the NMOS T80 is again turned off. Further, the feedback control signal Vfbcont is returned to 1.4 V, the NMOS T84 is again turned on, the SRAM cell is returned to the low level memory holding state, and the inversion of the memory content does not occur.
- FIG. 8 shows signal waveforms at each node when the contents of the conventional SRAM cell of FIG. 2 are read from the SRAM cell in which the stored contents are held at a high level.
- the horizontal axis of FIG. 8 represents Time (time) (s: second), and the vertical axis represents Signal Swing (signal amplitude) (V).
- ⁇ indicates Vcellhold (cell hold voltage) characteristics
- Front ⁇ is Vcellwrite (cell write voltage) characteristics
- ⁇ is the Vcellread (cell read voltage) characteristic
- the chain line with x is the Vfbcont (feedback control signal line CWL signal, that is, feedback control signal) characteristic
- the chain line with + is the Vwrl (read control signal line WRL signal, that is, read control signal) characteristic
- the rear ⁇ is the Vbitsource (pulse power supply voltage for applying bit line potential) characteristics
- a chain line with ⁇ indicates Vbitscont (a pulse voltage for applying a potential of the bit line and a gate voltage applied to NMOST for controlling a connection state of the bit line).
- Table 4 shows sample values of signal waveforms at each node in FIG.
- the control signal Vbitscont that controls the potential of the bit line BL is changed from 1.4V to 0.0V, the NMOS T90 is turned off, and the bit line BL is set to high impedance. Put it in a state.
- the feedback control signal Vfbcont is changed from 1.4V to 0.0V to make the NMOS T84 non-conductive, and the node Vcellwrite and Vcellread are disconnected.
- the read control signal Vwr1 is changed from 0.0 V to 1.4 V to make the NMOS T80 conductive, and the bit line BL and the node Vcellread are connected.
- the bit line BL is further charged through the NMOST80 and the PMOST74 as shown in FIG. 8, and the potential Vbitline rises from VDD / 2. .
- This increased potential allows the sense amplifier to detect that the stored content is at a high level.
- the potential of the node Vcellread was initially 0.7 V, but the potential decreases immediately after the read operation starts. The degree is determined by the ratio of the impedances of the NMOS T80 and the PMOS T74. Since the node Vcellwrite and the Vcellread are disconnected, this potential is not taken into consideration in the simulation. Even if the value falls below the value, the stored contents are not reversed.
- control signal is returned to 0.0 V, and the NMOS T80 is again turned off. Further, the feedback control signal Vfbcont is returned to 1.4 V, the NMOS T84 is again turned on, and the SRAM cell returns to the high level memory holding state. In this case as well, it can be seen that the stored contents are not inverted.
- the potential of the node Vcellwrite in FIGS. 7 and 8 decreases when the feedback control signal Vfbcont changes from 1.4V to 0.0V. In the case of FIG. 7, it temporarily changes to a negative potential, and in the case of FIG. 8, it is lower than the high level potential VDD.
- the cause is that the node Vcellwrite is in a high impedance state due to the non-conduction of the NMOST84, that is, a state where there is no passage through which the electric charge is discharged or charged by a sufficient amount to maintain the potential, and therefore the node Vcellwrite is loaded.
- the SRAM cell of FIG. 2 has three control signal lines for one set of read and write ports, and it is desirable that the number is small.
- feedback in the row direction independent of the read control signal line RWL and the write control signal line WWL in the row direction of the SRAM memory device is performed in order to control the feedback control transistor to be non-conductive during the write operation and the read operation.
- the control signal line CWL was required.
- the control signal line can be reduced by one by connecting the gate electrode terminal to the write control signal line WWL with the feedback control transistor as the PMOST. That is, when the write control NMOST is non-conductive or conductive, the feedback control transistor may be conductive or non-conductive. However, since the feedback control PMOST becomes conductive during the read operation, the noise margin during the read operation is reduced.
- Patent Document 2 discloses an SRAM cell 100 shown in FIG. 9 in which a read buffer including a read control transistor and a buffer transistor and a read-only bit line are separately added.
- the drains of the PMOST110 and NMOST112 are connected to form an output signal node Q102, and their gates are connected to form an input signal node I102.
- the source of the PMOST110 is connected to the power supply line VDDL.
- the source of the NMOST 112 is connected to the power supply feedback line VSSL to constitute the inverter 102.
- the drains of the PMOST 114 and the NMOS T116 are connected to form an output signal node Q104, the gates are connected to the input signal node I104, the source of the PMOST114 is connected to the power supply line VDDL, and the source of the NMOST116 is connected to the power supply feedback line VSSL.
- Inverter 104 is configured in connection with.
- the output signal node Q102 of the inverter 102 is connected to the input signal node I104 of the inverter 104, and the output signal node Q104 is connected to the drain (or source) of the PMOST120 which is a feedback control transistor, and the source (or drain) of the PMOST120. Is connected to the input signal node I102 of the inverter 102 so that a positive feedback circuit (or latch circuit) is formed when the PMOST 120 is in a conductive state.
- the gate of the PMOST 120 is connected to the write control signal line WWL
- the input signal node I102 of the inverter 102 is connected to the source (or drain) of the NMOS T122 which is a write control transistor
- the drain (or source) of the NMOS T122 is a write-only bit.
- the output signal node Q102 of the inverter 102 is connected to the gate of the NMOS T124 that is a buffer transistor
- the source of the NMOS T124 is connected to the power supply feedback line VSSL
- the drain of the NMOS T124 is connected to the source (or drain) of the NMOS T126 that is a read control transistor.
- the drain (or source) of the NMOS T126 is connected to the read-only bit line R-BL, and the gate of the NMOS T126 is connected to the read control signal line RWL.
- the control circuit 130 gives an appropriate control signal to the decoding circuit for selecting this cell, WWL, and RWL.
- the SRAM cell 100 in FIG. 9 has a pair of bit lines R-BL and W-BL (referred to as one write port and one read port), and there are 2 control signal lines for the read operation and write operation.
- the feature is that there are few books and the noise margin in each operation can be increased simultaneously.
- reading is performed.
- a plurality of pairs of write and read-only bit lines W-BL and R-BL are required. Therefore, there is a concern that the number of wirings may increase extremely.
- the write operation can only be performed in one word unit. However, if the write operation can be performed in units of a plurality of words at the same time, the operation speed and the diversity of functions as a storage device can be realized.
- the object of the present invention is to eliminate the above-mentioned drawbacks and to have no restrictions on transistor dimensions due to ensuring the writing operation and the reading operation.
- the SRAM cell can be easily multi-ported, and the write operation and the read operation can be performed by one bit line. In other words, an SRAM cell in which one bit line can be used for both the write operation and the read operation is provided. There is.
- the present invention employs the following solutions in order to achieve the above object.
- the SRAM cell of the present invention includes a feedback control transistor that controls connection or disconnection of a positive feedback circuit between two inverters, particularly a memory cell, and has a write control transistor and a read control transistor connected to one bit line. And a read buffer transistor connected to the read control transistor.
- the SRAM cell includes a plurality of bit lines that can be shared for writing and reading operations of memory contents, and one read control line and one write control line corresponding to each bit line.
- a plurality of transistor groups each including a transistor are included.
- the SRAM cell has a plurality of bit lines that can be shared for writing and reading operations of memory contents, a single feedback control line, and a single read control line and a single write control corresponding to each bit line.
- bit lines that can be shared for writing and reading operations of memory contents
- a single feedback control line and a single read control line and a single write control corresponding to each bit line.
- control signal line pairs of the same number as the bit lines, each bit line, the feedback control line, and each component of each control signal line pair.
- it has a plurality of transistor pairs of the same number as the bit line, each having a write control transistor and a read control transistor as components, and further includes one buffer transistor and one feedback control transistor.
- the SRAM memory device configured by arranging the SRAM cells in an array, various combinations of the read operation and the write operation are simultaneously performed on the SRAM cells in different row directions according to the number of bit lines.
- a possible SRAM cell for a multiported SRAM device is constructed.
- Configuration 1 an SRAM cell, One bit line (BL), A control signal line pair consisting of one write control signal line (WWL) and one read control signal line (RWL) corresponding to the bit line (BL); A feedback control transistor (220); A write control transistor (222), a read control transistor (224), a buffer transistor (226), opposite in polarity to the feedback control transistor (220), A first inverter (202) having an output signal node (Q202) and an input signal node (I202); A second inverter (204) having an output signal node (Q204) and an input signal node (I204); The first and second inverters (202, 204) operate by being connected to a power supply line (VDDL) and a power supply feedback line (VSSL), respectively.
- VDDL power supply line
- VSSL power supply feedback line
- the output signal node (Q202) of the first inverter (202) is connected to the input signal node (I204) of the second inverter (204), and the output signal node (Q204) of the second inverter (204).
- the input signal node (I202) of the first inverter (202) are connected by the feedback control transistor (220), and the input signal node (I202) of the first inverter (202) and the bit line (BL ) Are connected by the write control transistor (222),
- the gates of the feedback control transistor (220) and the write control transistor (222) are connected to the write control signal line (WWL),
- the gate of the buffer transistor (226) is connected to the output signal node (Q204) of the second inverter (204), the source of the buffer transistor (226) is connected to the power supply feedback line (VSSL), and the buffer The drain of the transistor (226) and the bit line (BL) are connected by the read control transistor (224),
- the gate of the read control transistor (224) is connected to the read control signal
- Configuration 2 SRAM cell, A plurality of bit lines (BL1, BL2); The bit lines (BL1, BL2) corresponding to the bit lines (BL1, BL2) and comprising one write control signal line (WWL1, WWL2) and one read control signal line (RWL1, RWL2) The same number of control signal line pairs; Read control transistors (320, 322) corresponding to the respective bit lines (BL1, BL2), write control transistors (330, 332) having opposite polarities to the feedback control transistors (320, 322), and reading A plurality of transistor groups having the same number as the bit lines (BL1, BL2), each including a control transistor (334, 336) and a buffer transistor (324, 326); A first inverter (302) having an output signal node (Q302) and an input signal node (I302); A second inverter (304) having an output signal node (Q304) and an input signal node (I304); The first and second inverters (302, 304) operate by being connected to a power supply line (VDDL) and
- the output signal node (Q302) of the first inverter (302) is connected to the input signal node (I304) of the second inverter (304), and the output signal node (Q304) of the second inverter (304).
- the feedback control transistors (320, 322) are all connected in series between the input signal node (I302) of the first inverter (302) and the input signal node (I302) of the first inverter (302).
- the bit lines (BL1, BL2) are connected by the corresponding write control transistors (330, 332), Gates of the feedback control transistors (320, 322) and the write control transistors (330, 332) are connected to the corresponding write control signal lines (WWL1, WWL2),
- the gate of each buffer transistor (324, 326) is connected to the output signal node (Q304) of the second inverter (304), and the source of each buffer transistor (324, 326) is the power supply feedback line (VSSL).
- the corresponding read control transistors (334, 336) between the drains of the buffer transistors (324, 326) and the corresponding bit lines (BL1, BL2),
- the gates of the read control transistors (334, 336) are connected to the read control signal lines (RWL1, RWL2).
- Configuration 3 SRAM cell, A plurality of bit lines (BL1, BL2, BL3); The bit consisting of one write control signal line (WWL1, WWL2, WWL3) and one read control signal line (RWL1, RWL2, RWL3) corresponding to each bit line (BL1, BL2, BL3) A plurality of control signal line pairs equal in number to the lines (BL1, BL2, BL3); One feedback control line (CWL); A feedback control transistor (420); A buffer transistor (422); Write control transistors (430, 432, 434) and read control transistors (424, 426, 428) corresponding to the respective bit lines (BL1, BL2, BL3) and having opposite polarities to the feedback control transistors (420), respectively.
- WWL1, WWL2, WWL3 write control signal line
- RWL1, RWL2, RWL3 read control signal line
- a plurality of transistor groups having the same number as the bit lines (BL1, BL2, BL3), A first inverter (402) having an output signal node (Q402) and an input signal node (I402); A second inverter (404) having an output signal node (Q404) and an input signal node (I404);
- the first and second inverters (402, 404) operate by being connected to a power supply line (VDDL) and a power supply feedback line (VSSL),
- the output signal node (Q402) of the first inverter (402) is connected to the input signal node (I404) of the second inverter (404), and the output signal node (Q404) of the second inverter (404)
- the input signal node (I402) of the first inverter (402) is connected by the feedback control transistor (420),
- the gate of the feedback control transistor (420) is connected to the feedback control line (CWL),
- Configuration 4 SRAM cell, A plurality of bit lines (BL1, BL2, BL3); It consists of one write control signal line (WWL1) and one read control signal line (RWL1) corresponding to at least one bit line (BL1) of the bit lines (BL1, BL2, BL3).
- a control signal line pair A write control signal line (WWL2) or a read control signal line (RWL2) corresponding to the other bit lines (BL2, BL3); One feedback control line (CWL); A feedback control transistor (520); The write control transistors (530, 532) corresponding to the write control signal lines (WWL1, WWL2); Read control transistors (524, 526) corresponding to the read control lines (RWL1, RWL2), A buffer transistor (522); A first inverter (502) having an output signal node (Q502) and an input signal node (I502); A second inverter (504) having an output signal node (Q504) and an input signal node (I504); The first and second inverters (502, 504) operate by being connected to a power supply line (VDDL) and a power supply feedback line (VSSL), The output signal node (Q502) of the first inverter (502) is connected to the input signal node (I504) of the second inverter (504), and the output signal node (Q50
- the input signal node (I502) of the first inverter (502) are connected by the feedback control transistor (520),
- the gate of the feedback control transistor (520) is connected to the feedback control line (CWL)
- the input signal node (I502) of the first inverter (502) is connected to the corresponding bit line (BL1, BL2) through the write control transistor (530, 532),
- the gate of each write control transistor (530, 532) is connected to the corresponding write control signal line (WWL1, WWL2)
- the buffer transistor (522) has a gate connected to an output signal node (Q504) of the second inverter (504), a source of the buffer transistor (522) connected to the power supply feedback line (VSSL), and the buffer
- the drain of the transistor (522) is connected to the corresponding bit line (BL1, BL3) through the read control transistor (524, 526),
- the gates of the read control transistors (524, 526) are connected to the corresponding read control signal lines (RWL1, RWL2).
- Configuration 5 In the SRAM cell according to any one of Configurations 1 to 4, the first and second inverters (202, 302, 402, 502: 204, 304, 405, 504) have a P-type field effect. It is characterized by comprising transistors (210, 310, 410, 510) and N-type field effect transistors (212, 312, 412, 512).
- Configuration 6 The SRAM cell according to Configuration 5 is characterized in that each of the transistors is a fin-shaped double insulated gate field effect transistor, and two gate electrodes are commonly connected to operate in a three-terminal manner.
- the feedback control transistor (220, 320, 322, 420, 520) includes a P-type field effect transistor, and the buffer transistor (226, 226). 324, 326, 422, 522), write control transistors (222, 330, 332, 430, 432, 434, 530, 532), and read control transistors (224, 334, 336, 424, 426, 428, 524, 526). ) Is an N-type field effect transistor.
- Configuration 8 The SRAM cell according to Configuration 7, wherein each of the transistors is a fin-shaped double insulated gate field effect transistor, and two gate electrodes are connected in common to operate in three terminals. .
- the positive feedback circuit since the positive feedback circuit is disconnected in the write operation, the stored contents can be easily written. That is, since the input signal node (write node) of the inverter written in the SRAM cell has a high impedance, it is sufficient to apply an input signal for setting the output to a high level or a low level in the same manner as a normal inverter. It is.
- the read operation since the positive feedback circuit is configured, the write node does not become high impedance, and the read buffer transistor prevents the bit line potential from affecting the write node. Since it is highly resistant to noise, it is not necessary to adjust and set the dimensions of the read or write control transistor with respect to the transistors constituting the inverter in order to ensure a noise margin for the read operation.
- FIG. 1 shows a schematic diagram of a double insulated gate field effect transistor having a conventional fin-shaped structure and having two independent gate electrodes.
- FIG. 3 shows a control signal waveform diagram of the write operation, which is a simulation result of the write operation of the conventional SRAM cell of FIG.
- FIG. 3 shows signal waveforms at respective nodes when the contents of the conventional SRAM cell of FIG. 2 are read from the SRAM cell in which the stored contents are held at a low level.
- FIG. 3 shows signal waveforms at each node when reading the contents of the SRAM cell in which the stored contents of the conventional SRAM cell of FIG. 2 are held at a high level.
- FIG. 2 shows a configuration diagram of a conventional SRAM cell in which a read buffer including a read control transistor and a buffer transistor and a read-only bit line are separately added.
- 1 shows a configuration diagram of Embodiment 1 of an SRAM cell of the present invention.
- FIG. FIG. 3 is a circuit configuration diagram used for simulation including the SRAM cell of Example 1 of the present invention in order to confirm the operation.
- 12 is a simulation result of a high-level write operation in the SRAM cell of FIG. 11 of the present invention.
- 12 is a simulation result of a low-level write operation in the SRAM cell of FIG. 11 of the present invention.
- the simulation result of the read operation at that time is shown.
- the potential of the output signal node Q204 is held at a low level (0.0 V), and the simulation result of the read operation at that time is shown.
- FIG. 10 is a block diagram of the SRAM cell according to the first embodiment of the present invention.
- An SRAM circuit 200 having a single bit line BL, a write control signal line WWL, and a read control signal line RWL.
- the drains of the PMOST 210 and the NMOS T212 are connected to form an output signal node Q202, and each gate electrode is
- the first inverter 202 is configured by connecting to the input signal node I202, the source of the PMOST 210 being connected to the power supply line VDDL, and the source of the NMOS T212 being connected to the power supply feedback line VSSL.
- the drains of PMOST 214 and NMOST 216 are connected to form output signal node Q204, the gate electrodes are connected to form input signal node I204, the source of PMOS T214 is connected to power supply line VDDL, and the source of NMOS T216 is fed back to power supply feedback.
- a second inverter 204 is configured by connecting to the line VSSL.
- the output signal node Q202 of the first inverter 202 is connected to the input signal node I204 of the second inverter 204, and the output signal node Q204 is connected to the drain (or source) of the PMOST220 that is a feedback control transistor.
- the gate of the PMOST 220 is connected to the write control signal line WWL
- the input signal node I202 of the first inverter 202 is connected to the source (or drain) of the NMOS T222 which is a write control transistor
- the drain (or source) of the NMOS T222 is It is connected to the bit line BL, and its gate is connected to the write control signal line WWL.
- the output signal node Q204 of the second inverter 204 is connected to the gate of the NMOS T226 that is a buffer transistor, the source of the NMOS T226 is connected to the power supply feedback line VSSL, and the drain of the NMOS T226 is the source (or drain) of the NMOS T224 that is a read control transistor.
- the drain (or source) of the NMOS T224 is connected to the bit line BL, and the gate of the NMOS T224 is connected to the read control signal line RWL.
- the control circuit 230 appropriately controls the potential of the decoding circuit for selecting the cell, the write control signal line WWL, and the read control signal line RWL.
- the circuit operation of the SRAM cell 200 is performed based on the read control signal line RWL and the write control signal line WWL from the control circuit 230.
- both the write control signal line WWL and the read control signal line RWL to which the SRAM cell 200 is connected have a low potential (normally Is the same as the potential of the power supply feedback line VSSL)
- the NMOST 222 and the NMOST 224 are non-conductive
- the SRAM cell 200 is disconnected from the bit line BL
- the PMOST 220 is conductive and the first inverter 202 and the second Since the positive feedback circuit is configured with the inverter 204, the SRAM cell 200 is disconnected from the external circuit (sense circuit, other SRAM cell, etc.), and the stored contents are held. It has become.
- the potential of the bit line BL is set to a logic level corresponding to the content to be written, that is, high level (VDDL potential) or low level (VSSL potential), and the power is supplied through a low impedance state (usually a conductive transistor). It is connected to the supply line VDDL or the power supply feedback line VSSL and is in a state where charge and discharge of charge are extremely easy.
- the potential of the write control signal line WWL is increased, and the NMOST 222 is turned on and the PMOST 220 is turned off at the same time.
- the logic level of the bit line BL is transferred to the input signal node of the first inverter 202 through the NMOS T222, the output signal node Q202 of the first inverter 202 becomes its inverted level, and the output signal node of the second inverter 204 Q204 is an inversion level of the logic level of the output signal node Q202 of the first inverter 202. That is, the output signal node Q204 of the second inverter 204 and the input signal node I202 of the first inverter 202 have the same logic level.
- the level transferred to the input signal node I202 of the first inverter 202 decreases by the threshold voltage of the NMOS 222, so that the high potential value of the write control signal line WWL is set to the power supply.
- the potential of the supply line VDDL may be set higher by at least the threshold voltage.
- the potential of the write control signal line WWL is set to a low potential so that the NMOS T222 is turned off, and at the same time, the PMOST 220 is turned on to shift to a state of holding the stored memory contents.
- the potential of the input signal node I202 of the first inverter 202 is held by a parasitic capacitor such as a transistor connected to the first inverter 202, so that the memory content to be written is not inverted.
- the bit line BL is connected to the power supply line VDDL or the power supply feedback line VSSL through a high impedance state (usually a non-conductive transistor or the like. (Discharge is extremely difficult).
- the potential of the read control signal line RWL is set to a high potential, and the NMOS T224 is turned on.
- the output signal node Q204 of the second inverter 204 is at a high level, the NMOS T226 is in a conducting state. Accordingly, a discharge path for the charge of the bit line BL is formed through the NMOSTs 224 and 226.
- bit line BL Since the bit line BL is initially in a high impedance state and the further supply of electric charge is extremely small, the potential thereof decreases. This continues as long as the NMOST 224 is in a conductive state, and finally falls to the potential level (low level) of the power supply feedback line VSSL. On the other hand, if the output signal node Q204 of the second inverter 204 is at a low level, the NMOS T226 is in a non-conducting state, the charge discharge path of the bit line BL cannot be formed, and the bit line potential does not decrease.
- FIG. 11 is a circuit configuration diagram used for a simulation including the SRAM cell 200 of Example 1 of the present invention for confirming the operation.
- the same reference numerals as those in the embodiment of FIG. 10 have the same configuration and function, and the description thereof is omitted here.
- the control circuit 230 and the sense circuit are omitted.
- the potential of the power supply line VDDL is VDD (0.7 V in the simulation), and the potential of the power supply feedback line VSSL is the ground potential GND (0.0 V).
- the bit line BL is connected to the pulse signal source through the NMOS T240.
- the signal of the pulse signal source is represented by Vbitsource.
- a signal of the bit line BL is represented by Vbitline.
- Another independent pulse signal source is connected to the gate of the NMOS T240, and the conduction and non-conduction of the NMOS T240 (at this time, the bit line BL is in a low impedance state and a high impedance state) are controlled by the signal Vbitscont.
- the potential of the write control signal line WWL is driven by another independent pulse signal source, and the signal is represented by Vwwl.
- the potential of the read control signal line RWL is driven by another independent pulse signal source, and the signal is represented by Vwr1.
- Vcellwrite is the signal of the input signal node I202 of the first inverter 202
- Vcellhold is the signal of the output signal node Q202 of the first inverter 202 and the input signal node I204 of the second inverter 204
- Vcellread is the second inverter 204.
- Vrbfn represents a signal at a connection point between the drain of the NMOS T226 and the NMOS T224.
- FIG. 12 shows a simulation result of a high level write operation in the SRAM cell of FIG. 11 of the present invention.
- the horizontal axis of FIG. 12 represents Time (time) (s: second), and the vertical axis represents Signal Swing (signal amplitude) (V).
- ⁇ indicates Vcellhold (cell hold voltage) characteristics
- ⁇ is Vcellwrite (cell write voltage) characteristics
- ⁇ is the Vcellread (cell read voltage) characteristic
- X indicates a characteristic of Vwwl (a signal of the write control signal line WWL, that is, a write control signal).
- Table 5 shows the sampling values of the simulation results in FIG.
- the state of the SRAM cell is that Vcellwrite and Vcellread are at a low level (0.0 V) and Vcellhold is at a high level (0.7 V), and a write operation is performed so as to reverse this state.
- Vbitline of the bit line BL reaches a high level
- the potential of the write control signal line WWL is set to a high potential to make the NMOS T222 conductive, and at the same time, the PMOS T220 is made nonconductive to start the second inverter 204 from the second inverter 204.
- the positive feedback circuit to one inverter 202 is disconnected, and the first inverter 202 and the second inverter 204 are simply connected in cascade.
- the potential Vbitline of the bit line BL is transferred to the input signal node I202 of the first inverter 202, and the potential Vcellwrite of the input signal node I202 of the first inverter 202 changes to high level.
- the potential Vcellhold of the output signal node Q202 is sequentially changed to a low level, and the potential Vcellread of the output signal node Q204 of the second inverter 204 is sequentially changed to a high level.
- the potential of the write control signal line WWL is returned to a low potential to make the NMOST 222 nonconductive, and at the same time, the PMOST220 is made conductive to make a positive feedback circuit from the second inverter 204 to the first 202.
- FIG. 12 shows that Vcellwrite and Vcellread are maintained at a high level and Vcellhold is maintained at a low level when a time that can be regarded as a steady state elapses although there is a small potential drop transiently.
- FIG. 13 shows a simulation result of a low level write operation in the SRAM cell of FIG. 11 of the present invention.
- the horizontal axis in FIG. 13 represents Time (time) (s: second), and the vertical axis represents Signal Swing (signal amplitude) (V).
- ⁇ indicates Vcellhold (cell hold voltage) characteristics
- ⁇ is Vcellwrite (cell write voltage) characteristics
- ⁇ is the Vcellread (cell read voltage) characteristic
- X indicates a characteristic of Vwwl (a signal of the write control signal line WWL, that is, a write control signal).
- Table 6 shows the sampling values of the simulation results in FIG.
- the state of the SRAM cell is that Vcellwrite and Vcellread are at a high level (0.7 V) and Vcellhold is at a low level (0.0 V), and a write operation is performed so as to reverse this state.
- Vbitline of the bit line BL reaches a low level
- the potential of the write control signal line WWL is set to a high potential to make the NMOST 222 conductive, and at the same time, the PMOST220 is made nonconductive to start the second inverter 204 from the second inverter 204.
- the positive feedback circuit to one inverter 202 is disconnected, and the first inverter 202 and the second inverter 204 are simply connected in cascade.
- the potential Vbitline of the bit line BL is transferred to the input signal node I202 of the first inverter 202, and the potential Vcellwrite of the input signal node I202 of the first inverter 202 changes to a low level, so that the output signal of the first inverter 202
- the potential Vcellhold of the node Q202 is sequentially changed to a high level, and the potential of the output signal node Q204 of the second inverter 204 is sequentially changed to a low level.
- the potential of the write control signal line WWL is returned to a low potential to make the NMOS T222 nonconductive, and at the same time, the PMOST220 is made conductive to positively feed back from the second inverter 204 to the first inverter 202.
- a circuit is configured, and the state in which the written content is retained is entered.
- FIG. 13 certainly shows that Vcellwrite and Vcellread are kept at a low level and Vcellhold is kept at a high level.
- the low-level transfer efficiency of the PMOST 220 is poor, it is not in a non-conductive state but is in a high resistance state unless the potential of the write control signal line WWL is made lower than its threshold voltage by more than 0.0V.
- the impedance of the input signal node I202 of one inverter 202 is higher than that of the output signal node Q204 in the low impedance state of the second inverter 204. Therefore, when the hold state is entered, the input signal node I202 potential Vcellwrite of the first inverter 202 is affected by the redistribution of electric charge, and becomes a potential level slightly lower than the expected low level value of 0.0V. However, this does not cause inversion of stored contents. Even if the potential of the input signal node I202 of the first inverter 202 rises due to the influence of noise or the like, if the absolute value of the threshold voltage of the PMOST220 rises, the PMOST220 becomes in a low resistance state and becomes low.
- the output signal node Q204 of the second inverter 204 Since it is connected to the output signal node Q204 of the second inverter 204 in the impedance state, further increase is suppressed, and the inversion of the stored contents does not occur. If the absolute value of the threshold voltage of the PMOST 220 is reduced to approach 0 V, or rather set to a positive value, the above phenomenon is reduced. That is, the potential Vcellwrite of the input signal node I202 of the first inverter 202 can be kept close to 0.0 V that is an expected low level value.
- FIG. 14 shows a simulation result of the read operation at that time assuming that the potential Vcellread of the output signal node Q204 of the second inverter 204 is held at a high level (0.7 V) in the SRAM cell of FIG. 11 of the present invention. Show.
- the horizontal axis of FIG. 14 represents Time (time) (s: second), and the vertical axis represents Signal Swing (signal amplitude) (V).
- ⁇ indicates Vcellhold (cell hold voltage) characteristics
- ⁇ is Vcellwrite (cell write voltage) characteristics
- ⁇ is the Vcellread (cell read voltage) characteristic
- X indicates Vwwl (signal of write control signal line WWL, that is, write control signal) characteristic ( no arrow )
- ⁇ is the Vwrl (read control signal line WRL signal, that is, read control signal) characteristic
- ⁇ Indicates Vbitscont (a gate voltage applied to NMOST for controlling the connection state between the pulse power supply for applying the potential of the bit line and the bit line).
- Table 7 shows the sampling values of the simulation results in FIG.
- the NMOST 226 is in a conductive state and the drain potential Vrbfn is at a low level (0.0 V).
- the bit line BL is set to a high level, and after the potential is stabilized, the Vbitscont is set to a low potential to make the NMOS T240 nonconductive, and the bit line BL is set to a high impedance state.
- the potential Vwrl of the read control signal line WRL is set to a high potential, so that the NMOS T224 is changed from a non-conductive state to a conductive state.
- a discharge path to ground potential GND is formed through NMOST 224 and NMOST 226.
- bit line BL Since the bit line BL initially maintains a high impedance state and no charge charging path, its potential Vbitline starts to decrease as shown in FIG. At the same time, Vrbfn temporarily increases but does not exceed Vbitline, and finally decreases as shown in FIG. 14 as Vbitline decreases. This state continues while Vwrl is at a high potential, and eventually Vbitline and Vrbfn should settle to the GND level (0.0 V).
- Vwrl when Vwrl is kept at a high potential to some extent and then returned to a low potential again, the discharge path disappears, so the decrease in Vbitline does not proceed, and the value of Vbitline at that time is maintained.
- Vbrfn does not change that the NMOST 226 is in a conductive state, and further decreases faster because the parasitic capacitance is smaller than that of the bit line BL, and finally becomes the GND level (0.0).
- the holding state is entered, but as shown in FIG. 14, since Vcellread and Vcellwrite are both kept at the high level before the read operation, and Vcellhold is kept at the low level, the read operation does not invert the stored contents. I understand that.
- FIG. 15 shows that in the SRAM cell 200 of FIG. 11 of the present invention, the potential Vcellread of the output signal node Q204 of the second inverter 204 is held at a low level (0.0V), and Vcellhold is held at a high level (0.7V). The simulation result of the read operation at that time is shown. In the figure, Vcellread remains at 0.0 V, so the display is omitted to avoid complexity of the figure.
- the horizontal axis of FIG. 15 represents Time (time) (s: second), and the vertical axis represents Signal Swing (signal amplitude) (V).
- ⁇ indicates Vcellhold (cell hold voltage) characteristics
- ⁇ is Vcellwrite (cell write voltage) characteristics
- ⁇ indicates Vwrl (read control signal line WRL signal, that is, read control signal) characteristics
- * Vbitline (bit line voltage) characteristics + Is the Vrbfn (buffer transistor drain voltage) characteristic
- ⁇ Indicates Vbitscont (a gate voltage applied to NMOST for controlling the connection state between the pulse power supply for applying the potential of the bit line and the bit line).
- Table 8 shows the sampling values of the simulation results in FIG.
- the NMOST 226 is in a non-conductive state, but the drain potential Vrbfn is set to a low level (0.0 V). This is because if it is kept for a long time, it will be very close to the low level due to the influence of the leakage current of the NMOS T226, and the output signal node Q204 of the second inverter 204 is set to the high level as described above. This is because if there is a history to become low level.
- the bit line BL is set to the high level, and after the potential is stabilized, the Vbitscont is set to the low potential to make the NMOS T240 nonconductive, and the bit line BL is set to the high impedance state.
- the potential Vwrl of the read control signal line WRL is set to a high potential, and the NMOS T224 is changed from a non-conductive state to a conductive state.
- the NMOST 226 since the NMOST 226 is non-conductive, a discharge path from the bit line BL to the ground potential GND is not formed, so the potential Vbitline of the bit line BL should not decrease.
- the drain of the NMOS T226 receives the supply of charge from the bit line BL, and its potential Vrbfn increases. At the same time, the potential of Vbitline is lowered corresponding to the loss of the charge. Eventually, Vbitline and Vrbfn become constant values in a state where they almost coincide.
- This phenomenon is a so-called charge redistribution phenomenon.
- the parasitic capacitance of the bit line is sufficiently larger than the parasitic capacitance of the drain of the NMOS T 226, so that the decrease amount of Vbitline should actually be smaller than the case of FIG.
- the bit line BL and the drain of the NMOS T226 remain in a high impedance state, so that Vbitline and Vrbfn almost coincide with each other. And kept at a constant value.
- Vcellhold is kept at the high level before the reading operation (Vcellread is at the low level). It can be seen that there is no reversal of the stored contents in the operation. Note that Vcellwrite is negative because the read operation is performed after the low level is written as shown in FIG. 13, so that the input signal node I202 of the first inverter 202 is the same as described in FIG. This is because the output signal node Q204 of the second inverter 204 is connected with a high resistance. As a result, the stored contents were not reversed in the simulation.
- the absolute value of the threshold voltage of the PMOST 220 is used. For example, there is a means of making the size smaller temporarily or permanently only in the holding state.
- the sense circuit can determine what the stored content is based on the difference in the value of Vbitline. For example, if an input of an inverter having the same logic threshold value as that of the inverter of this SRAM cell is connected, the determination can be made based on the output.
- FIG. 16 is a configuration diagram of an SRAM cell according to the second embodiment of the present invention.
- FIG. 16 shows a plurality of bit lines and a plurality of control signal line pairs corresponding to each bit line, the number of which is the same as the number of bit lines, each including one write control signal line and one read control signal line.
- SRAM cell 300 having Using this SRAM cell 300, a multi-port SRAM device can be constructed. That is, in the SRAM device in which the SRAM cells are arranged in an array, when reading or writing is performed on each cell in one row direction (word direction), the same operation is performed on each cell in another row direction at the same time. Thus, an SRAM device can be configured.
- a pair of control lines is common to SRAM cells arranged in the same row direction, and a plurality of bit lines are common to SRAM cells arranged in the same column direction. . Different control line pairs are used for different rows, and the same plurality of bit lines different from those of other columns are used for different columns. However, the operation is the same.
- FIG. 16 there are two bit lines BL1 and BL2 that are common in the column direction, and corresponding to the bit line BL1, a first write control signal line WWL1 and a read control signal line RWL1 that are common in the row direction.
- An SRAM cell 300 having two control signal line pairs, one control signal line pair and a second control signal line pair consisting of a write control signal line WWL2 and a read control signal line RWL2, corresponding to the bit line BL2. Show.
- the drains of the PMOST 310 and the NMOS T312 are connected to form an output signal node Q302, the gate electrodes are connected to form an input signal node I302, the source of the PMOST310 is connected to the power supply line VDDL, and the source of the NMOST312 is the power supply feedback line.
- a first inverter 302 is configured by connecting to VSSL.
- the drains of the PMOST 314 and the NMOS T316 are connected to form an output signal node Q304, the gate electrodes are connected to the input signal node I304, the source of the PMOST314 is connected to the power supply line VDDL, and the source of the NMOST316 is connected to the power supply feedback.
- a second inverter 304 is configured by connecting to the line VSSL.
- the output signal node Q302 of the first inverter 302 is connected to the input signal node I304 of the second inverter 304.
- the output signal node Q304 of the second inverter 304 and the input signal node I302 of the first inverter 302 are connected by providing two feedback control transistors, PMOST320 and 322, which are connected in series.
- NMOSTs 330 and 332 which are write control transistors, are prepared corresponding to the write control signal lines WWL1 and WWL2 belonging to each control signal line pair, and the respective sources are connected to the input signal node I302 of the first inverter 302. The other drain is connected to the corresponding bit lines BL1 and BL2.
- NMOSTs 334 and 336 as read control transistors and NMOSTs 324 and 326 as buffer transistors are prepared corresponding to the read control signal lines RWL1 and RWL2, and the sources of the NMOSTs 334 and 336 are connected to the drains of the NMOSTs 324 and 326, respectively.
- NMOSTs 334 and 336 are connected to corresponding bit lines BL1 and BL2, respectively, and the gates are connected to corresponding read control signal lines RWL1 and RWL2, respectively. Further, the gates of the PMOSTs 320 and 322 are connected to the write control signal lines WWL1 and WWL2, respectively.
- Read operation is performed in the same manner as in the first embodiment by selecting either one or all of the read control signal lines, that is, setting the potential to a high potential. At this time, it is a matter of course that the bit line for performing the read operation is kept in a potential state for that purpose. In the read operation, two or more read control signal lines connected to the same SRAM cell can be selected simultaneously. A simultaneous read operation is also possible for SRAM cells arranged in different rows. However, the bit lines used should be different. Furthermore, for each of the SRAM cells arranged in different rows, a certain row can be a write operation, and another row can be a read operation.
- each bit line can be used for various combinations of read and write operations.
- the bit line on which the read operation and the write operation are performed should be different.
- the SRAM cell In the hold state, the SRAM cell is disconnected from each bit line. However, the non-conducting NMOST is in a connected state, and a leakage current or the like may flow. However, they are separated in the sense that the stored contents are not inverted by the potential change of the bit line. Further, the PMOSTs 320 and 322, which are two feedback control transistors, are in a conductive state to form a positive feedback circuit.
- the NMOS transistors 324 and 326 which are buffer transistors, can be replaced by a single buffer transistor having the same size and structure.
- the number of cases will be small, when reading the stored contents to a plurality of different bit lines at the same time, the reading speed decreases because the resistance of the buffer transistor in the discharge path increases multiple times in the worst case. If the speed reduction is within an allowable range, the common use has an effect of reducing the area increase in realizing the SRAM cell. When the above case cannot be ignored, the embodiment of FIG. 16 is effective.
- FIG. 17 is a configuration diagram of an SRAM cell according to the third embodiment of the present invention.
- FIG. 17 shows the case where the SRAM cell has three bit lines.
- the SRAM cell 400 of FIG. 17 has three bit lines BL1, BL2, and BL3, and a control signal having one write control signal line and one read control signal line corresponding to each bit line as constituent elements. It has line pairs (WWL1, RWL1), (WWL2, RWL2) and (WWL3, RWL3), and one feedback control signal line CWL.
- the control circuit 440 outputs an appropriate signal to each component of each control signal line pair.
- the first inverter 402 is composed of a PMOST 410 and an NMOST 412, and its input signal node is I 402 and its output signal node is Q 402.
- the second inverter 404 includes a PMOST 414 and an NMOS T416, and its input signal node is I404 and its output signal node is Q404.
- the output signal node Q402 of the first inverter 402 and the input signal node I404 of the second inverter 404 are connected.
- the output signal node Q404 of the second inverter 404 and the input node I402 of the first inverter 402 are connected through one feedback control transistor, PMOST420, and the gate of the PMOST420 is connected to the feedback control signal line CWL.
- the output signal node Q404 of the second inverter 404 is connected to the gate of the NMOS T422 that is one buffer transistor, and the source of the NMOS T422 is connected to the power supply feedback line VSSL.
- the drain of the NMOS T422 is connected to the sources of the NMOSTs 424, 426 and 428 which are read control transistors.
- the drains of the NMOSTs 424, 426, and 428 are connected to the bit lines BL1, BL2, and BL3, respectively, and the gates are read control signal lines RWL1, RWL2, and RWL3, which are components of the control signal line pair corresponding to each bit line. Are connected to each.
- the input signal node I402 of the first inverter 402 is connected to the sources of NMOSTs 430, 432, and 434, which are write control transistors, and the drains thereof are connected to the bit lines BL1, BL2, and BL3, respectively, and the gates are connected to the respective bits.
- NMOSTs 430, 432, and 434 which are write control transistors
- the drains thereof are connected to the bit lines BL1, BL2, and BL3, respectively, and the gates are connected to the respective bits.
- write control signal lines WWL1, WWL2, and WWL3 which are components of the control signal line pair corresponding to the line.
- the PMOST 420 sets the potential of the feedback control signal line CWL to a high potential and makes it non-conductive only when the write operation is selected.
- a positive feedback circuit is configured between the first inverter 402 and the second inverter 404 in a conductive state.
- the signal of the feedback control signal line CWL may be logically the logical sum of the signals of the write control signal lines WWL1, WWL2, and WWL3.
- An NMOST may be used instead of the PMOST, but the logic of the signal on the feedback control signal line CWL is the above inversion.
- one feedback control transistor is used to reduce the number of transistors. Instead, one feedback control signal line is provided, and the gate is controlled from the feedback control signal line so that the feedback control transistor is turned off during the write operation. A signal is applied. Furthermore, the buffer transistor is also shared to reduce the increase in the number of transistors.
- the above embodiment shows the case where there are three bit lines, there may be two or three or more.
- the number of transistors in the SRAM cell need only be increased by 2 for each bit line. Therefore, when an SRAM memory device is realized as an integrated circuit, the ratio of the area increase to the bit line increase of the SRAM cell can be reduced.
- FIG. 18 is a configuration diagram of an SRAM cell according to the fourth embodiment of the present invention.
- the first inverter 502 includes a PMOST 510 and an NMOS T512, and its input signal node is I502 and its output signal node is Q502.
- the second inverter 504 includes a PMOST 514 and an NMOST 516, and its input signal node is I504 and its output signal node is Q504.
- the output signal node Q502 of the first inverter 502 and the input signal node I504 of the second inverter 504 are connected.
- the output signal node Q504 of the second inverter 504 and the input signal node I502 of the first inverter 502 are connected through one feedback control transistor PMOST520, and the gate of the PMOST520 is connected to the feedback control signal line CWL.
- the output signal node Q504 of the second inverter 504 is connected to the gate of the NMOS T522 which is one buffer transistor, and the source of the NMOS T522 is connected to the power supply feedback line VSSL.
- the drain of the NMOST 522 is connected to the sources of the NMOSTs 524 and 526 which are read control transistors.
- the drains of the NMOSTs 524 and 526 are connected to the bit lines BL1 and BL3, respectively, and the gates are connected to the read control signal lines RWL1 and RWL2 corresponding to the bit lines, respectively.
- the input signal node I502 of the first inverter 502 is connected to the sources of the NMOSTs 530 and 532 which are write control transistors, the drains thereof are connected to the bit lines BL1 and BL2, respectively, and the gates thereof are connected to the respective bit.
- the write control signal lines WWL1 and WWL2 corresponding to the lines are respectively connected.
- the PMOST 520 sets the potential of the feedback control signal line CWL to a high potential and makes it non-conductive only when the write operation is selected. In other cases, a positive feedback circuit is configured between the first inverter 502 and the second inverter 504 in a conductive state.
- bit line BL1 and one control signal line pair (WWL1, RWL1) corresponding thereto there is one bit line BL1 and one control signal line pair (WWL1, RWL1) corresponding thereto, the other bit line BL2 is used exclusively for writing, and the bit line BL3 is used exclusively for reading.
- One write control line WWL2 corresponds to the bit line BL2
- one read control line RWL2 corresponds to the bit line BL3.
- the write control signal line and the corresponding write control transistor can be reduced, or the read control signal line and the corresponding read control transistor can be reduced. Can be suppressed.
- a function as a flexible storage device can be realized by a function of a target storage device such as a combination of reading out two lines.
- each transistor used was a fin-shaped double insulated gate field effect transistor shown in the schematic diagram of FIG. .
- 601 is a first gate electrode
- 602 is a second gate electrode
- 603 is a first gate oxide film
- 604 is a second gate oxide film
- 605 is a source region
- 606 is a source region 605.
- the first electrode, 607 is the second electrode of the source region 605, 608 is the channel region
- 609 is the drain region
- 610 is the first electrode of the drain region 609
- 611 is the second electrode of the drain region 609.
- Each electrode is provided on the side surface of a fin-shaped semiconductor layer (semiconductor section having a rectangular cross section made up of 605, 608, and 609), and each electrode functions as a so-called heat radiating fin, and has the effect of widening the cooling or heat transfer area. is there.
- the length of the gate electrodes 601 and 602 was 50 nm, the thickness of the fin was 10 nm, and the height of the fin was 100 nm. In the three-terminal operation, twice the fin height corresponds to the so-called channel width. In order to speed up the change of the bit line potential, only NMOST is dared to be five times. This can be realized by, for example, a method of connecting five NMOSTs having the same structure as the NMOST in parallel. Table 9 shows constants such as dimensions of the MOS transistors used in the simulation.
- the voltage VDD of the power supply line of the SRAM cell was 0.7V, and the voltage VSS of the power supply feedback line was 0.0V.
- a so-called fin-type double-insulated gate-gate field effect that is configured in crystalline silicon on an insulating layer on a substrate as disclosed in Patent Document 3 and Patent Document 4, and in which current flows parallel to the substrate.
- transistors two gate electrodes are formed integrally with a channel sandwiched between them and others are electrically separated as shown in FIG. 4
- the channel width is the height of the fin. It is not easy to change the height of each transistor.
- the SRAM cell when configured using these fin-shaped double insulated gate field effect transistors, if the present invention is applied, it can be configured with the same channel width.
- a storage device can be configured.
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Abstract
Description
図2においては、P形のMOST(PMOST)40およびN形のMOST(NMOST)42の各ドレインを出力信号ノードQ42に接続し、各ゲート電極を入力信号ノードI42に接続し、PMOST40のソースはノードVD42において電源供給線VDDLに接続し、さらにNMOST42のソースはノードVS42において電源帰還線VSSLに接続して第一のインバータ32が構成されており、またPMOST44およびNMOST46の各ドレインを出力信号ノードQ44に接続し、各ゲート電極を入力信号ノードI44に接続し、PMOST44のソースはノードVD44において電源供給線VDDLに接続し、さらにNMOST46のソースはノードVS44において電源帰還線VSSLに接続して第二のインバータ34が構成されている。さらに、第一のインバータ32の出力信号ノードQ42は第二のインバータ34の入力信号ノードI44に接続し、第二のインバータ34の出力信号ノードQ44は帰還制御トランジスタであるPMOST50のドレイン(またはソース)に接続され、PMOST50のソース(またはドレイン)は第一のインバータ32の入力信号ノードI42に接続して、PMOST50が導通状態のときに正帰還回路(またはラッチ回路)が構成されるようになっている。さらに、PMOST50のゲートはノードP10において帰還回路制御信号を供給するワード線CWLに接続され、第一のインバータ32の入力信号ノードI42は書き込み制御トランジスタであるNMOST52のソース(またはドレイン)に接続され、NMOST52のドレイン(またはソース)はノードD8において一本のビット線BLに接続され、ゲート電極はノードP8において書き込み制御信号を供給する書き込み制御信号線WWLに接続されている。また第二のインバータ34の出力信号ノードQ44は読み出し制御トランジスタであるNMOST54のソース(またはドレイン)に接続され、NMOST54のドレイン(またはソース)はノードD9において上記ビット線BLに接続され、NMOST54のゲート電極はノードP9において読み出し制御信号を供給する読み出し制御信号線RWLに接続されている。制御回路60はこのセルを選択するためのデコード回路やWWL線、CWL線やRWL線の電位を適切に制御し、それぞれの制御信号を生成する。
図2のような一つのビット線で書き込み動作及び読み出し動作を行うSRAMセルを用いた記憶装置はビット線に誘起する雑音電圧による誤動作(特に読み出し動作においての誤動作)の対策が必要であるが、1キャパシタDRAMと同様にいわゆるオープンビットライン方式を採用してその対策とすることができる。図3において、インバータ86(点線で囲まれた部分回路)はPMOST70およびNMOST72とで構成され、インバータ88(点線で囲まれた部分回路)はPMOST74およびNMOST76とで構成され、インバータ86の出力信号ノードとインバータ88の入力信号ノードが結線されている。このノードをVcellholdと呼ぶ。また、インバータ86の入力信号ノードをVcellwriteと、インバータ88の出力信号ノードをVcellreadと呼ぶが、これらは帰還制御トランジスタであるNMOST84で接続されている。NMOST84の導通、非導通状態はそのゲートに印加される制御信号Vfbcontにより定まる。ノードVcellreadおよびVcellwriteはそれぞれ読み出し制御トランジスタであるNMOST80および書き込み制御トランジスタであるNMOST82により一つのビット線BLに接続されている。NMOST80および82の導通、非導通状態はそれぞれのゲート電極端子に印加される制御信号VwrlおよびVwwlによって定まる。ビット線BLには、記憶装置アレイの他の行のセルが多数接続されていることを想定して負荷容量Cbitを接続した。またその電位はNMOST90によりビット線電位制御信号源Vbitsourceに制御される。NMOST90のゲート電極端子には制御信号Vbitscontが印加され、NMOST90を非導通状態とすることによりビット線BLを高インピーダンス状態(電荷の放電や充電が極めて制限された状態)にすることができる。なお、ノードの記号でそのノードの信号波形の記号も表すことにする。
△はVfbcont(帰還制御信号線CWLの信号、すなわち帰還制御信号)特性、
●はVwwl(書き込み制御信号線WWLの信号、すなわち書き込み制御信号)特性を示す。
図5の特性より、VfbcontとVwwlは時間的に交互に一定値をとる。
-はVcellhold(セルのホールド電圧、すなわち第一のインバータの出力ノードの電圧)特性、
+はVcellwrite(セルの書き込み電圧、すなわち第一のインバータの入力ノード電圧)特性、
実線はVcellread(セルの読み出し電圧、すなわち第二のインバータの出力ノード電圧)特性、
*はVbitline(ビット線電圧)特性を示す。
◇はVcellhold(セルのホールド電圧)特性、
□はVcellwrite(セルの書き込み電圧)特性、
△はVcellread(セルの読み出し電圧)特性、
×はVfbcont(帰還制御信号線CWLの信号、すなわち帰還制御信号)特性、
*はVbitline(ビット線電圧)特性、
+はVwrl(読み出し制御信号線WRLの信号、すなわち読み出し制御信号)特性、
-付き実線はVbitsource(ビット線の電位を与えるためのパルス電源の電圧)特性、
-付き鎖線はVbitscont(ビット線の電位を与えるためのパルス電源とビット線の接続状態を制御するためのNMOSTに与えるゲート電圧)特性を示す。
◇はVcellhold(セルのホールド電圧)特性、
前面□はVcellwrite(セルの書き込み電圧)特性、
△はVcellread(セルの読み出し電圧)特性、
×付き鎖線はVfbcont(帰還制御信号線CWLの信号、すなわち帰還制御信号)特性、
*はVbitline(ビット線電圧)特性、
+付き鎖線はVwrl(読み出し制御信号線WRLの信号、すなわち読み出し制御信号)特性、
後面□はVbitsource(ビット線の電位を与えるためのパルス電源の電圧)特性、
-付き鎖線はVbitscont(ビット線の電位を与えるためのパルス電源とビット線の接続状態を制御するためのNMOSTに与えるゲート電圧)特性を示す。
本発明のSRAMセルは、メモリセル、特に二つのインバータ間の正帰還回路を接続または切断制御する帰還制御トランジスタを備え、一本のビット線に接続された書き込み制御トランジスタと読み出し制御トランジスタとを有し、さらにその読み出し制御トランジスタに接続された読み出しバッファトランジスタを有する。
構成1:SRAMセルであって、
一本のビット線(BL)と、
該ビット線(BL)に対応する、一本の書き込み制御信号線(WWL)および一本の読み出し制御信号線(RWL)からなる制御信号線対と、
帰還制御トランジスタ(220)と、
該帰還制御トランジスタ(220)とは極性が反対の、書き込み制御トランジスタ(222)と、読み出し制御トランジスタ(224)と、バッファトランジスタ(226)と、
出力信号ノード(Q202)および入力信号ノード(I202)を有する第一のインバータ(202)と、
出力信号ノード(Q204)および入力信号ノード(I204)を有する第二のインバータ(204)とを備え、
前記第一および第二のインバータ(202,204)は電源供給線(VDDL)および電源帰還線(VSSL)にそれぞれ接続されて動作し、
前記第一のインバータ(202)の出力信号ノード(Q202)は前記第二のインバータ(204)の入力信号ノード(I204)に接続し、前記第二のインバータ(204)の出力信号ノード(Q204)と前記第一のインバータ(202)の入力信号ノード(I202)間は前記帰還制御トランジスタ(220)で接続し、前記第一のインバータ(202)の入力信号ノード(I202)と前記ビット線(BL)間は前記書き込み制御トランジスタ(222)で接続し、
前記帰還制御トランジスタ(220)および前記書き込み制御トランジスタ(222)のそれぞれのゲートは前記書き込み制御信号線(WWL)に接続し、
前記バッファトランジスタ(226)のゲートは前記第二のインバータ(204)の出力信号ノード(Q204)に接続し、前記バッファトランジスタ(226)のソースは前記電源帰還線(VSSL)に接続し、前記バッファトランジスタ(226)のドレインと前記ビット線(BL)間は前記読み出し制御トランジスタ(224)で接続し、
前記読み出し制御トランジスタ(224)のゲートは前記読み出し制御信号線(RWL)に接続することを特徴とする。
複数本のビット線(BL1,BL2)と、
該ビット線(BL1,BL2)に対応する、一本の書き込み制御信号線(WWL1,WWL2)および一本の読み出し制御信号線(RWL1,RWL2)とからなる、前記ビット線(BL1,BL2)と同数の複数の制御信号線対と、
前記各ビット線(BL1,BL2)に対応する、帰還制御トランジスタ(320,322)、該帰還制御トランジスタ(320,322)とは極性がそれぞれ反対の、書き込み制御トランジスタ(330,332)と、読み出し制御トランジスタ(334,336)、バッファトランジスタ(324,326)とからなる、前記ビット線(BL1,BL2)と同数の複数のトランジスタ群と、
出力信号ノード(Q302)および入力信号ノード(I302)を有する第一のインバータ(302)と、
出力信号ノード(Q304)および入力信号ノード(I304)を有する第二のインバータ(304)とを備え、
前記第一および第二のインバータ(302,304)は電源供給線(VDDL)および電源帰還線(VSSL)にそれぞれ接続されて動作し、
前記第一のインバータ(302)の出力信号ノード(Q302)は前記第二のインバータ(304)の入力信号ノード(I304)に接続し、前記第二のインバータ(304)の出力信号ノード(Q304)と前記第一のインバータ(302)の入力信号ノード(I302)間は前記帰還制御トランジスタ(320,322)をすべて直列接続し、前記第一のインバータ(302)の入力信号ノード(I302)と前記ビット線(BL1,BL2)間は対応する前記書き込み制御トランジスタ(330,332)で接続し、
前記各帰還制御トランジスタ(320,322)および前記書き込み制御トランジスタ(330,332)のゲートは、対応する前記書き込み制御信号線(WWL1,WWL2)に接続し、
前記各バッファトランジスタ(324,326)のゲートは前記第二のインバータ(304)の出力信号ノード(Q304)に接続し、前記各バッファトランジスタ(324,326)のソースは前記電源帰還線(VSSL)に接続し、前記各バッファトランジスタ(324,326)のドレインと対応する前記各ビット線(BL1,BL2)間は対応する前記各読み出し制御トランジスタ(334,336)で接続し、
前記各読み出し制御トランジスタ(334,336)のゲートは前記読み出し制御信号線(RWL1,RWL2)に接続することを特徴とする。
複数本のビット線(BL1,BL2,BL3)と、
前記各ビット線(BL1,BL2,BL3)に対応する、一本の書き込み制御信号線(WWL1,WWL2,WWL3)および一本の読み出し制御信号線(RWL1,RWL2,RWL3)とからなる、前記ビット線(BL1,BL2,BL3)と同数の複数の制御信号線対と、
一本の帰還制御線(CWL)と、
帰還制御トランジスタ(420)と、
バッファトランジスタ(422)と、
前記各ビット線(BL1,BL2,BL3)に対応する、前記帰還制御トランジスタ(420)とは極性がそれぞれ反対の、書き込み制御トランジスタ(430,432,434)および読み出し制御トランジスタ(424,426,428)とからなる、前記ビット線(BL1,BL2,BL3)と同数の複数のトランジスタ群と、
出力信号ノード(Q402)および入力信号ノード(I402)を有する第一のインバータ(402)と、
出力信号ノード(Q404)および入力信号ノード(I404)を有する第二のインバータ(404)とを備え、
前記第一および第二のインバータ(402,404)は電源供給線(VDDL)および電源帰還線(VSSL)に接続されて動作し、
前記第一のインバータ(402)の出力信号ノード(Q402)は第二のインバータ(404)の入力信号ノード(I404)に接続し、第二のインバータ(404)の出力信号ノード(Q404)と前記第一のインバータ(402)の入力信号ノード(I402)間は前記帰還制御トランジスタ(420)で接続し、
前記帰還制御トランジスタ(420)のゲートは前記帰還制御線(CWL)に接続し、
前記第一のインバータ(402)の入力信号ノード(I402)と前記各ビット線(BL1,BL2,BL3)間は対応する前記各書き込み制御トランジスタ(430,432,434)で接続し、
前記バッファトランジスタ(422)のゲートは前記第二のインバータ(404)の出力信号ノード(Q402)に接続し、前記バッファトランジスタ(422)のソースは前記電源帰還線(VSSL)に接続し、前記バッファトランジスタ(422)のドレインと前記各ビット線(BL1,BL2,BL3)間は対応する前記各読み出し制御トランジスタ(424,426,428)で接続し、前記読み出し制御トランジスタ(424,426,428)のゲートは前記ビット線(BL1,BL2,BL3)に対応する前記制御信号線対の前記各読み出し制御信号線(RWL1,RWL2,RWL3)に接続したことを特徴とする。
複数本のビット線(BL1,BL2,BL3)と、
該ビット線(BL1,BL2,BL3)のうちの少なくとも一本のビット線(BL1)に対応する、一本の書き込み制御信号線(WWL1)と一本の読み出し制御信号線(RWL1)とからなる制御信号線対と、
他のビット線(BL2、BL3)に対応する書き込み制御信号線(WWL2)または読み出し制御信号線(RWL2)と、
一本の帰還制御線(CWL)と、
帰還制御トランジスタ(520)と、
前記書き込み制御信号線(WWL1,WWL2)に対応する前記書き込み制御トランジスタ(530,532)と、
前記読み出し制御線(RWL1,RWL2)に対応する読み出し制御トランジスタ(524,526)と、
バッファトランジスタ(522)と、
出力信号ノード(Q502)および入力信号ノード(I502)を有する第一のインバータ(502)と、
出力信号ノード(Q504)および入力信号ノード(I504)を有する第二のインバータ(504)とを備え、
前記第一および第二のインバータ(502,504)は電源供給線(VDDL)および電源帰還線(VSSL)に接続されて動作し、
前記第一のインバータ(502)の出力信号ノード(Q502)は前記第二のインバータ(504)の入力信号ノード(I504)に接続し、前記第二のインバータ(504)の出力信号ノード(Q504)と前記第一のインバータ(502)の入力信号ノード(I502)間は前記帰還制御トランジスタ(520)で接続し、
前記帰還制御トランジスタ(520)のゲートは前記帰還制御線(CWL)に接続し、
前記第一のインバータ(502)の入力信号ノード(I502)は前記書き込み制御トランジスタ(530,532)を通して対応するビット線(BL1,BL2)に接続し、
前記各書き込み制御トランジスタ(530,532)のゲートは対応する書き込み制御信号線(WWL1,WWL2)に接続し、
前記バッファトランジスタ(522)のゲートは前記第二のインバータ(504)の出力信号ノード(Q504)に接続し、前記バッファトランジスタ(522)のソースは前記電源帰還線(VSSL)に接続し、前記バッファトランジスタ(522)のドレインは前記読み出し制御トランジスタ(524,526)を通して対応するビット線(BL1,BL3)に接続し、
前記読み出し制御トランジスタ(524,526)のゲートは対応する前記読み出し制御信号線(RWL1,RWL2)に接続することを特徴とする。
図10は本発明のSRAMセルの実施例1の構成図を示す。
それぞれ一本の、ビット線BL、書き込み制御信号線WWLおよび読み出し制御信号線RWLを有するSRAM回路200であって、まずPMOST210およびNMOST212の各ドレインを接続して出力信号ノードQ202とし、各ゲート電極を接続して入力信号ノードI202とし、PMOST210のソースは電源供給線VDDLに接続し、さらにNMOST212のソースは電源帰還線VSSLに接続して第一のインバータ202が構成されている。同様にPMOST214およびNMOST216の各ドレインを接続して出力信号ノードQ204とし、各ゲート電極を接続して入力信号ノードI204とし、PMOST214のソースは電源供給線VDDLに接続し、さらにNMOST216のソースは電源帰還線VSSLに接続して第二のインバータ204が構成されている。また、第一のインバータ202の出力信号ノードQ202は第二のインバータ204の入力信号ノードI204に接続され、その出力信号ノードQ204は帰還制御トランジスタであるPMOST220のドレイン(またはソース)に接続され、PMOST220のソース(またはドレイン)は第一のインバータ202の入力信号ノードI202に接続して、PMOST220が導通状態のときに正帰還回路(またはラッチ回路)が構成されるようになっている。さらに、PMOST220のゲートは書き込み制御信号線WWLに接続され、第一のインバータ202の入力信号ノードI202は書き込み制御トランジスタであるNMOST222のソース(またはドレイン)に接続され、NMOST222のドレイン(またはソース)はビット線BLに接続され、そのゲートは書き込み制御信号線WWLに接続されている。また第二のインバータ204の出力信号ノードQ204はバッファトランジスタであるNMOST226のゲートに接続され、NMOST226のソースは電源帰還線VSSLに接続され、NMOST226のドレインは読み出し制御トランジスタであるNMOST224のソース(またはドレイン)に接続され、NMOST224のドレイン(またはソース)はビット線BLに接続され、NMOST224のゲートは読み出し制御信号線RWLに接続されている。制御回路230はこのセルを選択するためのデコード回路や書き込み制御信号線WWLや読み出し制御信号線RWLの電位を適切に制御する。
◇はVcellhold(セルのホールド電圧)特性、
□はVcellwrite(セルの書き込み電圧)特性、
△はVcellread(セルの読み出し電圧)特性、
*はVbitline(ビット線電圧)特性、
×はVwwl(書き込み制御信号線WWLの信号、すなわち書き込み制御信号)特性を示す。
◇はVcellhold(セルのホールド電圧)特性、
□はVcellwrite(セルの書き込み電圧)特性、
△はVcellread(セルの読み出し電圧)特性、
*はVbitline(ビット線電圧)特性、
×はVwwl(書き込み制御信号線WWLの信号、すなわち書き込み制御信号)特性を示す。
◇はVcellhold(セルのホールド電圧)特性、
□はVcellwrite(セルの書き込み電圧)特性、
△はVcellread(セルの読み出し電圧)特性、
*はVbitline(ビット線電圧)特性、
×はVwwl(書き込み制御信号線WWLの信号、すなわち書き込み制御信号)特性(矢印なし)、
○はVwrl(読み出し制御信号線WRLの信号、すなわち読み出し制御信号)特性、
+はVrbfn(バッファトランジスタのドレインの電圧)特性、
-はVbitscont(ビット線の電位を与えるためのパルス電源とビット線の接続状態を制御するためのNMOSTに与えるゲート電圧)特性を示す。
◇はVcellhold(セルのホールド電圧)特性、
□はVcellwrite(セルの書き込み電圧)特性、
○はVwrl(読み出し制御 信号線WRLの信号、すなわち読み出し制御信号)特性、
*はVbitline(ビット線電圧)特性、
+はVrbfn(バッファトランジスタのドレインの電圧)特性、
-はVbitscont(ビット線の電位を与えるためのパルス電源とビット線の接続状態を制御するためのNMOSTに与えるゲート電圧)特性を示す。
書き込み制御信号線WWL1およびWWL2のどちらかが選択されると、すなわちどちらかを高電位とすると、それに対応したどちらかのビット線BL1およびBL2の電位が第一のインバータ302の入力信号ノードI302に転送される。このとき同時に、それに対応したどちらかのPMOST320と322は非導通となるので正帰還回路は切断されており、第一の実施例と同様に書き込み動作が行われる。同じSRAMセルに接続されている二個以上の書き込み制御信号線を同時に選択することは正常動作の保証ができないので禁止すべきである。異なる行に配置されたSRAMセルに対しては同時書き込み動作可能である。
SRAMセルが三本のビット線を有する場合について図17に示す。図17のSRAMセル400は三本のビット線BL1、BL2およびBL3を有し、各ビット線に対応する、一本の書き込み制御信号線と一本の読み出し制御信号線を構成要素とする制御信号線対(WWL1、RWL1)、(WWL2、RWL2)および(WWL3、RWL3)と、一本の帰還制御信号線CWLとを有する。制御回路440は上記各制御信号線対の各構成要素に適切な信号を出力する。
第一のインバータ502はPMOST510とNMOST512とで構成され、その入力信号ノードはI502、出力信号ノードはQ502である。同様に第二のインバータ504はPMOST514とNMOST516とで構成され、その入力信号ノードはI504、出力信号ノードはQ504である。第一のインバータ502の出力信号ノードQ502と第二のインバータ504の入力信号ノードI504は接続されている。第二のインバータ504の出力信号ノードQ504と第一のインバータ502の入力信号ノードI502は一個の帰還制御トランジスタであるPMOST520を通して接続され、PMOST520のゲートは帰還制御信号線CWLに接続されている。また、第二のインバータ504の出力信号ノードQ504は一個のバッファトランジスタであるNMOST522のゲートに接続され、NMOST522のソースは電源帰還線VSSLに接続されている。NMOST522のドレインは読み出し制御トランジスタであるNMOST524および526の各ソースに接続されている。NMOST524および526の各ドレインはそれぞれビット線BL1、BL3に接続されており、各ゲートは各ビット線に対応する読み出し制御信号線RWL1およびRWL2にそれぞれ接続されている。第一のインバータ502の入力信号ノードI502は書き込み制御トランジスタであるNMOST530および532の各ソースに接続され、その各ドレインはビット線BL1およびBL2にそれぞれ接続されており、またその各ゲートは前記各ビット線に対応する書き込み制御信号線WWL1およびWWL2にそれぞれ接続されている。
Claims (8)
- SRAMセルであって、
一本のビット線と、
該ビット線に対応する、一本の書き込み制御信号線および一本の読み出し制御信号線からなる制御信号線対と、
帰還制御トランジスタと、
該帰還制御トランジスタとは極性が反対の、書き込み制御トランジスタと、読み出し制御トランジスタと、バッファトランジスタと、
出力信号ノードおよび入力信号ノードを有する第一のインバータと、
出力信号ノードおよび入力信号ノードを有する第二のインバータとを備え、
前記第一および第二のインバータは電源供給線および電源帰還線にそれぞれ接続されて動作し、
前記第一のインバータの出力信号ノードは前記第二のインバータの入力信号ノードに接続し、前記第二のインバータの出力信号ノードと前記第一のインバータの入力信号ノード間は前記帰還制御トランジスタで接続し、前記第一のインバータの入力信号ノードと前記ビット線間は前記書き込み制御トランジスタで接続し、
前記帰還制御トランジスタおよび前記書き込み制御トランジスタのそれぞれのゲートは前記書き込み制御信号線に接続し、
前記バッファトランジスタのゲートは前記第二のインバータの出力信号ノードに接続し、前記バッファトランジスタのソースは前記電源帰還線に接続し、前記バッファトランジスタのドレインと前記ビット線間は前記読み出し制御トランジスタで接続し、
前記読み出し制御トランジスタのゲートは前記読み出し制御信号線に接続することを特徴とするSRAMセル。 - SRAMセルであって、
複数本のビット線と、
該ビット線に対応する、一本の書き込み制御信号線および一本の読み出し制御信号線とからなる、前記ビット線と同数の複数の制御信号線対と、
前記各ビット線に対応する、帰還制御トランジスタ、該帰還制御トランジスタとは極性がそれぞれ反対の、書き込み制御トランジスタと、読み出し制御トランジスタ、バッファトランジスタとからなる、前記ビット線と同数の複数のトランジスタ群と、
出力信号ノードおよび入力信号ノードを有する第一のインバータと、
出力信号ノードおよび入力信号ノードを有する第二のインバータとを備え、
前記第一および第二のインバータは電源供給線および電源帰還線にそれぞれ接続されて動作し、
前記第一のインバータの出力信号ノードは前記第二のインバータの入力信号ノードに接続し、前記第二のインバータの出力信号ノードと前記第一のインバータの入力信号ノード間は前記帰還制御トランジスタをすべて直列接続し、前記第一のインバータの入力信号ノードと前記ビット線間は対応する前記書き込み制御トランジスタで接続し、
前記各帰還制御トランジスタおよび前記書き込み制御トランジスタのゲートは、対応する前記書き込み制御信号線に接続し、
前記各バッファトランジスタのゲートは前記第二のインバータの出力信号ノードに接続し、前記各バッファトランジスタのソースは前記電源帰還線に接続し、前記各バッファトランジスタのドレインと対応する前記各ビット線間は対応する前記各読み出し制御トランジスタで接続し、
前記各読み出し制御トランジスタのゲートは前記読み出し制御信号線に接続することを特徴とするSRAMセル。 - SRAMセルであって、
複数本のビット線と、
前記各ビット線に対応する、一本の書き込み制御信号線および一本の読み出し制御信号線とからなる、前記ビット線と同数の複数の制御信号線対と、
一本の帰還制御線と、
帰還制御トランジスタと、
バッファトランジスタと、
前記各ビット線に対応する、前記帰還制御トランジスタとは極性がそれぞれ反対の、書き込み制御トランジスタおよび読み出し制御トランジスタとからなる、前記ビット線と同数の複数のトランジスタ群と、
出力信号ノードおよび入力信号ノードを有する第一のインバータと、
出力信号ノードおよび入力信号ノードを有する第二のインバータとを備え、
前記第一および第二のインバータは電源供給線および電源帰還線に接続されて動作し、
前記第一のインバータの出力信号ノードは第二のインバータの入力信号ノードに接続し、第二のインバータの出力信号ノードと前記第一のインバータの入力信号ノード間は前記帰還制御トランジスタで接続し、
前記帰還制御トランジスタのゲートは前記帰還制御線に接続し、
前記第一のインバータの入力信号ノードと前記各ビット線間は対応する前記各書き込み制御トランジスタで接続し、
前記バッファトランジスタのゲートは前記第二のインバータの出力信号ノードに接続し、前記バッファトランジスタのソースは前記電源帰還線に接続し、前記バッファトランジスタのドレインと前記各ビット線間は対応する前記各読み出し制御トランジスタで接続し、前記読み出し制御トランジスタのゲートは前記ビット線に対応する前記制御信号線対の前記各読み出し制御信号線に接続したことを特徴とするSRAMセル。 - SRAMセルであって、
複数本のビット線と、
該ビット線のうちの少なくとも一本のビット線に対応する、一本の書き込み制御信号線と一本の読み出し制御信号線とからなる制御信号線対と、
他のビット線に対応する書き込み制御信号線または読み出し制御信号線と、
一本の帰還制御線と、
帰還制御トランジスタと、
前記書き込み制御信号線に対応する前記書き込み制御トランジスタと、
前記読み出し制御線に対応する読み出し制御トランジスタと、
バッファトランジスタと、
出力信号ノードおよび入力信号ノードを有する第一のインバータと、
出力信号ノードおよび入力信号ノードを有する第二のインバータとを備え、
前記第一および第二のインバータは電源供給線および電源帰還線に接続されて動作し、
前記第一のインバータの出力信号ノードは前記第二のインバータの入力信号ノードに接続し、前記第二のインバータの出力信号ノードと前記第一のインバータの入力信号ノード間は前記帰還制御トランジスタで接続し、
前記帰還制御トランジスタのゲートは前記帰還制御線に接続し、
前記第一のインバータの入力信号ノードは前記書き込み制御トランジスタを通して対応するビット線に接続し、
前記各書き込み制御トランジスタのゲートは対応する書き込み制御信号線に接続し、
前記バッファトランジスタのゲートは前記第二のインバータの出力信号ノードに接続し、前記バッファトランジスタのソースは前記電源帰還線に接続し、前記バッファトランジスタのドレインは前記読み出し制御トランジスタを通して対応するビット線に接続し、
前記読み出し制御トランジスタのゲートは対応する前記読み出し制御信号線に接続することを特徴とするSRAMセル。 - 請求項1から4のいずれか1項記載のSRAMセルにおいて、前記第一および第二のインバータはP形電界効果トランジスタとN形電界効果トランジスタとで構成することを特徴とするSRAMセル。
- 請求項5記載のSRAMセルにおいて、前記各トランジスタをフィン(ひれ)形構造の二重絶縁ゲート電界効果トランジスタとし、二つのゲート電極を共通接続して三端子動作させることを特徴とするSRAMセル。
- 請求項1から4のいずれか1項記載のSRAMセルにおいて、前記帰還制御トランジスタはP形電界効果トランジスタからなり、前記バッファトランジスタ、書き込み制御トランジスタ、および読み出し制御トランジスタはN形電界効果トランジスタからなることを特徴とするSRAMセル。
- 請求項7記載のSRAMセルにおいて、前記各トランジスタをフィン(ひれ)形構造の二重絶縁ゲート電界効果トランジスタとし、二つのゲート電極を共通接続して三端子動作させることを特徴とするSRAMセル。
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PCT/JP2010/004354 WO2011013298A1 (ja) | 2009-07-29 | 2010-07-02 | Sramセル |
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US (1) | US8537603B2 (ja) |
JP (1) | JP5382886B2 (ja) |
WO (1) | WO2011013298A1 (ja) |
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US20130088931A1 (en) * | 2011-10-10 | 2013-04-11 | International Business Machines Corporation | Asymmetric memory cells |
CN112992225A (zh) * | 2021-02-19 | 2021-06-18 | 中国科学院微电子研究所 | 一种sram存储单元、sram存储器以及数据存储方法 |
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TWI463493B (zh) * | 2011-03-08 | 2014-12-01 | Univ Nat Chiao Tung | 靜態隨機存取記憶體胞元及其操作方法 |
US9406348B2 (en) * | 2013-12-26 | 2016-08-02 | Semiconductor Energy Laboratory Co., Ltd. | Memory cell including transistor and capacitor |
US9177636B1 (en) | 2014-05-09 | 2015-11-03 | International Business Machines Corporation | 8T based SRAM cell and related method |
CN106328190B (zh) * | 2015-06-30 | 2019-03-26 | 中芯国际集成电路制造(上海)有限公司 | 静态随机存储单元 |
TWI609375B (zh) * | 2016-01-21 | 2017-12-21 | 國立成功大學 | 雙字線非同步驅動的記憶細胞及具此記憶細胞的記憶體 |
TWI698871B (zh) * | 2017-01-03 | 2020-07-11 | 聯華電子股份有限公司 | 六電晶體靜態隨機存取記憶體單元及其操作方法 |
US10658026B2 (en) * | 2017-05-26 | 2020-05-19 | Taiwan Semiconductor Manufacturing Company Limited | Word line pulse width control circuit in static random access memory |
CN109545251B (zh) * | 2017-09-22 | 2021-01-05 | 联华电子股份有限公司 | 由静态随机存取存储器组成的存储器元件的布局图案 |
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Also Published As
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JP5382886B2 (ja) | 2014-01-08 |
US8537603B2 (en) | 2013-09-17 |
JPWO2011013298A1 (ja) | 2013-01-07 |
US20120120717A1 (en) | 2012-05-17 |
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