TWI559478B - 預置通孔之嵌入式封裝 - Google Patents

預置通孔之嵌入式封裝 Download PDF

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TWI559478B
TWI559478B TW103127157A TW103127157A TWI559478B TW I559478 B TWI559478 B TW I559478B TW 103127157 A TW103127157 A TW 103127157A TW 103127157 A TW103127157 A TW 103127157A TW I559478 B TWI559478 B TW I559478B
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microelectronic
metal post
thickness
microelectronic assembly
metal
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TW201507080A (zh
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貝勒卡塞姆 哈巴
依利亞斯 穆罕默德
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英凡薩斯公司
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Description

預置通孔之嵌入式封裝
本申請案敘述例如可併入微電子組件中的結構，以及用於製造此種結構的方法，微電子組件可包含未封裝的半導體晶粒或已封裝的半導體晶粒。
例如半導體晶片的微電子裝置通常需要許多對於其他電子元件的輸入與輸出連接。半導體晶片或其他類似裝置的輸入與輸出接點通常設置成類似格柵的型態，其實質上覆蓋該裝置的表面(通常稱為「區域陣列」)，或者設置成伸長的列，其可延伸平行於該裝置的前表面的每一邊緣且相鄰於該每一邊緣，或在前表面的中心中。通常，例如晶片的裝置必須實體安裝於基板上(例如印刷電路板)，且該裝置的接點必須電連接於電路板的導電特徵。
半導體晶片通常設置於封裝中，封裝促進在製造期間以及在安裝晶片於外部基板上(例如電路板或其他電路平板)的期間晶片的處理。例如，許多半導體晶片設置於適於表面安裝的封裝中。已經提出此種一般類型的數種封裝來用於多種應用。最一般的，此種封裝包含介電質元件(通 常稱為「晶片載體」)，具有形成為板狀或蝕刻金屬結構的端子在該介電質上。這些端子通常藉由例如沿著晶片載體本身延伸的細線路之特徵以及藉由延伸於晶片接點與端子或線路之間的細引線或導線，而連接於晶片本身的接點。在表面安裝操作中，封裝係置於電路板上，使得封裝上的每一端子對準於電路板上的對應接墊。焊錫或其他接合材料設置於端子與接墊之間。藉由加熱該組件來熔化或「迴焊」焊錫或者活化該接合材料，該封裝可永久地接合在定位。
許多封裝包含焊錫塊係為焊錫球的形式，通常直徑為大約0.005mm與大約0.8mm之間，附接於封裝的端子。具有焊錫球陣列從其底表面突伸的封裝通常稱為球柵陣列或「BGA(ball grid array)」封裝。其他封裝(稱為平面柵格陣列或「LGA(land grid array)」封裝)係藉由焊錫形成的薄層或平面而固定至基板。此種封裝可以很精小。一些封裝(通常稱為「晶片級封裝」)占據電路板的面積係等於(或僅稍微大於)該封裝中所併入的裝置的面積。這是有利的，因為它減小組件的整體尺寸，並且允許使用基板上的各種裝置之間的短互連，這接著限制了裝置之間的信號傳輸時間，且因此促成組件以高速操作。
可提供中介層作為互連元件，具有其接點以及頂與底表面在其頂或底表面之一者處電連接於一或更多個已封裝或未封裝半導體晶粒，且在其頂或底表面之另一者處電連接於另一元件。在一些實例中，另一元件可為封裝基板，封裝基板接著可電連接於另一個元件，其可為或可包含電路平板。
雖然本領域中有上述所有進展，微電子組件、微電子組件的 個別元件(例如，中介層與微電子元件)與製造微電子組件的方法方面仍需要再進一步的改良。
本文揭示微電子組件與製造微電子組件的方法。在一些實施例中，一種微電子組件包含一微電子元件，其具有一前表面、圍繞該前表面的邊緣表面、與在該前表面處的複數個接點，該微電子元件具有一第一厚度係自該前表面延伸於一第一方向。該微電子組件包含實質上剛性的金屬柱，其延伸於該柱設置於該邊緣表面與該微電子組件的一對應邊緣之間。每一金屬柱具有一側壁，該側壁將此種金屬柱的第一與第二端部表面在該第一方向中彼此分隔，其中該金屬柱的該側壁具有小於大約1微米的一均方根(rms)表面粗糙度。該微電子組件包含一封裝部，其一第二厚度係延伸於該封裝部的第一與第二表面之間的該第一方向中，該封裝部接觸於該微電子元件的至少該邊緣表面與該金屬柱的該側壁，其中該金屬柱之延伸至少部分通過該第二厚度，且該封裝部使相鄰的金屬柱彼此絕緣。該微電子組件具有分別相鄰於該封裝部的該第一與第二表面之第一與第二側部，且該微電子組件具有端子在該第一側部處。該微電子組件包含一絕緣層，其覆蓋在該第一側部處之該封裝部的該第一表面，並且具有一厚度延伸自該封裝部的該第一表面。該微電子組件包含連接元件，其延伸自該金屬柱的該第一端部表面並且通過該絕緣層的該厚度。該第一連接元件電連接至少一些該第一端部表面於對應的端子，其中至少一些連接元件具有的橫剖面係小於該金屬柱的橫剖面。該微電子組件包含一導電再分布結構， 其沉積於該絕緣層上。該再分布結構通過至少一些該連接元件而電連接該端子於該金屬柱的對應第一端部表面，其中至少一些該金屬柱係電耦接於該微電子元件的該接點。
在一實施例中，該金屬柱從該封裝部的該第一表面延伸至該封裝部的該第二表面。
在一實施例中，該第一厚度係小於或等於該第二厚度之一者。
在一實施例中，該微電子組件另包含第二連接元件，其延伸於該封裝部的該第二厚度的該第一方向中、從該金屬柱的該第二端部表面延伸至該封裝部的該第二表面。
在一實施例中，該第二連接元件具有側壁係具有大於大約1微米的一rms表面粗糙度。
在一實施例中，該金屬柱延伸於該封裝部的該第二厚度的第一方向中，至少大約為該第二厚度的50%。
在一實施例中，至少一些該第二連接元件具有一橫剖面係小於該金屬柱的橫剖面。
在一實施例中，該微電子組件另包含第二端子，其在該微電子組件的該第二側部處。該再分布結構係沉積於該微電子組件的該第二側部上，並且通過該第二連接元件的至少一者而電連接該第二端子於該金屬柱的對應第二端部表面。
在一實施例中，該微電子組件另包含第二端子，其在該微電子組件的該第二側部處。該微電子組件另包含一第二絕緣層，其覆蓋在該 微電子組件的該第二側部處之該封裝部的該第二表面，並且其厚度延伸自該封裝部的該第二表面。該微電子組件另包含第二連接元件，其延伸自該金屬柱的該第二端部表面，並且通過該第二絕緣層的該厚度，該第二連接元件電連接至少一些該第二端部表面於對應的第二端子，其中至少一些第二連接元件的橫剖面係小於該金屬柱的橫剖面。
在一實施例中，該第一與第二厚度係相同。
在一實施例中，該微電子組件另包含第二端子，其在該微電子組件的該第二側部處。該再分布結構包含線路延伸於橫越該第一方向的一第二方向中、超出該金屬柱的該邊緣表面，其中該第一端子的至少一者通過該線路而電耦接於該第一端部表面，或者該第二端子通過該線路而電耦接於該第二端部表面。
在一實施例中，該微電子組件包含一第二微電子元件，其至少部分覆蓋該第一微電子元件，其中該第二微電子元件具有一第一表面、圍繞該第一表面的邊緣表面，該第二微電子元件之一厚度，係自該第二微電子元件的該第一表面延伸於該第一方向中，其中該封裝部接觸於該第二微電子元件的至少該邊緣表面。
在一實施例中，一種形成一微電子組件的方法包含：形成包含一微電子元件的一結構，該微電子元件具有一前表面、圍繞該前表面的邊緣表面、與在該前表面處的複數個接點，以及形成實質上剛性的金屬柱，其延伸於該第一方向中。該柱設置於該邊緣表面的至少一者與該微電子組件的一對應邊緣之間。每一金屬柱具有一側壁，該側壁將此種金屬柱的第一與第二端部表面彼此分隔，該金屬柱的該側壁具有小於大約1微米的一均 方根(rms)表面粗糙度。該方法包含形成一封裝部，其具有一第二厚度係延伸於該封裝部的第一與第二表面之間的該第一方向中。該封裝部接觸於該微電子元件的至少該邊緣表面與該金屬柱的該側壁，其中該金屬柱延伸至少部分通過該第二厚度，且該封裝部使相鄰的金屬柱彼此電性絕緣。該方法包含沉積一絕緣層，其覆蓋該封裝部的該第一表面，並且厚度延伸自該封裝部的該第一表面。該方法包含形成連接元件，其延伸自該金屬柱的該第一端部表面並且通過該絕緣層的該厚度，其中至少一些連接元件的橫剖面係小於該金屬柱的橫剖面。該方法包含沉積一導電再分布結構於該絕緣層上，該再分布層電連接至少一些金屬柱於該微電子元件的該接點。該方法包含形成端子於該微電子組件的一第一側部處、相鄰於該封裝部的該第一表面，其中該連接元件電連接至少一些第一端部表面於對應的端子。
在一實施例中，在形成該結構之前，該金屬柱從一導電層的一第一表面延伸於該第一方向中，該柱設置於該導電層的該第一表面的一第一部分與該導電層的一對應邊緣之間。
在一實施例中，形成該結構另包含：附接該微電子元件的該前表面至該導電層的該第一表面的該第一部分。
在一實施例中，在形成該結構之前，該方法另包含：提供一基板，該基板之一厚度係延伸於該第一方向中、從該基板的一第一表面至一第二表面，該基板之複數個剛性元件自該基板的該第二表面處延伸於該第一方向中；以及沉積一導電材料於該基板的該第二表面與該剛性元件的表面上，以形成該金屬柱與導電層。
在一實施例中，在形成該封裝部之後，該方法另包含：移除 該基板與該剛性元件，以曝露出該金屬柱中的開孔，該金屬柱中的該開孔從該微電子組件的該前側延伸於該第一方向中；以及在沉積該絕緣層之前，利用額外的導電材料來充填該開孔。
在一實施例中，在形成該封裝部之後且在沉積該絕緣層之前，該方法另包含：移除該導電層，以曝露出該金屬柱的該第一端部表面。
在一實施例中，該方法另包含：形成一第二絕緣層，其覆蓋該封裝部的該第二表面，並且具有厚度延伸自該封裝部的該第二表面；形成第二連接元件，其延伸自該金屬柱的該第二端部表面並且通過該第二絕緣層的該厚度，其中至少一些第二連接元件的橫剖面係小於該金屬柱的橫剖面；沉積該再分布結構於該第二絕緣層上；以及形成第二端子於該微電子組件的該第二側部處、相鄰於該封裝部的該第二表面，其中該第二端子覆蓋該再分布結構，其中該第二連接元件通過該再分布結構而電連接至少一些第二端部表面於對應的第二端子。
在一實施例中，該方法另包含：形成開孔以延伸於金屬柱之第二端部表面與該封裝部的該第二表面之間，該開孔曝露出該金屬柱的第二端部表面的至少部分；以及形成第二連接元件，其延伸通過該封裝部中的該開孔並且電連接於在該第二端部表面處的至少一些金屬柱。
在一實施例中，在形成該結構之前，該微電子元件的該前表面係附接於一載體。
在一實施例中，形成該結構另包含：附接該載體至該金屬柱，使得該微電子元件並列於該導電層的該第一表面的該第一部分。
在一實施例中，該微電子元件與該導電層的該第一表面的該 第一部分從此分隔。
在一實施例中，在形成該封裝部之後，該方法另包含：移除該載體，以曝露出該微電子元件的該前表面與該金屬柱的該第二端部表面；以及移除該導電層，以曝露出該金屬柱的該第一端部表面。
100‧‧‧微電子組件
102‧‧‧微電子元件
104‧‧‧前表面
106‧‧‧邊緣表面
108‧‧‧第一厚度
110‧‧‧第一方向
112‧‧‧接點
114‧‧‧金屬柱
116‧‧‧側壁
118‧‧‧第一端部表面
120‧‧‧第二端部表面
122‧‧‧封裝部
123‧‧‧第一表面
124‧‧‧第二厚度
125‧‧‧第二表面
126‧‧‧再分布結構
127‧‧‧第一側部
128‧‧‧連接元件
129‧‧‧第二側部
130‧‧‧第一側部
131‧‧‧端子
132‧‧‧第二連接元件
133‧‧‧第二端子
134‧‧‧第二側部
135‧‧‧電路板
136‧‧‧絕緣層
137‧‧‧線路
140‧‧‧第二絕緣層
142、144‧‧‧絕緣層
150、160、170、180、190、192‧‧‧微電子組件
181‧‧‧第一表面
182‧‧‧第二微電子元件
183‧‧‧邊緣表面
184‧‧‧第二表面
185‧‧‧接點
193‧‧‧第二微電子元件
194‧‧‧第一表面
195‧‧‧邊緣表面
196‧‧‧接點
200‧‧‧方法
300‧‧‧結構
302‧‧‧導電層
303‧‧‧第一部分
304‧‧‧第一表面
306‧‧‧開孔
308‧‧‧開孔
400‧‧‧結構
402‧‧‧導電層
403‧‧‧第一部分
404‧‧‧第一表面
406‧‧‧開孔
500‧‧‧載體
502‧‧‧結構
504‧‧‧導電層
506‧‧‧第一部分
508‧‧‧第一表面
600‧‧‧基板
602‧‧‧第一表面
604‧‧‧第二表面
606‧‧‧剛性元件
608‧‧‧開孔
第1-1圖為本案較佳實施例之微電子組件的側部示意圖；第1-2圖為本案較佳實施例之微電子組件的側部示意圖；第1-3圖為本案較佳實施例之微電子組件的側部示意圖；第1-4圖為本案較佳實施例之微電子組件的側部示意圖；第1-5圖為本案較佳實施例之微電子組件的俯視橫剖面視圖；第1-6圖為本案較佳實施例之微電子組件的部分俯視示意圖；第1-7圖為本案較佳實施例之堆疊結構中的複數個微電子組件的側部示意圖；第1-8圖為本案較佳實施例之微電子組件的部分俯視示意圖；第1-9圖為本案較佳實施例之微電子組件的部分俯視示意圖；第1-10圖為本案較佳實施例之微電子組件的部分俯視示意圖；第2圖為本案較佳實施例之形成微電子組件的方法的流程圖；第3-1至3-6圖為本案較佳實施例之製造微電子組件的方法中的各階段；第4-1至4-6圖為本案較佳實施例之製造微電子組件的方法中的各階段；第5-1至5-6圖為本案較佳實施例之製造微電子組件的方法中的各階段； 第6-1至6-5圖為本案較佳實施例之製造微電子組件的方法中的各階段。
本發明將更詳細敘述於下。
本文所述的所有範圍包含端點，包含那些敘述範圍「之間」的兩個值。例如「大約」、「大體上」、「實質上」與類似者的用語係解釋為修改一用語或值，使得它不是絕對的值，但是不會讀到先前技術。此種用語將由修改為本領域中熟習技藝者所瞭解的那些用語之用語與狀況來界定。這至少包含：針對用於測量一值的給定技術，預期的實驗誤差、技術誤差、與儀器誤差的程度。
應另外瞭解到，範圍格式的敘述僅為了方便與簡化，且不該解釋為本發明的範圍之非彈性限制。因此，範圍的敘述應視為已經具體揭示所有可能的次範圍，以及該範圍內的個別數值。例如，範圍的敘述(例如，從1到6)應視為已經具體揭示次範圍，例如從1到3、從1到4、從1到5、從2到4、從2到6、從3到6等，以及該範圍內的個別數值，例如1、2、2.3、3、4、5、5.7與6。不管範圍的廣度這都適用。
當在此揭示案中參照元件使用時，元件(例如，導電元件、接點、金屬柱、端子、結構、或其他元件)在元件(例如，微電子元件、中介層、電路板、或其他基板)的表面「處」的陳述係表示：當元件未組裝於任何其他元件時，該元件可以接觸於一理論點，該理論點移動於垂直於元件表面的方向中、從元件外部朝向元件表面。因此，在元件表面處的元件可從此種表面突伸；可齊平於此種表面；或可相對於此種表面凹陷於 元件中的孔或凹部中。
第1-1至1-3圖為本案較佳實施例之微電子組件。本文所揭示的微電子組件的各種實施例可單獨或組合使用。
第1-1圖為本案較佳實施例之微電子組件100的側部示意圖。微電子組件100包含微電子元件102。微電子元件102具前表面104與圍繞前表面104的邊緣表面106。微電子元件102的第一厚度108可自前表面104延伸於第一方向110中。微電子元件包含複數個接點112在前表面104處。範例性微電子元件102可包含半導體晶粒、已封裝的半導體晶粒、或類似者的任何一或更多者。
微電子組件100包含複數個實質上剛性的金屬柱114，金屬柱114設置於至少一邊緣表面106與微電子組件100的對應邊緣之間。微電子組件100之微電子元件102與金屬柱114可參考第1-5圖。
每一金屬柱114包含側壁116，側壁116將第一與第二端部表面118、120在第一方向110中彼此分隔。金屬柱114的側壁116可具有小於大約1微米的均方根(rms,root mean square)表面粗糙度。使用本文所揭示以及下面所討論的方法，可達成側壁116的此種低表面粗糙度。在一實施例中，金屬柱可大於大約99%的圓柱形。例如，金屬柱的低表面粗糙度、形狀、與其他特徵可藉由本文所討論的方法來形成。金屬柱114可包含一或更多種金屬，其選自銅(Cu)、鎳(Ni)、金(Au)、或其合金。微電子組件100包含封裝部122(Encapsulation)，封裝部122之第二厚度124係延伸於封裝部122的第一與第二表面123、125之間的第一方向110中。封裝部122至少接觸於微電子元件102之邊緣表面106與複數金屬柱114的側壁116。在一實施例中，例如 第1-1圖，封裝部122的第二厚度124係大約等於微電子元件102的第一厚度108。封裝部122可藉由模製封裝材料(例如，陶瓷複合物)而形成。在具體的範例中，封裝部122可為微粒狀物質合成物層，其包含聚合體基質與裝載在聚合體基質內的微粒狀物質。此種合成物層可例如藉由沉積未固化的聚合體材料而形成，未固化的聚合體材料具有微粒狀物質裝載材料在其中，微粒狀物質裝載材料選擇性地為具有低熱膨脹係數("CTE",coefficient of thermal expansion)的介電質材料。
金屬柱114至少部分延伸通過封裝部122。在一實施例中，例如第1-1圖，金屬柱114之延伸係完全通過封裝部122的第二厚度124，並從微電子組件100的第一側部127延伸至第二側部129。第一與第二側部127、129可分別相鄰於封裝部122的第一與第二表面123、125。
微電子組件100之端子131在微電子組件的第一側部127處。在一些實施例中，微電子組件之第二端子133在微電子組件的第二側部129處。端子131、133可以用表面的方式將微電子組件100電耦接於其他元件，例如另一微電子組件、中介層、印刷電路板(PCB)、或其他此種元件，該元件分別相鄰於微電子組件的第一與第二側部127、129。在一範例實施例中，微電子組件可包含於垂直堆疊的結構中，如同第1-7圖。例如，相鄰的另一微電子組件可堆疊於並且覆蓋該微電子組件之第二側部129，或堆疊於第一側部127處，以覆蓋電路板135或另一元件，例如中介層。許多垂直堆疊的配置與元件都可能，且不限於第1-7圖所示的範例實施例。
微電子組件100在微電子組件100的第一側部127處可包含絕緣層136。在一範例實施例中，絕緣層包含介電質材料。絕緣層136覆蓋微 電子元件102的前表面104與金屬柱114的第一端部表面118。連接元件128之延伸可從第一端部表面118通過絕緣層136的厚度，以電連接於第一端部表面118與接點112。連接元件128至少可連接一些第一端部表面118與對應的端子131。如同第1-1至1-4圖所示，端子131可通過再分布結構126耦接於第一連接元件。但是，在一些實施例中，端子131可覆蓋絕緣層136。在其他實施例中，端子131可形成於絕緣層136中，或者替代地形成於覆蓋絕緣層136的另一絕緣層中。絕緣層136可包含一或更多個聚合體材料，例如聚酰亞胺、聚酰胺、或可光成像的材料，其在一些實例中可為苯並環丁烷(BCB,benzocyclobutane)。
微電子組件100在微電子組件100的第二側部129處可包含第二絕緣層140。第二絕緣層140可包含絕緣層136所述的任何實施例及/或變換例。第二連接元件132之延伸，可通過第二絕緣層140的厚度，以電連接於第二端部表面120。第二連接元件132可連接至少一些第二端部表面120與對應的第二端子133。第二連接元件可包含連接元件128所述的任何實施例及/或變換例。
至少一些連接元件128、132之橫剖面係分別小於第一與第二端部表面118、120處金屬柱114的橫剖面。在一些實例中，連接元件128、132與金屬柱114的對準可用較小橫剖面改良。改良的對準可產生改良的繞線。連接元件128、132可具有側壁，該側壁之均方根(rms)表面粗糙度係大於金屬柱114的側壁116的均方根(rms)表面粗糙度。在一實施例中，連接元件128、132的側壁之rms表面粗糙度係大於大約1微米。連接元件128、132可由任何合適的材料形成，例如上面針對金屬柱114所討論的那些材料，或 者其他材料。金屬柱114與對應的連接元件128、132的成分可相同或不同。
微電子組件100包含導電再分布結構126，其可沉積於絕緣層136、140上面。例如，在一些實施例中，例如第1-1至1-3圖所示，再分布結構可沉積於二絕緣層136、140上。替代地，在第1-4圖所示的範例實施例中，再分布結構126亦可沉積於絕緣層136上，但是沒有再分布結構及/或第二絕緣層140沉積於第二端部表面120上。在此種實施例中，第二端部表面120可充當做第二端子131。在一些實施例中，再分布結構126係整合於絕緣層136或140，以及連接元件128或132。
當再分布結構126在上面時，端子131的一部分與金屬柱114下方的邊緣表面連接，當再分布結構126在下面時，第二端子133的一部分與金屬柱114上方的邊緣表面連接。在範例實施例中，如第1-6圖的俯視圖所示，再分布結構的線路137延伸於橫越第一方向110的第二方向中，超出金屬柱114的邊緣表面。至少一端子131可通過線路137而電耦接第一端部表面118。相似的，至少一第二端子133可通過線路137而電耦接第二端部表面120。在其他實施例中，如第1-1至1-4圖所示，在微電子組件的第一側部127處，至少一些線路137可電耦接微電子元件102的接點112至金屬柱114。在其他實施例中，如第1-6圖所示，一或二端子113、133可為整合的結構，其線路的態樣係延伸超出金屬柱114的邊緣表面，如第1-6圖的右邊所示。
第1-2圖為本案較佳實施例之微電子組件150的側部示意圖。微電子組件150可包含如同微電子組件100所述的任何實施例及/或變換例，除了其他有提及的部分之外。在本發明的一實施例中，如同微電子組件150中所示，封裝部122的第二厚度124可超過微電子元件102的第一厚度 108。
第1-3圖為本案較佳實施例之微電子組件160的側部示意圖。微電子組件160可包含微電子組件100所述的任何實施例及/或變換例，除了其他有提及的部分之外。在本發明的一實施例中，如同微電子組件160所示，金屬柱114部分延伸於第一方向110中、通過第二厚度124。在一實施例中，金屬柱之延伸約為第二厚度124的至少大約50%。在一實施例中，第二連接元件132可從金屬柱114的第二端部表面120延伸於封裝部122的第二厚度124的第一方向中，如同第1-3圖所示。雖然圖示之橫剖面係小於在第二端部表面120處的金屬柱114的橫剖面，但是在一些實施例中，第二連接元件132的橫剖面亦可大於金屬柱114的橫剖面。微電子組件160中，第二介電質層140可選擇省略。
第1-4圖為本案較佳實施例之微電子組件170的側部示意圖。微電子組件170可包含微電子組件100所述的任何實施例及/或變換例，除了其他有提及的部分之外。如第1-4圖所示，微電子組件170不包含沉積於第二端部表面120上的再分布結構126。
第1-8圖為本案較佳實施例之微電子組件180的側部示意圖。微電子組件180可包含微電子組件100所述的任何實施例及/或變換例，除了其他有提及的部分之外。如同第1-8圖所示，微電子組件180包含第二微電子元件182。在一些實施例中，第二微電子元件182至少部分覆蓋微電子元件102。在一範例中，如同第1-8圖所示，第二微電子元件完全覆蓋微電子元件102。第二微電子元件182可包含第一表面181與圍繞第一表面181的邊緣表面183。第二微電子元件182之一厚度係延伸於第一方向，從第二微電 子元件182的第一表面181朝向第二微電子元件182的第二表面184。微電子元件182之接點185在第二表面184處。至少一些金屬柱114可電耦接於第二微電子元件182的接點185。在一範例中，接點185可通過第二連接元件132與線路137而電耦接於金屬柱114。
第1-9圖為本案較佳實施例之微電子組件190的側部示意圖。微電子組件190可包含微電子組件160所述的任何實施例及/或變換例，除了其他有提及的部分之外。如同第1-9圖所示，微電子組件190包含第二微電子元件182，封裝部較厚。
第1-10圖為本案較佳實施例之微電子組件192的側部示意圖。微電子組件192可包含微電子組件100所述的任何實施例及/或變換例，除了其他有提及的部分之外。如同第1-10圖所示，再分布層126可選擇不在於第二絕緣層140之上。第二微電子元件193覆蓋第二絕緣層140。第二微電子元件193具有第一表面194與圍繞第一表面194的邊緣表面195。第二微電子元件193之厚度係延伸於第一方向，並且始於第一表面194。微電子元件193之接點196在第一表面194處。在一範例中，接點196可直接耦接於第二連接元件132。在另一範例中，其中再分布層126設置於絕緣層140與第二微電子元件193之間，接點196可通過再分布層126而電耦接於至少一些第二連接元件132。封裝部122可覆蓋到第二微電子元件193的邊緣表面195。另外，封裝部122亦可圍繞第二微電子元件193。
第2圖為本案較佳實施例之微電子組件的製造方法200的流程圖。方法200係根據第3-1至3-6圖、第4-1至4-6圖、與第5-1至5-6圖的微電子組件100、160、與150的階段而敘述。但是，方法200可應用至本發明的 其他實施例，或本發明的範圍內的其他微電子組件。
第3-1圖所示結構300，其具有微電子元件102與金屬柱114。如同第3-1圖所示，結構300之微電子元件102與金屬柱114係藉由導電層302分別支撐於前表面104與第一端部表面118處。在步驟202，結構300可藉由連接微電子元件102的前表面104與導電層302的第一表面304的第一部分303而形成。金屬柱114設置於第一表面304與導電層302的邊緣。
在附接微電子元件102至導電層302之前，金屬柱114可預先形成於導電層302的第一表面304上。例如，將光阻覆蓋於導電層302，再將金屬電鍍於圖案化光阻中的開孔中，以形成金屬柱114。用於形成金屬柱的其他合適方法也可使用，包含例如，濺鍍、燒結、其他物理或化學增進式沉積處理。
在步驟204中，可形成封裝部122。封裝部122可藉由模製而形成。在模製封裝部122之後，可選擇使封裝部122變薄，以達到所欲的第二厚度124。如第3-2圖所示，封裝部122可接觸微電子元件102的邊緣表面106與金屬柱114的側壁116。在微電子組件100的實施例中，微電子元件102的第一厚度108與封裝部122的第二厚度124相同。
在形成封裝部122之後，可移除導電層302，以曝露出金屬柱114的第一端部表面118。移除導電層302之後的結構300如第3-3圖所示。導電層302可藉由任何合適的處理來移除，例如蝕刻、拋光、或其組合。
在步驟206中，絕緣層136與連接元件128可形成於微電子組件100的第一側部127處，如第3-3至3-4圖所示。絕緣層136可覆蓋微電子元件102的前表面與金屬柱114的第一端部表面118。接著第3-5圖形成開孔 306。開孔306延伸於絕緣層136厚度的第一方向中，並且曝露出金屬柱114的第一端部表面118的至少部分以及微電子元件102的接點112。開孔306可藉由光微影術來形成，之後藉由移除絕緣層136的材料，以曝露出第一端部表面118與接點112的部分。另外，亦可藉由雷射或機械鑽孔形成開孔306。開孔306有粗糙的側壁表面，其可導致連接元件128具有大於大約1微米的rms表面粗糙度。藉由電鍍、物理氣相沉積(PVD)、化學氣相沉積(CVD)或類似製程，連接元件128可形成於開孔306中。
同理，第二絕緣層140可覆蓋微電子元件102與金屬柱114的第二端部表面120。接著形成開孔308，開孔308延伸於第二絕緣層140厚度的第一方向110中，並且曝露出金屬柱114的部分第二端部表面120。開孔308之形成可藉由任何實施例及/或變換例及/或製造方法。藉由電鍍、物理氣相沉積(PVD)、化學氣相沉積(CVD)或其他類似製程，第二連接元件132可形成於開孔308中。
在步驟208，沉積再分布結構126。如第3-6圖所示，再分布結構126覆蓋絕緣層136、140。再分布結構126可包含一或更多個絕緣層142、144分別覆蓋絕緣層136、140。一或更多個絕緣層142、144可圖案化，以曝露出連接元件128、132的部分表面。端子131、133可電耦接於連接元件128、132的表面。端子131、133可藉由任何合適的方法來形成，例如電鍍或類似製程。
雖然上述為連續製造微電子組件100的第一側部130與第二側部134，再分布結構126可藉由任何合適的處理步驟順序來製造。例如，可形成絕緣層136、140，之後形成開孔306、308，之後形成第一與第二連 接元件128、132，或者其他的處理步驟順序。
第4-1至4-6圖為本案較佳實施例之製造微電子組件160方法的各個階段。製造微電子組件160的一些態樣係類似於上面相關於微電子組件100的製造所討論者。
第4-1圖為結構400，其具有微電子元件102與金屬柱114。如第4-1圖所示，結構400之微電子元件102與金屬柱114係藉由導電層402而分別支撐於前表面104與第一端部表面118處。在步驟202，結構400可藉由附接微電子元件102的前表面104至導電層402的第一表面404的第一部分403而形成。金屬柱114設置於第一表面404的第一部分403與導電層402的對應邊緣之間。
在附接微電子元件102至導電層402之前，金屬柱114可預先形成於導電層402的第一表面404上。在導電層402上預先形成金屬柱114時，可包含預先形成導電層402上的金屬柱114的任何實施例及/或變換例及/或製造方法。
在步驟204，可形成封裝部122。封裝部122可藉由模製而形成。在模製封裝部122之後，可選擇使封裝部122變薄，以達到第二厚度124。如第4-2圖所示，封裝部122可接觸於微電子元件102的邊緣表面106與金屬柱114的側壁116。在微電子組件160的實施例中，金屬柱114延伸於第二厚度124的第一方向110，其延伸之長度為第二厚度124的大約50%。
在形成封裝部122之後，可移除導電層402，以曝露出金屬柱114的第一端部表面118。移除導電層402之後的結構400如第4-3圖。導電層402可藉由任何合適的處理來移除，例如蝕刻、拋光、或其組合。
在步驟206，在本發明的一些態樣中，絕緣層136與連接元件128可形成於微電子組件160的第一側部127處，如第4-5至4-6圖所示。絕緣層136與連接元件128的形成方法，可包含微電子組件100中的那些元件的製造所述的任何實施例及/或變換例及/或製造方法。
第二絕緣層140可選擇覆蓋微電子元件102與金屬柱114的第二端部表面120。接著，形成開孔406，開孔406延伸於封裝部122以及選擇性的第二絕緣層140(當存在時)的厚度的第一方向110中。開孔406曝露出金屬柱114的第二端部表面120的至少部分。開孔406可藉由光微影術來形成，之後藉由移除封裝部122以及選擇性的第二絕緣層140(當存在時)的材料，以曝露出金屬柱114的第二端部表面120的部分。當然，藉由雷射或機械鑽孔，亦可形成開孔406。開孔406之粗糙的側壁表面，其可導致第二連接元件132具有大於大約1微米的rms表面粗糙度。藉由電鍍、物理氣相沉積(PVD)、化學氣相沉積(CVD)或類似者，第二連接元件132可形成於開孔406中。
在步驟208，沉積再分布結構126。如第4-6圖所示，再分布結構126覆蓋絕緣層136、140。再分布結構126之形成方法，可包含微電子組件100中的那些元件的製造所述的任何實施例及/或變換例及/或製造方法。
雖然上述為微電子組件160的第一側部127與第二側部129上的連續製造步驟，再分布結構126亦可藉由任何合適的處理步驟順序來製造。
第5-1至5-6圖為本案較佳實施例之製造微電子組件150方法 中的各個階段。製造微電子組件150的一些態樣係類似於上面相關於微電子組件100與150的製造所討論的那些。
第5-1圖所示之微電子元件102，其藉由載體500支撐於前表面104上。結構502(如第5-2圖所示)可包含：藉由載體500而支撐於前表面104處的微電子元件102，以及藉由導電層504而支撐於第二端部表面120處的金屬柱114。在步驟202，結構502可藉由將金屬柱114的第一端部表面118附接於載體500而形成，微電子元件102位於導電層504的第一表面508的第一部分506。金屬柱114可設置於第一表面508的第一部分506與導電層504的對應邊緣之間，且從第一表面508延伸。
在附接至載體500之前，金屬柱114可預先形成於導電層504的第一表面508上。在導電層504上預先形成金屬柱114的方法，可包含在導電層302或402上預先形成金屬柱114所述的任何實施例及/或變換例及/或製造方法。
在步驟204，可形成封裝部122。封裝部122可藉由模製而形成。如第5-2至5-3圖所示，封裝部122的第二厚度124可界定於導電層504與載體500之間。雖然第5-3圖之第一厚度108係小於封裝部122的第二厚度124，但是在本發明的一些態樣中，微電子元件102之第一厚度108亦可等於封裝部122的第二厚度124。
在形成封裝部122之後，可移除載體500與導電層504，以分別曝露出金屬柱114的第一與第二端部表面118、120。移除導電層504與載體500之後的結構400係在第5-4圖中。導電層504與載體500可藉由任何合適的處理來移除，例如蝕刻、拋光、或其組合。
在步驟206與208中，可形成絕緣層136、140、連接元件128、130、與再分布結構126，如第5-4圖至第5-6圖所示。形成絕緣層136、140、連接元件128、130、與再分布結構126的方法，包含上述關於形成微電子組件100的再分布結構所述的任何實施例及/或變換例及/或製造方法。
雖然本發明在此已經參照特定實施例來敘述，可瞭解到，這些實施例僅是本發明的應用與原理的例示。因此，可瞭解到，可對例示的實施例做出各種修改，且可設想出其他配置，而未偏離所附申請專利範圍所界定之本發明的範圍與精神。
例如，第6-1至6-5圖為本案較佳實施例之製造微電子組件的各個階段。例如，第6-1至6-5圖中的製造階段可用於替代第3-1至3-2圖或第4-1至4-2圖中的那些製造階段。如第6-1圖所示，可提供基板600。基板600之厚度延伸於第一方向，從第一表面602至第二表面604。基板600之剛性元件606延伸於第一方向中，且位於基板600的第二表面604處。如第6-2圖所示，導電材料可沉積於第二表面604與剛性元件606的表面上，以形成金屬柱114與導電層。微電子元件102可附接至導電層，且之後可形成封裝部122，如第6-3圖所示。基板600可之後移除，以曝露出金屬柱114中的開孔608。金屬柱114中的開孔延伸於第一方向中，從微電子組件的第一側部127開始延伸。開孔608可充填材料，例如額外的導電材料，如第6-5圖所示。
100‧‧‧微電子組件
102‧‧‧微電子元件
104‧‧‧前表面
106‧‧‧邊緣表面
108‧‧‧第一厚度
110‧‧‧第一方向
112‧‧‧接點
114‧‧‧金屬柱
116‧‧‧側壁
118‧‧‧第一端部表面
120‧‧‧第二端部表面
122‧‧‧封裝部
124‧‧‧第二厚度
123‧‧‧第一表面
125‧‧‧第二表面
127‧‧‧第一側部
129‧‧‧第二側部
136‧‧‧絕緣層
131‧‧‧端子
126‧‧‧再分布結構
140‧‧‧第二絕緣層
137‧‧‧線路
133‧‧‧第二端子
132‧‧‧第二連接元件
142、144‧‧‧絕緣層

Claims (4)

  1. 一種微電子組件，包含：一微電子元件，具一前表面，圍繞該前表面的邊緣表面，及在該前表面處的接點，該微電子元件之一第一厚度係從該前表面的第一方向延伸而出；實質上剛性的金屬柱，延伸於該第一方向，該金屬柱設置於該邊緣表面與該微電子組件的一對應邊緣之間，每一金屬柱具有一側壁，該側壁將該金屬柱的第一與第二端部表面在該第一方向中彼此分隔，其中該金屬柱的該側壁之一均方根(rms)表面粗糙度小於大約1微米；一封裝部，其一第二厚度係延伸於該封裝部第一與第二表面之間的該第一方向中，該封裝部接觸該微電子元件的至少邊緣表面與該金屬柱的該側壁，其中該金屬柱至少部分延伸通過該第二厚度，且該封裝部使相鄰的金屬柱彼此電性絕緣；該微電子組件之第一與第二側部，係分別相鄰於該封裝部之第一與第二表面，且該微電子組件之端子係位於該第一側部；一絕緣層，覆蓋該第一側部之封裝部之第一表面，並且具有一厚度從該封裝部之第一表面延伸而出；連接元件，係從該金屬柱之第一端部表面延伸而出，並且通過該絕緣層之厚度，該連接元件電連接至少一些該第一端部表面與對應的端子，其中至少一些連接元件的橫剖面小於該金屬柱的橫剖面；以及一導電再分布結構，沉積於該第一絕緣層上，其中該再分布結構通過至 少一些該連接元件而電連接該端子與該金屬柱之對應第一端部表面；其中至少一些該金屬柱係電耦接於該微電子元件的接點。
  2. 如申請專利範圍第1項之微電子組件，其中該金屬柱從該封裝部之第一表面延伸至該封裝部的第二表面。
  3. 如申請專利範圍第1項之微電子組件，其中該第一厚度係小於或等於該第二厚度。
  4. 如申請專利範圍第1項之微電子組件，另包含：第二連接元件，該封裝部之第二厚度之第一方向之延伸，係從該金屬柱之第二端部表面至該封裝部之第二表面。
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US9167710B2 (en) 2015-10-20
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