KR100998859B1 - 반도체 장치 - Google Patents
반도체 장치 Download PDFInfo
- Publication number
- KR100998859B1 KR100998859B1 KR1020090055777A KR20090055777A KR100998859B1 KR 100998859 B1 KR100998859 B1 KR 100998859B1 KR 1020090055777 A KR1020090055777 A KR 1020090055777A KR 20090055777 A KR20090055777 A KR 20090055777A KR 100998859 B1 KR100998859 B1 KR 100998859B1
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- South Korea
- Prior art keywords
- opening
- film
- electrode
- insulating film
- organic resin
- Prior art date
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Images
Classifications
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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Abstract
Description
Claims (34)
- 반도체 장치에 있어서:게이트 전극;상기 게이트 전극 위의 게이트 절연막;상기 게이트 전극과 채널 영역 사이에 상기 게이트 절연막을 갖는 상기 게이트 전극 위의 상기 채널 영역;상기 채널 영역을 사이에 갖는 소스 영역 및 드레인 영역;상기 소스 영역 및 상기 드레인 영역 중 하나 상의 전극;상기 전극 위의 실리콘 질화물을 포함하는 무기 절연막으로서, 상기 전극의 일부분을 노출시키는 제 1 개구를 포함하는, 상기 무기 절연막;상기 무기 절연막 위의 유기 수지막으로서, 상기 제 1 개구 주변의 상기 무기 절연막의 일부분을 노출시키도록 상기 제 1 개구와 겹쳐지는 제 2 개구를 포함하는, 상기 유기 수지막; 및상기 유기 수지막 위의 화소 전극을 포함하고,상기 유기 수지막은 상기 제 2 개구 내에 볼록한 내벽 표면을 갖고,상기 화소 전극은 상기 제 1 개구 및 상기 제 2 개구를 통해 상기 전극과 접촉하는, 반도체 장치.
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- 반도체 장치에 있어서:게이트 전극;상기 게이트 전극 위의 게이트 절연막;상기 게이트 전극과 채널 영역 사이에 상기 게이트 절연막을 갖는 상기 게이트 전극 위의 상기 채널 영역;상기 채널 영역을 사이에 갖는 소스 영역 및 드레인 영역;상기 소스 영역 및 상기 드레인 영역 중 하나 상의 전극;상기 전극 위의 실리콘 질화물을 포함하는 무기 절연막으로서, 상기 전극의 일부분을 노출시키는 제 1 개구를 포함하는, 상기 무기 절연막;상기 무기 절연막 위의 유기 수지막으로서, 제 2 개구의 바닥에서 상기 제 2 개구의 에지는 상기 제 1 개구의 상부에서 상기 제 1 개구의 에지를 둘러싸는 방식으로 상기 제 1 개구와 겹쳐지는 상기 제 2 개구를 포함하는, 상기 유기 수지막; 및상기 유기 수지막 위의 화소 전극을 포함하고,상기 유기 수지막은 상기 제 2 개구 내에 볼록한 내벽 표면을 갖고,상기 화소 전극은 상기 제 1 개구 및 상기 제 2 개구를 통해 상기 전극과 접촉하는, 반도체 장치.
- 반도체 장치에 있어서:게이트 전극;상기 게이트 전극 위의 게이트 절연막;상기 게이트 전극과 채널 영역 사이에 상기 게이트 절연막을 갖는 상기 게이트 전극 위의 상기 채널 영역;상기 채널 영역을 사이에 갖는 소스 영역 및 드레인 영역;상기 소스 영역 및 상기 드레인 영역 중 하나에 전기적으로 접속된 전극;상기 전극 위의 실리콘 질화물을 포함하는 무기 절연막으로서, 상기 전극의 일부분을 노출시키는 제 1 개구를 포함하는, 상기 무기 절연막;상기 무기 절연막 위의 유기 수지막으로서, 제 2 개구의 바닥에서 상기 제 2 개구의 에지는 상기 제 1 개구의 상부에서 상기 제 1 개구의 에지를 둘러싸는 방식으로 상기 제 1 개구와 겹쳐지는 상기 제 2 개구를 포함하는, 상기 유기 수지막; 및상기 유기 수지막 위의 화소 전극을 포함하고,상기 유기 수지막은 상기 제 2 개구 내에 볼록한 내벽 표면을 갖고,상기 화소 전극은 상기 제 1 개구 및 상기 제 2 개구를 통해 상기 전극과 접촉하는, 반도체 장치.
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- 반도체 장치에 있어서:게이트 전극;상기 게이트 전극 위의 게이트 절연막;상기 게이트 전극과 채널 영역 사이에 상기 게이트 절연막을 갖는 상기 게이트 전극 위의 상기 채널 영역;상기 채널 영역을 사이에 갖는 소스 영역 및 드레인 영역;상기 소스 영역 및 상기 드레인 영역 중 하나 상의 전극;상기 전극 위의 실리콘 질화물을 포함하는 무기 절연막으로서, 상기 전극의 일부분을 노출시키는 제 1 개구를 포함하는, 상기 무기 절연막;상기 무기 절연막 위의 유기 수지막으로서, 제 2 개구를 포함하는, 상기 유기 수지막; 및상기 유기 수지막 위의 화소 전극을 포함하고,상기 무기 절연막의 상부 표면의 일부분은, 상기 무기 절연막의 상부 표면의 상기 일부분이 상기 제 2 개구의 바닥에서 상기 유기 수지막으로 덮여있지 않도록 상기 제 2 개구의 내부에 있고,상기 유기 수지막은 상기 제 2 개구 내에 볼록한 내벽 표면을 갖고,상기 화소 전극은 상기 제 1 개구 및 상기 제 2 개구를 통해 상기 전극과 접촉하는, 반도체 장치.
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- 제 1 항, 제 7 항, 제 8 항 또는 제 13 항 중 어느 한 항에 있어서,상기 볼록한 내벽 표면의 곡률 반경은 3 ㎛ 내지 30 ㎛인, 반도체 장치.
- 제 1 항, 제 7 항, 제 8 항 또는 제 13 항 중 어느 한 항에 있어서,상기 볼록한 내벽 표면의 곡률 반경은 연속적으로 변하는, 반도체 장치.
- 반도체 장치에 있어서:적어도 하나의 채널 영역, 소스 영역 및 드레인 영역을 포함하는 하부 게이트 타입 박막 트랜지스터;상기 소스 영역 및 상기 드레인 영역 중 하나 상의 전극;상기 전극 위의 실리콘 질화물을 포함하는 무기 절연막으로서, 상기 전극의 일부분을 노출시키는 제 1 개구를 포함하는, 상기 무기 절연막;상기 무기 절연막 위의 유기 수지막으로서, 상기 제 1 개구 주변의 상기 무기 절연막의 일부분을 노출시키도록 상기 제 1 개구와 겹쳐지는 제 2 개구를 포함하는, 상기 유기 수지막; 및상기 유기 수지막 위의 화소 전극을 포함하고,상기 유기 수지막은 상기 제 2 개구 내에 곡선 형태의 내벽 표면을 갖고,상기 화소 전극은 상기 제 1 개구 및 상기 제 2 개구를 통해 상기 전극과 접촉하는, 반도체 장치.
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- 반도체 장치에 있어서:적어도 하나의 채널 영역, 소스 영역 및 드레인 영역을 포함하는 하부 게이트 타입 박막 트랜지스터;상기 소스 영역 및 상기 드레인 영역 중 하나 상의 전극;상기 전극 위의 실리콘 질화물을 포함하는 무기 절연막으로서, 상기 전극의 일부분을 노출시키는 제 1 개구를 포함하는, 상기 무기 절연막;상기 무기 절연막 위의 유기 수지막으로서, 제 2 개구의 바닥에서 상기 제 2 개구의 에지는 상기 제 1 개구의 상부에서 상기 제 1 개구의 에지를 둘러싸는 방식으로 상기 제 1 개구와 겹쳐지는 상기 제 2 개구를 포함하는, 상기 유기 수지막; 및상기 유기 수지막 위의 화소 전극을 포함하고,상기 유기 수지막은 상기 제 2 개구 내에 곡선 형태의 내벽 표면을 갖고,상기 화소 전극은 상기 제 1 개구 및 상기 제 2 개구를 통해 상기 전극과 접촉하는, 반도체 장치.
- 제 1 항, 제 7 항, 제 8 항, 제 13 항, 제 20 항 또는 제 27 항 중 어느 한 항에 있어서,상기 무기 절연막은 적층 구조를 갖는, 반도체 장치.
- 제 1 항, 제 7 항, 제 8 항, 제 13 항, 제 20 항 또는 제 27 항 중 어느 한 항에 있어서,상기 화소 전극은 가시광에 대해 투명한 산화물 도전막을 포함하는, 반도체 장치.
- 제 1 항, 제 7 항, 제 8 항, 제 13 항, 제 20 항 또는 제 27 항 중 어느 한 항에 있어서,상기 소스 영역, 상기 드레인 영역, 및 상기 채널 영역은 하나의 반도체 막 내에 형성된, 반도체 장치.
- 제 1 항, 제 7 항, 제 8 항, 제 13 항, 제 20 항 또는 제 27 항 중 어느 한 항에 있어서,상기 유기 수지막과 상기 화소 전극 사이에 제 2 무기 절연막을 더 포함하는, 반도체 장치.
- 제 20 항 또는 제 27 항에 있어서,상기 곡선 형태의 내벽 표면의 곡률 반경은 3 ㎛ 내지 30 ㎛인, 반도체 장치.
- 제 20 항 또는 제 27 항에 있어서,상기 곡선 형태의 내벽 표면의 곡률 반경은 연속적으로 변하는, 반도체 장치.
- 제 1 항, 제 7 항, 제 8 항, 제 13 항, 제 20 항 또는 제 27 항 중 어느 한 항에 있어서,상기 전극은 금속을 포함하는, 반도체 장치.
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