JP2015201649A - 印刷可能半導体素子を製造して組み立てるための方法及びデバイス - Google Patents
印刷可能半導体素子を製造して組み立てるための方法及びデバイス Download PDFInfo
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- JP2015201649A JP2015201649A JP2015095093A JP2015095093A JP2015201649A JP 2015201649 A JP2015201649 A JP 2015201649A JP 2015095093 A JP2015095093 A JP 2015095093A JP 2015095093 A JP2015095093 A JP 2015095093A JP 2015201649 A JP2015201649 A JP 2015201649A
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Abstract
【解決手段】印刷可能半導体素子150は高分子転写デバイス175又は複合高分子転写デバイスの接触面170とコンフォーマル接触され、印刷可能半導体素子が接触面上に接触される。コンフォーマブルな転写デバイスの接触面上に堆積された印刷可能半導体素子は、接触面と基板160の受け面との間でコンフォーマルな接触を成す態様で基板の受け面と接触される。接触面は基板の受け面と接触される印刷半導体素子から分離され受け面上に組み立てられる。
【選択図】図1
Description
ここで、Eはヤング率であり、L0は平衡長、ΔLは加えられた応力下での長さ変化、Fは加えられた力、Aは力が加えられる面積である。また、ヤング率は、以下の方程式によりラメ定数に関して表わされてもよい。
ここで、λ及びμはラメ定数である。高いヤング率(すなわち「高弾性率」)及び低いヤング率(すなわち「低弾性率」)は、所定の材料、層又はデバイスにおけるヤング率の大きさの相対的な記述子である。本発明において、高いヤング率は、低いヤング率よりも大きく、好ましくは一部の用途において約10倍大きく、より好ましくは他の用途において約100倍大きく、更に好ましくは更に他の用途において約1000倍大きい。
方向に沿って向けられたラインの形態でSiO2のエッチマスクを規定することにより、体積比率がH3PO4(85重量%):H2O2(30重量%):H2O=1:13:12のH3PO4及びH2O2の水溶液を使用する異方性エッチングのための構造が形成される(図19のステップi)。このエッチング成分は、この形態で適用されると、高い異方性を示し、これにより、SiO2マスクストライプ下で厳格に規定される逆メサ形状のGaAsのプロファイルが形成される。十分なエッチング時間にわたって、各逆メサの2つの側壁が交差し、それにより、三角形の断面を有するワイヤが形成される。この三角形の断面は、図19のパネルA(左側)の上側の挿入画において例示されている。
と称する)を正確に測定するために前述した手順を使用してPDMS表面に対して転写された。図20Fは、エッチング時に本方法により形成されたワイヤの上端面の平均幅
の依存性を示すプロットを与えている。このプロットは、本発明のこの実施形態を使用すると最小で50nmまでの幅を有するGaAsワイヤを得ることができることを示している。幅とエッチング時間との間の線形な関係は、H3PO4−H2O2−H2O溶液中のGaAsのエッチング動力学に関する先の研究と一致する。すなわち、エッチング速度は、H2O2とH3PO4との間のモル比(nH2O2/nH3PO4)が2.3よりも大きく且つH2Oのモル分率(rH2O)が0.9以下の時(本発明者らの実験で使用されたエッチャントのnH2O2/nH3PO4及びrH2Oがそれぞれ7.8及び0.9である時)にエッチング時間に比例した。統計的な結果によれば、ワイヤの幅の分布(ワイヤの長さに沿って平均することにより決定される)は、〜50nmの幅を有するワイヤに関しては<9%であった。これは、〜16.8nmの平均幅を与えると報告された「ボトムアップ」ナノワイヤの1つのタイプにおける>14%変動よりも若干狭い。
もエッチング時間に大きく依存した。比率が100%を下回ったときに連続するGaAsナノワイヤを形成することができる。図20Fに示される曲線は、本発明のこの実施形態の適用から得られるナノワイヤの幅を〜40nmまで減らすことができることを示している。異なる平均幅を有するナノワイヤは、個々のワイヤに沿う同じ幅変化(すなわち、〜40nm)を実質的に示し、これは、個々のSiO2マスクラインに沿う幅変化(すなわち、〜36nm)に近かった。この比較により、ワイヤ側壁の粗さがエッチング時間に無関係に主にSiO2マスクストリップの粗いエッジによって生じることが確かめられる。したがって、マスクストライプの粗さを減少させるリソグラフィ処理を使用すると、ワイヤのエッジの粗さが減少する。この実施例で説明した転写印刷プロセスが、電気的な接続及び最終的な基板(すなわち、図19のPET)上にデバイスを製造するためにワイヤの本来の超平坦なエッチングされていない上端面を露出させることに留意することは重要である。
方向に沿って向けられた100μmの長さ及び2μmの幅を有していた。図21Aは、SiO2マスク層を介して平坦なPDMSスタンプに結合されたGaAsワイヤ配列から得られる走査型電子顕微鏡写真画像であり、ワイヤの順序が維持されていることを示している。図21Aの挿入画は、3つのワイヤの端部を比較的高い倍率で示しており、ワイヤの端部における破損を明確に表わしている。図21Bに示されるように、PDMSスタンプを硬化したPUから剥離すると、SiO2マスクストライプを有する滑らかな面(PDMSと同じ程度に滑らか)が現れて残る。図21Cに示されるように、BOEを用いてSiO2層をエッチング除去すると、GaAsワイヤの本来の上端面が露出される。図21Dは、GaAsワイヤが組み込まれたPU/PET基板から収集された光学画像であり、図19に示される方法を使用してPU/PET基板上に大面積のワイヤ配列を定期的に印刷できることを示している。他のパターン(例えば、長さが異なるワイヤから成るパッチ)を有するGaAsワイヤ配列をPU/PET基板に対して転写することもできる。
方向に沿うSiO2マスクラインを有する(100)InPウエハをエッチングすることにより、断面が三角形のInPワイヤが製造される。図22A〜Cは、PMDS基板及びPU/PET基板上のInPワイヤ配列の走査型電子顕微鏡写真画像を示している。これらのワイヤは、長さが50μmで且つ幅が2μmのSiO2ラインでパターニングされたInPウエハから製造された。図示のワイヤは、〜35μm及び〜1.7μmの長さ及び幅をそれぞれ有している。Br2のメタノール溶液中でのInPのエッチング作用は、ワイヤ端部の形状及び横方向アンダーカットに関して、H3PO4−H2O2の水溶液中でのGaAsのそれとは大きく異なっている。例えば、エッチングプロセスは、GaAsワイヤの製造において使用されるエッチマスクと同様のエッチマスクを用いた場合であっても、InPワイヤの全ての端部をマザーウエハから切り離した(図21)。また、InPにおけるアンダーカットの程度はGaAsにおけるそれよりも小さく、これは、エッチング時間を制御することによってではなく狭いSiO2ストライプを使用することにより幅が小さい(500nm未満)InPワイヤを更に簡単に形成できることを示している。
Engineering R”(Jan Haisma and G.A.C.M.Spierings,37 1〜60頁(2002))を参照)により達成されてもよい。場合によって、P−Nドープ層間に高品質な界面を有するP−N接合を形成することを妨げる可能性がある外側酸化物層等のP及びNドープ半導体層上の任意の他の絶縁層を剥離するため、P及びNドープ半導体層は、印刷前、印刷中、印刷後に処理される。場合によって、幾つかの実施形態では、接合されるドープ半導体表面上に存在する任意の水が除去される。第1及び第2のドープ半導体素子の組み立ては、本発明のソリューション印刷方法又は乾式転写コンタクト印刷方法を使用して行なわれてもよい。場合によって、本発明のこの態様の製造経路は、P−N接合をアニーリングしてPドープ半導体層とNドープ半導体層との間に良好な界面を形成するステップを更に備えていてもよい。アニーリングは、P−N接合部を支持する基板を著しく損傷させない十分低い温度、例えばプラスチック基板上に組み立てられるP−N接合のための約200℃よりも低い温度で行なわれることが好ましい。或いは、P−N接合は、基板とは別個の処理ステップでアニールされてもよい。この実施形態において、アニールされたP−N接合は、冷却できるとともに、その後、ソリューション印刷方法又は乾式転写コンタクト印刷方法により基板上に組み立てることができる。図35Aに示されるように、P及びNドープ半導体層上の接点(すなわち電極)は、リフトオフ処理前における個々のドープ半導体層上への堆積によって、或いは、基板上での組み立て後における印刷可能P−N接合上への堆積によって形成されてもよい。1つの実施形態において、接点は、1つ以上の金属の気相堆積を使用して形成される。
方法I
市販のSOIウエハ(SOITEC,p型、上端Si厚=100nm、抵抗率=13.5−22.5ohm−cm、145nm埋設酸化物層)を使用してμs−Si対象物の製造を行なった。SOIウエハを所望のピーナッツ形状の幾何学的形態(中央領域長さ:200μm、幅:25μm、ピーナッツの直径:50μm)へパターニングするためにフォトリソグラフィ(Shipley 1805レジスト)が使用された。その後、露出されたシリコンを除去するためにドライエッチング(Plasmatherm RIEシステム、SF6流、40accm、50ミリトール、RF電力=100W、45秒)が使用された。その後、HF(49%)溶液中で80秒間にわたって下側のSiO2がエッチングされた。方法Iの3600PDMSスタンプにおいて、特殊PDMS(Dow corning、3600、弾性率=8MPa)とSylgard 184(Dow corning、弾性率=1.8MPa)とが1:1の比率で混合されるとともに標準的なソフトリソグラフィパターニング方法を使用して硬化された。PU薄膜接着層(Norland光接着剤、No.73)を硬化するためにUV源(オゾン活性水銀ランプ、173μW/cm2)が使用された。これらの後者の膜は、バーコーティング処理(Meyer bar,RD specialties)を使用してPET基板(180μm厚、マイラー膜、Southwall technologies)上にコーティングされた。
方法IIにおいて、使用されるピーナッツ形状のサイズは、方法Iで使用されたサイズよりも小さかった(中央領域長さ:10μm、幅:2μm、端部の直径:5μm)。これらの構造を形成するため、RIEエッチング時間が25秒まで減少された点(側壁エッチングを最小限に抑えるため)を除き、同様の製造プロトコルが使用され、また、高濃度(49%)HF溶液中で30秒間にわたって埋設酸化物層がエッチングされた。後者のエッチングステップ後、サンプルは、水槽中で濯がれ、オーブン内において70℃で5分間乾燥された。その後、サンプルの上端に50ÅSiO2層が気相堆積された(Temescal FC−1800 Electron Beam Evaporator)。PDMSの薄い層をPET基板上に結合するため、PUの層は、最初に1000rpmで30秒間にわたってPET上にスピンキャスティングされ、その後、4分間にわたってUVO(173 □W/cm2)に晒された。その後、PDMSの膜は、1000rpmで30秒間にわたってPU上にスピンキャスティングされ、65℃で3時間にわたって熱的に硬化された。
T10×10/OES)から〜3cmの距離を隔ててUVOフォトマスクを通じて3分間にわたって光が照射された。露光後、PDMSスタンプがUVOフォトマスクから剥離され、露光されたPDMS面がピーナッツを支持するSOIウエハと接触された状態に配置された。70℃で30分間にわたって加熱した後、ピンセットを使用してPDMSをゆっくりと剥離し、それにより、照射領域と位置合わせされたμs−Siの部分を剥離した。
コーティングされたPETサンプルのITO側上において66%(v)SU−8 2000シンナーを有するSU−8 5が3000rpmで30秒間にわたって回転された。その後、SU−8エポキシがホットプレート上で〜1分間にわたって60℃で予備硬化された。その後、その表面上にμs−Siを有するPDMSスタンプ(方法I)が、エポキシ層と30秒間にわたって接触され、μs−Siを元のエポキシへ転写するために剥離された。その後、SU−8誘電体は、115℃で2分間にわたって完全に硬化されて、10秒間にわたってUVに晒され、115℃で2分間にわたってポストベークされた。その後、チタン接点(40nm)用の金属が電子ビーム気相堆積によって加えられた。この場合、1%HF溶液を使用したエッチングと併せて、標準的なフォトリソグラフィ法によりソース−ドレイン領域がパターニングされた。
結晶方向に沿って金属ストライプを規定することにより、トップダウン製造方法を使用してマイクロワイヤ(集積オーム接点を有する)を形成することができる。図41の処理ステップiに示されるように、金属ストライプ(3μm幅)の上端にフォトレジストのパターンが形成され、これらのライン間の開口が、隣接する金属ストライプ間に位置する。これらの開口により、エッチャント(H3PO4(85重量%):H2O2(30重量%:H2O=1:13:12の体積比)は、GaAsを異方性エッチングするためにGaAs表面へ拡散することができる。フォトレジストは、オームストライプとGaAsとの間の界面を露光から保護する。異方性エッチングは、逆メサを形成するとともに、GaAsの表面に沿ってアンダーカットし、それにより、断面が三角形で且つ幅が狭いGaAsワイヤがマザー基板から解放されて形成される。アンダーカットは、レジストの形状及びエッチング時間を制御することにより、ミクロン及び/又はナノメートルの長さスケールまで小さい幅を持つGaAsをもたらす。各ワイヤは、結果として得られるMESFETのチャンネル長を規定する間隔で離間される2つのオームストライプを有している。図41の処理ステップiiに示されるように、ポリ(ジメチルシロキサン)(PDMS)の平坦なエラストマースタンプをフォトレジストでコーティングされたGaAsワイヤに対して接触させると、PDMSの疎水性の表面とフォトレジストとの間にファンデルワールス結合が形成される。図41の処理ステップiiiに示されるように、この相互作用により、スタンプがマザーウエハから剥離される際に、全てのGaAsワイヤをウエハからPDMSの表面へと除去することができる。この転写プロセスは、リソグラフィにより規定されたワイヤの空間的構成(すなわち、アライメントされた配列)を維持する。GaAsワイヤを有するPDMSスタンプは、その後、光硬化可能な高分子の一種である液体ポリウレタン(PU、NEA 121、Norland Products社、クランベリー、ニュージャージー州)の薄い層でコーティングされたPETシートに対して積層される。
Claims (129)
- 第1の電極と、
第2の電極と、
前記第1及び第2の電極と電気的に接触した状態で位置されるとともに、単一無機半導体構造を備え、約20%以上の前記第1及び第2の電極間の充填比を与える印刷可能半導体素子と、
を備える電気デバイス。 - 前記印刷可能半導体素子が、約50%以上の前記第1及び第2の電極間の充填比を与える、請求項1に記載の電気デバイス。
- 前記印刷可能半導体素子が、マイクロ構造の印刷可能半導体素子又はナノ構造の印刷可能半導体素子を備える、請求項1に記載の電気デバイス。
- 前記印刷可能半導体素子が、
リボンと、
板状体と、
柱と、
円筒と、
ディスクと、
ブロックと、
から成るグループから選択される形状を有している、請求項1に記載の電気デバイス。 - 少なくとも1つの更なる印刷可能半導体素子を更に備え、更なる印刷可能半導体素子が前記第1及び第2の電極と電気的に接触している、請求項1に記載の電気デバイス。
- 第1の電極と、
第2の電極と、
前記第1及び第2の電極と電気的に接触した状態で位置されるとともに、約500ナノメートル以上の少なくとも1つの断面寸法を有する単一無機半導体構造を備える印刷可能半導体素子と、
を備える電気デバイス。 - 前記単一無機半導体構造が、約10ナノメートル以上の厚さと、約100ナノメートル以上の幅と、約1ミクロン以上の長さとを有している、請求項6に記載の電気デバイス。
- 前記単一無機半導体構造が、約10ナノメートル〜約100ミクロンの範囲から選択される厚さと、約100ナノメートル〜約1ミリメートルの範囲から選択される幅と、約1ミクロン〜約1ミリメートルの範囲から選択される長さとを有している、請求項6に記載の電気デバイス。
- 前記単一無機半導体構造が、幅に対する長さの比が約10以下である、請求項6に記載の電気デバイス。
- 前記単一無機半導体構造が、幅に対する長さの比が約1.5以下である、請求項6に記載の電気デバイス。
- 前記単一無機半導体構造が、幅に対する厚さの比が約0.1以下である、請求項6に記載の電気デバイス。
- 前記印刷可能半導体素子が、マイクロ構造の印刷可能半導体素子又はナノ構造の印刷可能半導体素子を備える、請求項6に記載の電気デバイス。
- 前記印刷可能半導体素子が、
リボンと、
板状体と、
柱と、
円筒と、
ディスクと、
ブロックと、
から成るグループから選択される形状を有している、請求項6に記載の電気デバイス。 - 少なくとも1つの更なる印刷可能半導体素子を更に備え、更なる印刷可能半導体素子が前記第1及び第2の電極と電気的に接触している、請求項6に記載の電気デバイス。
- 第1の電極と、
第2の電極と、
前記第1及び第2の電極と電気的に接触した状態で位置されるとともに、単一無機半導体構造を備え、前記無機半導体構造中の重金属不純物の濃度が原子100万個につき1以下である印刷可能半導体素子と、
を備える電気デバイス。 - 前記無機半導体構造中の重金属不純物の濃度が、原子10億個につき100以下である、請求項15に記載の電気デバイス。
- 前記無機半導体構造が、単結晶半導体材料、多結晶半導体材料を備えている、請求項15に記載の電気デバイス。
- 前記無機半導体構造がドープ結晶半導体材料を備える、請求項15に記載の電気デバイス。
- 少なくとも1つの更なる印刷可能半導体素子を更に備え、更なる印刷可能半導体素子が前記第1及び第2の電極と電気的に接触している、請求項15に記載の電気デバイス。
- 第1の電極と、
第2の電極と、
前記第1及び第2の電極と電気的に接触した状態で位置されるとともに、前記第1の電極、前記第2の電極又はこれらの両方に対するその位置が約50ミクロンの範囲内となるように選択される印刷可能半導体素子と、
を備える電気デバイス。 - 前記第1の電極、前記第2の電極又はこれらの両方に対する前記印刷可能半導体素子の位置が約20ミクロンの範囲内となるように選択される、請求項20に記載の電気デバイス。
- 前記第1の電極、前記第2の電極又はこれらの両方に対する前記印刷可能半導体素子の位置が約5ミクロンの範囲内となるように選択される、請求項20に記載の電気デバイス。
- 前記印刷可能半導体素子が第1及び第2の端部で終端する長さで延びており、前記印刷可能半導体素子の前記第1の端部が前記第1の電極から5ミクロンの範囲内に位置され、前記印刷可能半導体素子の前記第2の端部が前記第2の電極から5ミクロンの範囲内に位置されている、請求項20に記載の電気デバイス。
- 前記第1及び第2の電極が、前記印刷可能半導体素子の長さの50%よりも長い距離だけ離間されている、請求項20に記載の電気デバイス。
- 少なくとも1つの更なる印刷可能半導体素子を更に備え、更なる印刷可能半導体素子が前記第1及び第2の電極と電気的に接触している、請求項20に記載の電気デバイス。
- トランジスタと、
太陽電池と、
フォトダイオードと、
発光ダイオードと、
マイクロ電子機械デバイスと、
ナノ電子機械デバイスと、
レーザと、
P−N接合と、
センサと、
メモリデバイスと、
相補型論理回路と、
から成るグループから選択されるデバイスを備えている、請求項20に記載の電気デバイス。 - 第1の電極と、
第2の電極と、
それぞれが前記第1及び第2の電極と電気的に接触した状態で位置されるとともに、それぞれが単一無機半導体構造を備え、約20%以上の前記第1及び第2の電極間の充填比を与える複数の印刷可能半導体素子と、
を備える電気デバイスの配列。 - 第1の電極と、
第2の電極と、
それぞれが前記第1及び第2の電極と電気的に接触した状態で位置されるとともに、それぞれが約500ナノメートル以上の少なくとも1つの断面寸法を有する単一無機半導体構造を備える複数の印刷可能半導体素子と、
を備える電気デバイスの配列。 - 第1の電極と、
第2の電極と、
それぞれが前記第1及び第2の電極と電気的に接触した状態で位置されるとともに、それぞれが単一無機半導体構造を備え、前記各無機半導体構造中の重金属不純物の濃度が原子100万個につき1以下である複数の印刷可能半導体素子と、
を備える電気デバイスの配列。 - 第1の電極と、
第2の電極と、
それぞれが前記第1及び第2の電極と電気的に接触した状態で位置されるとともに、前記第1の電極、前記第2の電極又はこれらの両方に対するそれぞれの位置が約50ミクロンの範囲内となるように選択される複数の印刷可能半導体素子と、
を備える電気デバイスの配列。 - 前記印刷可能半導体素子が、選択されたアライメント軸に対して略長手方向に向けられている、請求項30に記載の電気デバイスの配列。
- 前記選択されたアライメント軸が、前記第1及び第2の電気接点の最も近い点を接続する軸に沿って延びている、請求項31に記載の電気デバイスの配列。
- 前記第1の電極、前記第2の電極又はこれらの両方に対する前記各印刷可能半導体素子の位置が約5ミクロンの範囲内となるように選択される、請求項30に記載の電気デバイスの配列。
- 前記各印刷可能半導体素子が第1及び第2の端部で終端する長さで延びており、前記印刷可能半導体素子の前記第1の端部のそれぞれが前記第1の電極から5ミクロンの範囲内に位置され、前記印刷可能半導体素子の前記第2の端部のそれぞれが前記第2の電極から5ミクロンの範囲内に位置されている、請求項30に記載の電気デバイスの配列。
- 前記各印刷可能半導体素子の互いに対する位置が、約5ミクロンの範囲内となるように選択される、請求項30に記載の電気デバイスの配列。
- 基板の受け面上に印刷可能半導体素子を組み立てるための方法であって、
単一無機半導体構造を備える前記印刷可能半導体素子を設けるステップと、
前記印刷可能半導体素子を、接触面を有するコンフォーマブルな転写デバイスと接触させ、前記接触面と前記印刷可能半導体素子との間の接触が前記印刷可能半導体素子を前記接触面に対して結合させ、それにより、前記印刷可能半導体素子がその上に配置された前記接触面が形成されるステップと、
前記接触面上に配置された前記印刷可能半導体素子を前記基板の前記受け面と接触させるステップと、
前記コンフォーマブルな転写デバイスの前記接触面と前記印刷可能半導体素子とを分離させ、前記印刷可能半導体素子が前記受け面上に転写され、それにより、前記基板の前記受け面上に前記印刷可能半導体素子を組み立てるステップと、
を備える方法。 - 前記コンフォーマブルな転写デバイスの接触面と前記印刷可能半導体素子の外面との間でコンフォーマル接触が成される、請求項36に記載の方法。
- 前記印刷可能半導体素子がその上に配置された前記接触面と前記基板の前記受け面との間でコンフォーマル接触が成される、請求項36に記載の方法。
- 前記接触面上に配置された前記半導体素子が、約5cm2に等しい受け面の面積にわたって約25ミクロン以上の配置精度をもって前記受け面の選択された領域と接触される、請求項36に記載の方法。
- 前記受け面上には接着層が設けられ、前記印刷可能半導体素子が、前記基板の前記受け面に対する前記印刷可能半導体素子の転写中に前記接着層と接触される、請求項36に記載の方法。
- 前記基板の前記受け面が、約10ミクロン〜約10メートルの範囲にわたって選択される曲率半径を有する湾曲面である、請求項36に記載の方法。
- 前記コンフォーマブルな転写デバイスがエラストマースタンプを備えている、請求項36に記載の方法。
- 前記印刷可能半導体素子をコンフォーマブルな転写デバイスと接触させる前記ステップ、前記接触面上に配置された前記印刷可能半導体素子を前記基板の前記受け面と接触させる前記ステップ、及び前記コンフォーマブルな転写デバイスの前記接触面と前記印刷可能半導体素子とを分離させる前記ステップが、前記印刷可能半導体素子を前記受け面上に乾式転写印刷する工程を備える、請求項36に記載の方法。
- 前記印刷可能半導体素子を設ける前記ステップが、マザー基板上に選択された方向で前記半導体素子を設ける工程を備え、前記半導体素子の前記選択された方向が、前記マザー基板と前記印刷可能半導体素子とを結合するアライメント維持要素により、前記接触面との接触中に維持される、請求項36に記載の方法。
- 前記接触面上に配置された前記印刷可能半導体素子を前記基板の前記受け面と接触させる前記ステップでは、デバイスが前記アライメント維持要素を解放し、それにより、前記印刷可能半導体素子が前記マザー基板から解放される、請求項44に記載の方法。
- それぞれが単一無機半導体構造を備える更なる複数の印刷可能半導体素子を設けるステップと、
前記印刷可能半導体素子を、接触面を有するコンフォーマブルな転写デバイスと接触させ、前記接触面と前記印刷可能半導体素子との間の接触が前記印刷可能半導体素子を前記接触面に対して結合させるとともに、前記印刷可能半導体素子の選択されたパターンを備える相対的な方向で前記印刷可能半導体素子がその上に配置された前記接触面を形成するステップと、
前記接触面上に配置された前記印刷可能半導体素子を前記基板の前記受け面と接触させるステップと、
前記コンフォーマブルな転写デバイスの前記接触面と前記印刷可能半導体素子とを分離させ、前記選択されたパターンを備える前記相対的な方向で前記印刷可能半導体素子が前記受け面上に転写されるステップと、
を更に備える、請求項36に記載の方法。 - 前記印刷可能半導体素子が、前記選択されたパターンを備える前記相対的な方向でマザー基板上に設けられ、前記相対的な方向が前記受け面に対する転写中に維持される、請求項46に記載の方法。
- 前記コンフォーマブルな転写デバイスが、前記印刷可能半導体素子の全てではなく選択された印刷可能半導体素子と接触面との間でコンフォーマル接触を形成し、それにより、前記選択されたパターンを備える前記相対的な方向でその上に前記印刷可能半導体素子が配置された前記接触面を形成し、前記相対的な方向が前記受け面に対する転写中に維持される、請求項46に記載の方法。
- 前記コンフォーマブルな転写デバイスの接触面上に接着材料のパターンが設けられ、接着材料の前記パターンの少なくとも一部が印刷可能半導体素子の前記選択されたパターンに対応している、請求項46に記載の方法。
- 半導体素子の前記選択されたパターンが前記基板の前記受け面上に良好な忠実度で形成される、請求項46に記載の方法。
- 前記コンフォーマブルな転写デバイスが、前記選択されたパターンに対応する相対位置を有する複数の接触面を有している、請求項46に記載の方法。
- 前記基板がプラスチック基板である、請求項36に記載の方法。
- トランジスタと、
太陽電池と、
フォトダイオードと、
発光ダイオードと、
マイクロ電子機械デバイスと、
ナノ電子機械デバイスと、
レーザと、
P−N接合と、
相補型論理回路と、
から成るグループから選択される電気デバイスを製造するための方法を備える、請求項36に記載の方法。 - 基板の受け面上に印刷可能半導体素子を組み立てるための方法であって、
単一無機半導体構造を備える前記印刷可能半導体素子を設け、前記印刷可能半導体素子が約500ナノメートル以上の少なくとも1つの断面寸法を有するステップと、
前記半導体素子を溶媒中に分散させ、それにより、前記溶媒中に前記半導体素子を備える懸濁液を形成するステップと、
前記懸濁液を前記受け面上にソリューション印刷することにより前記半導体素子を前記基板へ供給し、それにより、前記受け面上に前記半導体素子を組み立てるステップと、
を備える方法。 - 前記懸濁液を前記受け面上にソリューション印刷することにより前記半導体素子を前記基板へ供給する前記ステップが、
インクジェット印刷と、
熱転写印刷と、
毛管作用印刷と、
スクリーン印刷と、
から成るグループから選択される印刷技術を使用する、請求項54に記載の方法。 - 前記半導体素子を選択された方向で前記受け面の選択された領域へと方向付けるステップを更に備える、請求項54に記載の方法。
- 前記半導体素子が、静電気力、静磁気力又は音波を用いて選択された方向で前記受け面の前記選択された領域へと方向付けられる、請求項56に記載の方法。
- 更なる印刷可能半導体素子を設け、前記更なる印刷可能半導体素子のそれぞれが約500ナノメートル以上の少なくとも1つの断面寸法を有するステップと、
前記半導体素子を前記溶媒中に分散させ、それにより、前記溶媒中に前記半導体素子を備える懸濁液を形成するステップと、
前記懸濁液を前記受け面上にソリューション印刷することにより前記半導体素子を前記基板へ供給し、それにより、前記受け面上に前記半導体素子を組み立てるステップと、
を更に備える、請求項54に記載の方法。 - 前記半導体素子に結合する前記受け面の結合領域を設けるステップと、
前記半導体素子を前記受け面の前記結合領域に対して結合させるステップと、
を更に備える、請求項54に記載の方法。 - 前記結合領域が親水性又は疎水性である、請求項59に記載の方法。
- 前記基板がプラスチック基板である、請求項54に記載の方法。
- トランジスタと、
太陽電池と、
フォトダイオードと、
発光ダイオードと、
マイクロ電子機械デバイスと、
ナノ電子機械デバイスと、
レーザと、
P−N接合と、
相補型論理回路と、
から成るグループから選択される電気デバイスを製造するための方法を備える、請求項54に記載の方法。 - 前記印刷可能半導体素子がハンドル素子を更に備え、前記方法が、前記ハンドル素子を使用して前記半導体素子を選択された方向で前記受け面の選択された領域へと方向付けることを更に備える、請求項54に記載の方法。
- 印刷可能半導体素子を製造するための方法であって、
外面を有するウエハを設け、前記ウエハが無機半導体材料を備えるステップと、
マスクを適用することにより前記外面の選択された領域をマスキングするステップと、
前記ウエハの前記外面をエッチングすることにより、レリーフ構造と前記ウエハの少なくとも1つの露出面とを形成し、前記レリーフ構造が1つのマスキングされた側と1つ以上のマスキングされていない側とを有するステップと、
前記レリーフ構造の前記マスキングされていない側の少なくとも一部に対してマスクを適用するステップと、
前記ウエハの前記露出面を少なくとも部分的にエッチングすることにより、前記印刷可能半導体素子を製造するステップと、
を備える方法。 - 前記印刷可能半導体素子が、アライメント維持要素により前記ウエハに対して接続される、請求項64に記載の方法。
- 誘電体層を前記外面上に堆積させるステップを更に備え、前記半導体素子が誘電体と接触する無機半導体構造を備える、請求項64に記載の方法。
- 前記外面上に誘電体層を堆積させ、前記誘電体層が外側と反対側の内側を有し、前記誘電体層の前記外側が前記ウエハの前記外面と接触するステップと、
前記誘電体層の前記外側上に導電層を堆積させるステップと、
を更に備え、
前記半導体素子が無機半導体構造と誘電体と電極とを備え、前記誘電体が前記結晶半導体構造と前記電極との間に位置されている、請求項64に記載の方法。 - 1つ以上のアライメント維持要素を介してマザーウエハに対して接続される印刷可能半導体素子を製造するための方法であって、
外面を有する前記マザーウエハを設け、前記ウエハが無機半導体材料を備えるステップと、
マスクを適用することにより前記外面の選択された領域をマスキングするステップと、
前記ウエハの前記外面をエッチングすることにより、レリーフ構造と前記ウエハの少なくとも1つの露出面とを形成し、前記レリーフ構造が1つのマスキングされた側と1つ以上のマスキングされていない側とを有するステップと、
前記ウエハの前記露出面をエッチングするステップと、
前記レリーフ構造の完全な解放が妨げられるように前記露出面のエッチングを停止させ、それにより、1つ以上のアライメント維持要素を介してマザーウエハに対して接続される前記印刷可能半導体素子を製造するステップと、
を備える方法。 - 前記印刷可能半導体素子が第1の端部及び第2の端部を有するピーナッツ形状を成し、前記アライメント維持要素が、前記印刷可能半導体素子の前記第1及び第2の端部を前記マザーウエハに対して接続する、請求項68に記載の方法。
- 前記印刷可能半導体素子が第1の端部及び第2の端部を有するリボン形状を成し、前記アライメント維持要素が、前記印刷可能半導体素子の前記第1及び第2の端部を前記マザーウエハに対して接続する、請求項68に記載の方法。
- 印刷可能半導体素子を製造するための方法であって、
外面を有するウエハを設け、前記ウエハが無機半導体を備えるステップと、
第1のマスクを適用することにより前記外面の選択された領域をマスキングするステップと、
前記ウエハの前記外面をエッチングすることにより、複数のレリーフ構造を形成するステップと、
前記ウエハをアニールすることにより、アニール外面を形成するステップと、
第2のマスクを適用することにより前記アニール外面の選択された領域をマスキングするステップと、
前記アニール外面をエッチングすることにより、前記印刷可能半導体素子を形成するステップと、
を備える方法。 - 前記印刷可能半導体素子がアライメント維持要素を介して前記ウエハに対して接続される、請求項71に記載の方法。
- 印刷可能半導体素子を製造するための方法であって、
外面を有する超薄ウエハを設け、前記ウエハが無機半導体を備え且つ前記外面と直交する軸に沿う選択された厚さを有するステップと、
マスクを適用することにより前記外面の選択された領域をマスキングするステップと、
前記ウエハの前記外面をエッチングし、前記ウエハが前記外面と直交する前記軸に沿う前記厚さの全体にわたってエッチングされ、それにより、前記印刷可能半導体素子を形成するステップと、
を備える方法。 - 単一結晶無機半導体構造と、
前記結晶無機半導体構造に接続された少なくとも1つのハンドル素子と、
を備える印刷可能半導体素子。 - 前記ハンドル素子が、磁場、電場、又は、これらの両方に対して応答する、請求項74に記載の印刷可能半導体素子。
- 前記ハンドル素子が強磁性材料を備える、請求項74に記載の印刷可能半導体素子。
- 2つのハンドル素子を備える、請求項74に記載の印刷可能半導体素子。
- 前記単一結晶無機半導体構造が、中心軸に沿って延び且つ前記中心軸に沿って第1の端部及び第2の端部で終端するリボンであり、前記ハンドル素子が前記リボンの前記第1及び第2の端部に設けられている、請求項74に記載の印刷可能半導体素子。
- 基板の受け面上に印刷可能半導体素子を組み立てるための方法であって、
単一結晶無機半導体構造及びハンドル素子を備える前記半導体素子を設けるステップと、
溶媒中に前記半導体素子を分散させることにより、前記溶媒中に前記半導体素子を備える懸濁液を形成するステップと、
前記懸濁液を前記受け面上に分散させることにより前記半導体素子を前記基板に対して供給するステップと、
磁場、電場、又は、これらの両方を与えることにより前記受け面上で前記半導体素子をアライメントし、前記磁場、電場、又は、これらの両方が前記ハンドル素子と相互に作用することにより、前記ハンド体素子を選択された位置及び方向へ移動させる力が形成され、それにより、前記受け面上に前記半導体素子を組み立てるステップと、
を備える方法。 - 約500ナノメートル以上の少なくとも1つの断面寸法を有する単一結晶無機半導体構造を備える印刷可能なP−N接合であって、前記結晶無機半導体構造がNドープ領域と電気的に接触するPドープ領域を備えているP−N接合。
- プラスチック基板により支持されるトランジスタにおいて、
単一結晶無機半導体構造を備える印刷可能半導体素子と電気的に接触するソース電極と、
前記印刷可能半導体素子と電気的に接触するドレイン電極と、
前記ソース電極及びドレイン電極から分離されるゲート電極であって、前記ゲート電極に対する電位の印加が、前記印刷可能半導体素子を介したソース電極とドレイン電極との間の電子の流れに影響を与えるゲート電極と、
を備え、
100cm2V−1s−1以上のデバイス電界効果移動度を有しているトランジスタ。 - 支持面を有するフレキシブル基板と、
湾曲した内面を有し、前記湾曲した内面の少なくとも一部が前記フレキシブル基板の前記支持面に対して結合される半導体構造と、
を備える伸縮可能な半導体素子。 - 前記半導体構造が湾曲形態を成している、請求項82に記載の伸縮可能な半導体素子。
- 前記結晶無機半導体構造が、前記湾曲した内面と反対側の湾曲した外面を有している、請求項82に記載の伸縮可能な半導体素子。
- 前記湾曲した内面を有する前記半導体構造が歪みを受けている、請求項82に記載の伸縮可能な半導体素子。
- 前記湾曲した内面が少なくとも1つの凸領域を有している、請求項82に記載の伸縮可能な半導体素子。
- 前記湾曲した内面が少なくとも1つの凹領域を有している、請求項82に記載の伸縮可能な半導体素子。
- 前記湾曲した内面が周期波により特徴付けられる輪郭形状を有している、請求項82に記載の伸縮可能な半導体素子。
- 前記湾曲した内面が非周期波により特徴付けられる輪郭形状を有している、請求項82に記載の伸縮可能な半導体素子。
- 前記半導体構造が湾曲形態のリボンを備え、このリボンが、当該リボンの全長にわたって延びる周期波により特徴付けられる輪郭形状を有している、請求項82に記載の伸縮可能な半導体素子。
- 前記湾曲リボンが、約5ミクロン〜約50ミクロンの範囲にわたって選択される幅と、約50ナノメートル〜約500ナノメートルにわたって選択された厚さとを有している、請求項90に記載の伸縮可能な半導体素子。
- 前記湾曲した内面が、前記湾曲した内面に沿うほぼ全ての点で前記支持面に対して結合されている、請求項82に記載の伸縮可能な半導体素子。
- 前記湾曲した内面が、前記湾曲した内面に沿う選択された点で前記支持面に対して結合されている、請求項82に記載の伸縮可能な半導体素子。
- 前記フレキシブル基板がポリ(ジメチルシロキサン)を備えている、請求項82に記載の伸縮可能な半導体素子。
- 前記フレキシブル基板が約1ミリメートルに等しい厚さを有している、請求項82に記載の伸縮可能な半導体素子。
- 前記半導体構造が無機半導体材料である、請求項82に記載の伸縮可能な半導体素子。
- 前記半導体構造が単結晶無機半導体材料である、請求項82に記載の伸縮可能な半導体素子。
- 前記半導体構造が単結晶シリコンを備えている、請求項82に記載の伸縮可能な半導体素子。
- 伸縮可能な半導体素子を形成するための方法であって、
内面を有する印刷可能な半導体構造を設けるステップと、
予め歪みが加えられた拡張状態の弾性基板を設け、前記弾性基板が外面を有しているステップと、
前記印刷可能な半導体構造の前記内面の少なくとも一部を、予め歪みが加えられた拡張状態の前記弾性基板の前記外面に対して結合させるステップと、
前記弾性基板を緩和状態まで少なくとも部分的に弛緩させることができ、弾性基板の弛緩が前記印刷可能な半導体構造の内面を湾曲させ、それにより、湾曲した内面を有する前記伸縮可能な半導体素子を形成するステップと、
を備える方法。 - 予め歪みが加えられた前記弾性基板が第1の軸に沿って拡張される、請求項99に記載の方法。
- 予め歪みが加えられた前記弾性基板が前記第1の軸と直交する第2の軸に沿って拡張される、請求項100に記載の方法。
- 予め歪みが加えられた拡張状態の前記弾性基板が、前記弾性基板を曲げることにより形成される、請求項99に記載の方法。
- 予め歪みが加えられた拡張状態の前記弾性基板が、前記弾性基板を圧延することにより形成される、請求項99に記載の方法。
- 湾曲した内面を有する前記半導体をフレキシブルな受け基板に対して転写するステップを更に備える、請求項99に記載の方法。
- 予め歪みが加えられた前記弾性基板の前記外面に対する前記印刷可能な半導体構造の前記内面の少なくとも一部の結合が、前記印刷可能な半導体構造と予め歪みが加えられた前記弾性基板の前記外面との間の共有結合、前記印刷可能な半導体構造と予め歪みが加えられた前記弾性基板の前記外面との間のファンデルワールス相互作用、前記印刷可能な半導体構造と予め歪みが加えられた前記弾性基板の前記外面との間の接着層によって行なわれる、請求項99に記載の方法。
- 予め歪みが加えられた前記弾性基板の前記外面が、前記印刷可能な半導体構造と予め歪みが加えられた前記弾性基板の前記外面との間の結合を行なう複数の水酸基を有している、請求項99に記載の方法。
- 支持面を有するフレキシブル基板と、
湾曲した内面を有し、前記湾曲した内面の少なくとも一部が前記フレキシブル基板の前記支持面に対して結合される電気回路と、
を備える伸縮可能な電気回路。 - 前記電気回路が複数の集積デバイス部品を備えている、請求項107に記載の伸縮可能な電気回路。
- 前記集積デバイス部品が、
半導体素子と、
誘電体素子と、
電極と、
導体素子と、
ドープ半導体素子と、
から成るグループから選択される、請求項107に記載の伸縮可能な電気回路。 - 前記電気回路が湾曲形態を成している、請求項107に記載の伸縮可能な電気回路。
- 前記湾曲した内面を有する前記電気回路が歪みを受けている、請求項107に記載の伸縮可能な電気回路。
- 前記湾曲した内面が周期波により特徴付けられる輪郭形状を有している、請求項107に記載の伸縮可能な電気回路。
- 前記湾曲した内面が非周期波により特徴付けられる輪郭形状を有している、請求項105に記載の伸縮可能な電気回路。
- 伸縮可能な電気回路を形成するための方法であって、
内面を有する印刷可能な電気回路を設けるステップと、
予め歪みが加えられた拡張状態の弾性基板を設け、前記弾性基板が外面を有しているステップと、
前記印刷可能な電気回路の前記内面の少なくとも一部を、予め歪みが加えられた拡張状態の前記弾性基板の前記外面に対して結合させるステップと、
前記弾性基板を緩和状態まで少なくとも部分的に弛緩させることができ、弾性基板の弛緩が前記印刷可能な電気回路の内面を湾曲させることで、前記内面の少なくとも1つの湾曲が形成され、それにより、前記伸縮可能な電気回路を形成するステップと、
を備える方法。 - 前記電気回路が複数の集積デバイス部品を備えている、請求項114に記載の方法。
- 前記集積デバイス部品が、
半導体素子と、
誘電体素子と、
電極と、
導体素子と、
ドープ半導体素子と、
から成るグループから選択される、請求項114に記載の方法。 - 予め歪みが加えられた前記弾性基板が第1の軸に沿って拡張される、請求項114に記載の方法。
- 予め歪みが加えられた前記弾性基板が前記第1の軸と直交する第2の軸に沿って拡張される、請求項117に記載の方法。
- 予め歪みが加えられた拡張状態の前記弾性基板が、前記弾性基板を曲げることにより形成される、請求項114に記載の方法。
- 予め歪みが加えられた拡張状態の前記弾性基板が、前記弾性基板を圧延することにより形成される、請求項114に記載の方法。
- 湾曲した内面を有する前記印刷可能な電気回路をフレキシブルな受け基板に対して転写するステップを更に備える、請求項114に記載の方法。
- 予め歪みが加えられた前記弾性基板の前記外面に対する前記印刷可能な電気回路の前記内面の少なくとも一部の結合が、前記印刷可能な電気回路と予め歪みが加えられた前記弾性基板の前記外面との間の共有結合、前記印刷可能な電気回路と予め歪みが加えられた前記弾性基板の前記外面との間のファンデルワールス相互作用、前記印刷可能な電気回路と予め歪みが加えられた前記弾性基板の前記外面との間の接着層によって行なわれる、請求項114に記載の方法。
- 予め歪みが加えられた前記弾性基板の前記外面が、前記印刷可能な伝記回路と予め歪みが加えられた前記弾性基板の前記外面との間の結合を行なう複数の水酸基を有している、請求項114に記載の方法。
- 第1の電極と、
第2の電極と、
それぞれが前記第1及び第2の電極と電気的に接触した状態で位置される複数の印刷可能半導体素子と、
を備え、
前記印刷可能半導体素子の少なくとも1つの物理的寸法が約10%未満変化する電気デバイスの配列。 - 前記印刷可能半導体素子の平均長が約10%未満変化する、請求項124に記載の電気デバイスの配列。
- 前記印刷可能半導体素子の平均幅が約10%未満変化する、請求項124に記載の電気デバイスの配列。
- 前記印刷可能半導体素子の平均厚さが約10%未満変化する、請求項124に記載の電気デバイスの配列。
- 20個を越える印刷可能半導体素子を備える、請求項124に記載の電気デバイスの配列。
- 50個を越える印刷可能半導体素子を備える、請求項124に記載の電気デバイスの配列。
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