US20090294803A1 - Methods and devices for fabricating and assembling printable semiconductor elements - Google Patents

Methods and devices for fabricating and assembling printable semiconductor elements Download PDF

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US20090294803A1
US20090294803A1 US11/145,574 US14557405A US2009294803A1 US 20090294803 A1 US20090294803 A1 US 20090294803A1 US 14557405 A US14557405 A US 14557405A US 2009294803 A1 US2009294803 A1 US 2009294803A1
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United States
Prior art keywords
printable semiconductor
semiconductor element
printable
semiconductor elements
substrate
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US11/145,574
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US7622367B1 (en
Inventor
Ralph G. Nuzzo
John A. Rogers
Etienne Menard
Keon Jae Lee
Dahl-Young Khang
Yugang Sun
Matthew Meitl
Zhengtao Zhu
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University of Illinois
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University of Illinois
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Priority to US57707704P priority Critical
Priority to US60106104P priority
Priority to US65030505P priority
Priority to US66339105P priority
Priority to US67761705P priority
Priority to US11/145,574 priority patent/US7622367B1/en
Application filed by University of Illinois filed Critical University of Illinois
Assigned to THE BOARD OF TRUSTEES OF THE UNIVERSITY OF ILLINOIS reassignment THE BOARD OF TRUSTEES OF THE UNIVERSITY OF ILLINOIS ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: NUZZO, RALPH G, MENARD, ETIENNE, MEITL, MATTHEW, SUN, YUGANG, KHANG, DAHL-YOUNG, LEE, KEON JAE, ROGERS, JOHN A, ZHU, ZHENGTAO
Priority claimed from PCT/US2006/021161 external-priority patent/WO2006130721A2/en
Priority claimed from US11/421,654 external-priority patent/US7799699B2/en
Priority claimed from KR1020087000080A external-priority patent/KR101269566B1/en
Priority claimed from KR1020137011761A external-priority patent/KR101347687B1/en
Priority claimed from TW095119520A external-priority patent/TWI427802B/en
Priority claimed from CN201110077508.8A external-priority patent/CN102176465B/en
Priority claimed from US11/423,192 external-priority patent/US7943491B2/en
Priority claimed from US11/423,287 external-priority patent/US7521292B2/en
Priority claimed from US11/851,182 external-priority patent/US8217381B2/en
Publication of US7622367B1 publication Critical patent/US7622367B1/en
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Publication of US20090294803A1 publication Critical patent/US20090294803A1/en
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    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
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    • Y10S977/707Integrated with dissimilar structures on a common substrate having different types of nanoscale structures or devices on a common substrate
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10S977/00Nanotechnology
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    • Y10S977/724Devices having flexible or movable element

Abstract

The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.

Description

    CROSS REFERENCE TO RELATED APPLICATION
  • This application claims priority under 35 U.S.C. 119(e) to U.S. Provisional Patent Application Nos. 60/577,077, 60/601,061, 60/650,305, 60/663,391 and 60/677,617 filed on Jun. 4, 2004, Aug. 11, 2004, Feb. 4, 2005, Mar. 18, 2005, and May 4, 2005, respectively, which are hereby incorporated by reference in their entireties to the extent not inconsistent with the disclosure herein.
  • STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
  • This invention was made, at least in part, with United States governmental support awarded by Department of Energy under Grant No. DEFG02-91ER45439 and the Defense Advanced Projects Agency under Contract F8650-04-C-710. The United States Government has certain rights in this invention.
  • BACKGROUND OF INVENTION
  • Since the first demonstration of a printed, all polymer transistor in 1994, a great deal of interest has been directed at a potential new class of electronic systems comprising flexible integrated electronic devices on plastic substrates. [Garnier, F., Hajlaoui, R., Yassar, A. and Srivastava, P., Science, Vol. 265, pgs 1684-1686] Recently, substantial research has been directed toward developing new solution processable materials for conductors, dielectrics and semiconductors elements for flexible plastic electronic devices. Progress in the field of flexible electronics, however, is not only driven by the development of new solution processable materials but also by new device component geometries, efficient device and device component processing methods and high resolution patterning techniques applicable to plastic substrates. It is expected that such materials, device configurations and fabrication methods will play an essential role in the rapidly emerging new class of flexible integrated electronic devices, systems and circuits.
  • Interest in the field of flexible electronics principally arises out of several important advantages provided by this technology. First, the mechanical ruggedness of plastic substrate materials provides electronic devices less susceptible to damage and/or electronic performance degradation caused by mechanical stress. Second, the inherent flexibility of these substrate materials allows them to be integrated into many shapes providing for a large number of useful device configurations not possible with brittle conventional silicon based electronic devices. For example, bendable flexible electronic devices are expected to enable fabrication of new devices, such as electronic paper, wearable computers and large-area high resolution displays, that are not easily achieved with established silicon based technologies. Finally, the combination of solution processable component materials and plastic substrates enables fabrication by continuous, high speed, printing techniques capable of generating electronic devices over large substrate areas at low cost.
  • The design and fabrication of flexible electronic devices exhibiting good electronic performance, however, present a number of significant challenges. First, the well developed methods of making conventional silicon based electronic devices are incompatible with most plastic materials. For example, traditional high quality inorganic semiconductor components, such as single crystalline silicon or germanium semiconductors, are typically processed by growing thin films at temperatures (>1000 degrees Celsius) that significantly exceed the melting or decomposition temperatures of most plastic substrates. In addition, most inorganic semiconductors are not intrinsically soluble in convenient solvents that would allow for solution based processing and delivery. Second, although many amorphous silicon, organic or hybrid organic-inorganic semiconductors are compatible with incorporation into plastic substrates and can be processed at relatively low temperatures, these materials do not have electronic properties capable of providing integrated electronic devices capable of good electronic performance. For example, thin film transistors having semiconductor elements made of these materials exhibit field effect mobilities approximately three orders of magnitude less than complementary single crystalline silicon based devices. As a result of these limitations, flexible electronic devices are presently limited to specific applications not requiring high performance, such as use in switching elements for active matrix flat panel displays with non-emissive pixels and in light emitting diodes.
  • Progress has recently been made in extending the electronic performance capabilities of integrated electronic devices on plastic substrates to expand their applicability to a wider range of electronics applications. For example, several new thin film transistor (TFT) designs have emerged that are compatible with processing on plastic substrate materials and exhibit significantly higher device performance characteristics than thin film transistors having amorphous silicon, organic or hybrid organic-inorganic semiconductor elements. One class of higher performing flexible electronic devices is based on polycrystalline silicon thin film semiconductor elements fabricated by pulse laser annealing of amorphous silicon thin films. While this class of flexible electronic devices provides enhanced device electronic performance characteristics, use of pulsed laser annealing limits the ease and flexibility of fabrication of such devices, thereby significantly increasing costs. Another promising new class of higher performing flexible electronic devices is devices that employ solution processable nanoscale materials, such as nanowires, nanoribbons, nanoparticles and carbon nanotubes, as active functional components in a number of macroelectronic and microelectronic devices.
  • Use of discrete single crystalline nanowires or nanoribbons has been evaluated as a possible means of providing printable electronic devices on plastic substrates that exhibit enhanced device performance characteristics. Duan et al. describe thin film transistor designs having a plurality of selectively oriented single crystalline silicon nanowires or CdS nanoribbons as semiconducting channels [Duan, X., Niu, C., Sahl, V., Chen, J., Parce, J., Empedocles, S, and Goldman, J., Nature, Vol. 425, pgs, 274-278]. The authors report a fabrication process allegedly compatible with solution processing on plastic substrates in which single crystalline silicon nanowires or CdS nanoribbons having thicknesses less than or equal to 150 nanometers are dispersed into solution and assembled onto the surface of a substrate using flow-directed alignment methods to produce the semiconducting element of at thin film transistor. An optical micrograph provided by the authors suggests that the disclosed fabrication process prepares a monolayer of nanowires or nanoribbons in a substantially parallel orientation and spaced apart by about 500 nanometers to about 1,000 nanometers. Although the authors report relatively high intrinsic field affect mobilities for individual nanowires or nanoribbons (≈119 cm2V−1 s−1), the overall device field effect mobility has recently been determined to be “approximately two orders of magnitude smaller” than the intrinsic field affect mobility value reported by Duan et al. [Mitzi, D. B, Kosbar, L. L., Murray, C. E., Copel, M. Afzali, A., Nature, Vol. 428, pgs. 299-303]. This device field effect mobility is several orders of magnitude lower than the device field effect mobilities of conventional single crystalline inorganic thin film transistors, and is likely due to practical challenges in aligning, densely packing and electrically contacting discrete nanowires or nanoribbons using the methods and device configurations disclosed in Duan et al.
  • Use of a nanocrystal solutions as precursors to polycrystalline inorganic semiconductor thin films has also been explored as a possible means of providing printable electronic devices on plastic substrates that exhibit higher device performance characteristics. Ridley et al. disclose a solution processing fabrication method wherein a solution cadmium selenide nanocrystals having dimensions of about 2 nanometers is processed at plastic compatible temperatures to provide a semiconductor element for a field effect transistor. The authors report a method wherein low temperature grain growth in a nanocrystal solution of cadmium selenide provides single crystal areas encompassing hundreds of nanocrystals. Although Ridley et al. report improved electrical properties relative to comparable devices having organic semiconductor elements, the device mobilities achieved by these techniques (≈1 cm2V−1s−1) are several orders of magnitude lower than the device field effect mobilities of conventional single crystalline inorganic thin film transistors. Limits on the field effect mobilities achieved by the device configurations and fabrication methods of Ridley et al. are likely to arise from the electrical contact established between individual nanoparticles. Particularly, the use of organic end groups to stabilize nanocrystal solutions and prevent agglomeration may impede establishing good electrical contact between adjacent nanoparticles that is necessary for providing high device field effect mobilities.
  • Although Duan et al. and Ridley et al. provide methods for fabricating thin film transistors on plastic substrates, the device configurations described employ transistors comprising mechanically rigid device components, such as electrodes, semiconductors and/or dielectrics. Selection of a plastic substrate with good mechanical properties may provide electronic devices capable of performing in flexed or distorted orientations. However, such motion is expected to generate mechanical strain on the individual rigid transistor device components. This mechanical strain may induce damage to individual components, for example by cracking, and also may degrade or disrupt electrical contact between device components.
  • It will be appreciated from the foregoing that there is currently a need in the art for methods and device configurations for fabricating integrated electronic semiconductor-containing devices on plastic substrates. Printable semiconductor elements having good electrical characteristics are needed to allow effective device fabrication at temperatures compatible with assembly on plastic polymer substrates. In addition, methods of printing semiconductor materials onto large areas of plastic substrates are needed to enable continuous, high speed printing of complex integrated electrical circuits over large substrate areas. Finally, fully flexible electronic devices capable of good electronic performance in flexed or deformed device orientations are needed to enable a wide range of new flexible electronic devices.
  • SUMMARY OF THE INVENTION
  • The present invention provides methods, devices and device components for fabricating structures and/or devices, such as semiconductor-containing electronic devices, on substrate surfaces, such as plastic substrates. Specifically, the present invention provides printable semiconductor elements for fabricating electronic devices, optoelectronic devices and other functional electronic assemblies by flexible, low cost printing methods. It is an object of the present invention to provide methods and devices for fabricating semiconductor elements, such as unitary single crystalline inorganic semiconductors having selected physical dimensions ranging from about 10 s of nanometers to about 10 s of centimeters, which are capable of high precision assembly on substrate surfaces via a range of printing techniques. It is another object of the present invention to provide methods for assembling and/or patterning printable semiconductor elements using dry transfer contact printing and/or solution printing techniques which provide good placement accuracy and pattern fidelity over large substrate areas. It is further an object of the present invention to provide good electronic performance integrated electronic and/or optoelectronic devices comprising one or more printable semiconductor elements supported by a plastic substrate, particularly fully flexible thin film transistors having printable semiconductor elements exhibiting good electronic performance characteristics, such as field effect mobilities, threshold voltages and on-off ratios.
  • In one aspect the present invention provides methods of fabricating high performance electronic and/or optoelectronic devices or device components having one or more printable components, such as a printable semiconductor element. Electronic and optoelectronic devices which may be fabricated by the methods of the present invention, include but are limited to, transistors, diodes, light emitting diodes (LEDs), lasers, organic light emitting diodes (OLEDs), microelectromechanical systems (MEMS) and nanoelectromechanical systems (NEMS). Particularly, the present invention provides methods of assembling semiconductor elements and/or other device components via printing techniques into electronic and/or optoelectronic devices or device components which exhibit performance characteristics comparable to single crystalline semiconductor based devices fabricated by conventional high temperature processing methods.
  • In an embodiment of the present invention useful for device fabrication on substrates having low melting or decomposition temperatures, such as plastic substrates and semiconductor substrates, methods of the present invention comprise independently performable fabrication steps of: (1) forming one or more discrete, high quality semiconductor elements and (2) assembling and/or patterning these semiconductor elements and other device components on a substrate surface. For example, the present invention includes methods wherein independent, high quality printable inorganic semiconductors are generated by masking and etching bulk single crystalline inorganic semiconductor materials fabricated by conventional high temperature processing methods, such as high temperature (>1000 Celsius) film growth, doping and other processing techniques. After fabrication, such printable inorganic semiconductors are assembled onto one or more substrates surface by printing techniques which may be performed at relatively low temperatures (<about 400 degrees Celsius). An advantage of having independently performable preparation and patterning/assembly steps is that each step may be performed at ambient conditions, such as temperatures and ambient contamination levels (i.e. if clean room conditions are needed), which optimize the efficiencies, flexibilities and utilities of each independently performable fabrication step. For example, the present methods allow semiconductor materials to be fabricated at the high temperatures needed to generate high quality single crystalline semiconductors. Semiconductor element patterning and/or assembly, however, may be subsequently carried out at substantially lower temperatures favorable for device fabrication on substrates having low melting or decomposition temperatures, such as plastic substrates. In this manner, high performance devices may be fabricated on a wide range of substrate surfaces without significant melting, decomposition or damage to the substrate surface. Another advantage of separating semiconductor fabrication from semiconductor/device assembly is that integration of the semiconductor elements into high performance devices and device components may be achieved by a wide range of low cost and flexible assembly methods, such as dry transfer and solution printing techniques, which do not require clean room conditions and are compatible with continuous, high speed device fabrication on large areas of substrates. In the context of this aspect of the present invention, the present methods are compatible with printing on substrates comprising virtually any material, including plastic substrates and non-plastic substrates, such as semiconductor wafers, for example silicon wafers or GaAs wafers.
  • In another aspect, the present invention provides printable semiconductor elements for integration into high performance electrical and optoelectronic devices and device components. In the context of the present invention, the term “printable” relates to materials, structures, device components and/or integrated functional devices that may be transferred, assembled, patterned, organized and/or integrated onto or into substrates without exposure of the substrate to high temperatures (i.e. at temperatures less than or equal to about 400 degrees Celsius). Printable semiconductors of the present invention may comprise semiconductor structures that are able to be assembled and/or integrated onto substrate surfaces by dry transfer contact printing and/or solution printing methods. Exemplary semiconductor elements of the present invention may be fabricated by “top down” processing of a range of inorganic semiconductor materials including, but not limited to, single crystalline silicon wafers, silicon on insulator wafers, polycrystalline silicon wafers and GaAs wafers. Printable semiconductor elements derived from high quality semiconductor wafers, for example semiconductor wafers generated using conventional high temperature vapor deposition processing techniques, are beneficial for applications requiring good electronic performance because these materials have better purities and extents of crystallization than materials prepared using “bottom up” processing techniques, such as conventional techniques for making nanocrystals and nanowires. Another advantage provided by the “top-down” processing methods of the present invention is that printable semiconductor elements and arrays of printable semiconductor elements may be fabricated in well defined orientations and patterns, unlike “bottom-up” processing methods typically used for fabricating nanowires and nanoparticles. For example, semiconductor elements may be fabricated in arrays having positions and spatial orientations directly corresponding to the eventual positions and spatial orientations of these elements in functional devices or arrays of functional devices, such as transistor arrays or diode arrays.
  • Printable semiconductor elements may comprise unitary, single crystalline inorganic semiconductor structures having wide range of shapes, such as ribbon (or strips), discs, platelets, blocks, post, cylinders or any combinations of these shapes. Printable semiconductor elements of the present invention may have a wide range of physical dimensions, for example, thicknesses ranging from about 10 nanometers to about 100 microns, widths ranging from about 50 nanometers to about 1 millimeter and lengths ranging from about 1 micron to about 1 millimeter. Use of semiconductor elements having thicknesses greater than about 10 nanometers and widths greater than about 500 nanometer are preferred for some application because these dimensions may provide electronic devices exhibiting good electronic performance, such as thin film transistors having a device field effect mobility greater than or equal to about 100 cm2V−1s−1, and preferably greater than or equal to about 300 cm2V−1s−1 and more preferably greater than or equal to about 800 cm2V−1s−1. In addition, semiconductor elements having widths greater than about 10 nanometers can be assembled on substrates by a range of printing techniques with good placement accuracy and pattern fidelity.
  • Printable semiconductor elements of the present invention may also be provided with an alignment maintaining element that mechanically connects the printable semiconductor element to a mother substrate, such as a semiconductor wafer. Alignment maintaining elements are useful for maintaining a selected orientation and/or position of a printable semiconductor element during transfer, assembly and/or integration processing steps. Alignment maintaining elements are also useful for maintaining relative positions and orientations of a plurality of semiconductor elements defining a selected pattern of semiconductor elements during transfer, assembly and/or integration processing steps. In methods of the present invention, alignment maintaining elements preserve selected positions and orientations during contact (and bonding) of the printable semiconductor elements with the contact surface of a conformable transfer device. Useful alignment maintaining elements in this aspect of the present invention are capable of disengaging from the printable semiconductor elements upon movement of the conformable transfer device without significantly changing the selected positions and orientations of the printable semiconductor elements. Disengagement is typically achieved by fracture or release of the alignment maintaining elements during movement of the transfer device.
  • In one embodiment of the present invention, the printable semiconductor element has a peanut shape characterized by wider ends and a narrow central region. In this embodiment, alignment maintaining elements are provided via incomplete isotropic etching beneath the wider ends and complete isotropic etching beneath the central region. This processing lead to a semiconductor element connected to a mother substrate a two points corresponding to each end of the semiconductor element. In another embodiment, the printable semiconductor element has a ribbon shape extending along a central longitudinal axis. In this embodiment, alignment maintaining elements connect the both ends of the ribbon along the longitudinal axis to the mother substrate. In each embodiment, binding of the ribbon shaped or peanut shaped semiconductor element to the contact surface of a transfer device and movement of the transfer device results in fracture of both alignment maintaining elements and release of the printable semiconductor element from the mother substrate.
  • Printable semiconductor elements of the present invention have independently selectable physical dimensions, such as widths, heights, thicknesses surface roughness, and flatness, that are selectable with a high degree of accuracy. In an exemplary embodiment, physical dimensions of printable semiconductor elements may be selected to within less than about 5%. Large numbers of printable semiconductor elements having highly uniform selected physical dimension may be fabricated using the methods of the present invention. In an exemplary embodiment, large numbers of printable semiconductor elements can be fabricated having physical dimensions that vary by less than about 1%. The present invention, therefore, provides printable semiconductor elements without a significant size and shape distributions, in contrast to conventional methods of generating nanowires. A significant advantage of this approach is that structures and devices that integrate printable semiconductor elements of the present invention do not need to be built to tolerate dispersion in size and shape of the semiconductor elements. In some embodiments, printable semiconductor elements of the present invention have very low surface roughness, for example having a surface roughness less than about 0.5 nanometers root mean square. Printable semiconductor elements of the present invention may have one or more flat surfaces. This configuration is beneficial in some device fabrication applications because flat surfaces are useful for establishing interfaces with other device components, such as conducting, semiconducting and/or dielectric device components.
  • Further, the present methods and compositions of matter provide printable semiconductor elements comprising high quality semiconductor materials. In some embodiments useful for fabricating high performance electrical devices, printable semiconductor elements have a purity with a factor of about 1000 or less of conventional semiconductor wafer materials fabricated via high temperature processing techniques. For example, the present invention provides high purity semiconductor elements having oxygen impurities less than about 5 to 25 parts per million atoms, carbon impurities less than about 1 to 5 parts per million atoms, and heavy metal impurities less than or equal to about 1 part per million atoms (ppma), preferably less than or equal to about 100 parts per billion atoms (ppba) for some applications, and more preferably less than or equal to about 1 part per billion atoms (ppba) for some applications. Printable semiconductor elements having low levels of heavy metal impurities (e.g. less than about 1 parts per million atoms) are beneficial for applications and devices requiring good electronic performance, as the presence of heavy metals in semiconductor materials can severely degrade their electrical properties.
  • In addition, printable semiconductor elements of some aspects of the present invention have a very low resistivity gradient, for example a less than about 5% to 10% variation across their areas. This aspect of the present invention provides enhanced doping uniformity with respect to conventional semiconductor materials derived from “bottom up” processing techniques, such as nanowire and nanocrystal materials. Further, printable semiconductor elements of the present invention may comprise semiconductor materials exhibiting very few dislocations, for example less than 500 dislocations per square centimeter. Use of semiconductor elements comprising high quality semiconductor materials is beneficial for device fabrication applications requiring good electronic performance.
  • In addition, the present methods and compositions of matter provide printable semiconductor elements having highly uniform compositions. In this context, uniform composition refers to piece-to-piece uniformity with respect to purity, dopant concentrations, dopant spatial distributions and extents of crystallization. The high purities and good uniformity with respect to the composition of printable semiconductor elements of the present provide functional devices exhibiting enhanced reliability with respect to devices fabricated from conventional semiconductor materials derived from “bottom up” processing techniques, such as nanowire and nanocrystal materials.
  • Printable semiconductor elements of the present invention preferably have at least one smooth surface, such as the top or bottom surface of a microribbon, preferably exhibiting deviations from average surface position of less than 10 nanometers, and more preferably for some applications exhibiting deviations from average surface position of less than 1 Angstrom. Smooth surfaces of printable semiconductor elements of the present invention allow effective electrical contact and/or physical integration to be established with other device components in an integrated electronic device or optoelectronic device.
  • Alternatively, printable semiconductor elements of the present invention may comprise composite semiconductor elements having a semiconductor structure operationally connected to one or more additional structures, such as dielectric structures, conducting structures (e.g. electrode), additional semiconductor structures or any combination of these. Printable composite semiconductor elements provide materials and device components that may be easily and effectively integrated into complex electronic or optoelectronic devices. In addition, the assembly methods of the present invention allow printable semiconductor elements to be provided in array geometries wherein adjacent elements are close to each other, for example within 100 nanometers to 1 micron of each other. For example, a printable semiconductor element of the present invention comprises a unitary structure having a high quality semiconductor structure, such as a single crystalline inorganic semiconductor, operationally connected to an inorganic dielectric structure, such as a silicon oxide layer. This embodiment of the present invention is particular useful for fabrication of high performance thin film transistors because semiconductor and dielectric components may be assembled in a single printing step, and because use of unitary structures comprising both semiconductor and dielectric components results in insulator configurations exhibiting very low leakage of electric current from gate electrode to the semiconductor element or source and drain electrodes. In another embodiment, printable semiconductor elements of the present invention may comprise integrated functional devices, such as diodes, LEDs, transistors and OLEDS, which may be easily incorporated onto substrate surfaces.
  • The methods and compositions of the present invention provide a processing platform enabling fabrication of functional devices exhibiting enhanced reliability with respect to devices based on semiconductor materials generated via “bottom up” processing techniques, such as nanowires and nanocrystals. In this context, reliability refers to the capability of a functional devices to exhibit good electronic properties over extended operating periods and refers to piece-to-piece uniformity with respect to electrical properties of an ensemble of device fabricated using the present methods and compositions. For example, devices of the present invention exhibit very uniform threshold voltages (e.g. standard deviation of less than 0.08V) and very uniform device mobilities (e.g. standard deviation of less than about 13%). This represents improvements in uniformities of threshold voltages and device mobilities of a factor of about 40 and a factor of about 8, respectively, over nanowire based devices. The exceptional reliability of functional devices of the present invention is provided, at least in part, by the high degree of uniformity of the compositions and physical dimensions accessible using printable semiconductor elements of the present invention.
  • In another aspect, the present invention provides an electrical device comprising a first electrode, a second electrode and a printable semiconductor element positioned in electrical contact with said first and second electrodes. In one embodiment useful for applications requiring good electrical device performance, the printable semiconductor element comprises a unitary inorganic semiconductor structure having physical dimensions and shape that provides a fill factor between said first and second electrodes greater than or equal to about 20%, preferably greater than or equal to about 50% for some applications and more preferably greater than or equal to about 80% for some applications. Optionally, electrically devices of this embodiment may further comprise additional printable semiconductor elements, for example printable elements substantially longitudinally oriented, and optionally not in physical contact with each other. Importantly, multiple printable semiconductor elements of the present invention may be configured in devices or device arrays in a manner providing large fill factors (e.g. greater than or equal to 20%, 50% or 80%) and good electronic performance, in contrast to systems involving densely packed nanowire arrays. In one embodiment, the printable semiconductor element has at least one cross sectional dimension greater than or equal to about 500 nanometers. In one embodiment, the printable semiconductor element has a ratio of length to width equal to or less than about 10, preferably equal to or less than about 1.5 in for some applications. In one embodiment, the printable semiconductor element has a ratio of thickness to width equal to or less than about 0.1, preferably equal to or less than about 0.01 for some applications.
  • This aspect of the present invention further comprises arrays of electrical devices, such as transistors, diodes, photovoltaic devices, light emitting devices, comprising a first electrode, a second electrode and a plurality printable semiconductor elements positioned in electrical contact with the first and second electrode. In one embodiment, an array of electrical devices comprises over 20 printable semiconductor elements, preferably over 50 printable semiconductor elements for some applications and, more preferably over 100 printable semiconductor elements for some applications. In one embodiment useful for applications requiring good electrical device performance, the printable semiconductor elements provide a fill factor between said first and second electrodes greater than or equal to about 20%, preferably greater than or equal to about 50% for some applications and more preferably greater than or equal to about 80% for some applications. Printable semiconductor elements may be substantially longitudinally oriented with respect to a selected alignment axis, such as a selected alignment axis that extends along an axis which connects the closest points of said first and second electrical contacts. In one embodiment, the relative positions and orientations of the printable semiconductor elements are selected to within less than or equal to about 5 microns. In one embodiment providing good end to end registration of the semiconductor elements, each of said printable semiconductor elements extends a length and terminates in first and second ends. In this embodiment, the first ends of said printable semiconductor elements are positioned within 5 microns of the first electrode and the second ends of said printable semiconductor elements are positioned within 5 microns of said second electrode. In one embodiment, an array of electrical devices of the present invention comprises a plurality of printable semiconductors are provided in a configuration such that they are substantially longitudinally oriented, are not in physical contact with each other (i.e. do not overlap), and are in electrical contact with first and second electrodes. In one embodiment, at least one physical dimension, such as average length, average width and/or average thickness, of the printable semiconductor elements in the array of electrical devices varies by less than about 10%, preferably less than about 5% for some applications. In this embodiment, the printable semiconductor elements in the array have selected physical dimensions, such as average lengths, average widths and/or average thickness, that do not vary significantly (i.e. less than about 10%) from each other.
  • In another aspect, the present invention provides a transistor having a printable semiconductor element. In one embodiment, a transistor of the present invention comprises a source electrode, a printable semiconductor element, a gain electrode and a gate electrode. In this configuration, the source electrode and gain electrode are both in electrical contact with, and separated by, the printable semiconductor element, and the gate electrode is separated from the printable semiconductor element by the dielectric. The printable semiconductor element may comprise a unitary crystalline inorganic semiconductor structure having a thickness greater than or equal to about 50 nanometers, preferably for some applications greater than or equal to 100 nanometers and ever more preferably for some applications greater than or equal to 200 nanometers. The present invention also includes a transistor having a plurality of printable semiconductor elements in contact with source and drain electrodes. Use of a plurality of printable semiconductor elements in a single transistor may be beneficial in some applications because it may reduce the overall positional accuracy tolerances for various device components such as, source, drain and gate electrodes and dielectrics in field effect transistors. The present invention also includes embodiments wherein the printable semiconductor element is a stretchable semiconductor element. Use of one or more stretchable semiconductor elements in transistors of the present invention is beneficial because it provides good device performance and mechanical ruggedness in flexed, stretched or deformed device orientations.
  • In another embodiment, the present invention provides a high performance transistor supported by and/or in physical contact with a plastic substrate, such as a polyimide, polycarbonate or Mylar substrate. Transistors of this embodiment of the present invention may have a printable semiconductor element comprising a single crystalline inorganic semiconductor structure, such as a silicon or germanium. Such device configurations exhibit good device performance characteristics, such as field effect mobilities, threshold voltages, switching frequencies and on-off ratios. In an exemplary embodiment, a thin film transistor on a plastic substrate has a device field effect mobility comparable to the device field effect mobility of a transistor having a semiconductor element comprising a crystalline semiconductor fabricated by conventional high temperature processing methods, for example a device field effect mobility greater than or equal to 300 cm2V−1s−1, more preferably greater than or equal to 800 cm2V−1s−1. In another embodiment, the present invention provides a Si-MOS transistor having a single crystalline silicon printable semiconductor element capable of high frequency operation, such as operation at frequencies up to about 280 MHz.
  • In another embodiment, the present invention provides complementary metal-oxide semiconductor circuits comprising printable semiconductor elements. For example, printable semiconducting elements having lightly N (or P) type doped area between two highly P (or N) type doped area are used to form CMOS circuits. This capability is particularly interesting for applications requiring low power consumptions, as CMOS technology has a much smaller power dissipation over NMOS technology. Moreover, the CMOS technology has no static power dissipation, so this technology is particularly well suited for battery operated electronic systems. Finally, circuits design using CMOS technology are usually more compact than any over semiconductor technology, so more devices per surface area can be integrated.
  • In one embodiment, the dielectric and the semiconductor components of a transistor of this aspect of the present invention may comprise a unitary composite printable semiconductor element. Alternatively, the dielectric, gate electrode and semiconductor element of a transistor of this aspect of the present invention may comprise a unitary composite printable semiconductor element. Use of a composite printable semiconductor element having integrated semiconductor and insulator structures is preferred for some applications because it may provide very high quality dielectric-semiconductor interfaces in thin film transistors which exhibit very low leakage. In addition, use of a composite printable semiconductor element having integrated semiconductor and insulator structures also provides for efficient assembly of device components without the need for spin casting steps for integrating a dielectric layer in a thin film transistor.
  • In another embodiment, the present invention provides stretchable semiconductor elements capable of withstanding significant strain without fracturing. Stretchable semiconductor conductor elements of the present invention may exhibit good electronic performance even when undergoing significant strain, such as strain greater or equal about 0.5%, preferably 1% and more preferably 2%. Stretchable semiconductor elements of the present invention preferred for some applications are also flexible, and thus are capable of significant elongation, flexing, bending or deformation along one or more axes. Stretchable semiconductors that are flexible may also exhibit good electronic performance when in flexed, expanded, contracted, bent and/or deformed states. Stretchable and flexible semiconductor elements of the present invention may be printable, and may comprise composite semiconductor elements having a semiconductor structure operationally connected to other device components, such as dielectrics, electrodes and other semiconductors. The present invention includes a wide range of electronic and/or optoelectronic devices having stretchable and/or flexible semiconductor elements, such as transistors, diodes, LEDS, OLEDS, laser, micro- and nano-electromechanical devices.
  • A stretchable semiconductor element of the present invention comprises a flexible substrate having a supporting surface and a printable semiconductor structure having a curved internal surface. In this embodiment, at least a portion of the curved internal surface of the semiconductor structure is bonded to the supporting surface of the flexible substrate. Exemplary semiconductor structures having curved internal surfaces useful in present invention comprise bent semiconductor structures. In the context of this description, a “bent semiconductor structure” refers to a semiconductor structure having a curved conformation resulting from the application of a force. Bent semiconductor structures may have one or more folded regions. Bent semiconductor structures may be present in a coiled conformation or in a wrinkled conformation. Semiconductor structures having curved internal surfaces, such as bent semiconductor structures, may be bonded to a flexible substrate in a conformation that is under strain, such as a strain less than about 30%, a strain less than about 10% or a strain less than 1%.
  • Curved internal surfaces of stretchable semiconductors of the present invention may have any contour profile providing stretchablility or flexibility including, but not limited to, contour profiles characterized by at least one convex region, at least on concave region or a combination of at least one convex region and at least one concave region. In an embodiment, the curved internal surface of a stretchable and/or flexible semiconductor element has a contour profile characterized by a substantially periodic wave or a substantially aperiodic wave. In the context of this description, periodic and aperiodic waves may be any two or three dimensional wave form including but not limited to, sine waves, square waves, Aries functions, Gaussian waves, Lorentzian waves, or any combination of these. For example, an stretchable and flexible semiconductor element of the present invention comprises a bent semiconductor ribbon having a curved internal surface with a contour profile characterized by a substantially periodic wave extending along the length of the ribbon. Stretchable and flexible semiconductor elements of this embodiment may be expandable or contractible along an axis extending along the length of the ribbon, and may be bendable or deformable along one or more other axes.
  • The contour profile of semiconductor structures in this embodiment of the present invention may change when mechanical stressed or when forces are applied to the semiconductor element. Therefore, the ability to change contour profile of exemplary semiconductor structures may provide for their ability to expand, contract, flex, deform and/or bend without experiencing significant mechanical damage, fracture or a substantial reduction in electrical performance. The curved internal surface of the semiconductor structure may be continuously bonded to the supporting surface (i.e. bound at substantially all points along the curved internal surface). Alternatively, the curved internal surface of the semiconductor structure may be discontinuously bonded to the supporting surface, wherein the curved internal surface is bonded to the supporting surface at selected points along the curved internal surface.
  • The present invention also includes stretchable electronic devices and/or device components comprising a combination of a printable semiconductor structure and additional integrated device components, such as electrical contacts, electrodes, conducting layers, dielectric layers, and additional semiconductor layers (e.g. doped layers, P-N junctions etc.), all of which having curved internal surfaces that are supported by supporting surfaces of a flexible substrate. The curved internal surface configurations of the additional integrated device components enable then to exhibit good electronic performance even when undergoing significant strain, such as maintaining electrical conductivity or insulation with a semiconductor element while in a stretched or bent configuration. Additional integrated device components in this aspect of the present invention may have a bent configuration, such as a coiled or wrinkled configuration, as described above, and may be fabricated using techniques similar to those used to fabricate stretchable semiconductor elements. In one embodiment, for example, stretchable device components, including a stretchable semiconductor element, are fabricated independently and then interconnected. Alternatively, the semiconductor containing device may be fabricated in a planar configuration, and the resulting planar device is subsequently processed to provide curved internal surfaces to all or some of the device components.
  • Printable semiconductor elements of the present invention may comprise heterogeneous semiconductor elements exhibiting enhanced properties, such as enhanced mechanical, electrical, magnetic and/or optical properties, useful in a variety of device environments and configurations. Heterogeneous semiconductor elements are multicomponent structures comprising a semiconductor in combination with one or more additives. In this context of this description, additives comprise elements, molecules and complexes, aggregates and particles thereof, that are different from the semiconductor in which they are combined, such as additives having a different chemical compositions and/or physical states (e.g. crystalline, semicrystalline or amorphous states). Useful additives in this aspect of the invention include other semiconductor materials, N-type and P-type dopants such as arsenic, boron, and antimony, structural enhancers, dielectric materials and conducting materials. Heterogeneous semiconductor elements of the present invention include structures having spatial homogeneous compositions, such as uniformly doped semiconductor structures, and include structures having spatial inhomogeneous compositions, such as semiconductor structures having dopants with concentrations that vary spatially in one, two or three dimensions (i.e. a spatially inhomogeneous dopant distribution in the semiconductor element).
  • In another aspect, heterogeneous semiconductor elements comprise semiconductor structures having additional integrated functional device components, such as dielectric layers, electrodes, electrical contacts, doped contact layers, P-N junctions, additional semiconductor layers, and integrated multilayer stacks for charge confinement. Additional integrated functional device components of this aspect of the present invention include both semiconductor-containing structures and non-semiconductor-containing structures. In one embodiment, heterogeneous semiconductor elements comprise functional devices, such as transistors, diodes or solar cells, or multielement functional device components that are capable of being effectively patterned, assembled and/or interconnected on a substrate material.
  • Use of printable heterogeneous semiconductor elements provides certain advantages in the fabrication methods of the present invention. First, the “top down” processing approach of the present methods allows virtually any type of semiconductor processing, such as spatially controlled doping, to be carried out in fabrication steps separate from subsequent fabrication steps of (i) defining the spatial dimensions of the semiconductor elements and (ii) assembling the semiconductor elements on substrates and into functional devices. Separation of semiconductor processing from devices and device component assembly and interconnection in the present methods allows processing of semiconductor materials to be carried out under a range of conditions useful for generating very high quality semiconductor containing materials, including single crystal semiconductors having doped regions with well defined concentrations and spatial dopant distributions, and integrated, semiconductor multilayer stacks exhibiting high purities. For example, separation of semiconductor processing and device component assembly, allows for semiconductor processing at high temperatures and under conditions of highly controlled levels of impurities. Second, use of heterogeneous semiconductor elements comprising a plurality of integrated device components and/or functional devices allows for efficient high throughput printing of functional devices and arrays thereof in a commercially beneficial manner. For example, device fabrication methods of the present invention using heterogeneous semiconductor elements comprising a plurality of interconnected device components reduces the net number of fabrication steps and/or lowers the costs involved in manufacturing some devices.
  • In another aspect, the present invention provides methods of assembling, positioning, organizing, transferring, patterning and/or integrating printable semiconductor elements onto or into substrates via a range of printing methods, including dry transfer contact printing or solution printing techniques. Printing methods of the present invention are capable of integrating one or more semiconductor elements onto or into a substrate in a manner which does not substantially affect their electrical properties and/or mechanical characteristics. In addition, printing methods of the present invention are capable of assembling semiconductor elements onto or into selected regions of a substrate and in selected spatial orientations. Further, printing methods of the present invention are capable of integrating semiconductor elements and other device components into and/or onto a substrate in a manner providing high performing electronic and optoelectronic devices by establishing good conductivity between selected device components, good insulation between selected device components and/or good spatial alignment and relative positioning between device components.
  • In one embodiment of the present invention, semiconductor elements are assembled onto a substrate surface by dry transfer contact printing methods, such as soft lithographic microtransfer or nanotransfer methods. In one method, one or more printable semiconductor elements are contacted with a conformable transfer device having one or more contact surface(s). Contact established between the contact surface(s) and the printable semiconductor element(s) binds or associates the semiconductor element(s) to the contact surface(s). Optionally, conformal contact is established between the contact surface(s) and the printable semiconductor element(s) to facilitate binding or associate of these elements. At least a portion of the semiconductor element(s) disposed on the contact surface(s) is subsequently contacted with a receiving surface of the substrate. Optionally, the conformable transfer device also establishes conformal contact between the contact surface(s) having the semiconductor element(s) disposed thereon and at least a portion of the receiving surface. Separation of the contact surface of the conformable transfer device and the semiconductor element(s) transfers the semiconductor element(s) onto the receiving surface, thereby assembling the semiconductor element on the receiving surface of the substrate. In an embodiment preferred for device fabrication applications, printable semiconductor elements are positioned and/or integrated onto the substrate in selected regions and in selected spatial orientations. Optionally, the transfer process is repeated multiple times to provide patterning on large areas of a receiving surface of a substrate. In this embodiment, the transfer stamp having printable semiconductor elements is contacted with a different region of the receiving substrate for each successive patterning step. In this manner very large areas of a receiving surface may be pattern with semiconductor elements derived from a single mother wafer.
  • An advantage of the use of dry transfer contact printing methods in the present invention is that patterns of printable semiconductors elements may be transferred and assembled onto substrate surfaces in a manner preserving selected spatial orientations of semiconductor elements which define the pattern. This aspect of the present invention is particularly beneficial for applications wherein a plurality of printable semiconductor elements are fabricated in well defined positions and relative spatial orientations which directly correspond to a selected device configuration or array of device configurations. Transfer printing methods of the present invention are capable of transferring, positioning and assembling printable semiconductor elements and/o printable semiconductor containing functional devices including, but not limited to, transistors, optical waveguides, microelectromechanical systems, nanoelectromechanical systems, laser diodes, or fully formed circuits.
  • In another embodiment, the present invention provides selective transfer and assembly methods wherein some, but not all, of the printable semiconductors provided are transferred and assembled onto or into a substrate. In this embodiment, the conformable transfer device is capable of binding selectively to specific printable semiconductor elements provided. For example, the conformable transfer device may have a selected three dimensional relief pattern on its external surface having recessed regions and relief features. In this embodiment, recessed regions and relief features may be positioned such that only selected printable semiconductor elements are contacted by one or more contact surfaces provided by the relief pattern, and subsequently transferred and assembled onto the substrate surface. Alternatively, the conformable transfer device may have a contact surface or plurality of contact surfaces having a selected pattern of binding regions, such as chemically modified regions having hydroxyl groups extending from the contact surface and/or regions having one or more adhesive surface coatings. In this embodiment, only those semiconductor elements that are contacted with the binding regions on the contact surface(s) are bound to the transfer device, and subsequently transferred and assembled onto the substrate surface. An advantage of selective transfer and assembly methods of the present invention is that a first pattern of printable semiconductor elements characterized by a first set of positions and spatial orientations may be used to generate a second pattern of printable semiconductor elements different from the first pattern and characterized by a second set of positions and spatial orientations, corresponding to a selected device configuration or array of device configurations.
  • An exemplary conformable transfer device of the present invention comprises a dry transfer stamp, such as an elastomeric transfer stamp or composite, multi-layer patterning device. Conformable transfer devices useful for the present invention include patterning devices comprising a plurality of polymer layers as described in U.S. patent application Ser. No. 11/115,954, entitled “Composite Patterning Devices for Soft Lithography”, filed with the U.S. Patent and Trademark Office on Apr. 27, 2005, which is hereby incorporated by reference in its entirety. An exemplary patterning device useable in the methods of the present invention comprises a polymer layer having a low Young's Modulus, such as a poly(dimethylsiloxane) (PDMS) layer, preferably for some applications having a thickness selected from the range of about 1 micron to about 100 microns. Use of a low modulus polymer layer is beneficial because it provides transfer devices capable of establishing good conformal contact with one or more printable semiconductor elements, particularly printable semiconductor elements having curved, rough, flat, smooth and/or contoured exposed surfaces, and capable of establishing good conformal contact with substrate surfaces having a wide range of surface morphologies, such as curved, rough, flat, smooth and/or contoured substrate surfaces.
  • Optionally, transfer devices of the present invention may further comprise a second layer having an external surface opposite an internal surface, and having a high Young's modulus, such as high modulus polymer layer, ceramic layer, glass layer or metal layer. In this embodiment, the internal surface of the first polymer layer and the internal surface of the second high modulus layer are arranged such that a force applied to the external surface of the second high modulus layer is transmitted to the first polymer layer. Use of a high modulus second polymer layer (or backing layer) in transfer devices of the present invention is beneficial because it provides transfer devices having a net flexural rigidity large enough to provide good binding, transfer and assembly characteristics. For example, use of a transfer device having a net flexural rigidity selected from the range of about 1×10−7 Nm to about 1×10−5 Nm minimizes distortions of the positions of semiconductor elements and/or other structures bound to the contact surface(s) upon establishing conformal contact with a substrate surface. Use of a high modulus, rigid backing layer also is beneficial for preventing degradation of the printable semiconductor elements during transfer, for example by prevent cracking of the printable semiconductor layers. This attribute provides methods and devices of assembling printable semiconductor elements exhibiting high placement accuracy and good pattern fidelity. Transfer devices of the present invention may comprise additional layers, including polymer layers, for providing easy handling and maintenance, good thermal properties and for providing uniform distribution of a force applied to the transfer device to the entire contact surface(s), as taught in U.S. patent application Ser. No. 11/115,954, entitled “Composite Patterning Devices for Soft Lithography, filed with the U.S. Patent and Trademark Office on Apr. 27, 2005 which is incorporated by reference in its entirety herein.
  • In another approach, the principles of ‘soft adhesion’ are used to guide the transfer. Here, the viscoeleastic nature of the surface material on the transfer element leads to a peel force (i.e. the force that can lift objects from a surface) that depends on peel rate. At high peel rates, this force is large enough to remove objects from a substrate and transfer them onto a transfer element, even when the static surface energy of the transfer element is lower than that of the substrate. At low peel rates, this peel force is low. In some embodiments, by contacting a transfer element that supports an array of objects against a final substrate, and then peeling the element away slowly leads to the transfer of these objects from the transfer element to the substrate. This approach of the present invention using controlled peeling rates can be used in combination with the other transfer approaches described herein.
  • Transfer devices of the present invention may have a single continuous contact surface or a plurality of discontinuous contact surfaces. The contact surface(s) of transfer devices of the present invention may be defined by a selected three-dimensional dimensional relief pattern having recessed regions and relief features having selected physical dimensions. Contact surfaces useful in the present invention may be capable of binding printable semiconductor elements by van der Waals forces, covalent bonds, adhesive layers, chemically modified regions such as regions having hydroxyl groups disposed on their surfaces, dipole-dipole forces or combinations of these. Transfer devices of the present invention may have contact surfaces having any area.
  • A number of methods may be used to facilitate transfer of printable semiconductor elements from a contact surface into or onto a substrate surface. In an exemplary embodiment, the difference in surface energy of the substrate surface and the contact surface promotes transfer to the substrate surface. For example, transfer may be effectively achieved from a contact surface comprised of a PDMS layer having a lower surface energy to a substrate surface having a higher surface energy, such as a polyimide, polycarbonate or Mylar surface. In addition, a plastic substrate surface may be softened or partially melted by heating prior to and/or during contact with printable semiconductor elements to be transferred, thereby generating semiconductor elements embedded in the substrate. Allowing the substrate to cool and harden prior to separation of the contact surface from the semiconductor elements promotes efficient transfer. Alternatively, the substrate surface may have one or more chemical modified regions exhibiting an enhanced affinity of the substrate for the semiconductor elements. For example, modified regions may be covered by one or more adhesive layers or may be modified such that they undergo efficient covalent bonding, attractive van der Waals forces, dipole-dipole forces or combinations of these with semiconductor elements to promote efficient transfer and assembly. Alternatively, a partial polymerized polymer precursor may be contacted with the semiconductor elements or other device components and, subsequently polymerized, resulting in formation of a substrate having semiconductor elements embedded therein.
  • In an exemplary embodiment, printable semiconductor elements are fabricated having top surfaces coated with a thin release layer, such as a layer of photoresist used as a photomask patterned onto a substrate during the definition and fabrication of the printable semiconductor elements. The contact surface of a conformable transfer device is brought into conformal contact with the coated surfaces of the printable semiconductor element. The release layer facilitates bonding of the printable semiconductor elements to the contact surface of the transfer device. Surfaces of the printable semiconductor elements not coated with the release layer are then contacted with a receiving surface of a substrate. Next, the release layer is removed, for example by exposure to an appropriate solvent such as acetone, thereby separating the printable semiconductor elements from conformable transfer device. Optionally, the receiving surface may be coated with one or more adhesive layers to facilitate transfer of the printable semiconductor elements.
  • In another embodiment of the present invention, printable semiconductor elements are assembled onto a substrate surface by solution printing. In the context of this description, the term “solution printing” is intended to refer to processes whereby one or more structures, such as printable semiconductor elements, are dispersed into a carrier medium, such as a carrier fluid or solvent, and delivered in a concerted manner to selected regions of a substrate surface. In an exemplary solution printing method, delivery of structures to selected regions of a substrate surface is achieved by methods that are independent of the morphology and/or physical characteristics of the substrate surface undergoing patterning. In another embodiment, printable semiconductor elements remain suspended in a solvent until the solvent evaporates, or until an applied force, such as an electrostatic force, magnetic force or force provided by an acoustic wave, pulls the printable semiconductor elements out of solution and onto selected regions of the substrate. This functionality may be provided by selection of appropriate physical dimensions and masses of the printable semiconductor elements necessary to avoid premature sedimentation. In this way, the solution printing methods of the present invention differ materially from some fluidic self assembly methods in which elements suspended in a carrier medium fall out of solution due to the force of gravity and statistically fall into recessed regions of a substrate.
  • A method of assembling a printable semiconductor element on a receiving surface of a substrate of the present invention comprises the step dispersing a printable semiconductor element in a carrier medium, thereby generating a suspension comprising the semiconductor element in the carrier medium. The semiconductor element is delivered to the substrate by solution printing the suspension onto the receiving surface, thereby assembling the semiconductor element onto said receiving surface. In this embodiment, solution printing may be provided by a number of techniques known in the art including, but not limited to, ink jet printing, thermal transfer printing, and screen printing. Solution printing methods of the present invention may also employ self assembly alignment techniques. In one embodiment, for example, alignment, positioning and registration of printable semiconductor elements having patterned hydrophobic and hydrophilic groups are aligned on a receiving surface having complimentary patterned hydrophobic regions (such as methyl terminated surface groups) and hydrophilic regions (such as carboxylic acid terminated surface groups). Solution printing methods of the present invention may also employ capillary action of drops containing dispersed printable semiconductor elements to achieve alignment, positioning and registration.
  • Optionally, a number of methods may be used in the present invention to control the orientation, alignment and selective deposition of semiconductor elements and/or other device components on the substrate surface. These methods enable fabrication of complex integrated electronic and optoelectronic devices comprising a plurality of interconnected device components having precisely specified relative positions and spatial orientations. For example, electrostatic forces, acoustic waves and/or magnetostatic forces may be employed to facilitate positioning semiconductor elements and other device components in specific locations and in selected spatial orientations on a substrate surface. Alternatively, the properties and/or composition of the substrate surface itself may be modified in selected regions to achieve accurate placement of semiconductor elements and other device components. For example, selected regions of the substrate surface may be chemically modified such that they exhibit a selective affinity for semiconductor elements. In addition, the electrical properties of the substrate surface may be modified, for example by formation of potential holes in specific surface regions, to facilitate selective integration, orientation and alignment of printable semiconductor elements and other device components.
  • Printing methods of the present invention have a number of advantages important for the fabrication of high performance electronic and/or optoelectronic devices. First, printing methods of the present invention are capable of transferring and assembling inorganic single crystalline semiconductor structures without exposing these structures to mechanical strain large enough to induce significant damage or degradation, such as damage from cracking. Second, printing methods of the present invention are capable of positioning one or more semiconductor elements on selected regions of a substrate surface in selected orientations with good placement accuracy (i.e. good spatial registration with respect to a selected region of a receiving surface), preferably with spatial deviations from absolutely correct orientations and locations on a substrate less than or equal to 5 microns. Third, printing methods of the present invention are capable of generating patterns comprising a plurality of semiconductor elements, other device elements, integrated function devices or any combination of these having good fidelity with respect to a selected spatial configuration, such as a spatial configuration corresponding to a functional device or array of devices. Fourth, printing methods of the present invention may be carried out at relatively low temperatures (i.e. temperatures less than about 400 Celsius), and therefore are compatible with a wide range of substrates, particularly plastic substrates. Finally, printing methods of the present invention provide a low cost means of fabricating high performance electronic and/or optoelectronic devices, and do not require clean room conditions.
  • The present compositions and related methods of assembling, positioning, organizing, transferring, patterning and/or integrating printable semiconductor elements onto or into substrates may be used to fabricate virtually any structure comprising one or more semiconductor elements. These methods are particularly useful for fabricating complex integrated electronic or optoelectronic devices or device arrays, such as arrays of diodes, light emitting diodes, solar cells, transistors (FET and bipolar), and thin film transistors. The present compositions and related methods are also useful for fabrication of systems level integrated electrical circuits, such as complementary logic circuits, wherein printable semiconductor elements are printed onto a substrate in well defined spatial orientations and interconnected to form a desired circuit design. In one embodiment of this aspect of the invention, printable N-type and P-type heterogeneous semiconductor elements with selected dopant concentrations and dopant spatial distributions are assembled and interconnected to fabricate complex integrated circuits. In another embodiment, a plurality of printable semiconductor elements comprising different semiconductor materials are printed onto the same substrate and interconnected to fabricate complex integrated circuits.
  • The assembly methods of the present invention, however, are not limited to semiconductors. Rather these methods are broadly compatible with a wide range of materials that are not semiconductors. Materials that may be transferred and/or assembled by the methods of the present invention include, but are not limited to, insulating materials such as SiO2, connecting materials such as conductors, optical elements such as active optical materials, passive optical materials and fiber optic elements, materials for sensing applications and magnetic materials. Accordingly, the present methods, devices and device components may be used to fabricate a wide range of microsized and/or nanosized structures and assemblies of structures, such as microfluidic devices and structures, NEMS devices and arrays of NEMS devices and MEMS devices and arrays of MEMS devices. Particularly, the transfer and assembly methods of the present invention may be used to generate complex three-dimensional structures, such as integrated circuits, by sequential overlay of a plurality of printing levels.
  • The present compositions, and related fabrication, assembly and interconnection methods are useful for fabricating devices, particularly semiconductor based devices, on large areas of a wide range of substrates. A benefit of the present methods is that they are compatible with device assembly at temperatures that are compatible with most flexible substrates, including polymer materials such as thermoplastic materials, thermoset materials, reinforced polymer materials and composite polymer materials. However, the present methods are equally applicable to device fabrication on rigid and/or brittle substrates including ceramic materials, glasses, dielectric materials, conductors, metals and semiconductor materials. The applicability of these methods to device fabrication on brittle materials arises from the very low force imparted to substrates using the printing methods of the present invention. The present compositions and fabrication methods are also compatible with device fabrication on more unusual substrate materials, such as paper, wood and rubber, and contoured substrates, including curved substrates, curved rigid substrates, concave substrates, and convex substrates. For example, the present methods are capable of assembling and integrating printable semiconductor elements and other device components (e.g. electrodes, dielectric layers, P-N junctions etc.) on substrates, including rigid and flexible substrates, having a radius of curvature ranging from about 10 microns to about 10 meters.
  • In another aspect, the present fabrication methods are capable of heterogeneous integration of printable semiconductor elements into functional substrates. For example, the printing methods of the present invention are capable of depositing and integrating printable semiconductor elements into substrates having well defined semiconductor regions, conducting regions and/or insulating regions. An advantage of the present fabrication methods is that printable semiconductor elements can be printed onto functional substrates, such as integrated circuits or components of integrated circuits, in selected orientations and positions with high placement accuracy, particularly in the context of dry transfer contact printing methods of the present invention.
  • Printable semiconductor elements of the present invention may be fabricated from a wide range of materials. Useful precursor materials for fabricating printable semiconductor elements include semiconductor wafer sources, including bulk semiconductor wafers such as single crystalline silicon wafers, polycrystalline silicon wafers, germanium wafers; ultra thin semiconductor wafers such as ultra thin silicon wafers; doped semiconductor wafers such as P-type or N-type doped wafers and wafers with selected spatial distributions of dopants (semiconductor on insulator wafers such as silicon on insulator (e.g. Si—SiO2, SiGe); and semiconductor on substrate wafers such as silicon on substrate wafers and silicon on insulator. Further, printable semiconductor elements of the present invention may be fabricated from scrape or unused high quality or reprocessed semiconductor materials that are left over from semiconductor device processing using conventional methods. In addition, printable semiconductor elements of the present invention may be fabricated from a variety of nonwafer sources, such as a thin films of amorphous, polycrystalline and single crystal semiconductor materials (e.g. polycrystalline silicon, amorphous silicon, polycrystalline GaAs and amorphous GaAs) that is deposited on a sacrificial layer or substrate (e.g. SiN or SiO2) and subsequently annealed.
  • The present invention also includes methods of making printable semiconductor elements and flexible semiconductor elements. These methods enable fabrication of printable semiconductor elements and flexible semiconductor elements from a wide range of precursor materials, such as silicon on insulator wafers, single crystalline silicon wafers, thin films of polycrystalline crystalline silicon, ultra thin silicon wafers and germanium wafers. In addition, these methods are capable of generating printable semiconductor elements having a wide range of shapes and physical dimensions. Further, the present methods enable low cost fabrication of large arrays/patterns of printable semiconductor elements in well defined, relative spatial orientations.
  • In another aspect, the present invention provides a method for assembling a printable semiconductor element on a receiving surface of a substrate comprising the steps of: (1) providing the printable semiconductor element comprising a unitary inorganic semiconductor structure; (2) contacting the printable semiconductor element with a conformable transfer device having a contact surface, wherein contact between the contact surface and the printable semiconductor element binds or associates the printable semiconductor element to the contact surface, thereby forming the contact surface having the printable semiconductor element disposed thereon; (3) contacting the printable semiconductor element disposed on the contact surface with the receiving surface of the substrate; and (4) separating the contact surface of the conformable transfer device and the printable semiconductor element, wherein the printable semiconductor element is transferred onto the receiving surface, thereby assembling the printable semiconductor element on the receiving surface of the substrate. In one embodiment, this method of the present invention further comprises the steps of: (1) providing additional printable semiconductor elements each of which comprising a unitary inorganic semiconductor structure; (2) contacting the printable semiconductor elements with a conformable transfer device having a contact surface, wherein contact between the contact surface and the printable semiconductor element binds or associates the printable semiconductor elements to the contact surface and generates the contact surface having the printable semiconductor elements disposed thereon in relative orientations comprising a selected pattern of the printable semiconductor elements; (3) contacting the printable semiconductor elements disposed on the contact surface with the receiving surface of the substrate; and (4) separating the contact surface of the conformable transfer device and the printable semiconductor elements, wherein the printable semiconductor elements are transferred onto the receiving surface in the relative orientations comprising the selected pattern.
  • In another aspect, the present invention provides a method for assembling a printable semiconductor element on a receiving surface of a substrate comprising the steps of: (1) providing the printable semiconductor element comprising a unitary inorganic semiconductor structure, wherein the printable semiconductor element has at least one cross sectional dimension greater than or equal to about 500 nanometers; (2) dispersing the semiconductor element in a solvent, thereby generating a suspension comprising the semiconductor element in the solvent; and (3) delivering the semiconductor element to the substrate by solution printing the suspension onto the receiving surface thereby assembling the semiconductor element onto the receiving surface. In one embodiment, this method of the present invention further comprises the steps: (1) providing additional printable semiconductor elements, wherein each of the additional printable semiconductor elements has at least one cross sectional dimension greater than or equal to about 500 nanometers; (2) dispersing the semiconductor elements in the solvent, thereby generating a suspension comprising the semiconductor elements in the solvent; and (3) delivering the semiconductor elements to the substrate by solution printing the suspension onto the receiving surface, thereby assembling the semiconductor elements onto the receiving surface.
  • In another aspect, the present invention provides a method of fabricating a printable semiconductor element comprising the steps of: (1) providing a wafer having an external surface, the wafer comprising a semiconductor; (2) masking a selected region of the external surface by applying a mask; (3) etching (optionally anisotropically etching) the external surface of the wafer, thereby generating a relief structure on the wafer and at least one exposed surface of the wafer, wherein the relief structure has a masked side and one or more unmasked sides; (4) applying a mask to at least a portion of the unmasked sides of the relief structure; (5) at least partially etching the exposed surfaces of the wafer, thereby releasing a portion of the relief structure from the wafer and fabricating the printable semiconductor element. In this embodiment, mask may be applied to the unmasked sides of the relief structure by angled deposition methods, such as sputtering or vapor deposition, or by flowing a portion of the mask on the external surface onto the unmasked sides
  • In another aspect, the present invention provides a method of fabricating a printable semiconductor element comprising the steps of: (1) providing a wafer having an external surface, the wafer comprising a semiconductor; (2) masking selected regions of the external surface by applying a first mask; (3) etching (optionally anisotropically etching) the external surface of the wafer, thereby generating a plurality of relief structures; (4) annealing the wafer, thereby generating an annealed external surface; (5) masking selected regions of the annealed external surface by applying a second mask; and (6) etching (optionally anisotropically etching) the annealed external surface, thereby generating the semiconductor element.
  • In another aspect, the present invention provides a method of fabricating a printable semiconductor element comprising the steps of: (1) providing an ultra thin wafer having an external surface, the wafer comprising a semiconductor and having a selected thickness along an axis orthogonal to the external surface; (2) masking selected regions of the external surface by applying a mask; (3) etching (optionally anisotropically etching) the external surface of the wafer, wherein the wafer is etched throughout the thickness along the axis orthogonal to the external surface, thereby generating the printable semiconductor element.
  • In another embodiment, the present invention provides a method for making a flexible semiconductor element comprising the steps of: (1) providing a printable semiconductor structure having an internal surface; (2) providing a prestrained elastic substrate in an expanded state, wherein the elastic substrate has an external surface; and (3) bonding the internal surface of the printable semiconductor structure to the external surface of the prestrained elastic substrate in an expanded state; and allowing the elastic substrate to relax at least partially to a relaxed state, wherein relaxation of the elastic substrate bends the internal surface of the printable semiconductor structure thereby generating a semiconductor element having a curved internal surface. In an exemplary embodiment, the prestrained elastic substrate is expanded along a first axis, a second axis orthogonal to the first axis or both. The prestrained elastic substrate in an expanded state may be formed by bending the elastic substrate or rolling the elastic substrate. Optionally, the method of this aspect of the present invention may further comprise the step of transferring the semiconductor having a curved internal surface to a receiving substrate that is flexible.
  • In another embodiment, the present invention provides a method for fabricating a printable semiconductor element connected to a mother wafer via one or more alignment maintaining elements comprising the steps of: (1) providing the mother wafer having an external surface, the wafer comprising an inorganic semiconductor material; (2) masking a selected region of the external surface by applying a mask; (3) etching the external surface of the wafer, thereby generating a relief structure and at least one exposed surface of the wafer, wherein the relief structure has a masked side and one or more unmasked sides; (4) etching the exposed surfaces of the wafer; and (5) stopping etching of the exposed structure so that complete release of the relief structure is prevented, thereby fabricating the printable semiconductor element connected to a mother wafer via one or more alignment maintaining elements. In one embodiment of this method the printable semiconductor element has a peanut shape with a first end and a second end, wherein the alignment maintaining elements connect the first and second ends of the printable semiconductor element to the mother wafer. In another embodiment of this method the printable semiconductor element has a ribbon shape with a first end and a second end, wherein the alignment maintaining elements connect the first and second ends of the printable semiconductor element to the mother wafer.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 schematically illustrates an exemplary method of the present invention for producing and assembling printable semiconductor elements comprising ribbons of single crystalline silicon.
  • FIG. 2 provides a schematic diagram illustrating a selective dry transfer contact printing method for assembling printable semiconductor element on a receiving surface of a substrate.
  • FIGS. 3A-C, are schematic diagrams showing devices, device configurations and device components useful in selective dry transfer contact printing methods of the present invention. FIG. 3D provides a photograph of an array of photodiodes printed onto a spherical surface of a polycarbonate lens (FL 100 mm). FIG. 3E provides a scanning electron micrograph of an array of photodiodes printed onto the curved surface of a spherical glass lens (FL 1000 mm). Contrast in the image provided in FIG. 3E is slightly enhanced to show p-doped regions. FIG. 3F provides a plot of electric current (μA) verse bias potential (volts) illustrating the light response of the photodiodes pictured in FIG. 3E.
  • FIGS. 4A1 and 4A2 show a preferred shape of a printable semiconductor element for assembly methods of the present invention using dry transfer contact printing. FIG. 4A1 provides a perspective view and FIG. 4A2 provides a top plan view. FIGS. 4B1 and 4B2 show a preferred shape of a printable semiconductor element for assembly methods of the present invention using dry transfer contact printing. FIG. 4B1 provides a perspective view and FIG. 4B2 provides a top plan view.
  • FIGS. 5A-C presents optical and scanning electron micrographs of a range of printable semiconductor elements comprising microstrips of single crystalline silicon having selected physical dimensions
  • FIG. 6 presents an image of transferred printable semiconductor elements comprising single crystalline silicon microstrips on a PDMS coated polyimide sheet.
  • FIG. 7 presents an optical micrograph image of a thin film transistor having a printable semiconductor element.
  • FIG. 8 provides a plot showing current-voltage (IV) characteristics of a device made on a pre-oxidized Si wafer.
  • FIG. 9 provides a plot showing transfer characteristics measured at VDS=0.1 V of a device made on a Mylar sheet coated with ITO gate and polymer dielectric.
  • FIGS. 10 A-H provide a schematic diagrams illustrating a method of the present invention for making an array of thin film transistors having composite printable semiconductor elements.
  • FIGS. 11A-D provide diagrams illustrating a method of the present invention for making a printable device comprising integrated gate electrode, gate dielectric, semiconductor, source electrode and drain electrode.
  • FIG. 12 provides an atomic force micrograph showing a stretchable printable semiconductor element of the present invention.
  • FIG. 13 shows an atomic force micrograph providing an expanded view of a semiconductor structure having curved internal surface.
  • FIG. 14 shows an atomic force micrograph of an array of stretchable printable semiconductor elements of the present invention.
  • FIG. 15 shows optical micrographs of stretchable printable semiconductor elements of the present invention.
  • FIG. 16 shows an atomic force micrograph of a stretchable printable semiconductor element of the present invention having a semiconductor structure bonded to a flexible substrate having a three dimensional relief pattern on its supporting surface.
  • FIG. 17 shows a flow diagram illustrating an exemplary method of making a stretchable semiconductor element of the present invention.
  • FIG. 18A shows an exemplary method of making printable semiconductor elements from a Si—Ge epi substrate.
  • FIG. 18B shows an exemplary method for fabricating printable semiconductor elements from a bulk silicon substrate, preferably a single crystalline silicon substrate.
  • FIG. 18C shows another exemplary method of fabricating printable semiconductor elements from a bulk silicon substrate, preferably a single crystalline silicon substrate.
  • FIG. 18D shows yet another exemplary method of fabricating printable semiconductor elements from a bulk silicon substrate, preferably a single crystalline silicon substrate.
  • FIG. 18E shows an exemplary method of fabricating printable semiconductor elements from an ultra thin silicon substrate.
  • FIG. 18F shows an exemplary method for making printable semiconductor elements from a thin film of polycrystalline silicon on a supporting substrate.
  • FIG. 18G shows an exemplary method for making printable semiconductor elements from a thin film of polycrystalline silicon on a SiO2 substrate.
  • FIGS. 18H(1) and 18H(2) illustrate a method for making single crystalline semiconductor thin films using printable semiconductor elements of the present invention.
  • FIG. 18I shows an exemplary method of fabricating printable semiconductor elements comprising micro-wires from GaAs substrate.
  • FIG. 18J shows an alternative method for fabricating printable semiconductor elements comprising single crystalline silicon ribbons.
  • FIG. 18K shows an alternative method for fabricating printable semiconductor elements comprising single crystalline silicon ribbons.
  • FIG. 19 provides a schematic diagram illustrating the steps of an exemplary method of generating and transferring nanowire arrays of GaAs to a substrate, such as plastic substrate comprising poly(ethylene terephthalate) (PET) sheet coated with a thin layer of cured polyurethane (PU).
  • FIG. 20A provides a scanning electron micrograph of free-standing GaAs wires obtained from GaAs wafer patterned with isolated SiO2 lines. FIGS. 20B-E show scanning electron micrograph images of individual wires obtained by etching the GaAs wafer patterned with 2 μm wide SiO2 lines. FIG. 20F provides a plot showing the dependence of the average width, w wires, of the top surfaces of wires fabricated by the present methods on etching time.
  • FIGS. 21A-G shows images of a variety of GaAs wire arrays printed on PDMS and PU/PET substrates.
  • FIGS. 22A-C shows scanning electron micrograph images of an InP wire array on PMDS and PU/PET substrates.
  • FIG. 23A provides a schematic diagram and image of an exemplary two terminal diode device comprising GaAs wire arrays. FIG. 23B shows the current-voltage (I-V) curves recorded for the two terminal diode device at different bend radii indicating that the two terminal diode device comprising GaAs wire arrays exhibited expected diode characteristics. FIG. 23C shows the current-voltage (I-V) curves measured for the two terminal diode device after relaxation after bending at different bend radii.
  • FIG. 24 provides a schematic diagram illustrating an exemplary method of the present invention for solution printing printable semiconductor elements having handle elements comprising magnetic tags.
  • FIG. 25 provides several optical images demonstrating the use of solution printing methods of the present invention to generate well order arrays of microstructures having handle elements comprising thin nickel layers.
  • FIG. 26A illustrates the steps used to fabricate exemplary bendable thin film transistors devices of the present invention. FIG. 26B presents a schematic illustration of the bottom gate device configuration of the thin film transistor together with high and low magnification optical images of part of the device array.
  • FIG. 27A presents current voltage characteristics of a bendable thin film transistor of the present invention that shows an effective device mobility of 140 cm2/Vs in the saturation regime and 260 cm2/Vs in the linear regime, as evaluated by application of standard field effect transistor models that ignore the effects of contacts. FIG. 27B presents transfer characteristics of several devices, plotted on linear (left axis) and logarithmic (right axis) scales. FIG. 27C shows the distribution of the linear effective mobilities of several bendable thin film transistors fabricate by the present methods.
  • FIG. 28A presents a high-resolution scanning electron micrograph of solution cast ribbons (left inset) illustrating the remarkable flexibility of the printable single crystal silicon semiconductor elements. The right inset in FIG. 28 shows a picture of the experimental setup used to bend the bendable thin film transistors evaluated in this study. FIG. 28B shows the small (˜<1%) linear variation of the epoxy dielectric capacitance when subject to tensile and compressive strains (see top inset). The lower inset in FIG. 28B presents the variation of the saturation current of a device measured for a gate and drain bias voltages of both 4 V.
  • FIG. 29A presents a schematic representation of a fabrication process for generating transistors comprising printable heterogeneous semiconductor elements on a PET substrate. FIG. 29B shows optical images of several devices having heterogeneous printable semiconductor elements fabricated using the present techniques.
  • FIG. 30A shows a plot of the normalized resistance, RtotalW,as as a function of L. for an arrangement of printable heterogeneous semiconductor elements and contact pads used to characterize the contact resistances (see inset). FIG. 30B shows Time-of-Flight Secondary Ion Mass Spectroscopy (TOF-SIMS) measurements that show the use of patterned SOG as a diffusion barrier (See, Schematic in FIG. 29A) localizes the dopants to desired regions in the silicon. In the image shown in FIG. 30B, the bright red color indicates high phosphorous concentration.
  • FIGS. 31A-D shows measurements corresponding to transistors comprising printable contact doped silicon semiconductor elements on an epoxy/ITO/PET substrate. FIG. 31A provides typical current-voltage characteristics of a single crystal silicon transistor with doped contacts on a PET substrate, with L=7 microns and W=200 microns. From the bottom to top, VG varies from −2 V to 6 V. FIG. 31 B provides transfer curves (Vd=0.1 V) of devices with channel lengths, from top to bottom, of 97 microns, 72 microns, 47 microns, 22 microns, 7 microns, and 2 microns. The channel width in each case is 200 microns. FIG. 31C shows the width-normalized resistance of devices in the ON state (RonW) as a function of channel length L at different gate voltages. The solid lines represent linear fits. The scaling is consistent with contacts that have negligible influence on device performance for this range of channel lengths. the inset in FIG. 31C shows the sheet conductance [Δ(RonW)/ΔL]−1, determined from the reciprocal of the slopes of the linear fitting in FIG. 31C, as a function of gate voltage. FIG. 31D shows effective mobility, evaluated in the linear regime, as a function of channel length for the devices with undoped (triangle) and doped (square) contacts.
  • FIG. 32A shows the change of the effective device mobility, normalized by the value in the unbent state, μ0eff, as a function of strain (or bending radius). FIG. 32B presents normalized effective mobilities μeff0eff after several hundred bending cycles (to a radius of 9.2 mm) that cause compressive strain at the device to vary between 0 and 0.98%.
  • FIG. 33 shows an example of a composite semiconductor structure fabricated using a heterogeneous integration method of the present invention comprising gallium nitride microstructures direct-bonded onto a silicon wafer (1 0 0).
  • FIG. 34A provides a process flow diagram schematically illustrating processing steps in a fabrication pathway for making a solar cell comprising a printable P-N junction. 34B shows a schematic diagram of a solar cell device configuration generated by the fabrication pathway illustrated in FIG. 34A. FIG. 34C shows the photodiode response observed upon illumination of a solar cell device having the configuration shown in FIG. 34B.
  • FIG. 35A provides a process flow diagram schematically illustrating processing steps in an alternative fabrication pathway for making a solar cell comprising printable P and N doped semiconductor layers. FIG. 35B shows a schematic diagram of a solar cell device generated using the fabrication pathway illustrated in FIG. 35A. FIG. 35C shows a SEM image of a top view of the solar cell schematically depicted in FIG. 35B. FIG. 35D provides a plot of current verse bias demonstrating the photodiode response of the solar cell shown in FIG. 35C. FIG. 35E shows plots of current verse bias corresponding to several different illumination intensities demonstrating the photodiode response of the solar cell shown in FIG. 35C.
  • FIG. 36A shows a process flow diagram illustrating an exemplary method of making an array of stretchable thin film transistors. FIG. 36B shows provides optical micrographs of an array of stretchable thin film transistors in relaxed and stretched configurations.
  • FIG. 37A provides a schematic diagram showing a processing method of the present invention (Method I) for patterning μs-Si elements onto a plastic substrate. FIG. 37B provides a schematic diagram illustrating an alternative processing method of the present invention (Method II) for patterning μs-Si elements onto a plastic substrate.
  • FIG. 38A shows the design of the so-called peanut shaped μs-Si objects used in methods of the present invention. Inset optical image in FIG. 38A shows the optimized HF etching condition where the buried oxide under the channel is removed while a sacrificial SiO2 portion remains. FIG. 38B shows an example of lost of this order when the Si objects are overetched in HF solution. FIGS. 38C, 38D, 38E and 38F shows a series of micrographs that depicts the progression of each step of the μs-Si transfer as effected using Method I.
  • FIGS. 39A and 39B provide optical images of the selective transfer of the μs-Si onto PU/PET sheet by 3600 PDMS stamp. FIG. 39C is an optical micrograph of a section of a Sylgard 184 coated PET substrate to which the μs-Si has been chemically bonded and subsequently transferred. A higher magnification image of the μs-Si transferred in this way is shown in FIG. 39D.
  • FIG. 40A illustrates an exemplary device geometry of a device fabricated using the peanut shaped μs-Si based on a transfer using Method I. FIG. 40B provides I-V curves of μs-Si TFTs at a range of gate voltage (Vg=−2.5 V to 20 V). FIG. 40C shows the transfer characteristics, measured at a constant source-drain voltage (Vsd=1V), indicated the effective mobility was 173 cm2/Vs. The inset in FIG. 40C shows an optical micrograph of actual device of the present invention.
  • FIG. 41 provides a schematic process flow diagram depicting steps involved in the process for fabricating μs-GaAs MESFETs on a poly(ethylene terephthalate) (PET) substrate. Anisotropic chemical etching produces wires from a standard (100) GaAs wafer. A printing technique that uses an elastomeric stamp transfers these wires from the wafer to the plastic device substrate in a manner that preserves spatial organization (i.e. ordered arrays). PR denotes photoresist.
  • FIG. 42A presents a schematic showing a cross section view of the geometry of a GaAs wire based MESFET on a plastic substrate (PU/PET). The source/drain electrodes form ohmic contacts to the n-GaAs layer. FIG. 42B shows a representative image of two GaAs wire based MESFETs on plastic each of which uses an array of ten GaAs wires, fabricated according to the process flow diagram of FIG. 41. FIG. 42C shows the image of a 2 cm×2 cm PET sheet with hundreds of transistors, clearly demonstrating its flexibility.
  • FIGS. 43A, 43B and 43C present results from a GaAs MESFET with a channel length of 50 μm, a gate length of 15 μm, similar to the one shown in FIG. 42B. FIG. 43A shows the current-voltage (between drain and source electrodes) curves at gate voltages between 0.5 to −2.0 V with steps of 0.5 V. FIG. 43B shows the transfer characteristics (i.e., IDS vs. VGS) of a GaAs MESFET of the present invention measured at different VDS. FIG. 43C shows the transfer curve at VDS=4 V, plotted as (IDS)1/2 vs. VGS, clearly showing a linear relationship as expected for a MESFET.
  • FIGS. 44A and 44B show gate-modulated current-voltage characteristics of a GaAs wire based MESFET on a flexible PET substrate (A) before bending; (B) after bending to a bend radius of 8.4 mm. FIG. 44C shows the gate-modulated current-voltage characteristics of the GaAs wire based MESFET after relaxing the bent substrate to its flat, unbent state. FIG. 44D shows the variation of IDS at VDS=4 V and VGS=0 V in 3 cycles in terms of bending (with different surface strains)/unbending, indicating that these MESFETs survive multiple bending cycles that cause the tensile strain at the device to vary between 0% and 1.2%, without significant change of their performance (<20%).
  • FIG. 45 provides a schematic diagram illustrating an exemplary device configuration of the present invention for a P type bottom gate thin film transistor on a plastic substrate.
  • FIG. 46 provides a schematic diagram illustrating an exemplary device configuration of the present invention for a complementary logic gate on a plastic substrate.
  • FIG. 47 provides a schematic diagram illustrating an exemplary device configuration of the present invention for a top gate thin film transistor on a plastic substrate.
  • DETAILED DESCRIPTION OF THE INVENTION
  • Referring to the drawings, like numerals indicate like elements and the same number appearing in more than one drawing refers to the same element. In addition, hereinafter, the following definitions apply:
  • “Printable” relates to materials, structures, device components and/or integrated functional devices that are capable of transfer, assembly, patterning, organizing and/or integrating onto or into substrates without exposure of the substrate to high temperatures (i.e. at temperatures less than or equal to about 400 degrees Celsius). In one embodiment of the present invention, printable materials, elements, device components and devices are capable of transfer, assembly, patterning, organizing and/or integrating onto or into substrates via solution printing or dry transfer contact printing.
    “Printable semiconductor elements” of the present invention comprise semiconductor structures that are able to be assembled and/or integrated onto substrate surfaces, for example using by dry transfer contact printing and/or solution printing methods. In one embodiment, printable semiconductor elements of the present invention are unitary single crystalline, polycrystalline or microcrystalline inorganic semiconductor structures. In this context of this description, a unitary structure is a monolithic element having features that are mechanically connected. Semiconductor elements of the present invention may be undoped or doped, may have a selected spatial distribution of dopants and may be doped with a plurality of different dopant materials, including P and N type dopants. The present invention includes microstructured printable semiconductor elements having at least one cross sectional dimension greater than or equal to about 1 micron and nanostructured printable semiconductor elements having at least one cross sectional dimension less than or equal to about 1 micron. Printable semiconductor elements useful in many applications comprises elements derived from “top down” processing of high purity bulk materials, such as high purity crystalline semiconductor wafers generated using conventional high temperature processing techniques. In one embodiment, printable semiconductor elements of the present invention comprise composite structures having a semiconductor operational connected to at least one additional device component or structure, such as a conducting layer, dielectric layer, electrode, additional semiconductor structure or any combination of these. In one embodiment, printable semiconductor elements of the present invention comprise stretchable semiconductor elements and/or heterogeneous semiconductor elements.
    “Cross sectional dimension” refers to the dimensions of a cross section of device, device component or material. Cross sectional dimensions include width, thickness, radius, and diameter. For example, printable semiconductor elements having a ribbon shape are characterized by a length and two cross sectional dimensions; thickness and width. For example, printable semiconductor elements having a cylindrical shape are characterized by a length and the cross sectional dimension diameter (alternatively radius).
    “Fill factor” refers to the percentage of the area between two elements, such as first and second electrodes, that is occupied by a material, element and/or device component. In one embodiment of the present invention, first and second electrodes are provided in electrical contact with one or more printable semiconductor elements that provide a fill factor between first and second electrodes greater than or equal to 20%, preferably greater than or equal to 50% for some applications and more preferably greater than or equal to 80% for some applications.
    “Supported by a substrate” refers to a structure that is present at least partially on a substrate surface or present at least partially on one or more intermediate structures positioned between the structure and the substrate surface. The term “supported by a substrate” may also refer to structures partially or fully embedded in a substrate.
    “Solution printing” is intended to refer to processes whereby one or more structures, such as printable semiconductor elements, are dispersed into a carrier medium and delivered in a concerted manner to selected regions of a substrate surface. In an exemplary solution printing method, delivery of structures to selected regions of a substrate surface is achieved by methods that are independent of the morphology and/or physical characteristics of the substrate surface undergoing patterning. Solution printing methods useable in the present invention include, but are not limited to, ink jet printing, thermal transfer printing, and capillary action printing.
    “Substantially longitudinally oriented” refers to an orientation such that the longitudinal axes of a population of elements, such as printable semiconductor elements, are oriented substantially parallel to a selected alignment axis. In the context of this definition, substantially parallel to a selected axis refers to an orientation within 10 degrees of an absolutely parallel orientation, more preferably within 5 degrees of an absolutely parallel orientation.
    “Stretchable” refers to the ability of a material, structure, device or device component to be strained without undergoing fracture. In an exemplary embodiment, a stretchable material, structure, device or device component may undergo strain larger than about 0.5% without fracturing, preferably for some applications strain larger than about 1% without fracturing and more preferably for some applications strain larger than about 3% without fracturing.
    The terms “flexible” and “bendable” are used synonymously in the present description and refer to the ability of a material, structure, device or device component to be deformed into a curved shape without undergoing a transformation that introduces significant strain, such as strain characterizing the failure point of a material, structure, device or device component. In an exemplary embodiment, a flexible material, structure, device or device component may be deformed into a curved shape without introducing strain larger than or equal to about 5%, preferably for some applications larger than or equal to about 1%, and more preferably for some applications larger than or equal to about 0.5%.
    “Semiconductor” refers to any material that is a material that is an insulator at a very low temperature, but which has a appreciable electrical conductivity at a temperatures of about 300 Kelvin. In the present description, use of the term semiconductor is intended to be consistent with use of this term in the art of microelectronics and electrical devices. Semiconductors useful in the present invention may comprise element semiconductors, such as silicon, germanium and diamond, and compound semiconductors, such as group IV compound semiconductors such as SiC and SiGe, group III-V semiconductors such as AlSb, AlAs, Aln, AlP, BN, GaSb, GaAs, GaN, GaP, InSb, InAs, InN, and InP, group III-V ternary semiconductors alloys such as AlxGa1-xAs, group II-VI semiconductors such as CsSe, CdS, CdTe, ZnO, ZnSe, ZnS, and ZnTe, group I-VII semiconductors CuCl, group IV-VI semiconductors such as PbS, PbTe and SnS, layer semiconductors such as PbI2, MoS2 and GaSe, oxide semiconductors such as CuO and Cu2O. The term semiconductor includes intrinsic semiconductors and extrinsic semiconductors that are doped with one or more selected materials, including semiconductor having p-type doping materials and n-type doping materials, to provide beneficial electrical properties useful for a given application or device. The term semiconductor includes composite materials comprising a mixture of semiconductors and/or dopants. Specific semiconductor materials useful for in some applications of the present invention include, but are not limited to, Si, Ge, SiC, AlP, AlAs, AlSb, GaN, GaP, GaAs, GaSb, InP, InAs, GaSb, InP, InAs, InSb, ZnO, ZnSe, ZnTe, CdS, CdSe, ZnSe, ZnTe, CdS, CdSe, CdTe, HgS, PbS, PbSe, PbTe, AlGaAs, AlInAs, AlInP, GaAsP, GaInAs, GaInP, AlGaAsSb, AlGaInP, and GaInAsP. Porous silicon semiconductor materials are useful for applications of the present invention in the field of sensors and light emitting materials, such as light emitting diodes (LEDs) and solid state lasers. Impurities of semiconductor materials are atoms, elements, ions and/or molecules other than the semiconductor material(s) themselves or any dopants provided to the semiconductor material. Impurities are undesirable materials present in semiconductor materials which may negatively impact the electrical properties of semiconductor materials, and include but are not limited to oxygen, carbon, and metals including heavy metals. Heavy metal impurities include, but are not limited to, the group of elements between copper and lead on the periodic table, calcium, sodium, and all ions, compounds and/or complexes thereof. Gold is a specific heavy metal impurity which significantly degrades the electrical properties of semiconductors.
    “Plastic” refers to any synthetic or naturally occurring material or combination of materials that can be molded or shaped, generally when heated, and hardened into a desired shape. Exemplary plastics useful in the devices and methods of the present invention include, but are not limited to, polymers, resins and cellulose derivatives. In the present description, the term plastic is intended to include composite plastic materials comprising one or more plastics with one or more additives, such as structural enhancers, fillers, fibers, plasticizers, stabilizers or additives which may provide desired chemical or physical properties.
    “Dielectric” and “dielectric material” are used synonymously in the present description and refer to a substance that is highly resistant to flow of electric current. Useful dielectric materials include, but are not limited to, SiO2, Ta2O5, TiO2, ZrO2, Y2O3, SiN4, STO, BST, PLZT, PMN, and PZT.
    “Polymer” refers to a molecule comprising a plurality of repeating chemical groups, typically referred to as monomers. Polymers are often characterized by high molecular masses. Polymers useable in the present invention may be organic polymers or inorganic polymers and may be in amorphous, semi-amorphous, crystalline or partially crystalline states. Polymers may comprise monomers having the same chemical composition or may comprise a plurality of monomers having different chemical compositions, such as a copolymer. Cross linked polymers having linked monomer chains are particularly useful for some applications of the present invention. Polymers useable in the methods, devices and device components of the present invention include, but are not limited to, plastics, elastomers, thermoplastic elastomers, elastoplastics, thermostats, thermoplastics and acrylates. Exemplary polymers include, but are not limited to, acetal polymers, biodegradable polymers, cellulosic polymers, fluoropolymers, nylons, polyacrylonitrile polymers, polyamide-imide polymers, polyimides, polyarylates, polybenzimidazole, polybutylene, polycarbonate, polyesters, polyetherimide, polyethylene, polyethylene copolymers and modified polyethylenes, polyketones, poly(methyl methacrylate, polymethylpentene, polyphenylene oxides and polyphenylene sulfides, polyphthalamide, polypropylene, polyurethanes, styrenic resins, sulphone based resins, vinyl-based resins or any combinations of these.
    “Elastomer” refers to a polymeric material which can be stretched or deformed and return to its original shape without substantial permanent deformation. Elastomers commonly undergo substantially elastic deformations. Exemplary elastomers useful in the present invention may comprise, polymers, copolymers, composite materials or mixtures of polymers and copolymers. Elastomeric layer refers to a layer comprising at least one elastomer. Elastomeric layers may also include dopants and other non-elastomeric materials. Elastomers useful in the present invention may include, but are not limited to, thermoplastic elastomers, styrenic materials, olefenic materials, polyolefin, polyurethane thermoplastic elastomers, polyamides, synthetic rubbers, PDMS, polybutadiene, polyisobutylene, poly(styrene-butadiene-styrene), polyurethanes, polychloroprene and silicones.
    The term “electromagnetic radiation” refers to waves of electric and magnetic fields. Electromagnetic radiation useful for the methods of the present invention includes, but is not limited to, gamma rays, X-rays, ultraviolet light, visible light, infrared light, microwaves, radio waves or any combination of these.
    “Good electronic performance” and “high performance” are used synonymously in the present description and refer to devices and device components have electronic characteristics, such as field effect mobilities, threshold voltages and on-off ratios, providing a desired functionality, such as electronic signal switching and/or amplification. Exemplary printable semiconductor elements of the present invention exhibiting good electronic performance may have intrinsic field effect mobilities greater than or equal 100 cm2V−1s−1, preferably for some applications greater than or equal to about 300 cm2V−1s−1. Exemplary transistors of the present invention exhibiting good electronic performance may have device field effect mobilities great than or equal to about 100 cm2V−1s−1, preferably for some applications greater than or equal to about 300 cm2V−1s−1, and more preferably for some applications greater than or equal to about 800 cm2V−1s−1. Exemplary transistors of the present invention exhibiting good electronic performance may have threshold voltages less than about 5 volts and/or on-off ratios greater than about 1×104.
    “Large area” refers to an area, such as the area of a receiving surface of a substrate used for device fabrication, greater than or equal to about 36 inches squared.
    “Device field effect mobility” refers to the field effect mobility of an electrical device, such as a transistor, as computed using output current data corresponding to the electrical device.
    Conformal contact” refers to contact established between surfaces, coated surfaces, and/or surfaces having materials deposited thereon which may be useful for transferring, assembling, organizing and integrating structures (such as printable semiconductor elements) on a substrate surface. In one aspect, conformal contact involves a macroscopic adaptation of one or more contact surfaces of a conformable transfer device e to the overall shape of a substrate surface. In another aspect, conformal contact involves a microscopic adaptation of one or more contact surfaces of a conformable transfer device to a substrate surface leading to an intimate contact with out voids. The term conformal contact is intended to be consistent with use of this term in the art of soft lithography. Conformal contact may be established between one or more bare contact surfaces of a conformable transfer device and a substrate surface. Alternatively, conformal contact may be established between one or more coated contact surfaces, for example contact surfaces having a transfer material, printable semiconductor element, device component, and/or device deposited thereon, of a conformable transfer device and a substrate surface. Alternatively, conformal contact may be established between one or more bare or coated contact surfaces of a conformable transfer device and a substrate surface coated with a material such as a transfer material, solid photoresist layer, prepolymer layer, liquid, thin film or fluid.
    “Placement accuracy” refers to the ability of a transfer method or device to transfer a printable element, such as a printable semiconductor element, to a selected position, either relative to the position of other device components, such as electrodes, or relative to a selected region of a receiving surface. “Good placement” accuracy refers to methods and devices capable of transferring a printable element to a selected position relative to another device or device component or relative to a selected region of a receiving surface with spatial deviations from the absolutely correct position less than or equal to 50 microns, more preferably less than or equal to 20 microns for some applications and even more preferably less than or equal to 5 microns for some applications. The present invention provides devices comprising at least one printable element transferred with good placement accuracy.
    “Fidelity” refers to a measure of how well a selected pattern of elements, such as a pattern of printable semiconductor elements, is transferred to a receiving surface of a substrate. Good fidelity refers to transfer of a selected pattern of elements wherein the relative positions and orientations of individual elements are preserved during transfer, for example wherein spatial deviations of individual elements from their positions in the selected pattern are less than or equal to 500 nanometers, more preferably less than or equal to 100 nanometers.
    “Young's modulus” is a mechanical property of a material, device or layer which refers to the ratio of stress to strain for a given substance. Young's modulus may be provided by the expression;
  • E = ( stress ) ( strain ) = ( L 0 Δ L × F A ) ; ( II )
  • wherein E is Young's modulus, L0 is the equilibrium length, ΔL is the length change under the applied stress, F is the force applied and A is the area over which the force is applied. Young's modulus may also be expressed in terms of Lame constants via the equation:
  • E = μ ( 3 λ + 2 μ ) λ + μ ; ( III )
  • wherein λ and μ are Lame constants. High Young's modulus (or “high modulus”) and low Young's modulus (or “low modulus”) are relative descriptors of the magnitude of Young's modulus in a give material, layer or device. In the present invention, a High Young's modulus is larger than a low Young's modulus, preferably about 10 times larger for some applications, more preferably about 100 times larger for other applications and even more preferably about 1000 times larger for yet other applications.
  • In the following description, numerous specific details of the devices, device components and methods of the present invention are set forth in order to provide a thorough explanation of the precise nature of the invention. It will be apparent, however, to those of skill in the art that the invention can be practiced without these specific details.
  • This invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. The present invention provides a variety of semiconductor elements that are printable including single crystalline inorganic semiconductors, composite semiconductor elements comprising a semiconductor structure operationally connected to one or more other device components, and stretchable semiconductor elements. The methods, devices and device components of the present invention are capable of generating high performance electronic and optoelectronic devices and arrays of devices, such as thin film transistors on flexible plastic substrates.
  • FIG. 1 schematically illustrates exemplary methods of the present invention for producing and assembling printable semiconductor elements comprising ribbons of single crystalline silicon. The process begins by providing a silicon-on-insulator (SOI) substrate 100 having a thin single crystalline silicon layer 105, a buried SiO2 layer 107 and Si handling layer 108. Optionally, the surface native oxide layer on thin single crystalline silicon layer 105, if present, may be removed, for example by exposing the surface of the SOI substrate 100 to dilute (1%) HF. Upon adequately stripping the native oxide layer, selected regions of external surface 110 of SOI substrate 100 are masked, thereby forming a pattern of mask elements 120, masked regions 125 and exposed surface regions 127 on external surface 110. In the embodiment shown in FIG. 1, external surface 110 is patterned with rectangular aluminum and gold surface layers which provide mask elements 120 that are capable of inhibiting etching of the masked regions 125 of external surface 110. Mask elements 120 may have any size and shape including, but not limited to, square, rectangular, circular, elliptical, triangular shapes or any combinations of these shapes. In an exemplary embodiment, patterns of Al/Au layers providing mask elements having desired geometries are fabricated using microcontact printing, nanocontact printing techniques, or photolithography, and etching methods (TFA for Au; AL-11 premixed Cyantec etchant for Al). Deposition of mask elements comprising thin metal films may be provided by an electron beam evaporator, such as a Temescal BJD1800, for example by sequential deposition of Al (20 nm; 0.1 nm/s) and then Au (100 nm; 1 nm/s).
  • External surface 110 of SOI substrate 100 is anisotropically etched downward. As shown in FIG. 1, although material is selectively removed from exposed surface regions 127, mask elements 120 prevent etching of masked regions 125, thereby generating a plurality of relief features 140 comprising single crystalline silicon structures having slightly angled side walls 141. In an exemplary embodiment wherein relief features have side walls 141 having a thickness 147 of about 100 nanometers, exposed surface regions 127 are exposed to tetramethylammonium hydroxide (TMAH) for about 3.5 minutes. In this embodiment, etching generates smooth sidewalls on relief features 140 of single crystal silicon having Al/Au mask elements 120, preferably with deviations from average surface positions of less than 10 nanometers. Relief features 140 may be lifted off of the substrate 100 when the underlying SiO2 layer 107 is partially or completely isotropically etched away, for example using concentrated (49%) HF. Liftoff of the relief features 140 generates printable semiconductor elements 150 comprising discrete single crystalline silicon structures having one surface covered by a mask element. Mask elements 120, Al/Au layers in the present example, may be removed or may be integrated directly into a final device structure, for example, as the source and drain electrodes in a thin film transistor. As shown in FIG. 1, the printable semiconductor elements 150 may be assembled onto the receiving surface of substrate surface 160, such as a plastic substrate, by either dry transfer contact printing techniques (schematically shown by arrow 166) or by solution casting methods (schematically shown by arrow 165). Both assembly methods may be carried out at room temperature in an ambient environment and, therefore, are compatible with a wide range of substrates, including low cost, flexible plastic substrates.
  • Use of dry transfer contact printing methods to assemble printable semiconductor elements has the benefit of taking advantage of the known orientations and positions of the printable semiconductor elements just prior to their liftoff from the SOI substrate. In this case, procedures similar to those of soft lithographic transfer printing techniques are used to move the printable semiconductor elements from the SOI (after etching away the SiO2 but before lifting off the silicon) to desired locations on the device substrate. In particular, a conformable elastomeric transfer element picks up the objects from the SOI surface and transfers them to a desired substrate. Similarly, the printable semiconductor elements can be directly transferred onto thin plastic substrates by Au cold welding using receptacle pads defined on the surface of the target substrate.
  • In an exemplary method, at least a portion of printable semiconductor elements 150 are brought into conformal contact with the contact surface 170 of a conformable transfer device 175, such as an elastomeric transfer stamp, polymer transfer device or composite polymer transfer device, thereby bonding at least a portion of printable semiconductor elements 150 onto the contact surface 170. Printable semiconductor elements 150 disposed on the contact surface 170 of conformable transfer device 175 are brought into contact with a receiving surface of substrate 160, preferably in a manner establishing conformal contact between contact surface 170 and the receiving surface of substrate 160. Contact surface 170 is separated from printable semiconductor elements 150 in contact with receiving surface of substrate 160, thereby assembling printable semiconductor elements 150 onto the receiving surface. This embodiment of the present invention is capable of generating a pattern on the receiving surface comprising printable semiconductor elements 150 in well defined positions and spatial orientations. In the embodiment shown in FIG. 1, printable semiconductor elements 150 are operationally connected to gold pads 162 present on the receiving surface of substrate 160.
  • FIG. 2 provides a schematic diagram illustrating a selective dry transfer contact printing method for assembling printable semiconductor element on a receiving surface of a substrate. A plurality of printable semiconductor elements 300 are fabricated on a mother substrate 305 in a first pattern 310 of printable semiconductor elements 300 characterized by well defined positions and spatial orientations. A conformable transfer device 315 having a contact surface 320 with a plurality of discrete binding regions 325 is brought into conformal contact with at least a portion of printable semiconductor elements 300 on mother substrate 305. Binding regions 325 on contact surface 320 are characterized by an affinity for printable semiconductor elements 310, and may be chemically modified regions, such regions having hydroxyl groups extending from the surface of a PDMS layer, or regions coated with one or more adhesive layers. Conformal contact transfers at least a portion of printable semiconductor elements 310 which contact binding regions 325 on contact surface 320. Printable semiconductor elements 310 transferred to contact surface 320 are brought into contact with receiving surface 330 of substrate 335, which may be a flexible substrate such as a plastic substrate. Subsequent separation of semiconductor elements 310 and contact surface 320 results in assembly of the semiconductor elements 310 on receiving surface 330 of substrate 335, thereby generating a second pattern 340 of printable semiconductor elements characterized by well defined positions and spatial orientations different from the first pattern of printable semiconductor elements 340. As shown in FIG. 2, the printable semiconductor elements 340 that remain on mother substrate 305 are characterized by a third pattern 345 of printable semiconductor elements different from first and second patterns of printable semiconductor elements. Printable semiconductor elements 340 comprising the third pattern 345 may be subsequently transferred to and/or assembled onto substrate 335 or another substrate using the printing methods of the present invention, including selective dry transfer methods.
  • FIGS. 3A-C, are schematic diagrams showing devices, device configurations and device components useful in selective dry transfer contact printing methods of the present invention. FIG. 3A shows a plurality of printable semiconductor elements 300 on a mother substrate 305, wherein selected printable semiconductor elements 300 have one or more adhesive coatings 350. As shown in FIG. 3A, adhesive coatings 350 are provided in a well defined pattern. FIG. 3B shows a conformable transfer device 315 having a contact surface 320 with a plurality of discrete binding regions 325 provided in a well defined pattern. FIG. 3C shows a conformable transfer device 315 having a three dimensional relief pattern 355 comprising relief features 360 provided in a well defined pattern. In the embodiment shown in FIG. 3C, relief pattern 355 provides a plurality of contact surfaces 320 that may be optionally coated with one or more adhesive layers. Patterns of adhesive coatings 350, binding regions 325 and relief features 360 preferably corresponding to relative positions and spatial orientations of printable semiconductor elements 300 in device configurations or device array configurations, such as thin film transistor array configurations.
  • Use of dry transfer printing methods are useful in the present invention for assembling, organizing and integrating printable semiconductor elements on substrates having a wide range of compositions and surface morphologies, including curved surfaces. To demonstrate this functional capability of the present methods and compositions, semiconductor elements comprising silicon photodiodes were printed directly (i.e. no adhesive) onto the curved surfaces of a variety of optical lenses using dry transfer printing methods employing an elastomeric stamp. FIG. 3D provides a photograph of an array of photodiodes printed onto a spherical surface of a polycarbonate lens (FL 100 mm). FIG. 3E provides a scanning electron micrograph of an array of photodiodes printed onto the curved surface of a spherical glass lens (FL 1000 mm). Contrast in the image provided in FIG. 3E is slightly enhanced to show p-doped regions. FIG. 3F provides a plot of electric current (μA) verse bias potential (volts) illustrating the light response of the photodiodes pictured in FIG. 3E.
  • FIGS. 4A1 and 4A2 show a preferred shape of a printable semiconductor element for assembly methods of the present invention using dry transfer contact printing. FIG. 4A1 provides a perspective view and FIG. 4A2 provides a top plan view. Printable semiconductor element comprises a ribbon 500 extending along a central longitudinal axis 502 having a first end 505, center region 510 and second end 515. As shown in FIG. 4A, the width of ribbon 500 selectively varies along its length. Particularly, first and second ends 505 and 515 are wider than center region 510. In an exemplary method, ribbon 500 is formed by etching mother substrate 520. In this embodiment, mother substrate is isotropically exposed to an enchant until ribbon 500 is only attached to mother substrate 520 by two alignment maintaining elements comprising sacrificial layers 525 proximate to first and second ends 505 and 515. At this point in the fabrication process the etching process is stopped, and the ribbon 500 is brought into contact with and/or bonded to a conformable transfer device. Sacrificial layers 525 are broken and ribbon 500 is released as the transfer device is moved away from mother substrate 520. This method may also be applied to dry transfer contact printing of a plurality of printable semiconductor elements having shapes as shown in FIG. 4. An advantage of this method of the present invention is that the orientations and relative positions of a plurality of ribbons 500 on mother substrate 520 may be precisely preserved during transfer, assembly and integration steps. Exemplary ranges for the thickness of the sacrificial layers are ˜1 um down to ˜100 nm with ribbons widths between ˜2 um and 100 um. Interestingly, the cleavage of the ribbons typically occurs at the extremity of the objects (very close to the point/edge where the ribbons are attached to the mother wafer). Wide ribbons usually do not distort during the lift-off process are they are bonded to the stamp.
  • FIGS. 4B1 and 4B2 show a preferred shape of a printable semiconductor element for assembly methods of the present invention using dry transfer contact printing. FIG. 4B1 provides a perspective view and FIG. 4B2 provides a top plan view. Printable semiconductor element comprises ribbons 527 extending along a parallel central longitudinal axes 528. Ribbons 527 are held in a selected position and orientation by alignment maintaining elements 530 which connect at least on end of the ribbon along the central longitudinal axes 528 to mother substrate 529. alignment maintaining elements 530 are fabricated during patterning of ribbons 527 by not defining one or both ends of the ribbon along their central longitudinal axes. Alignment maintaining elements 530 are broken and ribbons 527 are released upon contact with the ribbons with the contact surface of a transfer device and subsequent movement away from mother substrate 520.
  • To achieve assembly by solution printing, at least a portion of printable semiconductor elements 150 are dispersed into a carrier medium, thereby generating a suspension 190 comprising semiconductor element elements 150 the carrier medium. Printable semiconductor elements 150 are delivered to the substrate and assembled by solution printing the suspension onto the receiving surface of substrate 160. Solution printing may be provided by a number of techniques known in the art including, but not limited to, ink jet printing, thermal transfer printing and screen printing. In the embodiment shown in FIG. 1, printable semiconductor elements 150 are operationally connect to gold pads 162 present on the receiving surface of substrate 160.
  • FIGS. 5A-C presents optical and scanning electron micrographs of a range of printable semiconductor elements 150 comprising microstrips of single crystalline silicon having selected physical dimensions. Printable semiconductor elements are shown in ethanol suspensions and as cast onto substrates of various types. FIG. 5A shows an optical micrograph of a solution cast tangled mat of silicon rods (widths 2 microns; thickness 2 microns; lengths ˜15 millimeters). The inset image shows printable silicon strips (roughly 10 million of them) dispersed in a solution of ethanol. The low resolution SEM image in FIG. 5B illustrates the mechanical flexibility range of some flat microstrips (thickness 340 nanometers; widths 5 microns; lengths ˜15 millimeters) solution casted onto a bare silicon wafer. FIG. 5C presents a high resolution SEM image of one of these objects. Note the extremely smooth sidewalls generated by the anisotropic wet etching procedures.
  • Printable semiconductor elements in the form of wires, platelets and disks may also be formed using the methods of the present invention. By use of large area soft lithographic techniques, it is possible, in a single low cost processing sequence, to produce large numbers (i.e. billions) of printable semiconductor elements with lateral dimensions down to 50 nm and with nearly any geometry. Printable semiconductor elements having lateral dimension as small as 20 nanometer may also be fabricated by the methods of present invention. For use in thin film transistors in flexible electronic systems, printable semiconductor elements comprising long (˜10 microns) and narrow (˜1 microns) strips of single crystalline silicon are particularly useful.
  • FIG. 6 presents an image of transferred printable semiconductor elements comprising single crystalline silicon microstrips on a PDMS coated polyimide sheet having a thickness of about 25 microns. The top inset pictures illustrate the intrinsic flexibility of this system. The bottom inset shows a top view micrograph of printable silicon dense microstrips (25 microns wide, ˜2 microns spaced apart) cold welded on a thin Ti/Au coated Mylar sheet. As shown in FIG. 6, the printable semiconductor elements comprising silicon microstrips are well aligned and transferred with controlled orientation. No cracking of the printable semiconductor elements induced by assembly was observed upon careful examination using scanning electron microscopy, even when the substrate was bent significantly. Similar results were obtained (without the need of an elastomeric layer) using a Au coated thin Mylar sheet as illustrated by the bottom inset micrograph picture. A coverage density close to 100% can be achieved in this manner.
  • The present invention also provides composite printable semiconductor elements comprising a semiconductor structure operationally connect to one or more other device components, such as dielectric elements, conducting elements (i.e. electrodes) or additional semiconductor elements. An exemplary printable semiconductor elements of the present invention that is particularly useful for fabricating thin film transistors comprises an integrated semiconductor and dielectric element. Such composite printable semiconductor elements provide transistors having high quality, leak free dielectrics and avoids the need for separate spin casting steps for fabricating the dielectric element in a thin film transistor. In addition, use of composite printable semiconductor elements enables efficient device fabrication on large substrate areas by low cost printing techniques.
  • The following references relate to self assembly techniques which may be used in methods of the present invention to transfer, assembly and interconnect printable semiconductor elements via contact printing and/or solution printing techniques: (1) “Guided molecular self-assembly: a review of recent efforts”, Jiyun C Huie Smart Mater. Struct. (2003) 12, 264-271; (2) “Large-Scale Hierarchical Organization of Nanowire Arrays for Integrated Nanosystems”, Whang, D.; Jin, S.; Wu, Y.; Lieber, C. M. Nano Lett. (2003) 3(9), 1255-1259; (3) “Directed Assembly of One-Dimensional Nanostructures into Functional Networks”, Yu Huang, Xiangfeng Duan, Qingqiao Wei, and Charles M. Lieber, Science (2001) 291, 630-633; and (4) “Electric-field assisted assembly and alignment of metallic nanowires”, Peter A. Smith et al., Appl. Phys. Lett. (2000) 77(9), 1399-1401.
  • All references cited in this application are hereby incorporated in their entireties by reference herein to the extent that they are not inconsistent with the disclosure in this application. Some references provided herein are incorporated by reference to provide details concerning sources of starting materials, additional starting materials, additional reagents, additional methods of synthesis, additional methods of analysis and additional uses of the invention. It will be apparent to one of ordinary skill in the art that methods, devices, device elements, materials, procedures and techniques other than those specifically described herein can be applied to the practice of the invention as broadly disclosed herein without resort to undue experimentation. All art-known functional equivalents of methods, devices, device elements, materials, procedures and techniques specifically described herein are intended to be encompassed by this invention.
  • U.S. Patent Application Nos. 60/577,077, 60/601,061, 60/650,305, 60/663,391 and 60/677,617 filed on Jun. 4, 2004, Aug. 11, 2004, Feb. 4, 2005, Mar. 18, 2005, and May 4, 2005, respectively, are hereby incorporated by reference herein in their entireties to the extent not inconsistent with the disclosure of this application.
  • When a group of materials, compositions, components or compounds is disclosed herein, it is understood that all individual members of those groups and all subgroups thereof are disclosed separately. When a Markush group or other grouping is used herein, all individual members of the group and all combinations and subcombinations possible of the group are intended to be individually included in the disclosure. Every formulation or combination of components described or exemplified herein can be used to practice the invention, unless otherwise stated. Whenever a range is given in the specification, for example, a temperature range, a time range, or a composition range, all intermediate ranges and subranges, as well as all individual values included in the ranges given are intended to be included in the disclosure.
  • As used herein, “comprising” is synonymous with “including,” “containing,” or “characterized by,” and is inclusive or open-ended and does not exclude additional, unrecited elements or method steps. As used herein, “consisting of” excludes any element, step, or ingredient not specified in the claim element. As used herein, “consisting essentially of” does not exclude materials or steps that do not materially affect the basic and novel characteristics of the claim. In each instance herein any of the terms “comprising”, “consisting essentially of” and “consisting of” may be replaced with either of the other two terms.
  • Example 1 Thin Film Transistor Having a Printable Semiconductor Element
  • The ability of printable semiconductor elements of the present invention to provide semiconductor channels in thin film transistors was verified by experimental studies. Specifically, it is a goal of the present invention to provide thin film transistors capable of fabrication on a flexible plastic substrates by printing methods. Further, it is a goal of the present invention to provide high performance thin film transistors on plastic substrates having field effect mobilities, on-off ratios and threshold voltages similar to or exceeding thin film transistors fabricated by convention high temperature processing methods.
  • FIG. 7 presents an optical micrograph image of a thin film transistor having a printable semiconductor element. The illustrated transistor 531 comprises source electrode 532, drain electrode 533, printable semiconductor element 534, dielectric (not shown in the micrograph in FIG. 7) and gate electrode (also not shown in the micrograph in FIG. 7). The thin film transistor is supported by a substrate comprising of a Mylar sheet coated with indium tin oxide (ITO, ˜100 nanometers thick) as a gate and a photocured epoxy as a gate dielectric (SU8-5; Microchem Corp). The capacitance of the dielectric (2.85 nF/cm2) was evaluated using capacitor test structures formed near the device. This device uses a solution cast printable semiconductor element comprising a ˜5 millimeter long, 20 micron width and 340 nanometer thick microstrip fabricated from a p-doped SOI wafer (Soitec) with a 340 nanometer device layer thickness and resistivity of 14-22 ohm cm. A 25 nanometer thick layer of SiO2 was grown on top of the silicon by dry oxidation in a horizontal quartz tube furnace. Source and drain electrodes of Al (20 nanometer)/Au (180 nanometer) where defined by liftoff techniques. The semiconductor channel length is 50 microns and the width is 20 microns.
  • FIGS. 8 and 9 show electrical measurements collected from thin film transistors of the present invention having a printable semiconductor element. The device operates similarly to a back gated SOI device with a top contact configuration. The semiconductor uses a width equal to a 20 microns microstrip of single crystal silicon in a channel whose length is equal to 50 microns. The printable semiconductor element in this case was patterned by solution casting methods. The source/drain contacts were defined by photolithography and lift off.
  • FIG. 8 provides a plot showing current-voltage (IV) characteristics of a device made on a pre-oxidized Si wafer. FIG. 9 provides a plot showing transfer characteristics measured at VDS=0.1 V of a device made on a Mylar sheet coated with ITO gate and polymer dielectric. The slope of this curve defines an effective device mobility (using the physical width of the source and drain electrodes, which is equal to the width of the semiconductor element microstrip in this case) of 180 cm2/Vs. The Al/Au metallization for the contacts to the printable semiconductor element provides reasonably low resistance Schottky barrier contacts to the silicon, as expected for an Al (work function of 4.2 eV) metallization on p-doped silicon. Aluminum is well known to diffuse rapidly into silicon, but no special care was taken to avoid localized aluminum-silicon interactions as no post metallization high temperature annealing step was carried out. The on/off ratio of this device is slightly lower than 103. Analysis of the transfer characteristic of FIG. 9 indicates a linear field effect mobility of 180 cm2V−1s−1 using a parallel plate model for the dielectric capacitance. This analysis ignores the effects of contacts and processing induced changes in the threshold voltage.
  • Even with perfect contacts, there are theoretical arguments to suggest that transistors which incorporate very high aspect ratio (i.e. ultra large length to width ratios) semiconducting elements in the channel region (i.e. nanotubes or nanowires) will have responses that are different than those of conventional devices. To avoid these effects, we chose printable semiconductor elements comprising microstrips having widths on the same order of magnitude with the transistor channel length. The properties (mobilities, normalized transconductance, on/off ratio) observed here are ˜¾ to those of thin film transistors made on the SOI substrate after etching of the Si but before liftoff. In these measurements the buried SiO2 oxide acts as the dielectric and the silicon supporting substrate acts as the gate electrode. This result demonstrates that the processing steps used to produce the printable semiconductor elements and to transfer it to the device substrate do not alter significantly the properties of the silicon or its surfaces that result from the initial patterning and silicon etching steps. It also indicates that the van der Waals interface with the SU8 dielectric is capable of supporting good device properties.
  • A principle advantage of the fabrication method of the present example is that it separates the crystal growth and processing of the silicon from the plastic substrate and other components of the devices. In addition, the methods of processing printable semiconductor elements of the present invention are highly flexible in the processing sequences and in the materials choices that are possible. For example, an SiO2 layer can be formed on one side of the silicon (by, for example, growing a thermal oxide before lifting off the Si elements or lifting the SOI buried oxide together with the Si device layer) to yield an integrated dielectric, in a strategy similar to that for the integrated source/drain metallization demonstrated here. A dielectric introduced in this manner may avoid the significant challenges that can be associated with leakage, hysteresis, doping, trapping, etc. in many solution cast thin dielectrics on plastic substrates.
  • FIGS. 10 A-H provide a schematic diagram illustrating a method of the present invention for making an array of thin film transistors having composite printable semiconductor elements. As shown in FIG. 10 A, gate electrodes 547 are deposited on the surface 548 of a thin sheet of a flexible substrate, such as Kapton, Mylar or PET. Gate electrodes may be patterned on the flexible substrate by any means known in the art including but not limited to photolithography, microtransfer printing, nanotransfer printing, soft lithography or combinations of these. As shown in FIG. 10B, the method further comprises the step of fabricating a plurality of composite printable semiconductor elements 550 comprising single crystalline silicon structures 555 operationally connected to a SiO2 dielectric element 560. As illustrated in FIG. 10B, composite printable semiconductor elements 550 have a ribbon shape extending a selected length 552 along a central longitudinal axis 551. Composite printable semiconductor element 550 has a selected thickness 553 and a width that varies as a function of thickness.
  • As shown in FIG. 10C, the method further comprises the step of assembling composite printable semiconductor elements 550 onto gate electrodes 547 and substrate 548 via dry transfer contact printing or solution printing. Composite printable semiconductor elements 550 are oriented such that SiO2 dielectric elements 560 are in contact with gate electrodes 547. As shown in FIG. 10D, the method further comprises the step of spin coating a thin layer of positive photoresist 561 on the patterned surface of substrate 548. Alternatively, the thin layer of positive photoresist 561 may be applied to the pattern surface of substrate 548 using a roller. Regions of photoresist 561 not masked by gate electrodes 547 are exposed to a beam of electromagnetic radiation transmitted through underside 562 of substrate 548. Use of an optically transmissive substrate 548 is preferred for this method of the present invention, particularly a substrate 548 that is at least partially transparent in ultraviolet and/or visible regions of the electromagnetic spectrum. As shown in FIG. 10E, the method further comprises the step of developing the thin photoresist layer. As shown in this figure, the regions of thin photoresist layer 561 that are shadow masked by the gate electrodes are undeveloped. As shown in FIG. 10F, the method further comprises the step of dry or wet etching the integrated SiO2 dielectric, thereby opening contacts for source and drain electrodes. In the embodiment illustrated by FIG. 10F this is achieved by exposing the patterned surface of substrate 548 to a CF4 plasma. As shown in FIG. 10G, the method further comprises the step of defining source and drain electrodes by shadow mask evaporation. The alignment of semiconductor elements, source electrodes and drain electrodes does not need to be very precise because the semiconductor channels will be defined in the next fabrication step. As shown in FIG. 10H, the method further comprises the step of defining the semiconductor channel by lifting off the positive resist, for example by exposure to a solvent such as acetone.
  • FIGS. 11A-D provide diagrams illustrating a method of the present invention for making a printable device comprising integrated gate electrode, gate dielectric, semiconductor, source electrode and drain electrode. As shown in FIG. 11A, a high quality gate dielectric is grown by thermal oxidation of the surface of a SOI wafer. Next, the gate electrode material (such as metal or doped poly-silicon) is deposited. Selected regions of the top surface are subsequently masked using for example a lithography process. In one embodiment, an array of identical patterns with controlled spacing will be defined in a single masking step. Printable semiconductor elements are then fabricated by anisotropically wet and/or dry etching. Preferentially, three different selective etching processes are carried out sequentially to etch away the exposed areas of the gate electrode material, the gate dielectric and the top silicon layer.
  • A lithography process, as shown in FIG. 11B, is used to define the channel of the transistors. In this process step, the exposed areas of the gate electrode material are etched away (dry or wet etching). As shown in FIG. 11C, the photo-resist is then heated above its glass transition, thereby initiating a reflow process. The reflowing distance of the photoresist can be selected by carefully selecting an appropriate thickness of the photo-resist layer, the glass transition temperature of the photo-resist layer or the temperature and duration of the reflow process. The exposed areas of the gate dielectric are then etched using an HF solution.
  • Next, a metallization process, as shown in FIG. 11D, is carried out, followed by lifting off the metal deposited onto the photoresist to complete the fabrication of a printable device. The source and drain electrodes are self aligned with the gate, and the spacing between source and drain electrodes may be selected by the adjusting the different parameters, such as temperature and duration, of the reflow process.
  • The printable device shown in FIG. 11D may be transferred and assembled onto a substrate, such as a plastic substrate, by the dry transfer or solution printing methods of the present invention. The self aligned process illustrated in FIGS. 11A-D presents a simple way to integrate all the elements necessary for the realization of a printable device, such as a MOSFET device. A significant advantage of this fabrication method of the present invention is that all processes steps which require temperatures incompatible with plastic substrates (e.g. requiring temperature>about 400 Celsius) may be carried on the SOI substrate prior to lifting off and transferring the device to the substrate. For example, additional processing steps such as doping of the source and drain contact areas, formation of silicide layers, and high temperature annealing of the device could be performed prior to transferring the elements onto a plastic substrate.
  • Example 2 Stretchable Printable Semiconductor Elements
  • The present invention provides stretchable printable semiconductor elements capable of providing good performance when stretched, flexed or deformed. Further, stretchable printable semiconductor elements of the present invention may be adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices.
  • FIG. 12 provides an atomic force micrograph showing a stretchable printable semiconductor element of the present invention. The stretchable printable semiconductor element 700 comprises a flexible substrate 705 having a supporting surface 710 and a bent semiconductor structure 715 having a curved internal surface 720. In this embodiment, at least a portion of the curved internal surface 720 of bent semiconductor structure 715 is bonded to the supporting surface 710 of the flexible substrate 705. The curved internal surface 720 may be bonded supporting surface 710 at selected points along internal surface 720 or at substantially all points along internal surface 720. The exemplary semiconductor structure illustrated in FIG. 12 comprises a bent ribbon of single crystalline silicon having a width equal to about 100 microns and a thickness equal to about 100 nanometers. The flexible substrate illustrated in FIG. 12 is a PDMS substrate having a thickness of about 1 millimeter. Curved internal surface 720 has a contour profile characterized by a substantially periodic wave extending along the length of the ribbon. As shown in FIG. 12, the amplitude of the wave is about 500 nanometers and the peak spacing is approximately 20 microns. FIG. 13 shows an atomic force micrograph providing an expanded view of a bent semiconductor structure 715 having curved internal surface 720. FIG. 14 shows an atomic force micrograph of an array of stretchable printable semiconductor elements of the present invention. Analysis of the atomic force micrograph in FIG. 14 suggests that the bent semiconductor structures are compressed by about 0.27%. FIG. 15 shows optical micrographs of stretchable printable semiconductor elements of the present invention.
  • The contour profile of curved surface 720 allows the bent semiconductor structure 715 to be expanded or contracted along deformation axis 730 without undergoing substantial mechanical strain. This contour profile may also allow the semiconductor structure to be bent, flexed or deformed in directions other than along deformation axis 730 without significant mechanical damage or loss of performance induced by strain. Curved surfaces of semiconductor structures of the present invention may have any contour profile providing good mechanical properties, such as stretchability, flexibility and/or bendability, and/or good electronic performance, such as exhibiting good field effect mobilities when flexed, stretched or deformed. Exemplary contour profiles may be characterized by a plurality of convex and/or concave regions, and by a wide variety of wave forms including sine waves, Gaussian waves, Aries functions, square waves, Lorentzian waves, periodic waves, aperiodic waves or any combinations of these. Wave forms useable in the present invention may vary with respect to two or three physical dimensions.
  • FIG. 16 shows an atomic force micrograph of a stretchable printable semiconductor element of the present invention having a bent semiconductor structure 715 bonded to a flexible substrate 705 having a three dimensional relief pattern on its supporting surface 710. The three-dimensional relief pattern comprises recessed region 750 and relief features 760. As shown in FIG. 16, bent semiconductor structure 715 is bound to supporting surface 710 in recessed region 750 and on relief features 760.
  • FIG. 17 shows a flow diagram illustrating an exemplary method of making a stretchable semiconductor element of the present invention. In the exemplary method, a prestrained elastic substrate in an expanded state is provided. Prestraining can be achieved by any means known in the art including, but not limited to, roll pressing and/or prebending the elastic substrate. An exemplary elastic substrate useable in this method of the present invention is a PDMS substrate having a thickness equal to about 1 millimeter. The elastic substrate may be prestrained by expansion along a single axis or by expansion along a plurality of axes. As shown in FIG. 17, at least a portion of the internal surface of a printable semiconductor structure is bonded to the external surface of the prestrained elastic substrate in an expanded state. Bonding may be achieved by covalent bonding between the internal surface of the semiconductor surface, by van der Waals forces, by using adhesive or any combinations of these. In an exemplary embodiment wherein the elastic substrate is PDMS, the supporting surface of the PDMS substrate is chemically modified such that is has a plurality of hydroxyl groups extending from its surface to facilitate covalent bonding with a silicon semiconductor structure. Referring back to FIG. 17, after binding the prestrained elastic substrate and semiconductor structure, the elastic substrate is allowed to relax at least partially to a relaxed state. In this embodiment, relaxation of the elastic substrate bends the internal surface of said printable semiconductor structure, thereby generating a semiconductor element having a curved internal surface.
  • As shown in FIG. 17, the fabrication method may optionally include a second transfer step wherein the semiconductor structure 715 having a curved internal surface 720 is transferred from the elastic substrate to another substrate, preferably a flexible substrate. This second transfer step may be achieved by bringing an exposed surface of the semiconductor structure 715 having a curved internal surface 720 in contact with a receiving surface of the other substrate that binds to the exposed surface of the semiconductor structure 715. Bonding to the other substrate may be accomplished by any means in the are including covalent bonds, bonding via van der Waals forces and the use of adhesives.
  • Stretchable semiconductor elements of the present invention may be effectively integrated into a large number functional devices and device components, such as transistors, diodes, lasers, MEMS, NEMS, LEDS and OLEDS. Stretchable semiconductor elements of the present invention have certain advantages over conventional rigid inorganic semiconductors. First, stretchable semiconductor elements may be flexible, and thus, less susceptible to structural damage induced by flexing, bending and/or deformation than conventional rigid inorganic semiconductors. Second, as a bent semiconductor structure may be in a slightly mechanically strained state to provide a curved internal surface, stretchable semiconductor elements of the present invention may exhibit higher intrinsic field effect mobilities than conventional unstrained inorganic semiconductors. Finally, stretchable semiconductor elements are likely to provide good thermal properties because they are capable of expanding and contracting freely upon device temperature cycling.
  • Example 3 Methods of Making Printable Semiconductor Elements
  • The present invention provides methods of making printable semiconductor elements from a wide range of starting materials, including single crystalline wafers, silicon on substrate wafers, germanium wafers, thin films of polycrystalline silicon and ultra thin silicon wafers. Particularly, the present invention provides low cost methods of making large numbers of printable semiconductors in selected orientations and relative positions.
  • FIG. 18A shows an exemplary method for making printable semiconductor elements from a Si—Ge epi substrate. In this method, selective regions of a Si epi layer are masked by depositing a mask material, such as a thin films comprising a metal, SiO2 or SiN. This masking step defines shape and some of the physical dimensions (e.g. length and width for a ribbon) of the printable semiconductor elements to be fabricated. The exposed Si surface of the Si—Ge epi substrate is anisotropically etched by either dry or wet chemical etching methods. This generates relief features of silicon, preferably having smooth side walls, that can be effectively released from the Si—Ge epi substrate by lift off techniques, for example using selective SiGe wet etching provided by NH4OH:H2O2:H2O 1:1:4 at 50° C. Optionally, source electrode, gain electrode, gate electrode, dielectric element or any combinations of these may be integrated into the semiconductor element prior to lift off. An advantage of this fabrication method is that the mother substrate can be cleaned and re-used.
  • FIG. 18B shows an exemplary method for fabricating printable semiconductor elements from a bulk silicon substrate, preferably a single crystalline silicon substrate. In this method, a silicon wafer is first dry oxidized, for example in a quartz tube furnace at a temperature selected from the range of about 800 degrees Celsius to about 1200 degrees Celsius. Next, a thin layer of gate material is deposited on the oxidized surface of the silicon wafer. Exemplary gate materials include metals or doped polycrystalline silicon. The thin layer of gate material is selectively patterned with photoresist. This patterning step defines the shape and some of the physical dimensions (e.g. length and width for a ribbon) of the printable semiconductor elements to be fabricated. The thin layer of gate material and dielectric layer are anisotropically back etched, thereby generating relief features comprising a photoresist layer, gate material layer, dielectric layer and silicon layer and, preferably having smooth side walls. Next, the photoresist layer is reflowed, for example by annealing to a temperature selected from the range of about 100 degrees Celsius to about 130 degrees Celsius. Reflowing the photoresist transfers a portion of the photoresist to the side walls of the relief features. As shown in FIG. 18B, the exposed Si surface is isotropically etch using wet or dry etching methods, thereby releasing the relief features and generating composite printable semiconductor elements, preferably having smooth surfaces. Isotropic etching of the silicon may be achieved using a HNO3:NH4F:H2O 64:3:33 solution. Advantages of this fabrication method are the relatively low cost of the silicon substrate starting materials and the ability to reuse the mother substrate after planarization (ECMP).
  • FIG. 18C shows another exemplary method of fabricating printable semiconductor elements from a bulk silicon substrate, preferably a single crystalline silicon substrate. In this method, the external surface of a bulk silicon substrate is selectively patterned with photoresist. This patterning step defines the shape and some of the physical dimensions (e.g. length and width for a ribbon) of the printable semiconductor elements to be fabricated. The patterned substrate surface is anisotropically etched, preferably using dry etching methods such as reactive ion etching and inductive coupled plasma etching, thereby generating relief features, preferably relief features having smooth side walls. At least a portion of the side walls of the relief features are masked by depositing a masking material such as a thin layer of metal, SiO2 or SiN. In one embodiment, masking material is applied to the side walls of relief features by angled evaporative or sputtering deposition techniques combined with sample rotation to ensure deposition all exposed side walls. As shown in FIG. 18C, the exposed Si surface is isotropically etched using wet or dry etching methods, thereby releasing the relief features and generating printable semiconductor elements, preferably having smooth surfaces. Isotropic etching of the silicon may be achieved using a HNO3:NH4F:H2O 64:3:33 solution. Advantages of this fabrication method are the relatively low cost of the silicon substrate starting materials and the ability to reuse the mother substrate after planarization (ECMP).
  • FIG. 18D shows yet another exemplary method of fabricating printable semiconductor elements from a bulk silicon substrate, preferably a single crystalline silicon substrate. In this method, the external surface of a bulk silicon substrate is selectively patterned with photoresist. The patterned substrate surface is anisotropically etched, thereby generating relief features. Next the silicon substrate is annealed, for example by annealing in a quartz furnace at a temperature of about 1100 degrees Celsius and in nitrogen. Next, the surface of the annealed silicon substrate is patterned by masking selected regions with photoresist. This patterning step defines the shape and some of the physical dimensions (e.g. length and width for a ribbon) of the printable semiconductor elements to be fabricated. As shown in FIG. 18D, the patterned surface of the annealed Si substrate is anisotropically etched using wet or dry etching methods, thereby generating printable semiconductor elements, preferably having smooth surfaces. Advantages of this fabrication method are the relatively low cost of the silicon substrate starting materials, the ability to reuse the mother substrate after planarization (ECMP) and the ability to integrate source electrode, drain electrode, gate electrode and dielectric device components after the annealing step. In addition, wet etching may be used in the first etching step with a 110 silicon wafer.
  • FIG. 18E shows an exemplary method of fabricating printable semiconductor elements from an ultra thin silicon substrate. In this method, the external surface of an ultra thin silicon substrate is selectively patterned with photoresist. This patterning step defines the shape and some of the physical dimensions (e.g. length and width for a ribbon) of the printable semiconductor elements to be fabricated. The patterned substrate surface is anisotropically etched through thickness of the ultra thin silicon substrate, thereby printable semiconductor elements. Ultra thin silicon substrates having thicknesses selected from the range of about 10 microns to about 500 microns are preferred for some applications of this fabrication method. An advantage of this fabrication method is the relatively low cost of the ultra thin silicon substrate starting materials.
  • FIGS. 18F and 18G show exemplary methods for making printable semiconductor elements from thin films of polycrystalline silicon. In this method, a thin layer of polycrystalline silicon is deposited on a supporting substrate, such as glass or silicon substrate, having a sacrificial surface layers, such as a coating comprising SiN or SiO2. The polycrystalline thin film is then annealed, and selective regions of a the exposed surface are selectively masked by depositing a mask material, such as a thin films comprising a metals, SiO2 or SiN. This masking step defines shape and some of the physical dimensions (e.g. length and width for a ribbon) of the printable semiconductor elements to be fabricated. The patterned surface is anisotropically etched by either dry or wet chemical etching methods, generating relief features of silicon supported by the sacrificial layer, preferably relief features having smooth side walls. Isotropically etching the sacrificial layer releases the relief features, thereby generating printable semiconductor elements. An advantage of this fabrication method is that the supporting substrate can be cleaned an reused. Alternatively, a thin layer of polycrystalline silicon may be deposited directly on a SiO2 substrate. As shown in FIG. 18G, similar annealing, patterning, anisotropic etching and lift off steps may be used to generate printable semiconductor elements. Optionally, source electrode, gain electrode, gate electrode, dielectric element or any combinations of these may be integrated into the semiconductor element prior to lift off in either of these methods.
  • FIGS. 18H(1) and 18H(2) illustrate a method for making single crystalline semiconductor films using printable semiconductor elements of the present invention. As shown in FIG. 18H(1), an amorphous or poly-crystalline semiconductor thin film is prepared on the surface of a substrate comprising an insulating material, such as SiO2. The thin amorphous or poly-crystalline semiconductor film may prepared by any means known in the art including, but not limited to, deposition techniques such as vapor deposition or sputtering deposition. Also referring to FIG. 18H(1), a printable semiconductor element comprising a single crystalline semiconductor structure is transferred onto the surface of the substrate covered with the thin amorphous or poly-crystalline semiconductor film. Use of a single crystalline semiconductor structure having one long lateral dimension is preferred for some applications of this method. The present invention also includes methods wherein the printable semiconductor element comprising a single crystalline semiconductor structure is transferred onto the substrate surface prior to deposition of the amorphous or poly-crystalline semiconductor thin film.
  • As shown in FIG. 18H(2), the thin amorphous or poly-crystalline semiconductor film is annealed while in contact with the single crystalline semiconductor structure, for example by annealing at high temperatures such as temperatures greater than 1000 degrees Celsius. In this embodiment of the present invention, the single crystalline semiconductor structure acts as a seed promoting a phase transition throughout the thin film from an amorphous or poly-crystalline state to a well organized single crystalline state. As shown in FIG. 18H(2), the phase transition follows a front of a high temperature gradient which moves across the entire surface of the wafer. Different high temperature furnaces or focused optical systems may be used to produce the temperature gradient necessary to obtain an efficient phase conversion of the semiconductor thin film. An advantage of this process is that it may significantly reduce the cost of producing single crystalline semiconductor thin films, such as single crystalline silicon or germanium films.
  • FIG. 18I shows an exemplary method of fabricating printable semiconductor elements comprising micro-wires from GaAs substrate. As shown in this figure, the exposed surface of the GaAs substrate is patterned with mask material, such as photoresist. Patterning may be achieved by microcontact or nanocontact printing or via conventional photolithography, as shown in FIG. 18E. The patterned surface is anisotropically etched usi