CN101208805A - 纳米尺度沟道晶体管的块接触结构 - Google Patents
纳米尺度沟道晶体管的块接触结构 Download PDFInfo
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- CN101208805A CN101208805A CNA200680023301XA CN200680023301A CN101208805A CN 101208805 A CN101208805 A CN 101208805A CN A200680023301X A CNA200680023301X A CN A200680023301XA CN 200680023301 A CN200680023301 A CN 200680023301A CN 101208805 A CN101208805 A CN 101208805A
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- 239000004065 semiconductor Substances 0.000 claims abstract description 174
- 230000008878 coupling Effects 0.000 claims abstract description 6
- 238000010168 coupling process Methods 0.000 claims abstract description 6
- 238000005859 coupling reaction Methods 0.000 claims abstract description 6
- 229910052751 metal Inorganic materials 0.000 claims description 64
- 239000002184 metal Substances 0.000 claims description 64
- 239000000758 substrate Substances 0.000 claims description 52
- 238000000034 method Methods 0.000 claims description 50
- 239000000463 material Substances 0.000 claims description 32
- 125000006850 spacer group Chemical group 0.000 claims description 29
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 24
- 229910052710 silicon Inorganic materials 0.000 claims description 24
- 239000010703 silicon Substances 0.000 claims description 24
- 238000001259 photo etching Methods 0.000 claims description 21
- 230000008569 process Effects 0.000 claims description 19
- 238000005516 engineering process Methods 0.000 claims description 17
- 230000004888 barrier function Effects 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 14
- 229920002120 photoresistant polymer Polymers 0.000 claims description 13
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 11
- 239000002041 carbon nanotube Substances 0.000 claims description 9
- 229910021393 carbon nanotube Inorganic materials 0.000 claims description 9
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 7
- 229910052732 germanium Inorganic materials 0.000 claims description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 3
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- -1 silicon halide Chemical class 0.000 claims 1
- 239000010410 layer Substances 0.000 description 58
- 238000009413 insulation Methods 0.000 description 30
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 20
- 239000000377 silicon dioxide Substances 0.000 description 10
- 125000004429 atom Chemical group 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 229920005591 polysilicon Polymers 0.000 description 7
- 229910021332 silicide Inorganic materials 0.000 description 7
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 7
- 235000012239 silicon dioxide Nutrition 0.000 description 7
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 6
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 238000000231 atomic layer deposition Methods 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000002955 isolation Methods 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 239000010936 titanium Substances 0.000 description 5
- 229910052719 titanium Inorganic materials 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 239000013078 crystal Substances 0.000 description 4
- 238000013461 design Methods 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 238000000465 moulding Methods 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 229910052715 tantalum Inorganic materials 0.000 description 4
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 3
- 239000004411 aluminium Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 239000010941 cobalt Substances 0.000 description 3
- 229910017052 cobalt Inorganic materials 0.000 description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 238000011049 filling Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000002156 mixing Methods 0.000 description 3
- 239000002090 nanochannel Substances 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 241000027294 Fusi Species 0.000 description 2
- 229910005542 GaSb Inorganic materials 0.000 description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 229910052454 barium strontium titanate Inorganic materials 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 238000005868 electrolysis reaction Methods 0.000 description 2
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- 229910000765 intermetallic Inorganic materials 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- 229910005540 GaP Inorganic materials 0.000 description 1
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- 229910000676 Si alloy Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000003190 augmentative effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 239000010431 corundum Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 208000002173 dizziness Diseases 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- VTGARNNDLOTBET-UHFFFAOYSA-N gallium antimonide Chemical compound [Sb]#[Ga] VTGARNNDLOTBET-UHFFFAOYSA-N 0.000 description 1
- SCCCLDWUZODEKG-UHFFFAOYSA-N germanide Chemical compound [GeH3-] SCCCLDWUZODEKG-UHFFFAOYSA-N 0.000 description 1
- 125000005843 halogen group Chemical group 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000002070 nanowire Substances 0.000 description 1
- 230000000802 nitrating effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000004224 protection Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 238000004513 sizing Methods 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 1
- 239000004408 titanium dioxide Substances 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 238000003631 wet chemical etching Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
-
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
-
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
-
- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L2029/7858—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
-
- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78681—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
-
- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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Abstract
一种纳米尺度沟道器件的接触体系结构,具有耦合并延伸在具有多个并行半导体本体的源区和漏区之间的接触结构。所述接触结构能够接触具有亚光刻间距的并行半导体本体。
Description
技术领域
本发明涉及半导体集成电路制造领域,特别是涉及纳米尺度(nanoscale)沟道器件的接触结构。
背景技术
半导体器件的发展和对半导体器件小型化的不断追求导致在制作更小的结构时需要更好的制作过程,因为更小的器件通常等同于更快的切换时间,这会产生提高的性能。
为了获得该提高的器件性能,需要更小的器件沟道长度并且提出了在大块硅衬底和绝缘硅(SOI)衬底上的许多非平面器件配置如双栅,FinFET,三栅和ω栅。为了制作具有任意大驱动电流的纳米尺度晶体管,器件结构可包括附加的多个半导体本体(body)或指状部件(finger),从而产生多个并行沟道。图1是绝缘硅102上的多沟道三栅晶体管的透视图解。多沟道晶体管100包括具有绝缘层103的单晶硅衬底101,如在其上形成的埋氧层。在绝缘层上,多个半导体本体或指状部件105按图1所示的方式形成。在多个半导体本体105上形成栅绝缘层112,在栅绝缘层112上形成栅电极113,箍缚(strap)在多个半导体本体105上。源区116和漏区117在单晶半导体层中沿栅电极113的横向相反面来形成。
如图1所示,对于典型的三栅器件,各个半导体本体105具有在其上表面和侧壁上形成的栅绝缘层112。在每个半导体本体105上的每个栅绝缘层112上和附近形成栅电极113。如图1所示,各个半导体本体105还包括在半导体本体105中于栅电极113的相反面上形成的源区116和漏区117。如图1所示,半导体本体105的源区116和漏区117通过半导体材料电耦合在一起,所述半导体材料用于形成半导体本体105以形成源着陆垫(source landing pad)118和漏着陆垫(drain landing pad)119。源着陆垫118和漏着陆垫119各通过金属接触结构123电耦合到用于将各种晶体管100电互连在一起形成功能电路的互连金属(如金属1,金属2,金属3......)的上层。如图1所示,为了维持整个晶体管的并行电路结构,为每个半导体本体105提供了一对金属接触(contact)结构123,为源区116提供了第一金属接触结构以及为漏区117提供了第二金属接触。
金属接触结构如图1所示,随着半导体本体105的间距(pitch)的减小,金属接触结构123的间距110也一定减小。如果金属接触结构123的间距110没有随着并行半导体器件的间距的减小而减小,金属接触结构的总电阻、外部电阻(Rext),就会成为器件100的整个寄生电阻的重要部分。因此,金属接触结构123由金属接触结构123的最小光刻间距所制约,从而造成在金属接触结构123的最小光刻间距之下,随着半导体本体105的间距减小,Rext增大。
附图说明
图1是传统多沟道非平面晶体管的透视图的图解说明。
图2A是根据本发明具有金属接触结构的多沟道非平面晶体管的透视图的图解说明。
图2B是根据本发明具有金属接触结构的多沟道非平面晶体管的透视图的图解说明。
图2C是根据本发明具有金属接触结构的多沟道非平面晶体管的透视图的图解说明。
图2D是根据本发明具有金属接触结构的多沟道非平面晶体管的透视图的图解说明。
图3A-3L是制作根据本发明的具有金属接触结构的多沟道非平面晶体管的方法的透视图和横截面视图的图解说明。
具体实施方式
描述了多沟道非平面晶体管的一种新颖的接触结构和它的制作方法。为了提供对本发明的充分理解,在下面的描述中,阐述了许多具体细节,如具体的材料,尺寸和工艺等。为了避免不必要地使本发明变得不清楚,在另一些实例中,没有对公知的半导体工艺和制造技术进行特别详细的描述。
本发明的实施例包括器件接触结构,其中矩形金属结构与非平面晶体管的源区或漏区接触,所述非平面晶体管具有多个半导体本体,所述本体具有由单个栅电极并行控制的沟道。本发明的实施例包括器件接触结构,其中至少一个金属漏接触结构耦合到并延伸在多个半导体本体的漏区之间,以及至少一个金属接触结构耦合到并延伸在多沟道非平面晶体管的多个半导体本体的源区之间。因为矩形块接触结构与多个半导体本体接触,多沟道非平面器件的外部电阻(Rext)随着多个半导体器件的源区端和漏区端的电流密集度的降低而减小。这种方式下,矩形块结构增加了晶体管的切换(switching)速度。
通常,单个晶体管器件提供了足够的绝对电流来驱动电路逻辑功能。然而,随着晶体管沟道宽度缩小到纳米大小,单个晶体管携带的绝对电流也会减小。所以,虽然纳米尺度大小的器件提高了速度,它们的绝对电流却不再足以驱动大的负载,从而限制了单个纳米晶体管的应用。因此,将具有纳米沟道的纳米尺度器件配置且并行运行,使一组纳米器件能够以单个纳米沟道器件的速度运行并提供足够的绝对电流来驱动大的负载,这是很有利的。为了达到必要的驱动电流而并行运行的纳米尺度器件需要一个形状因素,它至少要与提供等量绝对电流的较大单个晶体管器件一样小。这个要求对于避免为提高纳米沟道器件的切换速度而牺牲的逻辑级集成是必要的,并可以被描述为布局(layout)效率。布局效率是并行非平面器件布局的绝对载流宽度(current carrying width)(Z)与占用相同布局宽度的典型平面器件的绝对载流宽度的比值。因为单个非平面纳米尺度晶体管相对于占用相同布局宽度的单个平面纳米尺度晶体管来说,增加了有效载流宽度(Z),所以单个非平面器件的布局效率明显高于100%。然而,如前所述,非平面结构实现的尺寸缩小导致相对低的绝对电流,很多这种非平面器件可能以并行配置方式来运行。除非并行非平面纳米尺度晶体管间的间距小于平面晶体管的最小间距,描述单个非平面器件所需的布局宽度才能够将布局效率减小到100%以下。因此,除非非平面器件的间距与沟道的尺寸按比例缩小,否则并行非平面器件的总载流宽度仍然小于单个平面器件的总载流宽度。因为,典型的平面晶体管具有与金属接触部件(feature)的最小光刻间距相似的沟道间距,所以为了确定单个纳米尺度晶体管本体,可能必须要依赖非光刻构成技术,如间隔区(spacer)和自调整,将非平面纳米尺度晶体管的间距减小到亚光刻(sub-lithographic)级别。这些技术的应用使得纳米尺度沟道器件的布局效率明显高于100%,然而因为平面晶体管总是有最小刻蚀间距,就不可能描述或光刻印刷每个晶体管沟道的单个源接触结构和漏接触结构。此外,即使非平面晶体管器件通过传统的光刻技术来印刷,那也可能是不切实际的昂贵或者很难达到传统接触结构所要求的严格尺寸控制。与传统的接触结构不同,本发明的实施例不受最小光刻间距的限制,不需要在多个纳米尺度晶体管之间共享最小的接触结构。本发明的实施例减小了通过金属接触结构的电流并降低了器件的Rext,从而增加了器件的切换速度。
图2A说明了根据本发明的一个实施例的有金属接触结构的多沟道非平面晶体管200的实例。尽管图2A所示的非平面晶体管200是三栅器件,其它非平面多沟道晶体管的设计,例如但不局限于双栅,ω栅,半导体纳米线,碳纳米管器件,也是本发明的实施例。多沟道非平面晶体管200形成于衬底202上。在本发明的某些实施例中,衬底202是包括在其上形成绝缘层203、如二氧化硅膜层的较低单晶硅衬底201的绝缘衬底。然而,多沟道非平面晶体管200可以形成于任何公知的绝缘衬底上,例如可由二氧化硅,氮化物,碳化物和刚玉形成的衬底。在本发明的某些实施例中,衬底202可以是“大块”半导体衬底,例如但不限于单晶硅衬底和砷化镓衬底。“大块”半导体衬底只是没有绝缘层203。在本发明的一个实施例中,衬底202是具有掺杂外延层的硅半导体衬底,所述外延层具有p型或n型传导性,浓度级别在每立方厘米1×1016至1×1019个原子之间。
在本发明的一个实施例中,多沟道非平面晶体管200包括在绝缘衬底202的绝缘体203上形成的多个半导体本体205。虽然图2A示出了本发明的三栅实施例,但应该明白非平面晶体管的其它实施例也是可能的,例如但不限于双栅、FinFET、ω栅、碳纳米管的设计。半导体器件205可以由任何公知的半导体材料形成,如硅(Si)、锗(Ge)、硅锗(SixGey)、砷化镓(GaAs)、锑化铟(InSb)、磷化镓(GaP)、锑化镓(GaSb)、磷化铟(InP)和碳纳米管。半导体本体205可以由任何公知的材料形成,这种材料可以通过应用外部电流控制可逆地从绝缘状态改变到导电状态。在希望晶体管200有最好的电气性能时,半导体器件205理想地是单晶膜层。例如,当晶体管200用于高性能应用中时,例如在高密度电路中,如微处理器,半导体本体205是单晶膜层。然而,当晶体管200用于要求不太高的性能的应用中时,如液晶显示中,半导体器件205可以是多晶膜层。在本发明的一个实施例中,绝缘体203使半导体器件205和单晶硅衬底201隔离。在本发明的一个实施例中,半导体本体205是单晶硅膜层。在用到“大块”衬底的本发明的一个实施例中,半导体本体205在“大块”半导体衬底的上部区域中形成。半导体器件205具有一对横向相反的侧壁206和207,它们被分开确定单个半导体本体或指状部件宽度的距离。此外,半导体本体205具有上表面208,对着衬底202上形成的下表面。上表面208和下表面之间的距离确定单个半导体本体的高度。在本发明的一个实施例中,单个本体高度基本上等于单个半导体本体宽度。在本发明的一个实施例中,单个半导体本体205的宽度和高度小于30纳米,理想的是小于20纳米。在本发明的一个实施例中,单个半导体本体的高度在单个半导体本体宽度的一半到两倍之间。在本发明的一个实施例中,两个相邻半导体器件之间的距离小于30纳米,理想的是小于20纳米。在本发明的一个实施例中,两个相邻的半导体器件间的距离小于单个半导体本体的宽度。在本发明的一个实施例中,半导体器件的间距,半导体本体的侧壁206和相邻的半导体本体的侧壁206之间的距离,是亚光刻的。在本发明的一个实施例中,半导体器件间的间距小于110纳米。
多沟道非平面晶体管200具有栅绝缘层212。如图2A所示,栅绝缘层212形成于半导体本体205上并环绕其三个面。如图2A所示,栅绝缘层212在半导体本体205的侧壁206上或邻近的地方、其上表面208上、其侧壁207上或邻近的地方形成。栅绝缘层212可以是任何公知的电介质层。在本发明的一个实施例中,栅绝缘层是二氧化硅(SiO2)、氮氧化硅(SiOxNy)、或氮化硅(Si3N4)电介质层。在本发明的一个实施例中,栅绝缘层212是氮氧化硅形成的厚度在5-20之间的膜层。在本发明的一个实施例中,栅绝缘层212是高k栅绝缘层,如氧化金属电介质层,例如但不限于五氧化二钽、二氧化钛、二氧化铪、氧化锆、氧化铝。栅绝缘层212可以是高K电介质的其它类型,例如但不限于钛酸锆(PZT)。
如图2A所示,多沟道非平面晶体管200具有栅电极213。如图2A所示,栅电极213在栅绝缘层212上和其周围形成。栅电极213形成于栅绝缘层212上或其附近,栅绝缘层212形成于半导体本体205的每一个的侧壁206上,栅电极213形成于栅绝缘层212上,栅绝缘层212形成于半导体本体205的每一个的上表面208上,以及栅电极213形成于栅绝缘层212上或其附近,栅绝缘层212形成于半导体本体205的每一个的侧壁207上。栅电极213具有一对横向相反的侧壁,它们被分开确定晶体管200的栅长度(Lg)的距离。在本发明的一个实施例中,栅电极213的横向相反的侧壁在垂直于半导体本体205的横向相反的侧壁206和207的方向上延伸。
栅电极213可由任何合适的栅电极材料构成。在本发明的一个实施例中,栅电极213由掺杂浓度在每立方厘米1×1019个原子到1×1020个原子的多晶硅构成。在本发明的一个实施例中,栅电极可以是金属栅电极,例如但不限于钨,钽,钛,镍,钴,铝,以及对应的氮化物和硅化物。在本发明的一个实施例中,栅电极是由碳纳米管形成的。在本发明的一个实施例中,栅电极由中间带(mid-gap)逸出功在4.6-4.9eV之间的材料形成。应该明白,栅电极213不一定是单一的物质,而可以是薄膜层的复合堆叠,例如但不限于多晶硅/金属电极或金属/多晶硅电极。
如图2A所示,多沟道非平面晶体管200具有半导体本体205的源区216和漏区217。如图2A所示,源区216和漏区217在半导体本体205中于栅电极213的相反面上形成。所形成的源区216和漏区217具有相同的传导性类型,例如n型或p型传导性。在本发明的一个实施例中,源区216和漏区217的掺杂浓度为每立方厘米1×1019到1×1020个原子。所形成的源区216和漏区217可具有均匀的浓度,或者可包括不同浓度或掺杂分布的子区域,例如上表面(例如源延伸区/漏延伸区)。
在本发明的一个实施例中,源区216和漏区217可包括形成于半导体器件205或其周围的硅片或其它半导体膜层。例如,半导体膜层可以是硅膜层或硅合金如锗化硅(SixGey),从而形成“提高的(raised)”源区和漏区。在本发明的一个实施例中,硅化物的膜层,例如但不限于硅化钛,硅化镍,以及硅化钴,形成于源区216和漏区217上。在本发明的一个实施例中,硅膜层直接形成于半导体器件205的上表面208上。在本发明的一个实施例中,源区216和漏区217是完全硅化的(FUSI)。
如图2A所示,在本发明的一个实施例中,半导体器件205的源区216和漏区217通过用于形成半导体本体205的材料电耦合在一起,以形成共同的源轨道(rail)或源着陆垫218和共同的漏轨道或漏着陆垫219。在一个备选实施例中,每个半导体本体205的源区216和漏区217保持互相电隔离,没有形成共同源着陆垫或漏着陆垫。
位于源区216和漏区217之间的半导体器件205的部分确定多沟道非平面晶体管200的一个沟道区,并被栅电极213环绕。在本发明的一个实施例中,沟道区是纯的或者未掺杂的单晶硅。在本发明的一个实施例中,沟道区是掺杂的单晶硅。在沟道区掺杂的情况下,通常掺杂的电导率级别在每立方厘米1×1016到1×1019个原子之间。在本发明的一个实施例中,在沟道区掺杂的情况下,通常掺杂成与源区216和漏区217相反的电导性类型。例如,当源区和漏区是n型电导性时,沟道区就会掺杂p型电导性。类似地,当源区和漏区是p型电导性时,沟道区就会是n型电导性。以这种方式,多沟道非平面晶体管200可分别形成NMOS晶体管或PMOS晶体管。
如图2A所示,多沟道非平面晶体管200封装在绝缘介质中,或者层间电介质(ILD)222中。在本发明的一个实施例中,ILD是低介电常数的材料,如多孔的膜层或掺氮的氧化物膜层。在本发明的一个实施例中,ILD由PSG、BPSG、二氧化硅、氮化硅或这些的组合或其它的公知的材料形成。
如图2A所示,多沟道非平面晶体管200通过具有矩接触结构223和226的ILD222电耦合到外部器件。接触结构可以由任何公知的导电材料形成,例如但不限于铝、金、钛、钨、银和碳纳米管。在本发明的一个实施例中,金属接触结构223和226是铜的。在本发明的一个实施例中,金属接触结构223和226具有附加的阻挡层,例如但不限于钽,氮化钽,钛,氮化钛。
应该明白,矩形块接触结构223和226可互相独立地定尺寸(dimensioned)。还应该明白,描述一个块接触结构的结构,如源接触结构223,可独立地应用到漏接触结构226的结构。因此,各种实施例中描述的或图2A到2D中所示的结构可按任何组合来用于源接触或漏接触。
在本发明的一个实施例中,如图2A所示,一个金属源接触结构223与源区216接触,一个金属漏接触结构226与多个半导体本体205的漏区217接触。在本发明的一个实施例中,金属源接触结构223的宽度224约等于半导体本体205的数目乘以晶体管的半导体本体205的间距,长度225约等于最小光刻部件尺寸。在本发明的一个实施例中,金属漏接触结构226的宽度约等于半导体本体205的数目乘以晶体管的半导体本体205的间距,长度约等于最小光刻部件尺寸。在本发明的另一个实施例中,源接触结构223的宽度224远大于长度225,而漏接触结构226的宽度约等于最小光刻尺寸。同样,漏接触结构226也可定成这样尺寸的块接触:宽度远大于长度,而源接触结构有最小光刻尺寸。在本发明的实施例中,考虑到容许一定的偏差,接触结构223的长度225可能比最小光刻尺寸大。
在本发明的一个实施例中,源接触结构223连接到共同源轨道或源着陆垫218,如图2A所示。在本发明的一个实施例中,金属漏接触结构226接触多沟道非平面晶体管200的共同漏轨道或漏着陆垫219。
通过以所述方式确定单个接触结构的尺寸,用于确定金属块接触结构位置的最小光刻间距已不再制约器件的设计,即使当半导体本体205的最小间距是亚光刻尺寸的时也是如此。此外,由于金属块接触结构宽度224变得远大于长度225,块接触结构223开始近似为一维插槽。由于改进的一维成像方法,这样的一维插槽的光刻确定长度225小于二维接触结构(宽度224约等于长度225)的长度。
在本发明的一个实施例中,如图2B所示,多源接触结构223和227与共同源着陆垫218接触,多个漏接触结构226和230与共同漏着陆垫219接触。在本发明的另一个实施例中,源接触结构与没有共同源着陆垫的多个源区接触,漏接触结构与没有共同漏着陆垫的多个漏区接触。在本发明的一个实施例中,块接触结构的宽度224远大于长度225,如图2B所示。在本发明的一个实施例中,接触结构223的宽度224不同于接触结构227的宽度228。在本发明的一个实施例中,接触结构223的长度225不同于接触结构227的长度229。
在本发明的一个实施例中,单个金属源接触结构223以自对准的方式直接接触到没有共同源着陆垫的多个源区216,而漏接触结构226通过漏着陆垫219接触到漏区217,如图2C所示。以类似的方式,金属漏接触结构直接接触到没有共同漏着陆垫的多个漏区。以这种方式,非平面器件的台阶(step)高度增加了金属源接触的有效表面积,因为金属接触结构包围了非平面源区216和非平面漏区217。正如非平面晶体管具有增加的沟道宽度,非平面接触也会有相对于线性接触来说增大的接触宽度,从而降低了接触电阻,并且降低了并联装置的总寄生电阻。
在本发明的某些实施例中,如图2D所示的多沟道非平面晶体管使用接触源区216或源着陆垫218的多个金属源接触结构223和227来电耦合到外部设备。在本发明的另一个实施例中,多个金属漏接触结构以相似的方式与漏区217接触。在本发明的一个实施例中,金属源接触结构223和227中的至少一个结构的宽度224大于半导体本体的间距但小于半导体本体的数目乘以半导体本体的间距,长度225与最小光刻部件尺寸相当。在本发明的另一些实施例中,金属漏接触结构226的至少一个的宽度大于半导体本体的间距但小于半导体本体的数目乘以半导体本体的间距,长度大约是最小光刻部件尺寸,并且接触漏区217或漏着陆垫219。
在本发明的一个实施例中,多个源接触结构223和227与源区216接触,单个金属漏接触结构226与漏区217或着陆垫219接触,如图2D所示。在本发明的某些实施例中,单个金属源接触结构与源区接触而多个漏接触结构与半导体本体的漏区接触。在本发明的一个实施例中,单个源接触结构与共同源着陆垫接触而多个漏接触结构与多个漏区接触。以此方式,在一个并行设备内可实现基本的扇出、加法器或其它逻辑运算,并且可利用如前所述的通过使用具有亚光刻间距的晶体管提供的高布局效率的优越性。因为半导体本体具有亚光刻间距,所以不是所有的半导体本体都必须被本发明的这个实施例中的接触结构223和227接触。然而,因为半导体本体并行运行,所以如果被结构223和227接触的半导体本体获得了足够的电流,那么某些半导体本体的接触失败不一定会影响到整个器件的运行。
图3A到3L图解说明了根据本发明的一个实施例的一种制作三栅极晶体管的方法。非平面晶体管的制作始于衬底302。如图3A所示,硅或半导体膜层在衬底302上形成。在本发明的一个实施例中,衬底302是绝缘衬底,例如图3A中所示。在本发明的一个实施例中,绝缘衬底302包括低单晶硅衬底301和绝缘层303,如二氧化硅膜层或氮化硅膜层。绝缘层303将半导体膜层304与衬底302隔离,并在实施例中形成了200-2000的厚度。绝缘层303有时被称为“埋氧”层。当硅或半导体膜层304在绝缘衬底301上形成时,绝缘衬底300上的硅或半导体(SOI)就产生了。在本发明的另一些实施例中,衬底302可以是“大块”半导体衬底,例如但不限于单晶硅衬底和砷化镓衬底。在用到了“大块”半导体衬底的本发明的一个实施例中,半导体膜层304只是半导体衬底的上部区域。因此,应该明白涉及半导体膜层304的实施例也适用于使用“大块”衬底的“大块”器件的实施例。在本发明的某些实施例中,衬底302是具有掺杂外延层的硅半导体衬底,具有p型或者n型传导性,浓度在每立方厘米1×1016到1×1019个原子之间。
虽然的半导体膜层304是硅膜层,但是在另一些实施例中,它可以是其它的半导体膜层,例如但不限于锗(Ge)、硅锗合金(SixGey)、砷化镓(GaAs)、InSb、GaP、GaSb、InP以及碳纳米管。在本发明的一个实施例中,半导体膜层304是纯(即未掺杂的)硅膜层。在另一些实施例中,半导体膜层304被掺杂成p型或n型导电性,密度在每立方厘米1×1016到1×1019个原子之间。半导体膜层304可原位(insitu)掺杂(即在它淀积的时候掺杂)或在它形成于衬底302以后通过例如离子注入掺杂。在形成后掺杂使PMOS和NMOS三栅器件在相同的绝缘衬底上很容易形成。在这一点上,半导体本体的掺杂级别能够决定器件的沟道区的掺杂级别。
在本发明的某些实施例中,半导体膜层304形成的厚度约等于所制作的三栅晶体管后续形成的半导体本体所要求的高度。在本发明的一个实施例中,半导体膜层304的厚度或高度小于30纳米,而且理想地小于20纳米尺度。在本发明的另一个实施例中,所形成的半导体膜层304的厚度约等于所制作的三栅晶体管要求的栅“长度”的三分之一。在本发明的另一个实施例中,半导体膜层304形成大于器件所要求的栅长的厚度。在本发明的某些实施例中,半导体膜层304形成到某个厚度,该厚度使所制作的三栅晶体管能够以对其设计的栅长(Lg)完全耗尽的方式来运行。
半导体膜层304可按任何公知的方式形成于绝缘衬底302上。在绝缘衬底上形成硅的一种方法,被称为植入氧(SIMOX)分离技术。当前用于形成SOI衬底的另一种技术是通常被称为结合SOI的外延硅膜层转移技术。在本发明的某些实施例中,半导体膜层304是“大块”半导体衬底的一部分。
这时,若需要,为了隔离将要在衬底中逐个形成的各种晶体管,隔离区域(未示出)可形成在衬底300中。隔离区域可利用例如公知的光刻和蚀刻技术通过蚀刻三栅晶体管周围的半导体膜层304的部分。若需要,可执行用绝缘膜层如二氧化硅来回填蚀刻区域。
这时,半导体本体可由半导体膜层304用公知的光刻和消减(subtractive)蚀刻技术确定半导体本体而形成。在本发明的某个实施例中,半导体本体具有光刻尺寸和间距。在本发明的某些实施例中,亚光刻制作技术如间隔区,可用于形成具有亚光刻间距的半导体本体,如图3B-3F所示。在一种方法中,第一掩膜层由公知的电介质或金属材料形成。在本发明的一个实施例中,第一掩膜层是氮化物。在本发明的一个实施例中,第一掩膜层是氧化物。在本发明的另一个实施例中,第一掩膜层是多晶硅。如图3B的透视图所示,第一掩膜层可通过使用公知的光刻和蚀刻工艺来确定成一种芯棒结构340。芯棒结构340如图3C横截面视图所示。芯棒340有足够的高度、宽度和间距使随后形成间隔区具有预定的间距和宽度。在本发明的某些实施例中,芯棒结构可通过使用的特定光刻装置来得到可分解的最小光刻间距341和宽度342。在本发明的一个实施例中,芯棒结构用193纳米光刻成型。在本发明的一个实施例中,芯棒结构具有大约110纳米的间距341。在本发明的一个实施例中,采用例如但不限于利用干蚀刻或湿蚀刻工艺的各向同性蚀刻等公知技术,使得用于确定芯棒340的光确定(photodefine)层在尺寸上进一步减小。在本发明的另一个实施例中,在通过各向同性蚀刻工艺成型后,芯棒结构340在尺寸上减小。
在本发明的某些实施例中,第二掩膜层351在芯棒结构上形成,如图3D所示。第二掩膜层材料是一类公知的适于形成具有使之能承受随后用于去除芯棒的方法的性质的间隔区。第二个掩膜层材料的厚度选择成可使随后形成的间隔区具有预定的宽度。在本发明的一个实施例中,第二掩膜层351可以是公的材料,例如但不限于氮化物、氧化物或多晶硅。第二掩膜层351可以是公知的金属材料。公知的淀积第二掩膜层351的技术可用于实现所要求的阶梯覆盖或所需的制作,例如但不限于化学气相淀积(CVD)、等离子体增强化学气相淀积(PECVD)、高密度等离子体(HDP)或原子层淀积(ALD)。
如图3E所示,第二掩膜材料可使用适于第二掩膜材料的公知的各向异性蚀刻技术来形成邻近芯棒340侧壁的间隔区352。
这样,可通过任何一种选择性去除芯棒而不大量改变间隔区352的蚀刻技术来去除芯棒。在本发明的一个实施例中,使用公知的湿化学蚀刻工艺来去除芯棒。在本发明的另一个实施例中,使用公知的等离子蚀刻工艺来去除芯棒。一旦芯棒被去除,具有预定间距353和宽度354的间隔区结构352保持,如图3F的截面图所示。在本发明的一个实施例中,间隔区结构352的间距353是亚光刻的。在本发明的一个实施例中,间隔区结构间距353大约是芯棒结构间距的一半。在本发明的一个实施例中,间隔区结构352的间距大约在55纳米左右。如图3G的透视图所示,间隔区结构352形成一个图案或多个图案,所述图案确定在半导体膜层304中随后形成半导体本体或散热片(fin)的位置。间隔区352的图案确定随后形成的三栅晶体管的半导体本体或散热片所要求的宽度354。在本发明的一个实施例中,间隔区结构352的宽度353小于或等于30纳米尺度,理想的是小于或等于20纳米尺度。正如本领域的技术人员应该明白的那样,间隔区结构352的形成过程是可重复进行的,每次会使间隔区结构352的数目加倍,而潜在地降低间隔区的间距353和间隔区的宽度354。
这时,若需要,为了在衬底300上形成三栅晶体管,光确定掩膜(未示出)可用于增大间隔区结构352,有选择地保护半导体膜层304没有受到间隔区结构352保护的部分。光刻胶掩膜还可以确定源着陆垫和漏着陆垫。着陆垫可用于将各种源区连接在一起以及将所制作的晶体管的各种漏区连接在一起。在本发明的某些实施例中,光刻胶掩膜还用于确定具有光刻间距的其它半导体本体。光刻胶掩膜可通过公知的光刻技术形成,包括掩蔽(masking)、暴露和形成均厚淀积光刻胶膜。形成光刻胶掩膜后,半导体膜层305蚀刻成与光刻胶掩膜和间隔区结构352对准,以分别形成一个或多个硅结构或散热片和源着陆垫或漏着陆垫318和319,如图3H所示。在本发明的某些实施例中,图3G中的半导体膜层304直到底下的埋氧层303暴露时才被蚀刻。在用到“大块”衬底的本发明的实施例中,半导体膜层304被蚀刻到理想的深度。公知的半导体蚀刻技术,如各向异性等离子蚀刻或反应性离子蚀刻可用于确定如图3H所示的半导体本体305。这时,可以用公知的技术去除间隔区结构352和光刻胶。这时,半导体本体305具有光刻间距的实施例和半导体本体305具有亚光刻的间距的实施例都可以用图3H来表示。
接着,如图3I所示,栅绝缘层在每个半导体305上以依赖于非平面器件的类型(双栅、三栅、ω栅、碳纳米尺度管)的方式来形成。在本发明的一个实施例中,栅绝缘层312是在每个半导体本体305的上表面和每个半导体本体305的横向相反侧壁上形成的。栅绝缘层可以是淀积的电介质或生长的电介质。在本发明的一个实施例中,栅绝缘层312是用干、湿氧化工艺生长的二氧化硅绝缘膜层。在本发明的一个实施例中,二氧化硅的厚度增长到5-15。在本发明的一个实施例中,栅绝缘层312是淀积电介质,例如但不限于高介电常数膜层,如氧化钽、氧化钛、氧化铪、氧化锆、氧化铝或其它高K电介质,如钛酸锶钡(BST)。高介电常数膜层可通过公知的技术形成,如采用化学气相淀积(CVD)和原子层淀积(ALD)。在本发明的一个实施例中,栅绝缘层可由这样的膜层的复合材料组成。
然后,如图3I所示,形成了栅电极313。栅电极313在形成于每个半导体本体305的上表面的栅绝缘层312上形成,在形成于每个半导体本体305的侧壁上或邻近地方的栅绝缘层312上或邻近的地方形成。栅电极可形成的厚度达到200-3000之间。在一个实施例中,栅电极的厚度是半导体本体305高度的至少3倍。在本发明的实施例中,栅电极材料包含多晶硅。在本发明另一的实施例中,栅电极材料包含多晶硅锗合金。在本发明的再一实施例中,栅电极材料还可包含金属膜层,如镍、钴、钨、钛、钽、氮化物和硅化物。在本发明的进一步实施例中,栅电极可以是碳纳米管。栅电极313可由公知的技术形成,如在衬底上均厚淀积栅电极材料然后用公知的光刻和蚀刻技术将栅电极材料成型。在本发明的某些实施例中,用于确定栅电极313的光刻过程使用用于制作非平面晶体管的最低或最小尺寸的光刻工艺。在本发明的一个实施例中,类似于为确定半导体本体305而描述的那个芯棒类型工艺或公知的氧化技术,可被用于形成具有亚光刻尺寸的栅电极313。在本发明的另一些实施例中,“替换栅(replacement gate)”方法用于形成栅电极313。
然后,晶体管的源区316和漏区317在半导体本体305中于栅电极313的相反面上形成,如图3I所示。在本发明的一个实施例中,源区和漏区包括尖端或源/漏延伸区,可通过在栅极的半导体本体中掺杂来形成。如果使用了源区318和漏区319,它们也会在这时掺杂。对于PMOS三栅晶体管来说,半导体散热片或本体305掺杂了p型电导,密度在每立方厘米1×1020-1×1021个原子之间。对于NMOS三栅晶体管来说,半导体散热片或器件305掺杂了n型电导离子,掺杂浓度在每立方厘米1×1020至1×1021个原子之间。在本发明的一个实施例中,硅膜层通过离子注入掺杂。在本发明的另一个实施例中,离子注入出现在垂直方向。当栅电极313是多晶硅电极时,它可以在离子注入的过程中掺杂。栅电极313用作以掩膜防止离子注入步骤掺杂三栅晶体管的沟道区。沟道区是硅本体305位于栅电极313下或周围的一部分。如果栅电极313是金属电极,绝缘硬掩膜可用于在离子注入的过程中阻止掺杂。在另一些实施例中,其它方法,如固态源扩散,可用于掺杂半导体本体以形成源延伸和漏延伸区域。在本发明的实施例中,在源、漏区或源、漏延伸区形成之前,“晕(halo)”区在硅体里形成。
然后,若需要,衬底可经进一步处理以形成更多的附加部件,如重掺杂源/漏接触区域,在源或漏区及栅电极上淀积硅或硅锗,以及在源接触区域/漏接触区域及在栅电极上形成硅化物。在本发明的实施例中,电介质侧壁间隔区可在栅电极的侧壁上形成。侧壁间隔区可用于补偿重源/漏接触注入,在有选择的硅或硅锗淀积、生长过程中隔离源/漏区与栅电极,以及用于在源区和漏区以及栅电极上形成硅化物或锗化物。在本发明的某些实施例中,实现了全面硅化过程(FUSI)。
然后,器件用绝缘层或中间介质层(ILD)322封装,如图3J所示,它们有足够的厚度来隔离器件。在本发明的某些实施例中,ILD 322由公知的材料构成如磷硅玻璃(PSG)、硼磷硅玻璃(BPSG)、正硅酸乙酯(TEOS)、二氧化硅、氮化硅或这些材料的复合。在本发明的一个实施例中,ILD 322是介电常数比二氧化硅低的材料,例如但不限于多孔电介质材料或掺杂碳的硅酸盐电介质材料。ILD可通过公知的工艺来覆盖淀积,例如但不限于低气压化学气相淀积(LPCVD)、PECVD和HDP。
然后,ILD 322被成型和蚀刻,以对金属接触结构360和363确定开口的位置,如图3K所示。在本发明的某些实施例中,用于确定接触开口360和363的光刻工艺具有大于半导体305的间距的最小光刻间距。在本发明的一个实施例中,用于确定接触开口360和363的光刻工艺是193纳米。在本发明的一个实施例中,所形成的接触开口360和363具有宽度尺寸361和长度362,宽度361约等于半导体本体305的数目乘以半导体本体305的间距,长度362约等于最小光刻部件尺寸。在本发明的一个实施例中,接触开口360和363具有宽度361和长度362,宽度361大于半导体本体305的间距但小于半导体305的数目乘以半导体的间距,长度362大约是最小光刻部件尺寸。在本发明的某些实施例中,接触开口360和363的宽度361远大于长度362。在本发明的某些实施例中,接触开口360和363可被想象成“一维”插槽,其长度362小于接触开口是二维(宽度大约和长度一样大)时可能的长度。在本发明的另一些实施例中,接触结构360和363的维数是不相等的。
在本发明的一个实施例中,接触开口360和363分别终止于源着陆垫318或漏着陆垫319。在本发明的另一个没有源着陆垫或漏着陆垫的实施例中,接触开口360和363分别设置成暴露多个源区316和多个漏区317。在本发明的某些实施例中,接触开口采用公知的各向异性等离子或反应性离子蚀刻工艺蚀刻到ILD 322中,这些工艺对半导体源区316和漏区317具有足够的选择性,使得ILD 322被完全去除以暴露非平面源区316和非平面漏区317(或着陆垫318和319)。
然后,用金属填充接触开口360,以形成金属接触结构323和326,如图3L所示。接触结构323和326可由公知的导电材料形成,例如但不限于铜、钨、铝、黄金或碳纳米管。接触开口360的填充可通过当前已知的任何技术来实现,例如但不限于物理气相淀积(PVD)、CVD、ALD、化学镀或电解镀或这些技术的组合。若需要,填充接触开口360的方法可包括公知的阻挡层的淀积,例如但不限于钽或钽氮化物或其它金属间化合物。若需要,填充接触开口360的方法可包括公知的籽晶层的淀积,例如但不限于铜、钛或其它金属间化合物。
然后,如图3L所示,用于形成金属接触结构323和326的导电物质用公知的电解、化学、机械去除手段或这些的组合来抛光。在本发明的一个实施例中,在镶嵌或双重镶嵌技术中使用了化学机械抛光(CMP)过程。以此方式,在需要时,导电接触结构323和326可被平坦化以与ILD 322基本水平,随后可与金属的附加层互连。
从而,描述了一种具有多个并行纳米尺度沟道、新颖的接触结构的器件和它的制作方法。
Claims (17)
1.一种器件,包括:
多个并行半导体本体,所述多个并行半导体本体的每一个具有上表面和一对横向相反的侧壁,所述并行半导体本体的每一个具有在源区和漏区之间的沟道部分;
单栅电极,邻近和在所述多个本体的每一个的所述沟道区上形成;
金属源接触,耦合并延伸在所述多个并行本体的每一个的所述源区之间;
金属漏接触,耦合并延伸在所述多个并行本体的每一个的所述漏区之间。
2.如权利要求1所述的器件,其中,所述并行本体具有第一宽度和第一间距,所述第一间距小于光刻工艺确定的间距。
3.如权利要求2所述的器件,其中,所述的光刻工艺使用193纳米光刻技术。
4.如权利要求2所述的器件,其中,所述第一间距小于110纳米。
5.如权利要求2所述的器件,其中,所述间距是由所述光刻工艺确定的所述间距的一半。
6.如权利要求1所述的器件,还包括与所述多个并行本体的所述源区直接接触的源着陆垫,其中,所述源着陆垫由与所述并行本体相同的材料形成,所形成的金属源接触与所述源着陆垫直接接触。
7.如权利要求1所述的器件,还包括与所述多个并行本体的所述漏区直接接触的漏着陆垫,其中,所述漏着陆垫由与所述多个并行本体相同的材料形成,所形成的金属漏接触与所述漏着陆垫直接接触。
8.如权利要求1所述的器件,其中,所述多个并行本体由从硅、锗、卤化硅、GaAs、InSb和碳纳米管组成的组中选出的材料形成。
9.如权利要求8所述的半导体器件,其中,所述多个并行本体在绝缘衬底上形成。
10.一种器件,包括:
多个并行半导体本体,所述多个并行半导体本体的每一个具有上表面和一对横向相反的侧壁,所述并行本体的每一个具有在源区和漏区之间的沟道部分;
单栅电极,邻近和在所述多个本体的每一个的所述沟道区上形成;
第一金属接触和第二金属接触,其中,所述第一金属接触和所述第二金属接触这两者中的至少一个耦合并延伸在所述多个并行本体之间。
11.一种形成半导体器件的方法,包括:
在半导体膜层上形成具有第一间距的多个并行间隔区;
蚀刻与所述多个并行间隔区对准的所述半导体膜层,以形成多个多个并行半导体本体;
邻近和在所述多个并行半导体本体上形成单栅电极;
在所述并行半导体本体的每一个中于所述栅电极的相反面上形成源区和漏区;
形成耦合并延伸在所述半导体本体的所述源区之间的单个金属源接触;以及
形成耦合并延伸在所述多个半导体本体的所述漏区之间的单个金属漏接触。
12.如权利要求11所述的方法,其中,所述多个并行间隔区通过以下方法形成:
形成并行部件的第一图案,与第一材料具有第二间距,其中所述第二间距比所述第一间距;
邻近和在并行部件的所述第一图案上均厚淀积第二材料的共形膜层;以及
各向异性地蚀刻所述共形膜层,以由所述第二材料形成所述多个并行间隔区;以及
去除所述第一材料的并行部件的所述第一图案。
13.如权利要求12所述的方法,其中,并行部件的所述第一图案通过在所述第一材料上形成光刻胶掩膜以及各向异性地蚀刻与所述光刻胶掩膜对准的所述第一材料来形成。
14.如权利要求13所述的方法,其中,所述光刻胶掩膜通过均厚淀积光刻胶膜层并使所述光刻胶膜层形成具有所述第二间距的多个并行部件来形成,所述第二间距是使用光刻工艺在所述光刻胶膜层中可确定的最小间距。
15.一种形成半导体器件的方法,包括:
形成多个并行半导体本体,其中,所述半导体本体的每一个具有在源区和漏区之间沟道区;
邻近和在所述多个并行半导体本体的所述沟道区上形成单栅电极;
在所述栅电极和所述多个并行半导体本体上形成绝缘层;
在所述绝缘层中形成单个漏开口,它暴露所述多个并行半导体本体的所述漏区并在所述漏区之间延伸,及在所述绝缘层中形成单个源开口,它暴露所述半导体本体的所述源区并在所述源区之间延伸;以及
用金属膜层填充所述单个漏区开口和所述单个源区开口,所述金属膜层与所述多个并行半导体本体的所述源区和所述漏区接触。
16.如权利要求15所述的方法,还包括,其中所述金属膜层被均厚淀积在所述源区开口和所述漏区开口中及所述绝缘层的上表面上;以及
从所述绝缘层的上表面抛光所述金属膜层,以形成单个漏接触和单个源接触。
17.如权利要求16所述的方法,其中,所述金属膜层利用无电镀的或电镀淀积工艺在所述开口中形成。
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Publication number | Publication date |
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KR20080024168A (ko) | 2008-03-17 |
US7279375B2 (en) | 2007-10-09 |
CN101208805B (zh) | 2014-07-30 |
GB0724762D0 (en) | 2008-01-30 |
JP2008544558A (ja) | 2008-12-04 |
TWI314779B (en) | 2009-09-11 |
DE112006001735T5 (de) | 2008-08-28 |
GB2442379B (en) | 2011-03-09 |
TW200715528A (en) | 2007-04-16 |
US7898041B2 (en) | 2011-03-01 |
GB2442379A (en) | 2008-04-02 |
US20080258207A1 (en) | 2008-10-23 |
WO2007005697A2 (en) | 2007-01-11 |
US20070001219A1 (en) | 2007-01-04 |
WO2007005697A3 (en) | 2007-04-12 |
KR101021369B1 (ko) | 2011-03-14 |
DE112006001735B4 (de) | 2010-11-18 |
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