BR112019001313A2 - estruturas de dispositivo de circuito integrado e técnicas de fabricação de frente e verso - Google Patents

estruturas de dispositivo de circuito integrado e técnicas de fabricação de frente e verso

Info

Publication number
BR112019001313A2
BR112019001313A2 BR112019001313-0A BR112019001313A BR112019001313A2 BR 112019001313 A2 BR112019001313 A2 BR 112019001313A2 BR 112019001313 A BR112019001313 A BR 112019001313A BR 112019001313 A2 BR112019001313 A2 BR 112019001313A2
Authority
BR
Brazil
Prior art keywords
devices
integrated circuit
processing
integrated
fets
Prior art date
Application number
BR112019001313-0A
Other languages
English (en)
Inventor
Block Bruce
R. Rao Valluri
Mehandru Rishabh
Ingerly Doug
Jun Kimin
O'brien Kevin
Morrow Patrick
Fischer Paul
S. Liao Szyua
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from PCT/US2016/068564 external-priority patent/WO2018106267A1/en
Priority claimed from PCT/US2017/048475 external-priority patent/WO2019040071A1/en
Application filed by Intel Corporation filed Critical Intel Corporation
Priority claimed from PCT/US2017/048752 external-priority patent/WO2018039645A1/en
Publication of BR112019001313A2 publication Critical patent/BR112019001313A2/pt

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Classifications

    • H—ELECTRICITY
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8221—Three dimensional integrated circuits stacked in different levels
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    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1876—Particular processes or apparatus for batch treatment of the devices
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H01L27/0694—Integrated circuits having a three-dimensional layout comprising components formed on opposite sides of a semiconductor substrate
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
    • G—PHYSICS
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02S—GENERATION OF ELECTRIC POWER BY CONVERSION OF INFRARED RADIATION, VISIBLE LIGHT OR ULTRAVIOLET LIGHT, e.g. USING PHOTOVOLTAIC [PV] MODULES
    • H02S20/00—Supporting structures for PV modules
    • H02S20/20—Supporting structures directly fixed to an immovable object
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
    • H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Abstract

arquiteturas de células de circuito integrado, incluindo tanto estruturas frontais como traseiras. um ou mais de entre implante traseiro, deposição de semicondutor, deposição de dielétrico, metalização, padronização de deposição dielétrica, metalização, padronização de película e transferência de camada de nível de bolacha é integrado com o processamento frontal. esse processamento de frente e verso pode implicar a revelação de um lado traseiro de estruturas fabricadas a partir de um lado frontal de um substrato. conjuntos de substrato hospedeiro-dador podem ser construídos para apoiar e proteger estruturas frontais durante o processamento traseiro. dispositivos frontais, tais como fets, podem ser modificados e/ou interligados durante o processamento traseiro. dispositivos traseiros, tais como fets, podem ser integrados a dispositivos frontais para expandir a funcionalidade do dispositivo, melhorar o desempenho ou aumentar a densidade do dispositivo.
BR112019001313-0A 2016-08-26 2017-08-25 estruturas de dispositivo de circuito integrado e técnicas de fabricação de frente e verso BR112019001313A2 (pt)

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US201662380316P 2016-08-26 2016-08-26
US62/380,316 2016-08-26
USPCT/US2016/068564 2016-12-23
PCT/US2016/068564 WO2018106267A1 (en) 2016-12-07 2016-12-23 Integrated circuit device with back-side interconnection to deep source / drain semiconductor
USPCT/US2017/048475 2017-08-24
PCT/US2017/048475 WO2019040071A1 (en) 2017-08-24 2017-08-24 FORMATION OF SHARED GRID PATTERNS AND VERTICAL STACK FINFET TRANSISTORS
PCT/US2017/048752 WO2018039645A1 (en) 2016-08-26 2017-08-25 Integrated circuit device structures and double-sided fabrication techniques

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US10872820B2 (en) 2020-12-22
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US20210175124A1 (en) 2021-06-10
US11854894B2 (en) 2023-12-26
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US20200035560A1 (en) 2020-01-30
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